WO2023169245A1 - 太阳能电池的制备方法及太阳能电池 - Google Patents

太阳能电池的制备方法及太阳能电池 Download PDF

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WO2023169245A1
WO2023169245A1 PCT/CN2023/078570 CN2023078570W WO2023169245A1 WO 2023169245 A1 WO2023169245 A1 WO 2023169245A1 CN 2023078570 W CN2023078570 W CN 2023078570W WO 2023169245 A1 WO2023169245 A1 WO 2023169245A1
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layer
opening
passivation layer
back surface
solar cell
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PCT/CN2023/078570
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English (en)
French (fr)
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孙召清
唐喜颜
周生厚
邓小玉
方亮
曲铭浩
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西安隆基乐叶光伏科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of solar photovoltaic technology, and in particular to a preparation method of solar cells and solar cells.
  • Crystalline silicon-amorphous silicon heterojunction (SHJ) cells are prepared by first depositing intrinsic hydrogenated amorphous silicon on the surface of crystalline silicon to passivate surface defects, and then depositing a doped hydrogenated amorphous silicon film.
  • Junction, SHJ battery has symmetrical structure, high open circuit voltage, low process temperature, good temperature characteristics, stable illumination and high bifacial ratio.
  • back-contact heterojunction (Heterojunction-IBC, HBC) batteries can be used.
  • HBC batteries use an interdigitated arrangement on the back to simultaneously set up an electron collection layer and a hole collection layer, so that the two collection layers
  • the layers are arranged in periodic finger-like and comb-like shapes on the back side, thereby avoiding losses caused by grid lines, amorphous silicon, transparent conductive films, etc. on the front side of the solar cell, and increasing the short-circuit current of SHJ cells.
  • processes such as photolithography, screen printing, masking, and masking are usually used to prepare two interdigitated collection layers on the back of the HBC cell.
  • Most processes require at least two mask placements, or at least two wet processes.
  • Etching different patterns makes the operation of using masks and etching solutions complicated and costly.
  • This application provides a solar cell preparation method and solar cell, aiming to simplify the HBC cell preparation process, reduce manufacturing costs, improve the accuracy of patterning in the process, reduce damage, and improve the finished product quality of HBC cells.
  • inventions of the present application provide a method for preparing a solar cell.
  • the method may include:
  • the silicon substrate including a back surface on which electrodes are disposed, and a front surface opposite to the back surface;
  • the back surface field including a second passivation layer and an electron collection layer
  • etching is used to form a third opening on the second passivation layer, the dielectric insulation layer and the first passivation layer at the position of the second opening.
  • the etching rate of the second passivation layer, the dielectric insulation layer and the first passivation layer by the etchant is greater than the etching rate of the electron collection layer;
  • the emitter including a third passivation layer and a hole collection layer;
  • Laser ablation is used to form a fourth opening on the third passivation layer and the hole collection layer at the position of the first opening.
  • the center position of the fourth opening overlaps with the center position of the first opening.
  • the width of the fourth opening is less than or equal to the width of the first opening and less than the width of the third opening.
  • the second passivation layer is a SiOx layer.
  • the electron collection layer is a Poly-Si(n+) layer.
  • the third passivation layer is an a-Si:H(i) layer.
  • the hole collection layer is a-Si:H(p+) layer, a-SiOx:H(p+) layer, a-SiCx:H(p+) layer, a-SiOxCy:H(p+) layer any of them.
  • the laser ablation includes any one of nanopulse laser and picosecond pulse laser.
  • the laser wavelength for laser ablation includes any one of 355 nanometers, 532 nanometers, and 1064 nanometers.
  • the thickness of the first passivation layer is less than 50 nm.
  • the thickness of the dielectric insulation layer is less than 500 nm.
  • the thickness of the second passivation layer is less than 5 nm.
  • the thickness of the electron collection layer is less than 500 nm.
  • the thickness of the third passivation layer is less than 50 nm.
  • the hole collecting layer has a thickness less than 100 nm.
  • the method further includes:
  • laser ablation is used to ablate the first passivation layer on the third passivation layer and the hole collection layer.
  • the fourth opening is formed at the position of the opening, it also includes:
  • Metal electrodes are prepared on the back side.
  • the thickness of the fourth passivation layer is less than 20 nm.
  • the thickness of the anti-reflection layer is less than 100 nm.
  • embodiments of the present application provide a solar cell, which includes a back surface with electrodes and a front surface opposite to the back surface;
  • the emitter and the back surface field in the back surface are periodically arranged in an interdigital shape, and the back surface field includes a SiOx/Poly-Si(n+) layer.
  • the solar cell is prepared using the preparation method described in the first aspect.
  • the side of the silicon substrate with electrodes is used as the back side, and the side opposite to the back side is used as the front side.
  • the first passivation is deposited sequentially on the back side.
  • a third opening is formed at the position of the opening, wherein the etching rate of the etchant used in wet etching to the second passivation layer, the dielectric insulation layer and the first passivation layer is greater than the etching rate to the electron collection layer,
  • the electron collection layer including the second opening is used as a mask in the process of wet etching the second passivation layer, the dielectric insulation layer and the first passivation layer to form a penetrating electron collection layer and a third passivation layer at the second opening.
  • the second passivation layer, the dielectric insulation layer and the third opening of the first passivation layer prepare an emitter on the back side.
  • the emitter includes a third passivation layer and a hole collection layer.
  • Laser ablation can be used on the third passivation layer. and a fourth opening is formed at the position of the first opening on the hole collecting layer.
  • the process of patterning the back emitter and back surface field of the silicon substrate adopts one wet etching and multiple laser ablation.
  • the laser ablation process has fast processing speed, high precision, low cost and little pollution. Therefore, by reducing wet etching, which is cumbersome, costly and polluting, the process can be effectively simplified, costs reduced, patterning accuracy improved, damage reduced, and the finished product quality of HBC batteries improved.
  • Figure 1 shows one of the step flow charts of the preparation method of solar cells provided by the embodiment of the present application
  • Figure 2 shows the second step flow chart of the solar cell preparation method provided by the embodiment of the present application
  • FIG. 3 is one of the schematic process flow diagrams of a solar cell preparation method provided by an embodiment of the present application.
  • Figure 4 is the second schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • FIG. 5 is a third schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • Figure 6 is the fourth schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • FIG. 7 is a schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • FIG. 8 is a schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • Figure 9 is a schematic seventh process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • FIG 10 is a schematic process flow diagram 8 of a solar cell preparation method provided by an embodiment of the present application.
  • Figure 11 is a schematic process flow diagram of a method for manufacturing a solar cell provided by an embodiment of the present application.
  • Figure 12 is a schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • Figure 13 is an eleventh schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • FIG. 14 is a schematic 12th process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • Figure 1 shows one of the step flow charts of the solar cell preparation method provided by the embodiment of the present application. As shown in Figure 1, the method may include:
  • Step 101 Provide a silicon substrate, which includes a back surface with electrodes and a front surface opposite to the back surface.
  • the silicon substrate can be a crystalline silicon substrate that has been processed by cleaning, texturing, etc., and the silicon substrate can include a single-sided arrangement.
  • the back side of the electrode, and the front side opposite the back side, the front side of the silicon substrate is the light incident side of the solar cell.
  • the light incident side of the silicon substrate can be textured Treatment, so that the silicon substrate has a light trapping structure on the front side of the light incident side, which plays an anti-reflective effect and ensures the performance of the finished solar cell.
  • Step 102 Deposit a first passivation layer and a dielectric insulation layer sequentially on the back surface.
  • a first passivation layer can be deposited on the back side of the silicon substrate.
  • the first passivation layer can passivate the dangling bonds on the surface of the silicon substrate, reduce the surface recombination of surface carriers and thereby improve the battery efficiency.
  • the first passivation layer can be prepared by thermal oxidation, physical vapor deposition, chemical vapor deposition and other processes.
  • a dielectric insulating layer can be deposited on the first passivation layer to form a composite layer of the first passivation layer and the dielectric insulating layer on the back side of the silicon substrate.
  • the dielectric insulating layer is used to insulate the electrons on the back side of the solar cell. collection area and hole collection area.
  • the dielectric insulation layer can be deposited and prepared by chemical vapor deposition.
  • Step 103 Use laser ablation to form a first opening on the first passivation layer and the dielectric insulation layer.
  • laser ablation can be used to remove part of the composite layer of the first passivation layer and the dielectric insulation layer to form the first opening. After removal, some areas of the silicon substrate are exposed through the first opening, and other areas are covered by the first passivation layer. and covered with a dielectric insulation layer.
  • the shape, position, and size of the first opening can be arranged according to the patterning requirements of the back surface field.
  • Step 104 Prepare a back surface field on the back surface, where the back surface field includes a second passivation layer and an electron collection layer.
  • the back surface field can be prepared on the back surface.
  • a second passivation layer can be deposited on the back surface of the silicon substrate, and then an electron collection layer can be deposited on the second passivation layer to form a composite layer to obtain the back surface field, where , the second passivation layer partially contacts the silicon substrate through the first opening, and other parts cover the dielectric insulating layer.
  • the second passivation layer can refer to the relevant description of the first passivation layer, and to avoid repetition, it will not be described again here;
  • the electron collection layer is used to realize selective transmission of electrons, and a material with selective transmission properties for electrons can be selected.
  • the electron collection layer can be prepared by a chemical vapor deposition method.
  • Step 105 Use laser ablation to form a second opening on the electron collection layer, where the second opening is spaced apart from the first opening.
  • laser ablation can be used to remove part of the electron collection layer, thereby forming a second opening on the electron collection layer.
  • the second passivation layer is partially exposed through the second opening on the electron collection layer, and other parts are Covered by an electron collection layer, the shape, position, and size of the second opening can be arranged according to the patterning requirements of the emitter, based on the intersection between the surface field and the emitter. Refers to the arrangement requirements.
  • the second opening and the first opening are spaced apart on the back.
  • the width and spacing of the second opening and the first opening can be set according to the performance, specifications, etc. of the specific battery, as well as process conditions, etc.
  • the embodiments of this application are There is no specific limit to this.
  • laser ablation is used to form a second opening on the electron collection layer.
  • the second opening is spaced apart from the first opening.
  • Laser ablation has better accuracy, thereby ensuring insulation between the positions of the second opening and the first opening.
  • the dielectric layer, that is, the second opening can be accurately formed using laser ablation without affecting the insulating dielectric layer, so that there is an insulating dielectric layer between the second opening and the first opening, ensuring that the distance between the first opening and the second opening is maintained Electrical insulation.
  • Step 106 Use wet etching to form a third opening on the second passivation layer, the dielectric insulation layer and the first passivation layer at the position of the second opening.
  • the wet etching The etching rate of the used etchant for the second passivation layer, the dielectric insulation layer and the first passivation layer is greater than the etching rate for the electron collection layer.
  • wet etching may be used to remove the second passivation layer, the dielectric insulation layer and the first passivation layer under the second opening on the electron collection layer to form the third opening. Due to differences in material properties, an etchant whose etching rate for the second passivation layer, dielectric insulation layer and first passivation layer is greater than the etching rate for the electron collection layer can be used, so that electrons can be removed during the etching process.
  • the collection layer serves as a mask in wet etching. After etching, part of the silicon substrate is exposed through the third opening, and other parts are covered by the first passivation layer.
  • the etchant used in wet etching may be an acidic etchant, for example, the etchant is hydrofluoric acid, and for another example, the etchant is hydrochloric acid.
  • the specific type of etchant is not limited in the embodiments of this application.
  • Step 107 Prepare an emitter on the back side, where the emitter includes a third passivation layer and a hole collection layer.
  • the emitter can be prepared on the back side of the silicon substrate.
  • a third passivation layer can be deposited on the back side of the silicon substrate, and then a hole collection layer can be deposited on the third passivation layer to prepare a composite layer as the emitter. pole, part of the third passivation layer contacts the silicon substrate through the third opening, and other parts cover the electron collection layer.
  • the third passivation layer may refer to the relevant description of the aforementioned first passivation layer. To avoid repetition, it will not be mentioned here. Let’s go into details again; the hole collection layer is used to realize selective transmission of holes, and a material with selective hole transmission properties can be selected.
  • the hole collection layer can be prepared by a chemical vapor deposition method.
  • Step 108 Use laser ablation to form a fourth opening on the third passivation layer and the hole collection layer at the position of the first opening.
  • laser ablation can be used to remove the third passivation layer and the hole collection layer at the first opening position to form a fourth opening, so that the electron collection layer is exposed through the fourth opening, and the hole collection layer is exposed through the fourth opening.
  • the third openings spaced apart from the fourth openings are exposed, so that the electron collection layer and the hole collection layer can be arranged spaced apart on the back side of the silicon substrate.
  • the back surface field on the back side of the rail base is in phase with the emitter. Arranged at intervals, the backside patterning of the silicon substrate is realized.
  • the side of the silicon substrate with electrodes is used as the back side, and the side opposite to the back side is used as the front side.
  • the first passivation is deposited sequentially on the back side.
  • a third opening is formed at the position of the opening, wherein the etching rate of the etchant used in wet etching to the second passivation layer, the dielectric insulation layer and the first passivation layer is greater than the etching rate to the electron collection layer,
  • the electron collection layer including the second opening is used as a mask in the process of wet etching the second passivation layer, the dielectric insulation layer and the first passivation layer to form a penetrating electron collection layer and a third passivation layer at the second opening.
  • the second passivation layer, the dielectric insulation layer and the third opening of the first passivation layer prepare an emitter on the back side.
  • the emitter includes a third passivation layer and a hole collection layer.
  • Laser ablation can be used on the third passivation layer. and a fourth opening is formed at the position of the first opening on the hole collecting layer.
  • the process of patterning the back emitter and back surface field of the silicon substrate adopts one wet etching and multiple laser ablation.
  • the laser ablation process has fast processing speed, high precision, low cost and little pollution. Therefore, by reducing wet etching, which is cumbersome, costly and polluting, the process can be effectively simplified, costs reduced, patterning accuracy improved, damage reduced, and the finished product quality of HBC batteries improved.
  • Figure 2 shows the second step flow chart of the solar cell preparation method provided by the embodiment of the present application. As shown in Figure 2, the method may include:
  • Step 201 Provide a silicon substrate 1.
  • the silicon substrate 1 includes a back side 1a on which electrodes are provided, and a front side 1b opposite to the back side 1a.
  • step 201 may refer to the relevant description of the foregoing step 101 to avoid duplication and will not be described again here.
  • FIG 3 is one of the schematic process flow diagrams of a solar cell preparation method provided by an embodiment of the present application.
  • a silicon substrate 1 is provided, wherein the silicon substrate 1 includes a back surface with electrodes.
  • the front surface 1a and the front surface 1b are opposite to the back surface 1a.
  • the back surface 1a has a planar structure, and the front surface 1b has a suede light-trapping structure.
  • Step 202 sequentially deposit the first passivation layer 2 and the dielectric insulation layer 3 on the back surface 1a.
  • the first passivation layer 2 may include silicon oxide, hydrogenated amorphous silicon and other materials that can passivate surface dangling bonds
  • the dielectric insulating layer 3 may include silicon oxide, silicon nitride and other insulating materials.
  • the thickness of the first passivation layer 2 is less than 50 nm.
  • the thickness of the dielectric insulation layer 3 is less than 500 nm.
  • the thickness of the first passivation layer 2 and the dielectric insulation layer 3 deposited on the back surface 1a of the silicon substrate 1 can be selected according to process conditions, application requirements, etc.
  • the thickness of the first passivation layer 2 can be is any thickness less than 50 nm
  • the thickness of the dielectric insulating layer 3 can be any thickness less than 500 nm.
  • FIG 4 is a second process flow diagram of a solar cell preparation method provided by an embodiment of the present application. As shown in Figure 4, a first passivation layer 2 and a dielectric insulating layer 3 are sequentially deposited on the back surface 1a of the silicon substrate 1.
  • Step 203 Use laser ablation to form the first opening 4 on the first passivation layer 2 and the dielectric insulation layer 3.
  • step 203 may correspond to the relevant description of step 103, and to avoid repetition, it will not be described again here.
  • the laser ablation includes nanopulse laser or picosecond pulse laser.
  • laser ablation is a process in which heat is transferred to the material surface through a high-energy laser beam to melt and vaporize the irradiated area to form a microstructure.
  • Laser ablation can use nano-pulse laser, picosecond pulse laser, etc., where , Nano-pulse laser refers to a laser process that uses nanomaterials as resonant cavities to generate laser light under optical excitation or electrical excitation.
  • the size of nano-pulse laser can reach nanometer scale; picosecond pulse laser is a picosecond-level ultra-short pulse width, repetitive Laser technology with adjustable frequency and high pulse energy can achieve high-speed and high-precision material processing.
  • Laser ablation using the above-mentioned technology can achieve fast and high-precision patterning.
  • the laser wavelength for laser ablation includes 355 nanometers, 532 nanometers or 1064 nanometers.
  • the laser wavelength selected in the laser ablation process can be 355 nanometers, 532 nanometers or 1064 nanometers. Different laser wavelengths can be selected and used according to the characteristics of the material's absorption of laser wavelengths, process conditions, etc., in the embodiments of this application There are no specific restrictions on this.
  • FIG. 5 is a third schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application. As shown in Figure 5, laser ablation is used to remove portions of the first passivation layer 2 and the dielectric insulation layer 3 to form the first opening. 4. At this time, the silicon substrate 1 is exposed through the first opening 4.
  • the first opening 4 is only used as an example, and the shape, position, and number of the first opening 4 are not specifically limited in the implementation of this application.
  • Step 204 Prepare a back surface field on the back surface 1a.
  • the back surface field includes the second passivation layer 5 and the electron collection layer 6.
  • step 204 may correspond to the relevant description of step 104, and to avoid repetition, it will not be described again here.
  • the second passivation layer 5 is a SiOx layer.
  • the electron collection layer 6 is a Poly-Si(n+) layer.
  • the second passivation layer 5 in the back surface field can be a silicon oxide SiOx layer
  • the electron collection layer 6 can be a Poly-Si(n+) layer. Therefore, the back surface field of the back surface 1a in the solar cell adopts a Silicon oxide passivation layer/phosphorus-doped polysilicon SiOx/Poly-Si(n+) layer structure with higher electron collection capability, hole collection using intrinsic hydrogenated amorphous silicon passivation layer/boron-doped hydrogenated amorphous silicon a- Si:H(i)/a-Si:H(p+) layer structure.
  • the high carrier selectivity and low contact resistance based on the back surface field of the SiOx/Poly-Si(n+) structure can effectively Improve solar cell conversion efficiency.
  • the thickness of the second passivation layer 5 is less than 5 nm.
  • the thickness of the electron collection layer 6 is less than 500 nm.
  • the thickness of the second passivation layer 5 and the electron collection layer 6 can be selected according to process conditions, application requirements, etc.
  • the thickness of the chemical layer 5 may be any thickness less than 5 nm
  • the thickness of the electron collection layer 6 may be any thickness less than 500 nm.
  • Figure 6 is a schematic process flow diagram of a method for preparing a solar cell provided by an embodiment of the present application.
  • a SiOx layer is deposited on the back side 1a of the silicon substrate 1 as the second passivation layer 5, and then A phosphorus-doped polycrystalline silicon Poly-Si(n+) layer is deposited on the second passivation layer 5 as the electron collection layer 6 , wherein the second passivation layer 5 contacts the silicon substrate 1 through the first opening 4 .
  • Step 205 Use laser ablation to form a second opening 7 on the electron collection layer 6.
  • the second opening 7 is spaced apart from the first opening 4.
  • step 205 may correspond to the relevant description of step 105, and to avoid repetition, it will not be described again here.
  • FIG. 7 is a process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • laser ablation is used to remove part of the electron collection layer 6 to form the second opening 7 , and the second opening 7 is spaced apart from the first opening 4 .
  • Step 206 Use wet etching to form a third opening 8 on the second passivation layer 5, the dielectric insulation layer 3 and the first passivation layer 2 at the position of the second opening 7, so The etching rate of the etchant used in the wet etching to the second passivation layer 5, the dielectric insulation layer 3 and the first passivation layer 2 is greater than the etching rate to the electron collection layer 6 rate.
  • the hole collection layer 10 since the hole collection layer 10 has high requirements on the surface of crystalline silicon in the subsequent process, and the process temperature of laser ablation is high, it may damage the surface of crystalline silicon. Therefore, the third opening can be wet etched.
  • the subsequent preparation requirements for the hole collection layer are met, but the wet etching process is cumbersome and costly.
  • Laser ablation can be selected instead of wet etching for other steps to simplify the process and improve accuracy.
  • Wet etching can use acid solution corrosion. The acid solution has a corrosive effect.
  • the reaction rate to the first passivation layer 2, the dielectric insulation layer 3 and the second passivation layer 5 is relatively fast, and the reaction rate to the electron collection layer 6 is very fast.
  • the electron collection layer 6 forming the second opening 7 can be used as a mask to etch the first passivation layer 2 , the dielectric insulation layer 3 and the second passivation layer 5 to form the second opening 7
  • the third opening 8 does not need to be placed, removed, or replaced with a mask, which reduces the preparation cost and improves the alignment accuracy.
  • other etchants that have a faster reaction rate to the first passivation layer 2, the dielectric insulation layer 3 and the second passivation layer 5 and a slower reaction rate to the electron collection layer 6 can also be selected. The application examples do not specifically limit this.
  • hydrofluoric acid is used for etching.
  • the reaction rate of hydrofluoric acid to the first passivation layer 2, the dielectric insulation layer 3 and the second passivation layer 5 is relatively fast, and the reaction rate to the electron collection layer 6 is relatively slow, that is, it is quite During hydrofluoric acid etching of the second passivation layer 5, the dielectric insulation layer 3 and the first passivation layer 2, the electron collection layer 6 is not etched, and the electron collection layer 6 functions as a mask.
  • FIG 8 is a schematic process flow diagram No. 6 of a solar cell preparation method provided by an embodiment of the present application.
  • an acidic solution is used for wet etching, and the electron collection layer 6 forming the second opening 7 is used as the The mask is used to etch the first passivation layer 2 , the dielectric insulation layer 3 and the second passivation layer 5 , and a third opening 8 is formed at the position of the second opening 7 through which the silicon substrate 7 can be exposed.
  • Step 207 Prepare an emitter on the back surface 1a.
  • the emitter includes a third passivation layer 9 and a hole collection layer 10.
  • step 207 may correspond to the relevant description of the aforementioned step 107. To avoid repetition, the details are not repeated here.
  • the third passivation layer 9 is an a-Si:H(i) layer.
  • the hole collection layer 10 is a-Si:H(p+) layer, a-SiOx:H(p+) layer, a-SiCx:H(p+) layer, a-SiOxCy:H(p+) layer any of the layers.
  • the third passivation layer 9 in the emitter may be an intrinsic hydrogenated amorphous silicon a-Si:H(i) layer
  • the hole transport layer 10 may be a boron-doped amorphous silicon a-Si:H(i) layer.
  • the H(p+) layer can also be an oxygen-doped amorphous silicon a-SiOx:H(p+) layer, or a carbon-doped amorphous silicon a-SiCx:H(p+) layer, or both. Oxygen and carbon amorphous silicon a-SiOxCy:H(p+) are not specifically limited in the embodiments of this application.
  • amorphous silicon may include microcrystalline silicon.
  • Microcrystalline silicon refers to a semiconductor containing a plurality of microcrystalline grains in amorphous silicon, where the average particle size of the microcrystalline grains may be in the range of 1 nm to 50 nm, such as The average particle diameter of the microcrystalline particles may be any value within the range of 1 nm to 50 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc.
  • the thickness of the third passivation layer 9 is less than 50 nm.
  • the hole collecting layer 10 has a thickness less than 100 nm.
  • the thickness of the third passivation layer 9 and the hole collection layer 10 can be selected according to process conditions, application requirements, etc.
  • the thickness of the chemical layer 9 may be any thickness less than 50 nm, and the thickness of the hole collection layer 10 may be any thickness less than 100 nm.
  • Figure 9 is a schematic process flow diagram of a solar cell preparation method provided in the embodiment of the present application.
  • an a-Si:H(i) layer is deposited on the back side 1a of the silicon substrate 1 as the third passivation layer.
  • passivation layer 9 and an a-Si:H(p+) layer is deposited on the third passivation layer 9 as the hole collection layer 10 , wherein the third passivation layer 9 contacts the silicon substrate 1 through the third opening 8 .
  • Step 208 Deposit the fourth passivation layer 11 and the anti-reflection layer 12 on the front surface 1b.
  • the fourth passivation layer 11 can be deposited on the front surface 1b of the silicon substrate 1.
  • the fourth passivation layer 11 can correspond to the relevant description of the first passivation layer 2 in the aforementioned step 102. To avoid repetition, in This will not be described again.
  • An anti-reflective layer 12 can be further deposited on the fourth passivation layer 11 to form a composite layer.
  • the anti-reflective layer 12 is used to reduce the reflection loss of incident light on the front side 1b.
  • the anti-reflective layer 12 can be selected from silicon nitride, silicon oxide or the like. Silicon oxide, etc., in the implementation of this application, can be prepared by chemical vapor deposition or other processes.
  • the fourth passivation layer 11 and the anti-reflection layer 12 are functional descriptions.
  • the fourth passivation layer 11 and the anti-reflection layer 12 can be the same film layer to achieve passivation function and anti-reflection at the same time. function, or different film layers can realize the passivation function respectively.
  • a layer can be added between the fourth passivation layer 11 and the anti-reflection layer 12
  • the front field can be used to improve the passivation effect on the battery. It is also possible to avoid adding a front field to avoid parasitic absorption caused by the front field and reduce the short-circuit current of the battery.
  • the thickness of the fourth passivation layer 11 is less than 20 nm.
  • the thickness of the anti-reflection layer 12 is less than 100 nm.
  • the thickness of the fourth passivation layer 11 and the anti-reflection layer 12 can be selected according to process conditions, application requirements, etc., and optionally, the thickness of the fourth passivation layer 11 can be deposited on the front surface 1b of the silicon substrate 1
  • the thickness of the anti-reflection layer 12 may be any thickness less than 20 nm, and the thickness of the anti-reflection layer 12 may be any thickness less than 100 nm.
  • FIG 10 is a schematic process flow diagram of a method for preparing a solar cell provided by an embodiment of the present application.
  • a hydrogenated amorphous silicon layer is deposited on the front side 1b of the silicon substrate 1 as the fourth passivation layer 11.
  • an anti-reflective layer 12 is deposited on the fourth passivation layer 11 .
  • Step 209 Use laser ablation to form a fourth opening 13 on the third passivation layer 9 and the hole collection layer 10 at the position of the first opening 4.
  • step 209 may refer to the relevant description of the foregoing step 108. To avoid repetition, the details are not repeated here.
  • the center position of the fourth opening 13 overlaps with the center position of the first opening 4, and the width of the fourth opening 13 is less than or equal to the width of the first opening 4 and less than the width of the first opening 4.
  • the width of the fourth opening 13 may be smaller than the width of the first opening 4 , which facilitates laser alignment during laser ablation, facilitates patterning of the laser process, and facilitates laser etching to form the fourth opening 13 . Moreover, the width of the fourth opening 13 is smaller than the width of the first opening, which facilitates subsequent formation of other openings between the fourth opening 13 and the third opening 8 . In addition, the width of the fourth opening 13 may also be equal to the width of the first opening 4 . In this regard, the embodiments of the present application are not limited here.
  • the fourth opening 13 is formed at the position of the first opening 4 , the center position of the fourth opening 13 may coincide with the center position of the first opening 4 , and the width is less than or equal to the width of the first opening 4 , further, the width of the fourth opening 13 should also be smaller than the width of the third opening 8.
  • the specific widths of the first opening 4, the third opening 8 and the fourth opening 13 can be set according to the application requirements and process conditions. The application examples do not specifically limit this.
  • FIG 11 is a schematic process flow diagram of a method for preparing a solar cell provided by an embodiment of the present application. As shown in Figure 11, laser ablation is used to remove a portion of the third opening 4 on the back side 1a of the silicon substrate 1. The passivation layer 9 and the hole collection layer 10 form a fourth opening 13 through which the electron collection layer 6 is exposed.
  • Step 210 Deposit a transparent conductive layer 14 on the back surface 1a.
  • a transparent conductive layer 14 is deposited on the back side 1a.
  • the deposited transparent conductive layer 14 can contact the electron collection layer 6 through the fourth opening 13, and contact the hole collection layer 10 through the third opening 8.
  • the transparent conductive layer 14 It has low resistivity and good photoelectric properties, and can efficiently collect carriers through the electron collection layer 6 and the hole collection layer 10 to ensure the efficiency of the finished solar cell.
  • the transparent conductive layer 14 can be magnetron sputtering or reactive plasma. It is prepared by deposition method, etc., and the transparent conductive layer 14 can be an indium tin oxide layer, a zinc oxide layer, etc.
  • FIG 12 is a schematic process flow diagram of a solar cell preparation method provided by the embodiment of the present application.
  • an indium tin oxide layer is deposited on the back side 1a of the silicon substrate 1 as a transparent conductive layer 14, wherein the transparent The conductive layer 14 is in contact with the electron collection layer 6 through the fourth opening 13 and in contact with the hole collection layer 10 through the third opening 8 .
  • the thickness of the transparent conductive layer 14 is less than 100 nm.
  • the thickness of the transparent conductive layer 14 deposited on the back surface 1a of the silicon substrate 1 can be selected according to process conditions, application requirements, etc.
  • the thickness of the transparent conductive layer 14 can be any thickness less than 100 nm.
  • Step 211 Use laser ablation to form a fifth opening 15 between the fourth opening 13 and the third opening 8 on the back surface 1a.
  • the fifth opening 15 penetrates the transparent conductive layer 14 and at least partially The dielectric insulation layer 3 is retained.
  • the position of the fourth opening 13 can be used as an electron collection area
  • the position of the third opening 8 can be used as a hole collection area.
  • the electron collection area can be separated and the transparent conductive layer 14 between the electron collection area and the hole collection area, and retain the dielectric insulating layer 3 between the electron collection area and the hole collection area to ensure the insulation effect between the electron collection area and the hole collection area, wherein, Laser ablation is used to form a fifth opening 15 between the fourth opening 13 and the third opening 8 on the front side 1 b.
  • the depth of the fifth opening 15 should completely penetrate the thickness of the transparent conductive layer 14 and at least partially retain the dielectric insulating layer 3
  • the thickness of the transparent conductive layer 14 is such that there is no conduction between the electron collection area and the hole collection area, and the dielectric insulating layer 3 remains isolated. That is, the fifth opening 15 can block the transparent conductive layer 14 , but the fifth opening 15 does not penetrate the dielectric insulation layer 3 .
  • the fifth opening 15 needs to penetrate the transparent conductive layer 14, and continue to penetrate until reaching the dielectric insulation layer 3. If the width of the fourth opening 13 is equal to the width of the first opening 4 , then when the fifth opening 15 is provided, the fifth opening 15 can only pass through the transparent conductive layer 14 .
  • Figure 13 is an eleventh schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • laser ablation is used to create the fourth opening 13 and the third opening 8 on the back side 1a of the silicon substrate 1
  • a fifth opening 15 is formed between the transparent conductive layer 14 and the dielectric insulating layer 3.
  • the fifth opening 15 can penetrate the transparent conductive layer 14 and retain the dielectric insulating layer 3.
  • the other film layers between the transparent conductive layer 14 and the dielectric insulating layer 3 can be formed according to process conditions and application requirements. Wait for removal or retention.
  • Step 212 Prepare a metal electrode on the back surface 1a.
  • a metal electrode can be further prepared on the electrode side.
  • the metal electrode can include a metal electrode 16a that collects holes, and a metal electrode 16b that collects electrons.
  • screen printing, electroplating and other processes can be used to prepare metal electrodes.
  • the material of the metal electrodes can be metals such as silver, copper, aluminum, tin, or an alloy of at least two metals such as silver, copper, aluminum, tin, etc. The embodiments of the present application do not specifically limit this.
  • Figure 14 is the twelfth schematic process flow diagram of a solar cell preparation method provided by an embodiment of the present application.
  • a metal electrode is prepared on the back side 1a of the silicon substrate 1, including a metal electrode in the third opening 8.
  • a metal electrode 16 a for collecting holes is prepared on the transparent conductive layer 14 at the position, and a metal electrode 16 b for collecting electrons is prepared on the transparent conductive layer 14 at the position of the fourth opening 13 .
  • the side of the silicon substrate with electrodes is used as the back side, and the side opposite to the back side is used as the front side.
  • the first passivation is deposited sequentially on the back side.
  • a third opening is formed at the position of the opening, wherein the etching rate of the etchant used in wet etching to the second passivation layer, the dielectric insulation layer and the first passivation layer is greater than the etching rate to the electron collection layer,
  • the electron collection layer including the second opening is used as a mask in the process of wet etching the second passivation layer, the dielectric insulation layer and the first passivation layer to form a penetrating electron collection layer and a third passivation layer at the second opening.
  • the second passivation layer, the dielectric insulation layer and the third opening of the first passivation layer prepare an emitter on the back side.
  • the emitter includes a third passivation layer and a hole collection layer.
  • Laser ablation can be used on the third passivation layer. and a fourth opening is formed at the position of the first opening on the hole collecting layer.
  • the process of patterning the back emitter and back surface field of the silicon substrate adopts one wet etching and multiple laser ablation.
  • the laser ablation process has fast processing speed, high precision, low cost and little pollution. Therefore, by reducing the wet etching process that is cumbersome, costly and polluting, It can effectively simplify the process, reduce costs, improve patterning accuracy, and reduce damage, thereby improving the finished product quality of HBC batteries.
  • Embodiments of the present application also provide a solar cell, which includes a back surface with electrodes and a front surface opposite to the back surface;
  • the emitter and the back surface field in the back surface are periodically arranged in an interdigital shape, and the back surface field includes a SiOx/Poly-Si(n+) layer.
  • the solar cell is prepared by using the solar cell preparation method described in any one of Figures 1 to 2.
  • the second passivation layer in the back surface field can be a silicon oxide SiOx layer
  • the electron collection layer can be a Poly-Si(n+) layer. Therefore, the back surface field on the electrode side in the solar cell adopts a higher Silicon oxide passivation layer/phosphorus-doped polysilicon SiOx/Poly-Si(n+) layer structure with electron collection capability, hole collection using intrinsic hydrogenated amorphous silicon passivation layer/boron-doped hydrogenated amorphous silicon a-Si: H(i)/a-Si:H(p+) layer structure.
  • the high carrier selectivity and low contact resistance based on the back surface field of the SiOx/Poly-Si(n+) structure can effectively improve solar energy. Battery conversion efficiency.

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Abstract

本申请提供了一种太阳能电池的制备方法及太阳能电池，涉及太阳能光伏技术领域。其中，该方法在对硅基底的背面进行发射极和背表面场图形化的过程中采用了一次湿法刻蚀与多次激光消融，激光消融工艺加工速度快、精度高、成本低、污染小，因此，通过减少实施操作繁琐、成本高、污染大的湿法刻蚀次数，采用激光消融能够有效简化工艺、降低成本，并提高图形化的精度，降低损伤，从而提高HBC电池的成品质量。

Description

太阳能电池的制备方法及太阳能电池
本申请要求在2022年3月9日提交中国专利局、申请号为202210235077.1、申请名称为“太阳能电池的制备方法及太阳能电池”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳能光伏技术领域，特别是涉及一种太阳能电池的制备方法及太阳能电池。
背景技术
晶硅-非晶硅异质结(Silicon Hetero-Junction，SHJ)电池通过在晶硅表面先沉积本征氢化非晶硅以钝化表面缺陷，再沉积掺杂的氢化非晶硅薄膜制备异质结，SHJ电池结构对称、开路电压高、工艺温度低、温度特性好、光照稳定且具有高双面率。进一步的，为了提升SHJ电池的短路电流，可以采用背接触异质结(Heterojunction-IBC，HBC)电池，HBC电池在背面采用叉指排列同时设置电子收集层和空穴收集层，使得两种收集层在背面呈周期性指状、梳状排列，从而避免了太阳能电池正面设置栅线、非晶硅、透明导电薄膜等造成的损失，提升了SHJ电池的短路电流。
目前，通常采用光刻、丝网印刷、掩膜、遮罩等工艺在HBC电池的背面制备叉指排列的两种收集层，多数工艺需要至少两次放置掩膜板，或至少两次湿法刻蚀不同图形，使得使用掩膜板、刻蚀溶液的操作复杂、成本较高，同时也可能存在对位精度低、损伤大的问题，影响成品质量。
申请内容
本申请提供一种太阳能电池的制备方法及太阳能电池，旨在简化HBC电池制备工艺、降低制造成本，并提高工艺中图形化的精度，降低损伤，提高HBC电池的成品质量。
第一方面，本申请实施例提供了太阳能电池的制备方法，该方法可以包括：
提供硅基底，所述硅基底包括设置电极的背面，以及与所述背面相对的正面；
在所述背面依次沉积第一钝化层和介质绝缘层；
采用激光消融在所述第一钝化层和所述介质绝缘层上形成第一开口；
在所述背面制备背表面场，所述背表面场包括第二钝化层和电子收集层；
采用激光消融在所述电子收集层上形成第二开口，所述第二开口与所述第一开口相间隔；
采用湿法刻蚀在所述第二钝化层、所述介质绝缘层和所述第一钝化层上所述第二开口的位置处形成第三开口，所述湿法刻蚀采用的刻蚀剂对所述第二钝化层、所述介质绝缘层和所述第一钝化层的刻蚀速率大于对所述电子收集层的刻蚀速率；
在所述背面制备发射极，所述发射极包括第三钝化层和空穴收集层；
采用激光消融在所述第三钝化层和空穴收集层上所述第一开口的位置处形成第四开口。
可选地，所述第四开口的中心位置与所述第一开口的中心位置重叠。
可选地，所述第四开口的宽度小于或等于所述第一开口的宽度，且小于所述第三开口的宽度。
可选地，所述第二钝化层为SiOx层。
可选地，所述电子收集层为Poly-Si(n+)层。
可选地，所述第三钝化层为a-Si:H(i)层。
可选地，所述空穴收集层为a-Si:H(p+)层、a-SiOx:H(p+)层、a-SiCx:H(p+)层、a-SiOxCy:H(p+)层中的任一种。
可选地，所述激光消融包括纳米脉冲激光、皮秒脉冲激光中的任一种。
可选地，所述激光消融的激光波长包括355纳米、532纳米、1064纳米中的任一种。
可选地，所述第一钝化层的厚度小于50nm。
可选地，所述介质绝缘层的厚度小于500nm。
可选地，所述第二钝化层的厚度小于5nm。
可选地，所述电子收集层的厚度小于500nm。
可选地，所述第三钝化层的厚度小于50nm。
可选地，所述空穴收集层的厚度小于100nm。
可选地，所述在所述背面制备发射极，所述发射极包括第三钝化层和空穴收集层之后，还包括：
在所述正面依次沉积第四钝化层和防反射层；
可选地，所述采用激光消融在所述第三钝化层和空穴收集层上所述第一 开口的位置处形成第四开口之后，还包括：
在所述背面沉积透明导电层；
采用激光消融在所述背面的所述第四开口和所述第三开口之间形成第五开口，所述第五开口穿透所述透明导电层且至少部分保留所述介质绝缘层；
在所述背面制备金属电极。
可选地，所述第四钝化层的厚度小于20nm。
可选地，所述防反射层的厚度小于100nm。
第二方面，本申请实施例提供了一种太阳能电池，该太阳能电池包括设置电极的背面，以及与所述背面相对的正面；
所述背面中发射极和背表面场呈叉指状周期性排列，所述背表面场包括SiOx/Poly-Si(n+)层。
可选地，所述太阳能电池采用第一方面所述的制备方法制备得到。
在本申请实施中，将硅基底设置电极的一侧作为背面，将与背面相对的一侧作为正面，在背面的背表面场、发射极图形化工艺中，先在背面依次沉积第一钝化层和介质绝缘层，再采用激光消融在第一钝化层和介质绝缘层上形成第一开口暴露硅基底；在背面再制备背表面场层，背表面场包括第二钝化层和电子收集层；采用激光消融在电子收集层上形成第二开口，第二开口与第一开口相间隔；再采用湿法刻蚀在第二钝化层、介质绝缘层和第一钝化层上第二开口的位置处形成第三开口，其中，湿法刻蚀采用的刻蚀剂对第二钝化层、介质绝缘层和第一钝化层的刻蚀速率大于对电子收集层的刻蚀速率，使得包含第二开口的电子收集层在湿法刻蚀第二钝化层、介质绝缘层和第一钝化层的过程中作为掩膜，以在第二开口处形成穿透电子收集层、第二钝化层、介质绝缘层和第一钝化层的第三开口；在背面再制备发射极，发射极包括第三钝化层和空穴收集层，可以采用激光消融在第三钝化层和空穴收集层上第一开口的位置处形成第四开口。在本申请实施中对硅基底的背面发射极和背表面场进行图形化的过程采用了一次湿法刻蚀与多次激光消融，激光消融工艺加工速度快、精度高、成本低、污染小，因此，通过减少实施操作繁琐、成本高、污染大的湿法刻蚀能够有效简化工艺、降低成本，并提高图形化的精度，降低损伤，从而提高HBC电池的成品质量。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它 目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本申请实施例提供的太阳能电池的制备方法步骤流程图之一；
图2示出了本申请实施例提供的太阳能电池的制备方法步骤流程图之二；
图3是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之一；
图4是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之二；
图5是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之三；
图6是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之四；
图7是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之五；
图8是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之六；
图9是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之七；
图10是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之八；
图11是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之九；
图12是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之十；
图13是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之十一；
图14是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之十二。
具体实施例
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面结合具体的实施例对本申请的技术方案进行详细说明。下面这些具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
参照图1，图1示出了本申请实施例提供的太阳能电池的制备方法步骤流程图之一，如图1所示，该方法可以包括：
步骤101、提供硅基底，所述硅基底包括设置电极的背面，以及与所述背面相对的正面。
本申请实施例中，可以应用于HBC电池的背面发射极和背表面场的图形化工艺中，其中，硅基底可以是经清洗、制绒等处理的晶体硅基板，硅基底可以包括单侧设置电极的背面，以及与背面相对的正面，则硅基底的正面是太阳能电池的入光侧。可选地，可以对硅基底的入光侧进行制绒处 理，从而使得硅基底在入光侧的正面具有陷光结构，起到减反射效果，保证成品太阳能电池的性能。
步骤102、在所述背面依次沉积第一钝化层和介质绝缘层。
本申请实施例中，可以在硅基底的背面先沉积第一钝化层，第一钝化层可钝化硅基底表面的悬挂键，减少表面载流子的表面复合从而提升电池效率，第一钝化层可以采用热氧化法、物理气相沉积法、化学气相沉积法等工艺制备得到。
本申请实施例中，可以再在第一钝化层上沉积介质绝缘层从而在硅基底的背面形成第一钝化层、介质绝缘层的复合层，介质绝缘层用于绝缘太阳能电池背面的电子收集区域和空穴收集区域。介质绝缘层可以采用化学气相沉积法沉积制备得到。
步骤103、采用激光消融在所述第一钝化层和所述介质绝缘层上形成第一开口。
本申请实施例中，可以采用激光消融去除部分第一钝化层和介质绝缘层的复合层以形成第一开口，去除后硅基底部分区域通过第一开口暴露，其他区域被第一钝化层和介质绝缘层覆盖，可选地，第一开口的形状、位置、大小可以根据背表面场的图形化要求布置。
步骤104、在所述背面制备背表面场，所述背表面场包括第二钝化层和电子收集层。
本申请实施例中，可以在背面制备背表面场，如可以在硅基底的背面先沉积第二钝化层，再在第二钝化层上沉积电子收集层形成复合层获得背表面场，其中，第二钝化层通过第一开口部分接触硅基底，其他部分覆盖介质绝缘层，第二钝化层可对应参照前述第一钝化层的相关描述，为避免重复，在此不再赘述；电子收集层用于实现电子选择性传输，可以选择对电子具有选择性传输性能的材料，可选地，电子收集层可以采用化学气相沉积方法制备。
步骤105、采用激光消融在所述电子收集层上形成第二开口，所述第二开口与所述第一开口相间隔。
本申请实施例中，可以采用激光消融去除部分的电子收集层，从而在电子收集层上形成第二开口，去除后第二钝化层通过电子收集层上的第二开口部分暴露，其他部分被电子收集层覆盖，其中，第二开口的形状、位置、大小可以根据发射极的图形化要求布置，基于被表面场与发射极呈叉 指排列的要求，第二开口与第一开口在背面相间隔，第二开口与第一开口的宽度、间距等可以根据具体电池的性能、规格等，以及工艺条件等设置，本申请实施例对此不作具体限制。
另外，采用激光消融在电子收集层上形成第二开口，第二开口与第一开口相间隔，激光消融具有较好的准确性，从而可以确保第二开口与第一开口的位置之间具有绝缘介质层，即利用激光消融可以精准的形成第二开口，并不影响绝缘介质层，使得第二开口与第一开口的位置之间具有绝缘介质层，确保第一开口与第二开口之间保持电绝缘。
步骤106、采用湿法刻蚀在所述第二钝化层、所述介质绝缘层和所述第一钝化层上所述第二开口的位置处形成第三开口，所述湿法刻蚀采用的刻蚀剂对所述第二钝化层、所述介质绝缘层和所述第一钝化层的刻蚀速率大于对所述电子收集层的刻蚀速率。
本申请实施例中，可以采用湿法刻蚀对电子收集层上第二开口下的第二钝化层、介质绝缘层和第一钝化层进行去除，以形成第三开口。由于材料特性的差异，可以采用对第二钝化层、介质绝缘层和第一钝化层的刻蚀速率大于对电子收集层刻蚀速率的刻蚀剂，从而在刻蚀过程中可以将电子收集层作为湿法刻蚀中的掩膜，刻蚀后硅基底部分通过第三开口暴露，其他部分被第一钝化层覆盖。
需要说明的是，在申请实施例中，湿法刻蚀采用的刻蚀剂可以为酸性刻蚀剂，例如，刻蚀剂为氢氟酸，再例如，刻蚀剂为盐酸。对于刻蚀剂的具体类型，本申请实施例在此不作限定。
步骤107、在所述背面制备发射极，所述发射极包括第三钝化层和空穴收集层。
本申请实施例中，可以在硅基底的背面再制备发射极，如可以在硅基底的背面先沉积第三钝化层，再在第三钝化层上沉积空穴收集层制备复合层作为发射极，第三钝化层部分通过第三开口接触硅基底，其他部分覆盖电子收集层，其中，第三钝化层可对应参照前述第一钝化层的相关描述，为避免重复，在此不再赘述；空穴收集层用于实现空穴选择性传输，可以选择对空穴具有选择性传输性能的材料，可选地，空穴收集层可以采用化学气相沉积方法制备。
步骤108、采用激光消融在所述第三钝化层和空穴收集层上所述第一开口的位置处形成第四开口。
本申请实施例中，可以采用激光消融去除第一开口位置处的第三钝化层和空穴收集层以形成第四开口，使得电子收集层通过第四开口暴露，而空穴收集层通过与第四开口相间隔的第三开口暴露，从而使得在硅基底的背面中电子收集层、空穴收集层可以相间隔排列，在此基础上，在轨基地的背面中背表面场与发射极相间隔排列，从而实现了硅基底的背面图形化。
在本申请实施中，将硅基底设置电极的一侧作为背面，将与背面相对的一侧作为正面，在背面的背表面场、发射极图形化工艺中，先在背面依次沉积第一钝化层和介质绝缘层，再采用激光消融在第一钝化层和介质绝缘层上形成第一开口暴露硅基底；在背面再制备背表面场层，背表面场包括第二钝化层和电子收集层；采用激光消融在电子收集层上形成第二开口，第二开口与第一开口相间隔；再采用湿法刻蚀在第二钝化层、介质绝缘层和第一钝化层上第二开口的位置处形成第三开口，其中，湿法刻蚀采用的刻蚀剂对第二钝化层、介质绝缘层和第一钝化层的刻蚀速率大于对电子收集层的刻蚀速率，使得包含第二开口的电子收集层在湿法刻蚀第二钝化层、介质绝缘层和第一钝化层的过程中作为掩膜，以在第二开口处形成穿透电子收集层、第二钝化层、介质绝缘层和第一钝化层的第三开口；在背面再制备发射极，发射极包括第三钝化层和空穴收集层，可以采用激光消融在第三钝化层和空穴收集层上第一开口的位置处形成第四开口。在本申请实施中对硅基底的背面发射极和背表面场进行图形化的过程采用了一次湿法刻蚀与多次激光消融，激光消融工艺加工速度快、精度高、成本低、污染小，因此，通过减少实施操作繁琐、成本高、污染大的湿法刻蚀能够有效简化工艺、降低成本，并提高图形化的精度，降低损伤，从而提高HBC电池的成品质量。
参照图2，图2示出了本申请实施例提供的太阳能电池的制备方法步骤流程图之二，如图2所示，该方法可以包括：
步骤201、提供硅基底1，所述硅基底1包括设置电极的背面1a，以及与所述背面1a相对的正面1b。
本申请实施例中，步骤201可对应参照前述步骤101的相关描述，避免重复，在此不再赘述。
图3是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之一，如图3所示，提供硅基底1，其中，硅基底1包括设置电极的背 面1a以及与背面1a相对的正面1b，背面1a为平面结构，正面1b为绒面陷光结构。
步骤202、在背面1a依次沉积第一钝化层2和介质绝缘层3。
本申请实施例中，第一钝化层2可以包括氧化硅、氢化非晶硅等可以钝化表面悬挂键的材料，介质绝缘层3可以包括氧化硅、氮化硅等绝缘材料，具体可参照前述步骤102的相关描述，为避免重复，在此不再赘述。
可选地，所述第一钝化层2的厚度小于50nm。
可选地，所述介质绝缘层3的厚度小于500nm。
本申请实施例中，在硅基底1的背面1a沉积第一钝化层2、介质绝缘层3的厚度可以根据工艺条件、应用需求等选择，可选地，第一钝化层2的厚度可以是小于50nm的任意厚度，介质绝缘层3的厚度可以是小于500nm的任意厚度。
图4是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之二，如图4所示，在硅基底1的背面1a依次沉积第一钝化层2和介质绝缘层3。
步骤203、采用激光消融在所述第一钝化层2和所述介质绝缘层3上形成第一开口4。
本申请实施例中，步骤203可对应参照前述步骤103的相关描述，为避免重复，在此不再赘述。
可选地，所述激光消融包括纳米脉冲激光或皮秒脉冲激光。
本申请实施例中，激光消融是通过高能激光束将热量传输到材料表面使照射区域内发生融化、气化从而形成微结构的工艺，激光消融可以采用纳米脉冲激光、皮秒脉冲激光等，其中，纳米脉冲激光指采用纳米材料为谐振腔，在光激发或电激发下产生激光的激光工艺，纳米脉冲激光的尺寸可以达到纳米量级；皮秒脉冲激光是皮秒级超短脉宽、重复频率可调、脉冲能量高的激光工艺，能够实现高速、高精度的材料加工，采用上述工艺实施激光消融能够实现快速、高精度的图形化。
可选地，所述激光消融的激光波长包括355纳米、532纳米或1064纳米。
本申请实施例中，激光消融的工艺中选择的激光波长可以是355纳米、532纳米或1064纳米，可以根据材料对激光波长吸收的特性、工艺条件等选择使用不同的激光波长，本申请实施例对此不作具体限制。
图5是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之三，如图5所示，采用激光消融去除部分的第一钝化层2和介质绝缘层3形成第一开口4，此时，硅基底1通过第一开口4暴露。该第一开口4仅作为示例，在本申请实施中对第一开口4的形状、位置、数量不作具体限制。
步骤204、在所述背面1a制备背表面场，所述背表面场包括第二钝化层5和电子收集层6。
本申请实施例中，步骤204可对应参照前述步骤104的相关描述，为避免重复，在此不再赘述。
可选地，所述第二钝化层5为SiOx层。
可选地，所述电子收集层6为Poly-Si(n+)层。
本申请实施例中，背表面场中第二钝化层5可以是氧化硅SiOx层，电子收集层6可以是Poly-Si(n+)层，因而在太阳能电池中背面1a的背表面场采用具有更高电子收集能力的氧化硅钝化层/磷掺杂多晶硅SiOx/Poly-Si(n+)层结构，空穴收集采用本征氢化非晶硅钝化层/硼掺杂氢化非晶硅a-Si:H(i)/a-Si:H(p+)层结构，在此基础上，基于SiOx/Poly-Si(n+)结构背表面场的高载流子选择性与低接触电阻，能够有效提升太阳能电池转换效率。
可选地，所述第二钝化层5的厚度小于5nm。
可选地，所述电子收集层6的厚度小于500nm。
本申请实施例中，在硅基底1的背面1a制备背表面场时，沉积第二钝化层5、电子收集层6的厚度可以根据工艺条件、应用需求等选择，可选地，第二钝化层5的厚度可以是小于5nm的任意厚度，电子收集层6的厚度可以是小于500nm的任意厚度。
图6是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之四，如图6所示，在硅基底1的背面1a上沉积SiOx层作为第二钝化层5，再在第二钝化层5上沉积磷掺杂多晶硅Poly-Si(n+)层作为电子收集层6，其中，第二钝化层5通过第一开口4与硅基底1接触。
步骤205、采用激光消融在所述电子收集层6上形成第二开口7，所述第二开口7与所述第一开口4相间隔。
本申请实施例中，步骤205可对应参照前述步骤105的相关描述，为避免重复，在此不再赘述。
图7是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示 意图之五，如图7所示，采用激光消融去除部分的电子收集层6形成第二开口7，第二开口7与第一开口4相间隔排列。
步骤206、采用湿法刻蚀在所述第二钝化层5、所述介质绝缘层3和所述第一钝化层2上所述第二开口7的位置处形成第三开口8，所述湿法刻蚀采用的刻蚀剂对所述第二钝化层5、所述介质绝缘层3和所述第一钝化层2的刻蚀速率大于对所述电子收集层6的刻蚀速率。
本申请实施例中，由于后续工艺中空穴收集层10对晶硅表面要求高，而激光消融的工艺温度较高，可能会损伤晶硅的表面，因此，第三开口可以采用湿法刻蚀以达到后续空穴收集层的制备要求，但湿法刻蚀工艺繁琐、成本高，其他步骤可以选择激光消融而不采用湿法刻蚀以简化工艺、提高精度。湿法刻蚀可以采用酸液腐蚀腐蚀，酸溶液具有腐蚀作用，对第一钝化层2、介质绝缘层3和第二钝化层5的反应速率较快，对电子收集层6的反应速率较慢，因而可以将形成第二开口7的电子收集层6作为掩膜进行第一钝化层2、介质绝缘层3和第二钝化层5的刻蚀，以在第二开口7处形成第三开口8，无需放置、去除、更换掩膜等，降低了制备成本、提高了对位精度。在本申请实施中也可以选择其他对第一钝化层2、介质绝缘层3和第二钝化层5的反应速率较快，对电子收集层6的反应速率较慢的刻蚀剂，本申请实施例对此不作具体限制。
例如，采用氢氟酸进行腐蚀，氢氟酸对第一钝化层2、介质绝缘层3和第二钝化层5的反应速率较快，对电子收集层6的反应速率较慢，即相当于氢氟酸刻蚀第二钝化层5、介质绝缘层3以及第一钝化层2，不刻蚀电子收集层6，电子收集层6相当于起到掩膜的作用。
图8是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之六，如图8所示，采用酸性溶液进行湿法刻蚀，将形成第二开口7的电子收集层6作为掩膜进行第一钝化层2、介质绝缘层3和第二钝化层5的刻蚀，在第二开口7的位置处形成第三开口8，硅基底7可以通过第三开口8暴露。
步骤207、在所述背面1a制备发射极，所述发射极包括第三钝化层9和空穴收集层10。
本申请实施例中，步骤207可对应参照前述步骤107的相关描述，为避免重复，在此不再赘述。
可选地，所述第三钝化层9为a-Si:H(i)层。
可选地，所述空穴收集层10为a-Si:H(p+)层、a-SiOx:H(p+)层、a-SiCx:H(p+)层、a-SiOxCy:H(p+)层中的任一种。
本申请实施例中，发射极中第三钝化层9可以是本征氢化非晶硅a-Si:H(i)层，空穴传输层10可以是硼掺杂非晶硅a-Si:H(p+)层，也可以是氧掺杂非晶硅a-SiOx:H(p+)层，也可以是碳掺杂非晶硅a-SiCx:H(p+)层，也可以是同时掺杂氧、碳的非晶硅a-SiOxCy:H(p+)，本申请实施例对此不作具体限制。
本申请实施例中，非晶硅可以包括微晶硅，微晶硅指非晶硅中包含多个微晶粒的半导体，其中，微晶粒的平均粒径可以在1nm至50nm范围内，如微晶粒的平均粒径可以是1nm、2nm、3nm、4nm、5nm、10nm、15nm、20nm、30nm、40nm、50nm等1nm至50nm范围内的任意数值。
可选地，所述第三钝化层9的厚度小于50nm。
可选地，所述空穴收集层10的厚度小于100nm。
本申请实施例中，在硅基底1的背面1a制备发射极时，沉积第三钝化层9、空穴收集层10的厚度可以根据工艺条件、应用需求等选择，可选地，第三钝化层9的厚度可以是小于50nm的任意厚度，空穴收集层10的厚度可以是小于100nm的任意厚度。
图9是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之七，如图9所示，在硅基底1的背面1a沉积a-Si:H(i)层作为第三钝化层9，在第三钝化层9上再沉积a-Si:H(p+)层作为空穴收集层10，其中，第三钝化层9通过第三开口8与硅基底1接触。
步骤208、在所述正面1b沉积第四钝化层11和防反射层12。
本申请实施例中，可以在硅基底1的正面1b沉积第四钝化层11，第四钝化层11可对应参照前述步骤102中第一钝化层2的相关描述，为避免重复，在此不再赘述。在第四钝化层11上可以进一步沉积防反射层12以形成复合层，防反射层12用于在正面1b减少入射光的反射损失，防反射层12可以选择氮化硅、氧化硅或等氧化硅等，在本申请实施中，可以采用化学气相沉积法制备，也可以采用其他工艺制备。
本申请实施例中，第四钝化层11、防反射层12为功能性描述，在制备工艺中第四钝化层11、防反射层12可以是同一膜层同时实现钝化功能与防反射功能，也可以是不同膜层分别实现钝化功能，在第四钝化层11、防反射层12为不同膜层的情况下，第四钝化层11与防反射层12之间可以添加 正面场以提升对电池的钝化效果，也可以不添加正面场以避免正面场造成寄生吸收，降低电池的短路电流。
可选地，所述第四钝化层11的厚度小于20nm。
可选地，所述防反射层12的厚度小于100nm。
本申请实施例中，在硅基底1的正面1b沉积第四钝化层11、防反射层12的厚度可以根据工艺条件、应用需求等选择，可选地，第四钝化层11的厚度可以是小于20nm的任意厚度，防反射层12的厚度可以是小于100nm的任意厚度。
图10是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之八，如图10所示，在硅基底1的正面1b沉积氢化非晶硅层作为第四钝化层11，再在第四钝化层11上沉积防反射层12。
步骤209、采用激光消融在所述第三钝化层9和空穴收集层10上所述第一开口4的位置处形成第四开口13。
本申请实施例中，步骤209可对应参照前述步骤108的相关描述，为避免重复，在此不再赘述。
可选地，所述第四开口13的中心位置与所述第一开口4的中心位置重叠，所述第四开口13的宽度小于或等于所述第一开口4的宽度，且小于所述第三开口8的宽度。
其中，第四开口13的宽度可以小于第一开口4的宽度，从而在通过激光消融时，便于激光进行对准，有利于激光工艺的图形化，进而便于激光刻蚀，形成第四开口13。并且，第四开口13的宽度小于第一开口的宽度，也便于后续在第四开口13与第三开口8之间形成其他开口。另外，第四开口13的宽度也可以等于第一开口4的宽度。对此，本申请实施例在此不作限定。
本申请实施例中，第四开口13在第一开口4的位置处形成，可以是第四开口13的中心位置与第一开口4的中心位置重合，且宽度小于或等于第一开口4的宽度，从进一步的，第四开口13的宽度也应小于第三开口8的宽度，具体第一开口4、第三开口8和第四开口13的宽度大小可以根据应用需求、工艺条件进行设置，本申请实施例对此不作具体限制。
图11是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之九，如图11所示，采用激光消融在硅基底1的背面1a的第一开口4位置处去除部分第三钝化层9和空穴收集层10形成第四开口13，其中，电子收集层6通过第四开口13暴露。
步骤210、在所述背面1a沉积透明导电层14。
本申请实施例中，在背面1a沉积透明导电层14，沉积的透明导电层14可以通过第四开口13接触电子收集层6，以及通过第三开口8接触空穴收集层10，透明导电层14电阻率低、光电特性好，能够高效的通过电子收集层6、空穴收集层10收集载流子，保证成品太阳能电池的效率，其中，透明导电层14可以采用磁控溅射法、反应等离子沉积法等方法制备得到，透明导电层14可以是氧化铟锡层、氧化锌层等。
图12是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之十，如图12所示，在硅基底1的背面1a沉积氧化铟锡层作为透明导电层14，其中，透明导电层14通过第四开口13与电子收集层6接触，通过第三开口8与空穴收集层10接触。
可选地，所述透明导电层14的厚度小于100nm。
本申请实施例中，在硅基底1的背面1a沉积透明导电层14的厚度可以根据工艺条件、应用需求等选择，可选地，透明导电层14的厚度可以是小于100nm的任意厚度。
步骤211、采用激光消融在所述背面1a的所述第四开口13和所述第三开口8之间形成第五开口15，所述第五开口15穿透所述透明导电层14且至少部分保留所述介质绝缘层3。
本申请实施例中，可以将第四开口13的位置处作为电子收集区，将第三开口8的位置处作为空穴收集区，为了隔离电子收集区与空穴收集区，可以隔断电子收集区和空穴收集区之间的透明导电层14，并保留电子收集区与空穴收集区之间的介质绝缘层3，以保证电子收集区与空穴收集区之间的绝缘效果，其中，可以采用激光消融在正面1b的第四开口13和第三开口8之间形成第五开口15，第五开口15的深度应完全穿透该透明导电层14的厚度，并且至少部分保留介质绝缘层3的厚度，以使电子收集区与空穴收集区之间不存在透明导电层14导通，也保留介质绝缘层3隔绝。即第五开口15可以隔断透明导电层14，但第五开口15未贯穿介质绝缘层3。
另外，在本申请实施例中，当开设第四开口13之后，若第四开口13的宽度小于第一开口4的宽度，那么在设置第五开口15时，第五开口15需要穿透透明导电层14，且继续穿透，直至到达介质绝缘层3停止。若第四开口13的宽度等于第一开口4的宽度，那么在设置第五开口15时，可以使得第五开口15仅穿过透明导电层14。
图13是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之十一，如图13所示，采用激光消融在硅基底1的背面1a上第四开口13与第三开口8之间形成第五开口15，其中，第五开口15可以穿透透明导电层14且保留介质绝缘层3，透明导电层14与介质绝缘层3之间的其他膜层可以根据工艺条件、应用需求等去除或保留。
步骤212、在所述背面1a制备金属电极。
本申请实施例中，在完成硅基底1的背面1a图形化后，可以进一步在电极侧制备金属电极，其中，金属电极可以包括收集空穴的金属电极16a，以及收集电子的金属电极16b，可选地，可以采用丝网印刷、电镀等工艺制备金属电极，金属电极的材料可以是银、铜、铝、锡等金属，也可以是银、铜、铝、锡等至少两种金属的合金，本申请实施例对此不作具体限制。
图14是本申请实施例提供的一种太阳能电池的制备方法的工艺流程示意图之十二，如图14所示，在硅基底1的背面1a制备金属电极，其中，包括在第三开口8的位置处透明导电层14上制备收集空穴的金属电极16a，在第四开口13的位置处透明导电层14上制备收集电子的金属电极16b。
在本申请实施中，将硅基底设置电极的一侧作为背面，将与背面相对的一侧作为正面，在背面的背表面场、发射极图形化工艺中，先在背面依次沉积第一钝化层和介质绝缘层，再采用激光消融在第一钝化层和介质绝缘层上形成第一开口暴露硅基底；在背面再制备背表面场层，背表面场包括第二钝化层和电子收集层；采用激光消融在电子收集层上形成第二开口，第二开口与第一开口相间隔；再采用湿法刻蚀在第二钝化层、介质绝缘层和第一钝化层上第二开口的位置处形成第三开口，其中，湿法刻蚀采用的刻蚀剂对第二钝化层、介质绝缘层和第一钝化层的刻蚀速率大于对电子收集层的刻蚀速率，使得包含第二开口的电子收集层在湿法刻蚀第二钝化层、介质绝缘层和第一钝化层的过程中作为掩膜，以在第二开口处形成穿透电子收集层、第二钝化层、介质绝缘层和第一钝化层的第三开口；在背面再制备发射极，发射极包括第三钝化层和空穴收集层，可以采用激光消融在第三钝化层和空穴收集层上第一开口的位置处形成第四开口。在本申请实施中对硅基底的背面发射极和背表面场进行图形化的过程采用了一次湿法刻蚀与多次激光消融，激光消融工艺加工速度快、精度高、成本低、污染小，因此，通过减少实施操作繁琐、成本高、污染大的湿法刻蚀 能够有效简化工艺、降低成本，并提高图形化的精度，降低损伤，从而提高HBC电池的成品质量。
本申请实施例还提供了一种太阳能电池，该太阳能电池包括设置电极的背面，以及与所述背面相对的正面；
所述背面中发射极和背表面场呈叉指状周期性排列，所述背表面场包括SiOx/Poly-Si(n+)层。
可选地，该太阳能电池采用图1至2任一所述的太阳能电池的制备方法制备得到。
在本申请实施中，背表面场中第二钝化层可以是氧化硅SiOx层，电子收集层可以是Poly-Si(n+)层，因而在太阳能电池中电极侧的背表面场采用具有更高电子收集能力的氧化硅钝化层/磷掺杂多晶硅SiOx/Poly-Si(n+)层结构，空穴收集采用本征氢化非晶硅钝化层/硼掺杂氢化非晶硅a-Si:H(i)/a-Si:H(p+)层结构，在此基础上，基于SiOx/Poly-Si(n+)结构背表面场的高载流子选择性与低接触电阻，能够有效提升太阳能电池转换效率。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请实施例并不受所描述的动作顺序的限制，因为依据本申请实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定都是本申请实施例所必须的。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本申请的保护之内。

Claims (10)

  1. 一种太阳能电池的制备方法，其中，所述方法包括：
    提供硅基底，所述硅基底包括设置电极的背面，以及与所述背面相对的正面；
    在所述背面依次沉积第一钝化层和介质绝缘层；
    采用激光消融在所述第一钝化层和所述介质绝缘层上形成第一开口；
    在所述背面制备背表面场，所述背表面场包括第二钝化层和电子收集层；
    采用激光消融在所述电子收集层上形成第二开口，所述第二开口与所述第一开口相间隔；
    采用湿法刻蚀在所述第二钝化层、所述介质绝缘层和所述第一钝化层上所述第二开口的位置处形成第三开口，所述湿法刻蚀采用的刻蚀剂对所述第二钝化层、所述介质绝缘层和所述第一钝化层的刻蚀速率大于对所述电子收集层的刻蚀速率；
    在所述背面制备发射极，所述发射极包括第三钝化层和空穴收集层；
    采用激光消融在所述第三钝化层和空穴收集层上所述第一开口的位置处形成第四开口。
  2. 根据权利要求1所述的方法，其中，所述第四开口的中心位置与所述第一开口的中心位置重叠；
    所述第四开口的宽度小于或等于所述第一开口的宽度，且小于所述第三开口的宽度。
  3. 根据权利要求1所述的方法，其中，所述第二钝化层为SiOx层；
    所述电子收集层为Poly-Si(n+)层。
  4. 根据权利要求1所述的方法，其中，所述第三钝化层为a-Si:H(i)层；
    所述空穴收集层为a-Si:H(p+)层、a-SiOx:H(p+)层、a-SiCx:H(p+)层、a-SiOxCy:H(p+)层中的任一种。
  5. 根据权利要求1所述的方法，其中，所述激光消融包括纳米脉冲激光、皮秒脉冲激光中的任一种；
    所述激光消融的激光波长包括355纳米、532纳米、1064纳米中的任一种。
  6. 根据权利要求1所述的方法，其中，所述第一钝化层的厚度小于50nm；和/或，
    所述介质绝缘层的厚度小于500nm；和/或，
    所述第二钝化层的厚度小于5nm；和/或，
    所述电子收集层的厚度小于500nm；和/或，
    所述第三钝化层的厚度小于50nm；和/或，
    所述空穴收集层的厚度小于100nm。
  7. 根据权利要求1所述的方法，其中，所述在所述背面制备发射极，所述发射极包括第三钝化层和空穴收集层之后，还包括：
    在所述正面依次沉积第四钝化层和防反射层；
    所述采用激光消融在所述第三钝化层和空穴收集层上所述第一开口的位置处形成第四开口之后，还包括：
    在所述背面沉积透明导电层；
    采用激光消融在所述背面的所述第四开口和所述第三开口之间形成第五开口，所述第五开口穿透所述透明导电层且至少部分保留所述介质绝缘层；
    在所述背面制备金属电极。
  8. 根据权利要求7所述的方法，其中，所述第四钝化层的厚度小于20nm；和/或，
    所述防反射层的厚度小于100nm。
  9. 一种太阳能电池，其中，所述太阳能电池包括设置电极的背面，以及与所述背面相对的正面；
    所述背面中发射极和背表面场呈叉指状周期性排列，所述背表面场包括SiOx/Poly-Si(n+)层。
  10. 根据权利要求9所述的太阳能电池，其中，所述太阳能电池采用权利要求1-8任一所述的制备方法制备得到。
PCT/CN2023/078570 2022-03-09 2023-02-28 太阳能电池的制备方法及太阳能电池 WO2023169245A1 (zh)

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