WO2023168817A1 - 存储芯片的测试方法、装置、存储介质与电子设备 - Google Patents

存储芯片的测试方法、装置、存储介质与电子设备 Download PDF

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WO2023168817A1
WO2023168817A1 PCT/CN2022/090619 CN2022090619W WO2023168817A1 WO 2023168817 A1 WO2023168817 A1 WO 2023168817A1 CN 2022090619 W CN2022090619 W CN 2022090619W WO 2023168817 A1 WO2023168817 A1 WO 2023168817A1
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core
test
memory
read
write
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PCT/CN2022/090619
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English (en)
French (fr)
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汪净
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长鑫存储技术有限公司
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Priority to US17/849,729 priority Critical patent/US20230290423A1/en
Publication of WO2023168817A1 publication Critical patent/WO2023168817A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory chip testing method, a memory chip testing device, a computer-readable storage medium, and an electronic device.
  • Memory chips are an integral part of most electronic products. In order to ensure the performance of memory chips after they go online, semiconductor manufacturers often test the memory chips before they leave the factory to detect the performance of the memory chips.
  • DRAM Dynamic Random Access Memory
  • a method for testing a memory chip includes: determining a memory block corresponding to each core in a multi-core processor, and the memory block is composed of a memory chip.
  • a local storage area composed of some storage units in the multi-core processor; perform read and write tests on the corresponding storage blocks through each core in the multi-core processor, and determine the test of the storage chip based on the test results of each storage block obtained by the test result.
  • the memory chip is divided into multiple memory blocks by the following method: according to the storage address of each memory unit in the memory chip, the memory chip is divided into blocks with the same size. Or storage blocks of different sized storage areas.
  • determining the storage block corresponding to each core in the multi-core processor includes: determining each storage block according to the address information of the storage block corresponding to each core in the multi-core processor.
  • the storage block corresponding to the core, the address information includes the storage address of the storage unit included in each storage block in the memory chip; the corresponding storage is performed by each core in the multi-core processor.
  • Performing read and write tests on blocks includes: performing read and write tests on corresponding memory blocks by each core in the multi-core processor, until the read and write tests on all memory blocks in the memory chip are completed, and each The test results of the storage block.
  • the step of using each core in the multi-core processor to respectively perform a read and write test on the corresponding storage block further includes: having each core in the multi-core processor perform a read and write test on the corresponding storage block.
  • the cores simultaneously perform read and write tests on any one or more corresponding storage blocks; or each of the cores in the multi-core processor performs read and write tests on any one or more corresponding storage blocks in sequence.
  • the test results of each memory block include whether a read or write error occurs in the memory unit in the corresponding memory block and the number of address digits at which the read or write error occurs.
  • the test results obtained based on the test Determining the test results of the memory chip based on the test results of each memory block includes: determining the memory unit where the read and write errors occur in the memory chip and the location of the memory unit where the read and write errors occur based on the test results of each memory block. address digits to obtain the test results of the memory chip.
  • the method before performing a read and write test on the corresponding storage block through each core in the multi-core processor, the method further includes: loading and Run the startup loader to activate each core in the multi-core processor, so that when each core is in an activated state, it performs a read and write test on the corresponding storage block; wherein the startup loader runs in a static state Within the random access memory, and when in the activation state, each of the cores runs in the boot loader.
  • the method when performing a read and write test on a corresponding storage block by each core in the multi-core processor, the method further includes: performing a read and write test on each of the storage blocks.
  • the test strategy for each memory block in the memory chip is determined.
  • the test strategy includes a test process for performing data read operations and/or data write operations on each of the memory blocks; from the Each core in the multi-core processor performs a data reading operation and/or a data writing operation on its corresponding storage block according to the test process.
  • the test strategy further includes test data of each test process, and each core in the multi-core processor performs the corresponding testing according to the test process.
  • the storage block performs a data reading operation and/or a data writing operation, and further includes: determining the target test data of the currently executed test process; and performing the data reading and/or data writing operations by each core in the respective corresponding storage block according to the currently executed test process. Data read operations and/or data write operations regarding the target test data.
  • the method further includes: when all cores in the multi-core processor complete read and write tests on their respective corresponding storage blocks according to the currently executed test process, control Each of the cores performs a read and write test on its corresponding storage block according to the next test process.
  • the method further includes: when performing a read and write test on each of the storage blocks, when any one or more cores in the multi-core processor execute according to the current When the test process completes the read and write test of the respective corresponding storage blocks, control the any one or more cores to enter the waiting state and trigger the counter to count; when the number of cores in the multi-core processor is determined according to the counting result of the counter When all cores enter the waiting state, each core in the multi-core processor is reactivated, and each core is controlled to perform a read and write test on its corresponding storage block according to the next test process.
  • the test strategy further includes an operation process of performing a global control operation on the memory unit in the memory chip
  • the method further includes: using any of the multi-core processors.
  • One core performs global control operations on all memory units in the memory chip according to the operation flow of the global control operation; wherein the global control operations include data retention operations and/or on the memory units in the memory chip. or data refresh operation.
  • the method further includes: when any one or more memory blocks are not tested, monitoring the test progress of each core, and utilizing the already completed memory blocks in the multi-core processor.
  • the core that completes the test performs a read and write test on any one of the one or more memory blocks until the read and write test on all memory blocks in the memory chip is completed.
  • the memory chip includes a dynamic random access memory.
  • a memory chip testing device includes: a determination module for determining a storage block corresponding to each core in a multi-core processor, where the storage block is partially stored in the memory chip.
  • a local storage area composed of units; a test module, used to perform read and write tests on the corresponding storage blocks through each core in the multi-core processor, and determine the memory chip based on the test results of each storage block obtained by the test test results.
  • the determination module divides the memory chip into multiple memory blocks by performing the following method: according to the storage address of each memory unit in the memory chip, divide the memory chip into Storage blocks divided into storage areas of the same size or different sizes.
  • the determining module is configured to determine the storage block corresponding to each core in the multi-core processor according to the address information of the storage block corresponding to each core, so The address information includes the storage address of the storage unit contained in each of the storage blocks in the memory chip; the test module is used to perform read and write tests on the corresponding storage blocks by each of the cores in the multi-core processor. , until the read and write test of all memory blocks in the memory chip is completed, and the test results of each memory block are obtained.
  • the test module is also configured to simultaneously perform read and write tests on any one or more corresponding memory blocks by each core in the multi-core processor; or by Each core in the multi-core processor sequentially performs read and write tests on any one or more corresponding storage blocks.
  • the test results of each memory block include whether a read or write error occurs in the memory unit in the corresponding memory block and the number of address digits at which the read or write error occurs.
  • the test module also uses Determine the memory unit where a read or write error occurs in the memory chip and the number of address bits of the memory unit where the read or write error occurs based on the test results of each of the memory blocks to obtain the test result of the memory chip.
  • the test module before performing a read and write test on the corresponding storage block through each core in the multi-core processor, is also configured to load the data through the multi-core processor. and run the startup loader to activate each core in the multi-core processor, so that each core can perform read and write tests on the corresponding storage block when it is in the activated state; wherein the startup loader runs on In the static random access memory, and when in the activation state, each of the cores runs in the boot loader.
  • the testing module when performing a read and write test on a corresponding storage block by each core in the multi-core processor, is also configured to perform a read/write test on each of the storage blocks.
  • a test strategy for each memory block in the memory chip is determined.
  • the test strategy includes a test process for performing a data read operation and/or a data write operation on each of the memory blocks.
  • Each core in the multi-core processor performs a data reading operation and/or a data writing operation on its corresponding storage block according to the testing process.
  • the test strategy also includes test data of each test process, and the test module is also used to determine the target test data of the currently executed test process; by each of the cores Data reading operations and/or data writing operations on the target test data are performed in respective corresponding storage blocks according to the currently executed test process.
  • the test module is also configured to complete the read and write tests on respective corresponding storage blocks when all cores in the multi-core processor complete the read and write tests on their respective corresponding storage blocks according to the currently executed test process. Control each core to perform a read and write test on its corresponding storage block according to the next test process.
  • the test module is also used to perform a read and write test on each of the storage blocks.
  • any one or more cores in the multi-core processor perform the current
  • any one or more cores are controlled to enter the waiting state and trigger counting by the counter.
  • it is determined according to the counting result of the counter When all the cores enter the waiting state, each core in the multi-core processor is reactivated, and each core is controlled to perform a read and write test on its corresponding storage block according to the next test process.
  • the test strategy also includes an operation process of performing global control operations on the memory units in the memory chip, and the test module is also used to control the memory unit in the multi-core processor.
  • Any core performs global control operations on all storage units in the memory chip according to the operation flow of the global control operation; wherein the global control operations include data retention operations on the storage units in the memory chip and /or data refresh operation.
  • the test module is also configured to monitor the test progress of each core when any one or more memory blocks are not tested, and utilize the multi-core processor to The core that has completed the test performs a read and write test on any one of the one or more memory blocks until the read and write test on all memory blocks in the memory chip is completed.
  • the memory chip includes a dynamic random access memory.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, any one of the above memory chip testing methods is implemented.
  • an electronic device including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the operation via executing the executable instructions. Perform any of the above memory chip testing methods.
  • Figure 1 shows a flow chart of a method for testing a memory chip in this exemplary embodiment
  • Figure 2 shows an example of a method for determining storage blocks in this exemplary embodiment
  • Figure 3 shows a sub-flow chart of a method for testing a memory chip in this exemplary embodiment
  • Figure 4 shows a structural block diagram of a memory chip testing device in this exemplary embodiment
  • Figure 5 shows a computer-readable storage medium for implementing the above method in this exemplary embodiment
  • FIG. 6 shows an electronic device for implementing the above method in this exemplary embodiment.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • Exemplary embodiments of the present disclosure first provide a method for testing a memory chip.
  • This method can use multiple cores of a multi-core processor to separately perform read and write tests on local storage areas in the memory chip to detect the read and write of the memory chip. performance, while achieving flexible testing of memory chips and improving the testing efficiency of memory chips.
  • the memory chip may be a dynamic random access memory, that is, DRAM.
  • the memory chip is a semiconductor memory and may include multiple memory units, where the memory unit is a memory chip equipped with the ability to store data and From the structural point of view of the unit with data reading and writing functions, a memory unit can be composed of a transistor and a capacitor. By controlling the amount of charge stored in the capacitor, it can represent whether a binary bit is 0 or 1.
  • a memory chip can include multiple memory cells, and the multiple memory cells can be arranged in any shape, such as a memory array in any shape.
  • Figure 1 shows a process of this exemplary embodiment, which may include the following steps S110 to S120:
  • Step S110 Determine the storage block corresponding to each core in the multi-core processor.
  • the memory block refers to a local storage area composed of some memory units in the memory chip. For multiple memory blocks, the number of memory units included in each memory block may be the same or different.
  • Multi-core processors refer to the integration of two or more complete computing engines, or cores, into one processor. At this time, the processor can support multiple processors on the system bus, and the bus controller provides all bus control signals and command signal. Multi-core processors can decompose the tasks to be processed into multiple parts, and assign each part to different core registers for multiple operators to operate together. The operation results are summarized and processed by one operator and distributed to the next step. Alternatively, each operation result can be directly sent to the next step under program control.
  • the memory chip may be divided into multiple memory blocks.
  • the memory block corresponding to each core may first be determined. For example, as shown in Figure 2, CPU1, CPU2, CPU3...CPUN, CPUa and CPUb are different cores respectively.
  • each memory block in the memory chip is divided into multi-core processors.
  • the memory block corresponding to CPU1 is memory block 1.
  • the memory blocks corresponding to the cores are different from each other.
  • the memory block corresponding to each core can be determined, that is, a unit combination composed of multiple memory units, achieving effective grouping of memory units and helping to improve the testing flexibility of memory chips.
  • the memory chip is divided into memory blocks with storage areas of the same size or different sizes.
  • the storage address is the number of the storage unit in the memory chip, and this number can uniquely identify a storage unit.
  • the storage unit in the memory chip can be divided into multiple storage blocks.
  • the size of each storage block can be arbitrary, and in each storage block, between each storage unit They can be adjacent or non-adjacent.
  • X memory units with consecutive storage addresses can be divided into one storage block according to the storage address of each storage unit.
  • the memory chip can be divided into multiple storage blocks according to the continuity of the storage addresses.
  • X is a positive integer.
  • each row of memory units or each column of memory units with the same row address or column address can also be divided into a memory block according to the storage address of each memory unit, that is, according to the rows and columns of the memory cells constituting the memory array in the memory chip.
  • Relationships divide a storage unit into storage blocks. By dividing the storage unit of the memory chip into multiple storage blocks, any grouping of storage units can be completed, and the grouping rules can be customized by testers, which can meet a variety of different testing and grouping needs and has high flexibility.
  • the address information of the storage block corresponding to each core in the multi-core processor can be determined. corresponding storage block.
  • the address information of the memory block may include the memory address of the memory unit included in each memory block of the memory chip.
  • the storage blocks corresponding to each core can be determined sequentially according to the address order of the storage blocks.
  • the memory block corresponding to each core can be determined to be composed of Storage area, that is to say, one core corresponds to X storage units, and the storage units in the storage blocks corresponding to each core are not repeated.
  • the tester can pre-configure the address correspondence between each core and the storage block. For example, the tester can establish a configuration table in advance based on the address correspondence between the core and the storage block. After determining each When the memory block corresponding to the core is determined, the memory block corresponding to each core and the storage address of the memory unit in the memory block can be determined according to the configuration table, so that the memory block corresponding to each core can be found in the memory chip.
  • the storage unit in the storage block corresponding to each core is unique, that is, any two storage units
  • There is no duplication of storage units in the block which can avoid the problem of low test efficiency caused by testing repeated units, as well as the problem of test disorder, which affects the test results.
  • Step S120 Perform a read and write test on the corresponding memory block through each core in the multi-core processor, and determine the test result of the memory chip based on the test results of each memory block obtained by the test.
  • the read and write test refers to fully writing or reading all the memory cells of the memory chip to be tested, or traversing according to the method of reading first and then writing or other different read/write combinations; the test results are used to characterize each memory unit. Whether a read or write error occurs, such as whether there is a storage unit where data cannot be written normally or the read data is inconsistent with the written data.
  • each core After determining the storage blocks corresponding to each core, each core can be used to perform read and write tests on its corresponding storage blocks. Each core determines the test results of its corresponding storage blocks. Then the multi-core processor can perform the test results of each storage block. The test results are analyzed and processed, such as statistics, deduplication, etc., to determine the test results of the memory chip. In this way, multi-core processors can run multiple cores at the same time to perform test tasks, so the testing efficiency of memory chips can be significantly improved.
  • step S120 the following method may also be performed:
  • the boot loader program is the BootLoader program. This program is the first piece of code executed by the embedded system after power-on.
  • the BootLoader program can initialize the hardware devices and establish the mapping table of the memory space, that is, build the appropriate system software and hardware environment for Call each core in a multi-core processor to prepare.
  • the boot loader may run in static random access memory, and each core runs in the boot loader when active. That is to say, in the activated state, each core performs the test task of the storage block respectively. At this time, each core is running in the boot loader.
  • static random access memory also known as SRAM (Static Random-Access Memory)
  • SRAM Static Random-Access Memory
  • the multi-core processor can be used to load and run the boot loader to complete the boot process and activate each core in the multi-core processor to complete the storage chip.
  • Multi-core scheduling of test tasks allows each core to perform read and write tests on the corresponding storage blocks in the active state. Since each core runs in the boot loader of SRAM when performing test tasks, it does not occupy the memory space of the memory chip. Therefore, it can meet the comprehensive testing requirements of the memory chip and improve the testing efficiency of the memory chip.
  • each core can be used to complete processing tasks independently. Therefore, in order to implement the read and write test of each storage block, in an optional implementation, the following method can be performed to implement each storage block.
  • Block read and write test :
  • Each core in the multi-core processor performs a read and write test on the corresponding memory block respectively until the read and write test on all memory blocks in the memory chip is completed, and the test results of each memory block are obtained.
  • Each core performs read and write tests on its corresponding storage blocks. For example, a certain number of cores can be controlled to perform read and write tests on their corresponding storage blocks at the same time. After the read and write tests are completed, each core can get the test results of the memory block it tested. At the same time, when one core corresponds to two or more storage blocks, the core can perform read and write tests on each of its associated storage blocks in sequence until the test of all storage blocks corresponding to the core is completed.
  • the cores in the multi-core processor can be controlled to test the memory blocks according to established rules, which can meet different testing requirements.
  • Each core in the multi-core processor performs read and write tests on any one or more corresponding storage blocks at the same time; or each core in the multi-core processor performs read and write tests on any one or more corresponding storage blocks in sequence. .
  • each core When each core performs read and write tests on different storage blocks at the same time, each core executes the test program on different storage blocks at the same time. In this way, each core runs in parallel, so the processing performance of the multi-core processor can be maximized and improved.
  • the test efficiency of memory chips when each core performs read and write tests on different memory blocks in turn, each core executes the test program on different memory blocks in turn.
  • This method can realize asynchronous operation of the cores and give full play to the capabilities of the multi-core processor.
  • the processing flexibility of the core For example, at the current moment, one core can execute the write test process and the other core can execute the read test process.
  • the multi-core processor can be controlled to perform read and write tests on the storage blocks according to different operating modes, which has high flexibility.
  • the testing methods of each storage block may be the same or different.
  • the testing method of a certain storage block may be expressed as a testing algorithm primitive: (w), (r, w), (r), (w), (r, w, r), (r), this method requires traversing the memory unit of the memory chip 6 times.
  • the test method of another memory block can be the test algorithm primitive: (w, r), ( w), (r), (w), this method only needs to traverse the memory cells of the memory chip 4 times.
  • (w) or (r) represents writing or reading operations on all memory cells of the memory chip
  • (r, w) represents the size of one access, such as 1 byte, 4 bytes, 8 bytes
  • the operation of reading first and then writing is performed on the storage unit of the memory chip to traverse all the storage units of the memory chip.
  • (r, w, r) means that the storage unit of the memory chip is read first, then written and then read according to the size of one access. operation to traverse all memory cells of the memory chip.
  • the data written twice can be the same or different.
  • Step S310 When performing read and write tests on each memory block, determine the test strategy for each memory block in the memory chip.
  • the test strategy may include a test process of performing data reading operations and/or data writing operations on each storage block.
  • the test process refers to the stage of performing data read and write operations on each storage block. Data read and write operations on the same test data can be regarded as a test process, or any data read operation or data write operation can be regarded as A testing process.
  • the test process may include the order and frequency of data reading and writing operations on each storage block.
  • the test strategy can also include test parameters when performing a data read operation or a data write operation, such as the voltage value of the control signal, etc.
  • the test process for each storage block can be determined in advance. For example, the operation steps that need to be performed for each storage block and the order of each operation step can be searched and determined based on the preconfigured test rule table.
  • Step S320 Each core in the multi-core processor performs a data reading operation and/or a data writing operation on its corresponding storage block according to the test process.
  • the multi-core processor can control each core to read and write data to its corresponding storage block according to a unified testing process. Through this method, it can be ensured that each storage block is tested using a unified test process to ensure the consistency, comprehensiveness and accuracy of the test. At the same time, because the test process can be configured by the tester, it can also improve the flexibility of the test. and convenience.
  • test strategy may also include various
  • step S320 can also be implemented through the following methods:
  • Each core performs a data reading operation and/or a data writing operation on the target test data in its corresponding storage block.
  • Test data refers to the write data set to test the read and write functions of the storage unit. Since the memory chip stores data in binary form, the test data can also be any binary sequence.
  • the target test data refers to the test data that needs to be read or written in the currently executed data reading operation or data writing operation.
  • the multi-core processor can control each core to perform a test task on the corresponding storage block.
  • each core can determine the currently executed test process, that is, data reading operation and/or data writing.
  • the corresponding target test data is operated, so that each core writes the target test data into or reads the target test data from its corresponding storage block.
  • the correctness of data writing in each test stage can be ensured.
  • it can also be determined based on the read data and test data whether the read data is correct, which can improve Determine the efficiency of test results, and testers can also set different test data for different test stages to meet the testing needs of each stage.
  • all cores in the multi-core processor can also complete the corresponding storage blocks according to the currently executed test process.
  • each core is controlled to perform read and write tests on its corresponding storage blocks according to the next test process.
  • each core executes each test process in sequence. Only when each core completes the current test process for each storage block, the next test process will be executed for each storage block. Therefore, testing errors can be avoided to a certain extent.
  • each core may be executing different test processes at the same time, resulting in test errors of storage blocks. Therefore, in order to achieve synchronous testing of each core, in an optional implementation, the following method can also be performed:
  • each core in the multi-core processor is reactivated, and each core is controlled to perform read and write tests on its corresponding storage blocks according to the next test process.
  • the core does not perform test tasks. For example, when a multi-core processor controls each core to start testing its corresponding storage block, each core is activated one by one, and the count continues to increase by 1. When the value of count is equal to the total number of activated cores, all cores enter the waiting state. That is, core synchronization is completed, and then the multi-core processor can control the activated core to execute the test process of the respective storage block according to the corresponding storage block allocation rules. When a core completes the currently executed test process, the multi-core processor can control the core to enter Waiting state, while the counter can count, such as count minus 1. As other cores gradually complete the currently executed test process, the trigger counter will continue to be decremented by 1 until it is cleared.
  • the multi-core processor can control each core to execute the next test process on its corresponding storage block. This method can ensure that the core can complete the test process within the specified limits, ensure the synchronization of the core execution test process, prevent the disorder of the test process from causing false errors in test results, avoid misjudgments, and improve test accuracy.
  • the test strategy may also include global control operations on the memory cells in the memory chip.
  • the global control operation is a non-access operation performed on the memory chip, which may include a data retention operation and/or a data refresh operation performed on the memory unit in the memory chip.
  • the data retention operation refers to controlling the data written to the memory chip to be retained for a period of time to ensure that the written data will not change unexpectedly due to factors such as time or leakage;
  • the data refresh operation refers to the high-speed operation of the memory unit.
  • the potential capacitor performs a periodic charging operation. This operation can maintain the stability of the high-potential capacitor so that it can continue to store data.
  • the data refresh operation can include a self-refresh operation or a controller-controlled refresh operation.
  • any core in the multi-core processor can also perform global control operations on all memory units in the memory chip according to the operation flow of the global control operation. For example, after completing any one or more test processes, the multi-core processor can control the core that finally completed the test process to perform data retention operations and data refresh operations on all memory cells in the memory chip. The execution time of this operation can be determined by the test Personnel are preset. By performing global control operations, the continuous storage of data can be ensured during the read and write test of the memory chip, thereby avoiding the impact of external factors on subsequent test results.
  • one core can correspond to one or more memory blocks.
  • the completion of the read and write test by all cores means that the entire test task is over.
  • the completion of the read and write test by all cores allocated memory blocks also means that the entire test task is over.
  • the number of cores N in the multi-core processor is less than the number of memory blocks M, when all cores complete the read and write test, there are still remaining memory blocks in the memory chip. At this time, in order to complete the read and write test of the remaining memory blocks, In an optional implementation, the following method can also be performed:
  • the multi-core processor can detect the storage blocks that have not been tested, thereby using the cores that have completed the test to The tested memory block is expanded for read and write tests.
  • CPUa is the core that completes the test first
  • CPUa can be used to first Perform read and write tests on N+1 storage blocks, monitor the test progress of all cores at the same time, and then use the latest core CPUb that has completed the read and write tests to perform read and write tests on the N+2th storage block until all storage blocks are read and written. test.
  • test results of the memory block it tested can be obtained.
  • the test results of each memory block are The test results can include whether a read or write error occurs in the memory unit in the corresponding memory block and the number of address bits where the read or write error occurs. Therefore, the test results of the memory chip can be obtained by the following methods:
  • the memory unit in the memory chip where the read and write errors occurred and the number of address digits of the memory unit where the read and write errors occurred are determined to obtain the test results of the memory chip.
  • the memory block corresponding to each core in the multi-core processor can be determined, and the corresponding memory block can be read and written through each core in the multi-core processor, and The test results of the memory chip are determined based on the test results of each memory block obtained by the test.
  • This solution divides the storage unit in the memory chip into multiple storage blocks and assigns them to different cores of the multi-core processor. It uses each core to perform read and write tests on the corresponding storage blocks, which can fully utilize the processing performance of the multi-core processor. Improve the testing efficiency of memory chips.
  • the memory chip testing device 400 may include: a determination module 410, which may be used to determine the memory block corresponding to each core in the multi-core processor.
  • the storage block is a local storage area composed of some storage units in the memory chip;
  • the test module 420 can be used to perform read and write tests on the corresponding storage blocks through each core in the multi-core processor, and based on the test results of each storage block The test results determine the test results of the memory chip.
  • the determination module 410 divides the memory chip into multiple memory blocks by performing the following method: according to the storage address of each memory unit in the memory chip, divide the memory chip into blocks with the same size or different sizes. The size of the storage area of the storage block.
  • the determining module 410 may be used to determine the storage block corresponding to each core in the multi-core processor according to the address information of the storage block corresponding to each core in the multi-core processor.
  • the address information includes each core in the memory chip.
  • the storage address of the storage unit contained in the storage block; the test module 420 can be used to perform read and write tests on the corresponding storage blocks by each core in the multi-core processor until the read and write tests on all storage blocks in the memory chip are completed. Get the test results of each storage block.
  • the test module 420 can also be used to simultaneously perform read and write tests on any one or more corresponding memory blocks by each core in the multi-core processor; or by using the core in the multi-core processor. Each core in turn performs read and write tests on any one or more corresponding storage blocks.
  • the test results of each storage block include whether a read or write error occurs in the storage unit in the corresponding storage block and the number of address digits in which the read or write error occurs.
  • the test module 420 can also be used to determine whether a read or write error occurs in the memory unit in the corresponding storage block.
  • the test results of each memory block determine the memory unit in the memory chip where the read and write errors occurred and the number of address bits in the memory unit where the read and write errors occurred, to obtain the test results of the memory chip.
  • the test module 420 before performing read and write tests on the corresponding storage blocks through each core in the multi-core processor, can also be used to load and run the boot loader through the multi-core processor, Activate each core in the multi-core processor so that when each core is in the activated state, it performs a read and write test on the corresponding storage block; wherein, the boot loader runs in the static random access memory, and when it is in the activated state, Each core runs in the boot loader.
  • the test module 420 when performing a read and write test on a corresponding storage block through each core in a multi-core processor, the test module 420 may also be used to perform a read and write test on each storage block, Determine the test strategy for each memory block in the memory chip.
  • the test strategy includes the test process of performing data reading operations and/or data writing operations on each memory block.
  • Each core in the multi-core processor performs testing on its corresponding storage according to the testing process.
  • Block performs data read operations and/or data write operations.
  • the test strategy also includes test data of each test process
  • the test module 420 can also be used to determine the target test data of the currently executed test process; each core performs the test process according to the currently executed test process. Data reading operations and/or data writing operations on the target test data are performed in respective corresponding storage blocks.
  • the test module 420 can also be used to control each core in the multi-core processor to complete the read and write test of its corresponding storage block according to the currently executed test process. The next test process performs read and write tests on the corresponding storage blocks.
  • the test module 420 can also be used to perform read and write tests on each storage block when any one or more cores in the multi-core processor complete the test process according to the currently executed test process.
  • any one or more cores are controlled to enter the waiting state, and a counter is triggered to count.
  • a counter is triggered to count.
  • each core in the multi-core processor is reactivated, and each core is controlled to perform read and write tests on its corresponding storage blocks according to the next test process.
  • the test strategy also includes an operation process of performing a global control operation on the memory unit in the memory chip.
  • the test module 420 can also be used to control any core in the multi-core processor according to the global control operation.
  • the operation flow of the operation is to perform global control operations on all memory cells in the memory chip; where the global control operations include data retention operations and/or data refresh operations on the memory cells in the memory chip.
  • the test module 420 can also be used to monitor the test progress of each core when any one or more memory blocks are not tested, and utilize the test results of the multi-core processor that have completed the test.
  • the core performs read and write tests on any one or more memory blocks until the read and write tests on all memory blocks in the memory chip are completed.
  • a memory chip includes a dynamic random access memory.
  • Exemplary embodiments of the present disclosure also provide a computer-readable storage medium on which a program product capable of implementing the method described above in this specification is stored.
  • various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code.
  • the program product is run on a terminal device, the program code is used to cause the terminal device to execute the above described instructions.
  • the steps according to various exemplary embodiments of the present disclosure are described in the "Exemplary Methods" section.
  • a program product 500 for implementing the above method according to an exemplary embodiment of the present disclosure is described. It can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be used on a terminal. device, such as a personal computer.
  • CD-ROM compact disk read-only memory
  • the program product of the present disclosure is not limited thereto.
  • a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.
  • Program product 500 may take the form of any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a readable signal medium may also be any readable medium other than a readable storage medium that can send, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., as well as conventional procedural programming. Language—such as "C” or a similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., provided by an Internet service). (business comes via Internet connection).
  • LAN local area network
  • WAN wide area network
  • Internet service e.g., provided by an Internet service
  • Exemplary embodiments of the present disclosure also provide an electronic device capable of implementing the above method.
  • An electronic device 600 according to such an exemplary embodiment of the present disclosure is described below with reference to FIG. 6 .
  • the electronic device 600 shown in FIG. 6 is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.
  • electronic device 600 may take the form of a general-purpose computing device.
  • the components of the electronic device 600 may include, but are not limited to: the above-mentioned at least one processing unit 610, the above-mentioned at least one storage unit 620, a bus 630 connecting different system components (including the storage unit 620 and the processing unit 610), and the display unit 640.
  • the storage unit 620 stores program code, and the program code can be executed by the processing unit 610, so that the processing unit 610 performs the steps according to various exemplary embodiments of the present disclosure described in the "Exemplary Method" section of this specification.
  • the processing unit 610 may perform the method steps shown in FIGS. 1 and 3 , etc.
  • the storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 621 and/or a cache storage unit 622, and may further include a read-only storage unit (ROM) 623.
  • RAM random access storage unit
  • ROM read-only storage unit
  • Storage unit 620 may also include a program/utility 624 having a set of (at least one) program modules 625 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • program/utility 624 having a set of (at least one) program modules 625 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • Bus 630 may be a local area representing one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or using any of a variety of bus structures. bus.
  • Electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboard, pointing device, Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with electronic device 600, and/or with Any device (eg, router, modem, etc.) that enables the electronic device 600 to communicate with one or more other computing devices. This communication may occur through input/output (I/O) interface 650.
  • the electronic device 600 may also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through the network adapter 660. As shown, network adapter 660 communicates with other modules of electronic device 600 via bus 630.
  • network adapter 660 communicates with other modules of electronic device 600 via bus 630.
  • modules or units of equipment for action execution are mentioned in the above detailed description, this division is not mandatory.
  • the features and functions of two or more modules or units described above may be embodied in one module or unit.
  • the features and functions of one module or unit described above may be further divided into being embodied by multiple modules or units.
  • the exemplary embodiments described here can be implemented by software or by software combined with necessary hardware. Therefore, the technical solution according to the exemplary embodiments of the present disclosure can be embodied in the form of a software product, and the software product can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.) or On the network, several instructions are included to cause a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the exemplary embodiments of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, or a network device, etc.

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Abstract

一种存储芯片的测试方法、存储芯片的测试装置、计算机可读存储介质与电子设备，属于半导体技术领域。所述方法包括：确定多核处理器中各核心对应的存储块（S110），所述存储块为由存储芯片中部分存储单元构成的局部存储区域；通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果（S120）。提高了多核处理器的利用率，提高了存储芯片的测试效率。

Description

存储芯片的测试方法、装置、存储介质与电子设备
相关申请的交叉引用
本申请要求于2022年03月11日提交的申请号为202210237604.2、名称为“存储芯片的测试方法、装置、存储介质与电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种存储芯片的测试方法、存储芯片的测试装置、计算机可读存储介质与电子设备。
背景技术
存储芯片是大多数电子产品的构成要件。为了保证存储芯片在上线后的使用性能，半导体制造厂商往往要在存储芯片出厂前进行测试，来检测存储芯片的使用性能。
目前，为了提高DRAM(Dynamic Random Access Memory，动态随机存取存储器)等存储芯片的测试效率，制造厂商通常会选择多任务操作系统环境来进行测试，但是由于操作系统是运行在DRAM中的，因而本身会占用一部分存储空间，而这一部分无法被测试到，导致整个存储芯片的测试全面性不足。
发明内容
根据本公开的第一方面，根据本公开的第一方面，提供一种存储芯片的测试方法，所述方法包括：确定多核处理器中各核心对应的存储块，所述存储块为由存储芯片中部分存储单元构成的局部存储区域；通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果。
在本公开的一种示例性实施方式中，通过以下方法将所述存储芯片划分为多个存储块：按照所述存储芯片中各存储单元的存储地址，将所述存储芯片划分为具有相同大小或不同大小的存储区域的存储块。
在本公开的一种示例性实施方式中，所述确定多核处理器中各核心对应的存储块，包括：根据所述多核处理器中各所述核心所对应的存储块的地址信息，确定各所述核心所对应的存储块，所述地址信息包括所述存储芯片中各所述存储块包含的存储单元的存储地址；所述通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，包括：由所述多核处理器中的各所述核心分别对相应的存储块进行读写测试，直至完成对所述存储芯片中的全部存储块的读写测试，得到各所述存储块的测试结果。
在本公开的一种示例性实施方式中，所述由所述多核处理器中的各所述核心分别对相应的存储块进行读写测试，还包括：由所述多核处理器中的各所述核心同时对各自对应的任意一个或多个存储块进行读写测试；或者由所述多核处理器中的各所述核心依次对各自对应的任意一个或多个存储块进行读写测试。
在本公开的一种示例性实施方式中，各所述存储块的测试结果包括对应的存储块中的存储单元是否发生读写错误和发生读写错误的地址位数，所述依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果，包括：依据各所述存储块的测试结果确定所述存储芯片中发生读写错误的存储单元和所述发生读写错误的存储单元的地址位数，以得到所述存储芯片的测试结果。
在本公开的一种示例性实施方式中，在通过所述多核处理器中的各所述核心对相应的存储块进行读写测试前，所述方法还包括：通过所述多核处理器加载和运行启动装载程序，激活所述多核处理器中的各所述核心，以使各所述核心在处于激活状态时，对相应的存储块进行读写测试；其中，所述启动装载程序运行于静态随机存取存储器内，且在处于所述 激活状态时，各所述核心运行于所述启动装载程序中。
在本公开的一种示例性实施方式中，在通过所述多核处理器中的各所述核心对相应的存储块进行读写测试时，所述方法还包括：在对各所述存储块进行读写测试时，确定所述存储芯片中各所述存储块的测试策略，所述测试策略包括对各所述存储块进行数据读取操作和/或数据写入操作的测试流程；由所述多核处理器中的各所述核心按照所述测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作。
在本公开的一种示例性实施方式中，所述测试策略还包括各所述测试流程的测试数据，所述由所述多核处理器中的各所述核心按照所述测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作，还包括：确定当前执行的测试流程的目标测试数据；由各所述核心按照所述当前执行的测试流程在各自对应的存储块中进行关于所述目标测试数据的数据读取操作和/或数据写入操作。
在本公开的一种示例性实施方式中，所述方法还包括：在所述多核处理器中的全部核心按照所述当前执行的测试流程完成对各自对应的存储块的读写测试时，控制各所述核心按照下一测试流程对各自对应的存储块进行读写测试。
在本公开的一种示例性实施方式中，所述方法还包括：在对各所述存储块进行读写测试时，当所述多核处理器中的任意一个或多个核心按照所述当前执行的测试流程完成对各自对应的存储块的读写测试时，控制所述任意一个或多个核心进入等待状态，并触发计数器计数；当根据所述计数器的计数结果确定所述多核处理器中的全部核心进入所述等待状态时，重新激活所述多核处理器中的各所述核心，并控制各所述核心按照所述下一测试流程对各自对应的存储块进行读写测试。
在本公开的一种示例性实施方式中，所述测试策略还包括对所述存储芯片中的存储单元进行全局控制操作的操作流程，所述方法还包括：由所述多核处理器中的任意一个核心按照所述全局控制操作的操作流程对所述存储芯片中的全部存储单元进行全局控制操作；其中，所述全局控制操作包括对所述存储芯片中的存储单元进行的数据保持操作和/或数据刷新操作。
在本公开的一种示例性实施方式中，所述方法还包括：当存在任意一个或多个存储块未进行测试时，监测各所述核心的测试进度，并利用所述多核处理器中已完成测试的核心对所述任意一个或多个存储块中的任意一个存储块进行读写测试，直至完成对所述存储芯片中的全部存储块的读写测试。
在本公开的一种示例性实施方式中，所述存储芯片包括动态随机存取存储器。
根据本公开的第二方面，提供一种存储芯片的测试装置，所述装置包括：确定模块，用于确定多核处理器中各核心对应的存储块，所述存储块为由存储芯片中部分存储单元构成的局部存储区域；测试模块，用于通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果。
在本公开的一种示例性实施方式中，所述确定模块通过执行以下方法将所述存储芯片划分为多个存储块：按照所述存储芯片中各存储单元的存储地址，将所述存储芯片划分为具有相同大小或不同大小的存储区域的存储块。
在本公开的一种示例性实施方式中，所述确定模块用于根据所述多核处理器中各所述核心所对应的存储块的地址信息，确定各所述核心所对应的存储块，所述地址信息包括所述存储芯片中各所述存储块包含的存储单元的存储地址；所述测试模块用于由所述多核处理器中的各所述核心分别对相应的存储块进行读写测试，直至完成对所述存储芯片中的全部存储块的读写测试，得到各所述存储块的测试结果。
在本公开的一种示例性实施方式中，所述测试模块还用于由所述多核处理器中的各所述核心同时对各自对应的任意一个或多个存储块进行读写测试；或者由所述多核处理器中的各所述核心依次对各自对应的任意一个或多个存储块进行读写测试。
在本公开的一种示例性实施方式中，各所述存储块的测试结果包括对应的存储块中的存储单元是否发生读写错误和发生读写错误的地址位数，所述测试模块还用于依据各所述存储块的测试结果确定所述存储芯片中发生读写错误的存储单元和所述发生读写错误的存储单元的地址位数，以得到所述存储芯片的测试结果。
在本公开的一种示例性实施方式中，在通过所述多核处理器中的各所述核心对相应的存储块进行读写测试前，所述测试模块还用于通过所述多核处理器加载和运行启动装载程序，激活所述多核处理器中的各所述核心，以使各所述核心在处于激活状态时，对相应的存储块进行读写测试；其中，所述启动装载程序运行于静态随机存取存储器内，且在处于所述激活状态时，各所述核心运行于所述启动装载程序中。
在本公开的一种示例性实施方式中，在通过所述多核处理器中的各所述核心对相应的存储块进行读写测试时，所述测试模块还用于在对各所述存储块进行读写测试时，确定所述存储芯片中各所述存储块的测试策略，所述测试策略包括对各所述存储块进行数据读取操作和/或数据写入操作的测试流程，由所述多核处理器中的各所述核心按照所述测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作。
在本公开的一种示例性实施方式中，所述测试策略还包括各所述测试流程的测试数据，所述测试模块还用于确定当前执行的测试流程的目标测试数据；由各所述核心按照所述当前执行的测试流程在各自对应的存储块中进行关于所述目标测试数据的数据读取操作和/或数据写入操作。
在本公开的一种示例性实施方式中，所述测试模块还用于在所述多核处理器中的全部核心按照所述当前执行的测试流程完成对各自对应的存储块的读写测试时，控制各所述核心按照下一测试流程对各自对应的存储块进行读写测试。
在本公开的一种示例性实施方式中，所述测试模块还用于在对各所述存储块进行读写测试时，当所述多核处理器中的任意一个或多个核心按照所述当前执行的测试流程完成对各自对应的存储块的读写测试时，控制所述任意一个或多个核心进入等待状态，并触发计数器计数，当根据所述计数器的计数结果确定所述多核处理器中的全部核心进入所述等待状态时，重新激活所述多核处理器中的各所述核心，并控制各所述核心按照所述下一测试流程对各自对应的存储块进行读写测试。
在本公开的一种示例性实施方式中，所述测试策略还包括对所述存储芯片中的存储单元进行全局控制操作的操作流程，所述测试模块还用于由所述多核处理器中的任意一个核心按照所述全局控制操作的操作流程对所述存储芯片中的全部存储单元进行全局控制操作；其中，所述全局控制操作包括对所述存储芯片中的存储单元进行的数据保持操作和/或数据刷新操作。
在本公开的一种示例性实施方式中，所述测试模块还用于当存在任意一个或多个存储块未进行测试时，监测各所述核心的测试进度，并利用所述多核处理器中已完成测试的核心对所述任意一个或多个存储块中的任意一个存储块进行读写测试，直至完成对所述存储芯片中的全部存储块的读写测试。
在本公开的一种示例性实施方式中，所述存储芯片包括动态随机存取存储器。
根据本公开的第三方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述任意一种存储芯片的测试方法。
根据本公开的第四方面，提供一种电子设备，包括：处理器；以及存储器，用于存储所述处理器的可执行指令；其中，所述处理器配置为经由执行所述可执行指令来执行上述任意一种存储芯片的测试方法。
附图说明
图1示出本示例性实施方式中一种存储芯片的测试方法的流程图；
图2示出本示例性实施方式中一种确定存储块的方法示例；
图3示出本示例性实施方式中一种存储芯片的测试方法的子流程图；
图4示出本示例性实施方式中一种存储芯片的测试装置的结构框图；
图5示出本示例性实施方式中一种用于实现上述方法的计算机可读存储介质；
图6示出本示例性实施方式中一种用于实现上述方法的电子设备。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。另外，下面所有的术语“第一”、“第二”、“第三”仅是为了区分的目的，不应作为本公开内容的限制。
本公开的示例性实施方式首先提供了一种存储芯片的测试方法，该方法可以利用多核处理器的多个核心分别对存储芯片中的局部存储区域进行读写测试，来检测存储芯片的读写性能，同时实现存储芯片的灵活测试，提高存储芯片的测试效率。本示例性实施方式中，存储芯片可以是动态随机存取存储器，即也就是DRAM，该存储芯片是一种半导体存储器，可以包括多个存储单元，其中，存储单元是存储芯片中具备存储数据和数据读写功能的单元，从构成结构来看，一个存储单元可以由一个晶体管和一个电容组成，通过控制电容内存储的电荷数量的多寡可以代表一个二进制比特是0还是1。一般而言，存储芯片中可以包括多个存储单元，且多个存储单元可以排布为任意形状，比如可以排布为任意形状的存储阵列。
图1示出了本示例性实施方式的一种流程，可以包括以下步骤S110～S120：
步骤S110.确定多核处理器中各核心对应的存储块。
其中，存储块是指由存储芯片中部分存储单元构成的局部存储区域，对多个存储块而言，各存储块所包含的存储单元的数量可以相同，也可以不同。多核处理器是指在一枚处理器中集成两个或多个完整的计算引擎，即核心，此时处理器能支持系统总线上的多个处理器，由总线控制器提供所有总线控制信号和命令信号。多核处理器可以把要处理的任务分解成多个部分，并将各部分分别给予不同的核心寄存器让多个运算器共同运算，将运算结果进行汇总后由一个运算器处理好分发给下一步，或者也可以直接由程序控制将各个运算结果下发给下一步。
本示例性实施方式中，存储芯片可以被划分为多个存储块，在进行测试时，可以首先确定每个核心所对应的存储块。例如，如图2所示，CPU1、CPU2、CPU3…CPUN、CPUa和CPUb分别为不同的核心，按照一个核心对应任意一个存储块的规则，将存储芯片中的 每个存储块划分给多核处理器中的每个核心，如CPU1所对应的存储块为存储块1。在这种方式中，核心对应的存储块互不相同。通过这种方法，可以确定每个核心所对应的存储块，即由多个存储单元构成的单元组合，实现了存储单元的有效分组，有助于提高存储芯片的测试灵活性。
随着存储芯片的存储容量的增加，存储芯片中的存储单元的数量越来越多，为了便于确定多核处理器中每个核心所对应的存储块，在一种可选的实施方式中，可以首先按照存储芯片中各存储单元的存储地址，将存储芯片划分为具有相同大小或不同大小的存储区域的存储块。其中，存储地址即为存储芯片中的存储单元的编号，该编号能够唯一标识一个存储单元。
按照存储芯片中各存储单元的存储地址，可以将存储芯片中的存储单元划分为多个存储块，每个存储块的大小可以是任意的，并且在每个存储块中，各个存储单元之间可以是相邻的，也可以是不相邻的。例如，可以按照各存储单元的存储地址，将存储地址连续的X个存储单元划分为一个存储块，这样可以将存储芯片按照存储地址的连续性划分为多个存储块。其中，X为正整数。再例如，也可以按照各存储单元的存储地址，将具有相同行地址或列地址的每一行存储单元或每一列存储单元划分为一个存储块，即按照存储芯片中构成存储阵列的存储单元的行列关系将存储单元划分为多个存储块。通过将存储芯片的存储单元划分为多个存储块，可以完成存储单元的任意分组，且分组规则可以由测试人员自定义，能够满足多种不同的测试和分组需求，具有较高的灵活性。
基于上述方法，在确定多核处理器中各核心对应的存储块时，在一种可选的实施方式中，可以通过根据多核处理器中各核心所对应的存储块的地址信息，确定各核心所对应的存储块。存储块的地址信息可以包括存储芯片的各个存储块中包含的存储单元的存储地址。例如，对于多核处理器的N个核心，可以按照存储块的地址先后顺序，依次确定各核心对应的存储块。再例如，也可以按照一个核心对应固定数量个存储单元的规则，来根据存储芯片中各存储单元的存储地址，将每个核心所对应的存储块确定为由存储芯片中X个存储单元构成的存储区域，也就是说，一个核心对应X个存储单元，各核心对应的存储块中的存储单元不重复。
此外，在一种可选的实施方式中，可以由测试人员预先配置各核心与存储块的地址对应关系，如可以由测试人员预先根据核心与存储块的地址对应关系建立配置表，在确定各核心对应的存储块时，便可以根据配置表确定每个核心所对应的存储块，以及存储块中的存储单元的存储地址，从而在存储芯片中查找到每个核心所对应的存储块。
由于存储地址标识存储单元的唯一性，通过上述根据存储块的地址信息确定各核心所对应的存储块的方法，可以确保各核心对应的存储块中的存储单元具有唯一性，即任意两个存储块中的存储单元不存在重复，能够避免测试重复单元而产生的测试效率较低的问题，以及测试紊乱的问题，影响测试结果。
步骤S120.通过多核处理器中的各核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定存储芯片的测试结果。
读写测试是指对要测试的存储芯片的存储单元进行全写满或者全读出，或者按照先读后写及其他不同的读/写组合的方式进行遍历；测试结果用于表征各存储单元是否发生读写错误，比如是否存在无法正常写入数据或读取数据与写入数据不一致的存储单元等。
在确定各核心所对应的存储块后，可以利用每个核心对各自对应的存储块进行读写测试，由各核心确定其对应的存储块的测试结果，然后多核处理器可以对各存储块的测试结果进行分析和处理，比如统计、去重等，来确定存储芯片的测试结果。在这种方式下，多核处理器可以同时运行多个核心执行测试任务，所以能够显著提高存储芯片的测试效率。
为了确保存储芯片的测试全面性，在一种可选的实施方式中，在步骤S120前，还可以执行以下方法：
通过多核处理器加载和运行启动装载程序，激活多核处理器中的各核心，以使各核心在处于激活状态时，对相应的存储块进行读写测试。
启动装载程序也就是BootLoader程序，该程序是嵌入式系统在加电后执行的第一段代码，通过BootLoader程序可以初始化硬件设备、建立内存空间的映射表，即搭建适当的系统软硬件环境，为调用多核处理器中的各个核心做好准备。启动装载程序可以运行于静态随机存取存储器内，且在处于激活状态时，各核心运行于启动装载程序中。也就是说，在激活状态时，各核心分别执行存储块的测试任务，此时各核心运行于启动装载程序中。其中，静态随机存取存储器，也就是SRAM(Static Random-Access Memory)是一种具有静止存取功能的存储器，在保持通电的状态下，不需要刷新便可以保存内部存储的数据。
对计算机系统而言，从开机通电到操作系统启动这一过程中，可以通过多核处理器加载和运行启动装载程序，完成该过程的引导，并激活多核处理器中的各个核心，完成存储芯片的测试任务的多核调度，进而使得各核心可以在激活状态下分别对相应的存储块进行读写测试。由于在执行测试任务时，各核心运行于SRAM的启动装载程序中，所以不会占用存储芯片的内存空间，所以可以满足存储芯片的全面测试需求，也能够提高存储芯片的测试效率。
在多核处理器中，每个核心均可以用于独立完成处理任务，因此，为了实现对各存储块的读写测试，在一种可选的实施方式中，可以执行以下方法，以实现各存储块的读写测试：
由多核处理器中的各核心分别对相应的存储块进行读写测试，直至完成对存储芯片中的全部存储块的读写测试，得到各存储块的测试结果。
由每个核心对各自对应的存储块进行读写测试，比如可以控制一定数量的核心对各自对应的存储块同时进行读写测试。在读写测试完成后，每个核心可以得到其测试的存储块的测试结果。同时，当一个核心对应两个及以上的存储块时，可以由该核心对其关联的各个存储块依次进行读写测试，直至完成该核心对应的所有存储块的测试。通过该方法，可以控制多核处理器中的核心按照既定规则对存储块进行测试，可以满足不同的测试需求。
进一步的，在一种可选的实施方式中，还可以执行以下方法：
由多核处理器中的各核心同时对各自对应的任意一个或多个存储块进行读写测试；或者由多核处理器中的各核心依次对各自对应的任意一个或多个存储块进行读写测试。
在各核心同时对不同存储块进行读写测试时，各核心同时执行对不同存储块的测试程序，这种方式下，各核心按照并行方式运行，所以可以最大化多核处理器的处理性能，提高存储芯片的测试效率；在各核心依次对不同存储块进行读写测试时，各核心依次执行对不同存储块的测试程序，这种方式可以实现核心的不同步运行，可以充分发挥多核处理器的核心的处理灵活性，比如在当前时刻时，一个核心可以执行写入测试过程，另一核心可以执行读取测试过程。通过上述方法，可以控制多核处理器按照不同的运行方式对存储块进行读写测试，具有较高的灵活性。
本示例性实施方式中，各存储块的测试方法可以相同，也可以不同，比如某个存储块的测试方法可以表示为测试算法原语：(w)，(r，w)，(r)，(w)，(r，w，r)，(r)，该方法需要对存储芯片的存储单元遍历6次，另一个存储块的测试方法可以是测试算法原语：(w，r)，(w)，(r)，(w)，该方法仅需要对存储芯片的存储单元遍历4次。其中，(w)或(r)表示对存储芯片的全部存储单元执行写入操作或读取操作，(r，w)表示按照一次访问的大小，比如1字节、4字节、8字节等对存储芯片的存储单元执行先读后写的操作，来遍历存储芯片的全部存储单元，(r，w，r)表示按照一次访问的大小对存储芯片的存储单元执行先读后写再读的操作，来遍历存储芯片的全部存储单元。在上述过程中，两次写入的数据可以相同，也可以不同。基于此，在一种可选的实施方式中，在通过多核处理器中的各核心对相应的存储块进行读写测试时，参考图3所示，还可以执行以下方法：
步骤S310，在对各存储块进行读写测试时，确定存储芯片中各存储块的测试策略。
其中，测试策略可以包括对各存储块进行数据读取操作和/或数据写入操作的测试流程。测试流程是指对各存储块进行数据读写操作的阶段，可以将关于同一测试数据的数据读写操作视为一个测试流程，也可以将任意一种数据读取操作或数据写入操作视为一个测试流程。测试流程可以包括对各存储块进行数据读写操作的操作顺序、频次等。除此之外，测试策略还可以包括执行数据读取操作或数据写入操作时的测试参数，如控制信号的电压值等。
在利用各核心对其关联的存储块进行读写测试时，可以预先确定每个存储块的测试流程。例如，可以根据预先配置的测试规则表查找和确定每个存储块需要执行的操作步骤和每个操作步骤的顺序等。
步骤S320，由多核处理器中的各核心按照测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作。
在进行测试时，可以由多核处理器控制各个核心按照统一的测试流程对各自对应的存储块进行数据读写操作。通过这种方法，可以确保各存储块采用统一的测试流程进行测试，保证测试的一致性、全面性和准确性，同时，由于测试流程可以由测试人员自行配置，所以也可以提高测试的灵活性和便利性。
进一步的，对于不同的测试流程而言，所写入存储块或从存储块中需要读取的测试数据可以是不同的，因此，在一种可选的实施方式中，测试策略还可以包括各测试流程的测试数据，步骤S320还可以通过以下方法实现：
确定当前执行的测试流程的目标测试数据；
由各核心在各自对应的存储块中进行关于目标测试数据的数据读取操作和/或数据写入操作。
测试数据是指测试存储单元的读写功能而设置的写入数据。由于存储芯片是以二进制形式存储数据的，所以测试数据也可以是任意一种二进制序列。目标测试数据是指当前执行的数据读取操作或数据写入操作中需要读取或写入的测试数据。
本示例性实施方式中，多核处理器可以控制各核心对相应的存储块执行测试任务，在执行测试任务时，各核心可以确定当前执行的测试流程，即数据读取操作和/或数据写入操作对应的目标测试数据，从而由各核心在各自对应的存储块中写入目标测试数据或从中读取目标测试数据。通过该方法，可以在写入测试数据时，确保每个测试阶段数据写入的正确性，在读取测试数据时，也可以依据读取的数据和测试数据确定读取数据是否正确，可以提高确定测试结果的效率，并且测试人员也可以为不同的测试阶段设置不同的测试数据，满足各阶段的测试需求。
另外，测试流程中的数据读写操作可以被顺序执行，因此，在一种可选的实施方式中，还可以在多核处理器中的全部核心按照当前执行的测试流程完成对各自对应的存储块的读写测试时，控制各核心按照下一测试流程对各自对应的存储块进行读写测试。
对于具有多个测试流程的测试任务来说，各核心按照顺序方式依次执行各测试流程，只有在各核心完成对各存储块的当前测试流程时，才会对各存储块执行下一测试流程，因而能够在一定程度避免测试出错。
本示例性实施方式中，由于存储块的大小可能是不同的，并且多核处理器中每个核心的速率也可能不同，所以即使测试刚开始时，各核心与存储块的访问顺序是对应的，但随着测试流程的切换或者对存储块的反复访问，可能会导致在同一时间，各核心在执行不同的测试流程，造成存储块的测试错误。因此，为了实现各核心的同步测试，在一种可选的实施方式中，还可以执行以下方法：
在对各存储块进行读写测试时，当多核处理器中的任意一个或多个核心按照当前执行的测试流程完成对各自对应的存储块的读写测试时，控制上述任意一个或多个核心进入等 待状态，并触发计数器计数；
当根据计数器的计数结果确定多核处理器中的全部核心进入等待状态时，重新激活多核处理器中的各核心，并控制各核心按照下一测试流程对各自对应的存储块进行读写测试。
在等待状态下，核心不执行测试任务。例如，在多核处理器控制各核心开始对各自对应的存储块进行测试时，各核心被一一激活，count持续加1，等到count的值等于被激活的核心总数时，核心全部进入等待状态，即核心同步完成，然后多核处理器可以控制被激活的核心按照相应的存储块分配规则执行各自存储块的测试流程，当某个核心完成当前执行的测试流程时，多核处理器可以控制该核心进入等待状态，同时计数器可以进行计数，如count减1。随着其他核心也陆续完成当前执行的测试流程，不断触发计数器减1，直到清零，此时所有进入等待状态的核心会被重新激活，同时触发计数器加1，直到全部核心回到等待状态时，控制所有核心执行下一测试流程。其中，count表示当前时刻处于等待状态的核心数量。当根据计数器的计数结果确定全部核心进入等待状态时，说明全部核心都完成了当前执行的测试流程，此时多核处理器可以控制各核心对各自对应的存储块执行下一测试流程。这种方法可以保证核心能够在规定界限内完成测试流程，确保核心执行测试流程的同步性，防止测试流程紊乱导致测试结果假性的错误，避免误判，提高测试准确率。
在对存储芯片进行测试时，有时候需要对存储芯片执行一些非访问型操作，因此，在一种可选的实施方式中，测试策略还可以包括对存储芯片中的存储单元进行全局控制操作的操作流程。其中，全局控制操作即为对存储芯片执行的非访问型操作，可以包括对存储芯片中的存储单元进行的数据保持操作和/或数据刷新操作。具体的，数据保持操作是指控制写入存储芯片的数据保持一段时间，来确保写入数据不会因为时间或漏电等因素发生不符合预期的变化；数据刷新操作是指对存储单元中的高电位电容执行的周期性地充电操作，该操作可以保持高电位电容的稳定，使其持续存储数据，数据刷新操作可以包括自刷新操作或控制器控制刷新操作等。
由此，在对各存储块进行读写测试时，还可以由多核处理器中的任意一个核心按照全局控制操作的操作流程对存储芯片中的全部存储单元进行全局控制操作。例如，在完成任意一个或多个测试流程后，多核处理器可以控制最后完成该测试流程的核心对存储芯片中的全部存储单元进行数据保持操作和数据刷新操作，该操作的执行时间可以由测试人员预先设置。通过执行全局控制操作，可以在对存储芯片进行读写测试的过程中，确保数据的持续存储，从而避免外部因素对之后的测试结果产生影响。
进一步的，如前所述，一个核心可以对应一个或多个存储块，在这种方式下，如图2中所示的，当多核处理器中的核心数量N与存储块的数量M相等时，所有核心完成读写测试意味着整个测试任务结束。当多核处理器中的核心数量N大于存储块的数量M时，所有分配存储块的核心完成读写测试也同样意味着整个测试任务结束。当多核处理器中的核心数量N小于存储块的数量M时，当所有核心完成读写测试时，此时存储芯片中仍存在剩余的存储块，此时为了完成剩余存储块的读写测试，在一种可选的实施方式中，还可以执行以下方法：
当存在任意一个或多个存储块未进行测试时，监测各核心的测试进度，并利用多核处理器中已完成测试的核心对任意一个或多个存储块中的任意一个存储块进行读写测试，直至完成对存储芯片中的全部存储块的读写测试。
在上述方法中，存储块与核心之间一一对应，当一个核心完成自己对应的存储块的测试时，多核处理器可以检测未进行测试的存储块，从而利用已完成测试的核心对未进行测试的存储块展开读写测试。例如，在如图2所示的存储块划分示例中，假设CPUa为最先完成测试的核心，则对于剩余未测试的存储块，即第N+1个存储块，则可以首先利用CPUa对第N+1个存储块进行读写测试，同时监测所有核心的测试进度，进而利用最新完成读写测试的核心CPUb对第N+2个存储块进行读写测试，直至完成所有存储块的读写测试。
在各核心完成各自对应的存储块的读写测试后，可以得到其测试的存储块的测试结果，而为了得到整个存储芯片的测试结果，在一种可选的实施方式中，各存储块的测试结果可以包括对应的存储块中的存储单元是否发生读写错误和发生读写错误的地址位数，因此，可以通过以下方法得到存储芯片的测试结果：
依据各存储块的测试结果确定存储芯片中发生读写错误的存储单元和发生读写错误的存储单元的地址位数，以得到存储芯片的测试结果。
在得到各存储块的测试结果后，可以统计各存储块中发生读写错误的存储单元和发生读写错误的存储单元的地址位数，可以得到整个存储芯片中发生读写错误的存储单元及其地址位数，即得到存储芯片的测试结果。
综上，根据本示例性实施方式中的存储芯片的测试方法，可以确定多核处理器中各核心对应的存储块，并通过多核处理器中的各核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定存储芯片的测试结果。本方案通过将存储芯片中的存储单元划分为多个存储块，并分配给多核处理器的不同核心，利用各核心对相应的存储块进行读写测试，可以充分利用多核处理器的处理性能，提高存储芯片的测试效率。
本示例性实施方式中还提供了一种存储芯片的测试装置，参考图4所示，存储芯片的测试装置400可以包括：确定模块410，可以用于确定多核处理器中各核心对应的存储块，存储块为由存储芯片中部分存储单元构成的局部存储区域；测试模块420，可以用于通过多核处理器中的各核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定存储芯片的测试结果。
在本公开的一种示例性实施方式中，确定模块410通过执行以下方法将存储芯片划分为多个存储块：按照存储芯片中各存储单元的存储地址，将存储芯片划分为具有相同大小或不同大小的存储区域的存储块。
在本公开的一种示例性实施方式中，确定模块410可以用于根据多核处理器中各核心所对应的存储块的地址信息，确定各核心所对应的存储块，地址信息包括存储芯片中各存储块包含的存储单元的存储地址；测试模块420可以用于由多核处理器中的各核心分别对相应的存储块进行读写测试，直至完成对存储芯片中的全部存储块的读写测试，得到各存储块的测试结果。
在本公开的一种示例性实施方式中，测试模块420还可以用于由多核处理器中的各核心同时对各自对应的任意一个或多个存储块进行读写测试；或者由多核处理器中的各核心依次对各自对应的任意一个或多个存储块进行读写测试。
在本公开的一种示例性实施方式中，各存储块的测试结果包括对应的存储块中的存储单元是否发生读写错误和发生读写错误的地址位数，测试模块420还可以用于依据各存储块的测试结果确定存储芯片中发生读写错误的存储单元和发生读写错误的存储单元的地址位数，以得到存储芯片的测试结果。
在本公开的一种示例性实施方式中，在通过多核处理器中的各核心对相应的存储块进行读写测试前，测试模块420还可以用于通过多核处理器加载和运行启动装载程序，激活多核处理器中的各核心，以使各核心在处于激活状态时，对相应的存储块进行读写测试；其中，启动装载程序运行于静态随机存取存储器内，且在处于激活状态时，各核心运行于启动装载程序中。
在本公开的一种示例性实施方式中，在通过多核处理器中的各核心对相应的存储块进行读写测试时，测试模块420还可以用于在对各存储块进行读写测试时，确定存储芯片中各存储块的测试策略，测试策略包括对各存储块进行数据读取操作和/或数据写入操作的测试流程，由多核处理器中的各核心按照测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作。
在本公开的一种示例性实施方式中，测试策略还包括各测试流程的测试数据，测试模 块420还可以用于确定当前执行的测试流程的目标测试数据；由各核心按照当前执行的测试流程在各自对应的存储块中进行关于目标测试数据的数据读取操作和/或数据写入操作。
在本公开的一种示例性实施方式中，测试模块420还可以用于在多核处理器中的全部核心按照当前执行的测试流程完成对各自对应的存储块的读写测试时，控制各核心按照下一测试流程对各自对应的存储块进行读写测试。
在本公开的一种示例性实施方式中，测试模块420还可以用于在对各存储块进行读写测试时，当多核处理器中的任意一个或多个核心按照当前执行的测试流程完成对各自对应的存储块的读写测试时，控制任意一个或多个核心进入等待状态，并触发计数器计数，当根据所述计数器的计数结果确定所述多核处理器中的全部核心进入所述等待状态时，重新激活多核处理器中的各核心，并控制各核心按照下一测试流程对各自对应的存储块进行读写测试。
在本公开的一种示例性实施方式中，测试策略还包括对存储芯片中的存储单元进行全局控制操作的操作流程，测试模块420还可以用于由多核处理器中的任意一个核心按照全局控制操作的操作流程对存储芯片中的全部存储单元进行全局控制操作；其中，全局控制操作包括对存储芯片中的存储单元进行的数据保持操作和/或数据刷新操作。
在本公开的一种示例性实施方式中，测试模块420还可以用于当存在任意一个或多个存储块未进行测试时，监测各核心的测试进度，并利用多核处理器中已完成测试的核心对任意一个或多个存储块中的任意一个存储块进行读写测试，直至完成对存储芯片中的全部存储块的读写测试。
在本公开的一种示例性实施方式中，存储芯片包括动态随机存取存储器。
上述装置中各模块的具体细节在方法部分实施方式中已经详细说明，未披露的方案细节内容可以参见方法部分的实施方式内容，因而不再赘述。
所属技术领域的技术人员能够理解，本公开的各个方面可以实现为系统、方法或程序产品。因此，本公开的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
本公开的示例性实施方式还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本公开的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当程序产品在终端设备上运行时，程序代码用于使终端设备执行本说明书上述“示例性方法”部分中描述的根据本公开各种示例性实施方式的步骤。
参考图5所示，描述了根据本公开的示例性实施方式的用于实现上述方法的程序产品500，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本公开的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
程序产品500可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质， 该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本公开操作的程序代码，程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
本公开的示例性实施方式还提供了一种能够实现上述方法的电子设备。下面参照图6来描述根据本公开的这种示例性实施方式的电子设备600。图6显示的电子设备600仅仅是一个示例，不应对本公开实施方式的功能和使用范围带来任何限制。
如图6所示，电子设备600可以以通用计算设备的形式表现。电子设备600的组件可以包括但不限于：上述至少一个处理单元610、上述至少一个存储单元620、连接不同系统组件(包括存储单元620和处理单元610)的总线630和显示单元640。
其中，存储单元620存储有程序代码，程序代码可以被处理单元610执行，使得处理单元610执行本说明书上述“示例性方法”部分中描述的根据本公开各种示例性实施方式的步骤。例如，处理单元610可以执行图1和图3所示的方法步骤等。
存储单元620可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)621和/或高速缓存存储单元622，还可以进一步包括只读存储单元(ROM)623。
存储单元620还可以包括具有一组(至少一个)程序模块625的程序/实用工具624，这样的程序模块625包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线630可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备600也可以与一个或多个外部设备700(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备600交互的设备通信，和/或与使得该电子设备600能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口650进行。并且，电子设备600还可以通过网络适配器660与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器660通过总线630与电子设备600的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备600使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的示例性实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，上述附图仅是根据本公开示例性实施方式的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例性实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开示例性实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开示例性实施方式的方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施方式。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施方式仅被视为示例性的，本公开的真正范围和精神由权利要求指出。

Claims (16)

  1. 一种存储芯片的测试方法，所述方法包括：
    确定多核处理器中各核心对应的存储块，所述存储块为由存储芯片中部分存储单元构成的局部存储区域；
    通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果。
  2. 根据权利要求1所述的方法，其中，通过以下方法将所述存储芯片划分为多个存储块：
    按照所述存储芯片中各存储单元的存储地址，将所述存储芯片划分为具有相同大小或不同大小的存储区域的存储块。
  3. 根据权利要求1所述的方法，其中，所述确定多核处理器中各核心对应的存储块，包括：
    根据所述多核处理器中各所述核心所对应的存储块的地址信息，确定各所述核心所对应的存储块，所述地址信息包括所述存储芯片中各所述存储块包含的存储单元的存储地址；
    所述通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，包括：
    由所述多核处理器中的各所述核心分别对相应的存储块进行读写测试，直至完成对所述存储芯片中的全部存储块的读写测试，得到各所述存储块的测试结果。
  4. 根据权利要求3所述的方法，其中，所述由所述多核处理器中的各所述核心分别对相应的存储块进行读写测试，还包括：
    由所述多核处理器中的各所述核心同时对各自对应的任意一个或多个存储块进行读写测试；或者
    由所述多核处理器中的各所述核心依次对各自对应的任意一个或多个存储块进行读写测试。
  5. 根据权利要求3所述的方法，其中，各所述存储块的测试结果包括对应的存储块中的存储单元是否发生读写错误和发生读写错误的地址位数，所述依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果，包括：
    依据各所述存储块的测试结果确定所述存储芯片中发生读写错误的存储单元和所述发生读写错误的存储单元的地址位数，以得到所述存储芯片的测试结果。
  6. 根据权利要求1所述的方法，其中，在通过所述多核处理器中的各所述核心对相应的存储块进行读写测试前，所述方法还包括：
    通过所述多核处理器加载和运行启动装载程序，激活所述多核处理器中的各所述核心，以使各所述核心在处于激活状态时，对相应的存储块进行读写测试；
    其中，所述启动装载程序运行于静态随机存取存储器内，且在处于所述激活状态时，各所述核心运行于所述启动装载程序中。
  7. 根据权利要求1所述的方法，其中，在通过所述多核处理器中的各所述核心对相应的存储块进行读写测试时，所述方法还包括：
    在对各所述存储块进行读写测试时，确定所述存储芯片中各所述存储块的测试策略，所述测试策略包括对各所述存储块进行数据读取操作和/或数据写入操作的测试流程；
    由所述多核处理器中的各所述核心按照所述测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作。
  8. 根据权利要求7所述的方法，其中，所述测试策略还包括各所述测试流程的测试数据，所述由所述多核处理器中的各所述核心按照所述测试流程对各自对应的存储块进行数据读取操作和/或数据写入操作，还包括：
    确定当前执行的测试流程的目标测试数据；
    由各所述核心按照所述当前执行的测试流程在各自对应的存储块中进行关于所述目标测试数据的数据读取操作和/或数据写入操作。
  9. 根据权利要求8所述的方法，其中，所述方法还包括：
    在所述多核处理器中的全部核心按照所述当前执行的测试流程完成对各自对应的存储块的读写测试时，控制各所述核心按照下一测试流程对各自对应的存储块进行读写测试。
  10. 根据权利要求9所述的方法，其中，所述方法还包括：
    在对各所述存储块进行读写测试时，当所述多核处理器中的任意一个或多个核心按照所述当前执行的测试流程完成对各自对应的存储块的读写测试时，控制所述任意一个或多个核心进入等待状态，并触发计数器计数；
    当根据所述计数器的计数结果确定所述多核处理器中的全部核心进入所述等待状态时，重新激活所述多核处理器中的各所述核心，并控制各所述核心按照所述下一测试流程对各自对应的存储块进行读写测试。
  11. 根据权利要求7所述的方法，其中，所述测试策略还包括对所述存储芯片中的存储单元进行全局控制操作的操作流程，所述方法还包括：
    由所述多核处理器中的任意一个核心按照所述全局控制操作的操作流程对所述存储芯片中的全部存储单元进行全局控制操作；
    其中，所述全局控制操作包括对所述存储芯片中的存储单元进行的数据保持操作和/或数据刷新操作。
  12. 根据权利要求3所述的方法，其中，所述方法还包括：
    当存在任意一个或多个存储块未进行测试时，监测各所述核心的测试进度，并利用所述多核处理器中已完成测试的核心对所述任意一个或多个存储块中的任意一个存储块进行读写测试，直至完成对所述存储芯片中的全部存储块的读写测试。
  13. 根据权利要求1所述的方法，其中，所述存储芯片包括动态随机存取存储器。
  14. 一种存储芯片的测试装置，所述装置包括：
    确定模块，用于确定多核处理器中各核心对应的存储块，所述存储块为由存储芯片中部分存储单元构成的局部存储区域；
    测试模块，用于通过所述多核处理器中的各所述核心对相应的存储块进行读写测试，并依据测试得到的各存储块的测试结果确定所述存储芯片的测试结果。
  15. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-13任一项所述的方法。
  16. 一种电子设备，包括：
    处理器；以及
    存储器，用于存储所述处理器的可执行指令；
    其中，所述处理器配置为经由执行所述可执行指令来执行权利要求1-13任一项所述的方法。
PCT/CN2022/090619 2022-03-11 2022-04-29 存储芯片的测试方法、装置、存储介质与电子设备 WO2023168817A1 (zh)

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