WO2023166832A1 - 撮像装置 - Google Patents

撮像装置 Download PDF

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Publication number
WO2023166832A1
WO2023166832A1 PCT/JP2022/047745 JP2022047745W WO2023166832A1 WO 2023166832 A1 WO2023166832 A1 WO 2023166832A1 JP 2022047745 W JP2022047745 W JP 2022047745W WO 2023166832 A1 WO2023166832 A1 WO 2023166832A1
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WIPO (PCT)
Prior art keywords
voltage
transistor
circuit
imaging device
pixel
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Ceased
Application number
PCT/JP2022/047745
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English (en)
French (fr)
Japanese (ja)
Inventor
正美 船橋
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to JP2024504377A priority Critical patent/JPWO2023166832A1/ja
Priority to CN202280091176.5A priority patent/CN118661425A/zh
Publication of WO2023166832A1 publication Critical patent/WO2023166832A1/ja
Priority to US18/796,257 priority patent/US20240405038A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to imaging devices.
  • imaging devices have been widely used in various product fields such as video cameras, digital still cameras, surveillance cameras, and vehicle-mounted cameras.
  • a CCD (Charge Coupled Device) type solid-state imaging device or a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device is used (see Patent Documents 1 and 2, for example).
  • the CMOS type solid-state imaging device has become mainstream. Since the CMOS-type solid-state imaging device can be manufactured using a general-purpose CMOS process, existing facilities can be used and the imaging device can be stably supplied. In addition, since the peripheral circuits can be mounted on the same chip, signals can be read out from the imaging element at high speed, and high speed and high resolution can be achieved.
  • an object of the present disclosure is to provide an imaging device with reduced noise.
  • an imaging device includes a first pixel and a second pixel, each including a photoelectric conversion unit that converts light into an electric charge and a first transistor connected to the photoelectric conversion unit.
  • a pixel a first wiring connected to one of the source and the drain of the first transistor of the first pixel, a second wiring connected to one of the source and the drain of the first transistor of the second pixel, and a first voltage and a first amplifier circuit connected to the first voltage line for amplifying the first voltage and outputting it to the first wiring and the second wiring.
  • FIG. 1 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Embodiment 1.
  • FIG. FIG. 2 is a diagram showing an exemplary circuit configuration of a pixel of the imaging device according to Embodiment 1.
  • FIG. FIG. 3 is a block diagram showing a circuit configuration for generating the second power supply voltage in FIG. 2.
  • FIG. 4 is a diagram showing detailed circuit configurations of the voltage generation circuit and the buffer circuit shown in FIG. 5 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Modification 1 of Embodiment 1.
  • FIG. 6 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Modification 2 of Embodiment 1.
  • FIG. 1 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Embodiment 1.
  • FIG. 2 is a diagram showing an exemplary circuit configuration of a pixel of the imaging device according to Embodiment 1.
  • FIG. 3 is a block diagram showing a circuit configuration for generating the second
  • FIG. 7 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Modification 3 of Embodiment 1.
  • FIG. 8 is a diagram schematically showing an exemplary circuit configuration of a buffer circuit included in the imaging device according to Embodiment 2.
  • FIG. 9 is a diagram schematically showing an exemplary circuit configuration of a buffer circuit included in an imaging device according to Embodiment 3.
  • FIG. 10 is a timing chart for explaining the operation of the buffer circuit included in the imaging device according to the third embodiment.
  • 11A is a diagram schematically showing an exemplary circuit configuration of a buffer circuit according to Modification 1 of Embodiment 3.
  • FIG. 11B is a diagram schematically showing an exemplary circuit configuration of a buffer circuit according to Modification 1 of Embodiment 3.
  • FIG. 12 is a diagram schematically showing an exemplary circuit configuration of a buffer circuit included in the imaging device according to the fourth embodiment
  • FIG. 13 is a diagram showing an exemplary circuit configuration of a pixel of an imaging device according to Embodiment 5.
  • FIG. 14 is a block diagram showing a circuit configuration for generating the second power supply voltage in FIG. 13.
  • FIG. 15 is a diagram schematically showing a camera system according to Embodiment 6.
  • kTC noise also referred to as “reset noise”
  • FD floating diffusion
  • pixel resetting is also referred to as “FD resetting” or simply "resetting”.
  • the voltage generating circuit that supplies this reference voltage has the role of flowing the operating current of the negative feedback amplifier in the pixel. A voltage drop occurs.
  • a non-limiting exemplary embodiment of the present application provides an imaging device that effectively suppresses deviation of reference voltages depending on columns of a pixel array and realizes reduction of image noise.
  • a first pixel and a second pixel each including a photoelectric conversion unit that converts light into an electric charge and a first transistor connected to the photoelectric conversion unit; a first wiring connected to one of the source and the drain of the first transistor of the first pixel; a second wiring, different from the first wiring, connected to one of the source and the drain of the first transistor of the second pixel; a first voltage line to which the first voltage is applied; a first amplifier circuit connected to the first voltage line for amplifying the first voltage and outputting it to the first wiring and the second wiring;
  • An imaging device comprising:
  • the first transistor has a gate connected to the photoelectric conversion unit and outputs a signal according to the amount of charge.
  • Item 1 The imaging device according to item 1.
  • the output of the first amplifier circuit is connected to the output of the second amplifier circuit, 3.
  • the imaging device according to any one of items 1 to 3.
  • the first amplifier circuit is a second transistor; a third transistor connected in series with the second transistor; including the gate of the second transistor is connected to the first voltage line; a first node between the second transistor and the third transistor is connected to the first wiring; 3.
  • the imaging device according to any one of items 1 to 3.
  • a voltage for causing the third transistor to function as a current source and a voltage for turning on the third transistor are alternately supplied to the gate of the third transistor. 7.
  • the first amplifier circuit includes a switch connected between the second voltage line and the gate of the third transistor; 7.
  • the first amplifier circuit includes a switch connected between the third voltage line and the first node; 7.
  • each of the first pixel and the second pixel includes a second transistor connected between the other of the source or drain of the first transistor and the photoelectric conversion unit; 3.
  • an imaging device includes: a plurality of pixels each including a photoelectric conversion unit that converts light into electric charge; and an amplification transistor that outputs a signal corresponding to the amount of the electric charge; a first wiring connected to one of the source and the drain of the amplification transistor of the first pixel among the pixels; a first voltage line to which a first voltage is applied; a first voltage line connected to the first voltage line; a first amplifier circuit that amplifies a first voltage and outputs the amplified voltage to the first wiring (see FIG. 4).
  • the first amplifier circuit is provided between the first voltage line to which the first voltage for generating the reference voltage is applied and the first wiring connected to one of the source and the drain of the amplification transistor. , the voltage drop due to the wiring resistance of the first voltage line is reduced, and the accuracy of the reference voltage applied to the amplifying transistor is improved. Therefore, the deviation of the reference voltage depending on the columns of the pixel array is effectively suppressed, and the image noise is reduced.
  • a second amplifier circuit connected to the first voltage line may be further provided for amplifying the first voltage and outputting it to the second wiring (see FIG. 4).
  • the output of the first amplifier circuit may be connected to the output of the second amplifier circuit (see FIG. 8).
  • the output terminals of the two amplifier circuits are connected to each other, so that variations in output voltage between the amplifier circuits due to differences in the characteristics of the transistors forming the amplifier circuits are reduced.
  • the first amplifier circuit includes a first transistor and a second transistor connected in series with the first transistor, the gate of the first transistor is connected to the first voltage line, and the A first node between the first transistor and the second transistor may be connected to the first wiring (see FIG. 4).
  • the first amplifier circuit can be realized with a small number of components, and an increase in the area of the column circuits in the imaging device can be suppressed.
  • a second voltage line to which a second voltage is applied and a third voltage line to which a third voltage is applied are further provided, and the first transistor and the second transistor are connected to the second voltage line and the It may be connected in series with the third voltage line (see FIG. 4). This allows the first amplifier circuit to operate using its own power supply different from that of the column circuit.
  • a voltage for causing the second transistor to function as a current source and a voltage for turning on the second transistor may be alternately supplied to the gate of the second transistor (see FIG. 9). .
  • the second transistor that constitutes the first amplifier circuit can have a mode of operating as a current source and a mode of drawing the potential of the FD at high speed.
  • the first amplifier circuit may include a switch connected between the second voltage line and the gate of the second transistor (see FIG. 9).
  • the first amplifier circuit may include a switch connected between a third voltage line and the first node (see FIG. 11A). As a result, the potential of the FD can be rapidly drawn to the target reset potential.
  • a fourth voltage line to which a fourth voltage is applied may be further provided, and the first amplifier circuit may include a switch connected between the fourth voltage line and the first node (FIG. 11B reference). This allows the potential of the FD to be quickly drawn to an arbitrary fourth voltage.
  • each of the plurality of pixels may include a reset transistor connected between the other of the source or the drain of the amplification transistor and the photoelectric conversion section (see FIG. 2). This reduces noise that occurs when the FD is reset.
  • a voltage generating circuit that supplies the first voltage to the first voltage line may be further provided (see FIG. 3). This eliminates the need to supply the first voltage from the outside.
  • FIG. 1 is a diagram schematically showing an exemplary circuit configuration of an imaging device 1 according to this embodiment.
  • the imaging device 1 shown in the figure includes a plurality of pixels 10 and peripheral circuits.
  • a plurality of pixels 10 form a pixel region by being two-dimensionally arranged on the semiconductor substrate.
  • a semiconductor substrate is not limited to a substrate that is entirely semiconductor.
  • the semiconductor substrate may be an insulating substrate provided with a semiconductor layer on the surface on which the pixel region is formed.
  • the plurality of pixels 10 are arranged in row and column directions.
  • row direction and column direction refer to directions in which rows and columns extend, respectively. That is, the vertical direction is the column direction and the horizontal direction is the row direction.
  • the plurality of pixels 10 may be arranged one-dimensionally.
  • the imaging device 1 can be a line sensor.
  • Each of the plurality of pixels 10 is connected to the power wiring 22 .
  • the power wiring 22 is a power supply wiring for a source follower power supply.
  • a predetermined power supply voltage is supplied to each pixel 10 through a power supply wiring 22 .
  • Each of the plurality of pixels 10 includes a photoelectric conversion section having a photoelectric conversion film laminated on a semiconductor substrate.
  • a photoelectric conversion unit is provided on a semiconductor substrate via a wiring layer. Further, as illustrated, the imaging device 1 has an accumulation control line 17 for applying the same constant voltage to all the photoelectric conversion units.
  • the peripheral circuits include a vertical scanning circuit 16, a load circuit 19, a column signal processing circuit 20, and a horizontal signal readout circuit 21.
  • the column signal processing circuit 20 and the load circuit 19 are arranged for each column of the pixels 10 arranged two-dimensionally. That is, in this example, the peripheral circuit includes multiple column signal processing circuits 20 and multiple load circuits 19 .
  • the vertical scanning circuit 16 is connected to the address signal line 30 and the reset signal line 26.
  • the vertical scanning circuit 16 is also called a row scanning circuit.
  • the vertical scanning circuit 16 applies a predetermined voltage to the address signal line 30 or the reset signal line 26 to select the plurality of pixels 10 arranged in each row on a row-by-row basis. As a result, the signal voltage of the selected pixel 10 is read out or the pixel 10 is reset.
  • the vertical scanning circuit 16 is also connected to the sensitivity adjustment line 32 .
  • the vertical scanning circuit 16 can supply a predetermined voltage to the multiple pixels 10 via the sensitivity adjustment line 32 .
  • each of the plurality of pixels 10 has one or more capacitive elements within the pixel.
  • the term "capacitor” means a structure in which a dielectric such as an insulating film is sandwiched between electrodes.
  • the "electrode” in this specification is not limited to electrodes formed of metal, but is interpreted to broadly include polysilicon layers and the like.
  • the pixels 10 arranged in each column are electrically connected to the column signal processing circuit 20 via vertical signal lines 18 corresponding to each column (hereinafter, electrical connection is simply referred to as "connection”). also called).
  • a load circuit 19 is electrically connected to the vertical signal line 18 .
  • the column signal processing circuit 20 performs noise suppression signal processing typified by correlated double sampling, analog-digital conversion (AD conversion), and the like.
  • the column signal processing circuit 20 is also called a row signal storage circuit.
  • a horizontal signal readout circuit 21 is electrically connected to a plurality of column signal processing circuits 20 provided corresponding to the columns of the pixels 10 .
  • the horizontal signal readout circuit 21 sequentially reads signals from the plurality of column signal processing circuits 20 to the horizontal common signal line 23 .
  • the horizontal signal readout circuit 21 is also called a column scanning circuit.
  • FIG. 2 is a diagram showing an exemplary circuit configuration of the pixel 10 of the imaging device 1 according to Embodiment 1.
  • the pixel 10 includes a photoelectric conversion section 100 that photoelectrically converts incident light, and a signal detection circuit SC that detects a signal generated by the photoelectric conversion section 100 .
  • the photoelectric conversion section 100 typically has a structure in which a photoelectric conversion film 120 is sandwiched between a counter electrode 110 and a pixel electrode 130 .
  • the photoelectric conversion film 120 is laminated on the semiconductor substrate on which the pixels 10 are formed.
  • the photoelectric conversion film 120 is made of an organic material or an inorganic material such as amorphous silicon.
  • a counter electrode 110 is provided on the light receiving surface side of the photoelectric conversion film 120 .
  • Counter electrode 110 is formed from a transparent conductive material. Examples of transparent conductive materials include ITO (Indium Tin Oxide).
  • a pixel electrode 130 is provided on the side facing the counter electrode 110 with the photoelectric conversion film 120 interposed therebetween. The pixel electrode 130 collects charges generated by photoelectric conversion in the photoelectric conversion film 120 .
  • the pixel electrode 130 is made of metal such as aluminum or copper, or polysilicon or the like that is doped with impurities to provide conductivity.
  • the counter electrode 110 is connected to the accumulation control line 17.
  • a pixel electrode 130 is connected to the charge storage region 44 .
  • the charge accumulation region 44 is also called FD or FD node.
  • FIG. When holes are used as signal charges, the potential of the counter electrode 110 should be higher than that of the pixel electrode 130 . A case in which holes are used as signal charges will be exemplified below.
  • a voltage of about 10 V, for example, is applied to the counter electrode 110 via the accumulation control line 17 . Thereby, signal charges are accumulated in the charge accumulation region 44 . Of course, electrons may be used as signal charges.
  • the signal detection circuit SC included in the pixel 10 includes an amplification transistor 34, a reset transistor 36, a first capacitive element 41, and a second capacitive element 42.
  • the second capacitive element 42 has a larger capacitance value than the first capacitive element 41 .
  • the gate of reset transistor 36 is connected to reset signal line 26 .
  • One of the source and drain of the reset transistor 36 and one electrode of the first capacitive element 41 are connected to the charge accumulation region 44 . That is, they have electrical connections with the pixel electrodes 130 .
  • the other of the source and drain of the reset transistor 36 and the other electrode of the first capacitor 41 are connected to one electrode of the second capacitor 42 .
  • the first capacitive element 41 is connected between the source and drain of the reset transistor 36 .
  • the node including the connection point between the first capacitive element 41 and the second capacitive element 42 may be called a reset drain node 46 .
  • the electrode that is not connected to the reset drain node 46 is connected to the sensitivity adjustment line 32 .
  • the potential of the sensitivity adjustment line 32 is set to 0V, for example.
  • the potential of the sensitivity adjustment line 32 need not be fixed during operation of the imaging device 1 .
  • a pulse voltage may be supplied from the vertical scanning circuit 16 (see FIG. 1).
  • the gate of the amplification transistor 34 is connected to the charge storage region 44 .
  • the gate of the amplification transistor 34 has electrical connection with the pixel electrode 130 .
  • One of the source and drain of the amplification transistor 34 (for example, the drain if the amplification transistor 34 is an N-channel MOSFET) is connected to the power supply wiring 22 .
  • the other of the source and drain of the amplification transistor 34 is connected to the vertical signal line 18 which is a signal line for transmitting the electric signal output from the amplification transistor 34 .
  • a source follower circuit is formed by the amplification transistor 34 and the load circuit 19 (see FIG. 1).
  • the amplification transistor 34 amplifies the signal generated by the photoelectric conversion section 100 .
  • pixel 10 includes address transistor 40 .
  • Address transistor 40 is also called a row select transistor.
  • the source or drain of the address transistor 40 is connected to the side of the source and drain of the amplification transistor 34 that is not connected to the power supply line 22 .
  • a gate of the address transistor 40 is connected to the address signal line 30 .
  • a voltage corresponding to the amount of signal charge accumulated in the charge accumulation region 44 is applied to the gate of the amplification transistor 34 .
  • Amplification transistor 34 amplifies this voltage.
  • the voltage amplified by the amplification transistor 34 is selectively read by the address transistor 40 as an electrical signal.
  • the signal detection circuit SC includes a feedback path fbl.
  • the signal detection circuit SC includes a feedback transistor 38 arranged on the feedback path fbl.
  • One of the source and drain of the feedback transistor 38 is connected to the side of the source and drain of the amplification transistor 34 connected to the vertical signal line 18 .
  • the other of the source and drain of feedback transistor 38 is connected to reset drain node 46 .
  • the gate of feedback transistor 38 is connected to feedback control line 28 .
  • a feedback path fbl is a path for negative feedback of the output of the amplification transistor 34 to the feedback transistor 38 .
  • the potential of charge storage region 44 is negatively fed back to feedback transistor 38 via amplification transistor 34 .
  • the feedback path fbl is provided for each pixel 10 without straddling the plurality of pixels 10 .
  • the output of the amplification transistor 34 is used as a reference voltage for resetting the charge accumulation region 44 .
  • the feedback path fbl means a path from the charge accumulation region 44 to the charge accumulation region 44 via the amplification transistor 34 , the feedback transistor 38 , the first capacitive element 41 or the reset transistor 36 .
  • feedback for noise cancellation can be performed within each pixel 10 . Accordingly, noise cancellation can be performed at high speed without being affected by the time constant of the vertical signal line 18 .
  • the output voltage of the amplification transistor 34 is applied to the reset transistor 36 . With such a configuration, the change in the voltage of the charge storage region 44 before and after the reset transistor 36 is turned off can be reduced, so that faster noise suppression can be achieved.
  • a voltage switching circuit 54 is connected to the power wiring 22 .
  • the voltage switching circuit 54 has a set of the first switch 51 and the second switch 52 .
  • the voltage switching circuit 54 switches between the first power supply voltage Va ⁇ b>1 and the second power supply voltage Va ⁇ b>2 to be supplied to the power supply line 22 .
  • the first power supply voltage Va1 is a read power supply voltage, eg, 3.3V
  • the second power supply voltage Va2 is a noise cancellation power supply voltage, eg, 0.3V.
  • the voltage switching circuit 54 may be provided for each pixel, or may be shared among the plurality of pixels 10 . Such a circuit configuration may reduce the effects of kTC noise.
  • a constant current source 8 is connected to the vertical signal line 18 .
  • address transistor 40 When address transistor 40 is on, address transistor 40, amplification transistor 34 and constant current source 8 form a source follower circuit.
  • a signal corresponding to the signal charge accumulated in the charge accumulation region 44 is output to the vertical signal line 18 and read out to the outside.
  • the constant current source 8 may be provided for each pixel 10 .
  • the constant current source 8 may be shared by multiple pixels 10 in order to reduce the number of elements per pixel.
  • the address transistor 40 When resetting the charge accumulation region 44 , the address transistor 40 is turned off to electrically isolate the amplification transistor 34 and the vertical signal line 18 . Also, the feedback transistor 38 is turned on. Also, the second switch 52 of the voltage switching circuit 54 is turned on. That is, the second power supply voltage Va2 is applied to the source and the drain of the amplification transistor 34 that are not connected to the vertical signal line 18 (that is, the power supply wiring 22). Furthermore, by turning on the reset transistor 36, the charge storage region 44 is reset and the voltage of the charge storage region 44 becomes the reference voltage.
  • the reset transistor 36 is turned off.
  • the signal detection circuit SC forms a feedback circuit whose amplification factor is -A ⁇ B times. Therefore, the kTC noise in the charge accumulation region 44 generated when the reset transistor 36 is turned off is suppressed by 1/(1+A ⁇ B) times. By doing so, the kTC noise can be suppressed.
  • the voltage of the feedback control line 28 is set between the high level and the low level, for example, at an intermediate voltage. In that case, the operating band of the feedback transistor 38 becomes a second band narrower than the first band.
  • the thermal noise generated by the feedback transistor 38 is suppressed by a factor of 1/(1+A.times.B) .sup.1/2 through the feedback path fbl.
  • the voltage of the feedback control line 28 is set to low level to turn off the feedback transistor 38 .
  • the kTC noise remaining in the charge accumulation region 44 at this time is the sum of the squares of the kTC noise caused by the reset transistor 36 and the kTC noise caused by the feedback transistor 38 .
  • Cs be the capacitance of the first capacitive element 41 and CFD be the capacitance of the charge storage region 44 .
  • the kTC noise of feedback transistor 38 without feedback suppression is (CFD/Cs) 1/2 times the kTC noise of reset transistor 36 without feedback suppression.
  • the kTC noise with feedback is suppressed by a factor of ⁇ 1+(1+A ⁇ B) ⁇ CFD/Cs ⁇ 1/2 /(1+A ⁇ B) when compared with the case without feedback.
  • the voltage of the address signal line 30 is set to high level to turn on the address transistor 40, and the voltage of the other of the source and the drain of the amplification transistor 34 (that is, the power supply line 22) becomes the first power supply voltage Va1.
  • the voltage switching circuit 54 is controlled as follows. In this state, amplifying transistor 34 and constant current source 8 form a source follower circuit.
  • the vertical signal line 18 has a voltage corresponding to the signal charge accumulated in the charge accumulation region 44 . At that time, the amplification factor of the source follower circuit is about one.
  • the voltage of the charge accumulation region 44 is changed from the reference voltage by the amount corresponding to the electrical signal generated in the photoelectric conversion section 100 .
  • the voltage of the charge accumulation region 44 is output to the vertical signal line 18 with an amplification factor of about one.
  • Random noise means output fluctuation when the signal charge generated in the photoelectric conversion unit 100 is 0, that is, kTC noise.
  • the kTC noise is suppressed by ⁇ 1+(1+A ⁇ B) ⁇ CFD/Cs ⁇ 1/2 /(1+A ⁇ B) times during the noise suppression period, and furthermore, during the readout period, the vertical signal line is suppressed at an amplification factor of about 1. 18. As a result, good image data with suppressed random noise can be obtained.
  • Each of the amplification transistor 34, reset transistor 36, feedback transistor 38 and address transistor 40 may be an N-channel MOSFET or a P-channel MOSFET. It is not necessary for all of these to be unified into either N-channel MOSFETs or P-channel MOSFETs.
  • the N-channel MOSFET is also simply referred to as "NMOS”
  • the P-channel MOSFET is simply referred to as "PMOS”.
  • FIG. 3 is a block diagram showing a circuit configuration for generating the second power supply voltage Va2 in FIG.
  • a voltage generating circuit 60 that supplies a first voltage which is a fixed voltage, and the first voltage supplied from the voltage generating circuit 60 are amplified and output to the second switch 52 as a second power supply voltage Va2.
  • a buffer circuit 62 is shown to do so.
  • the buffer circuit 62 is an example of a first amplifier circuit that amplifies the first voltage, and is an impedance converter with a voltage gain of 1, for example.
  • the voltage generation circuit 60 may be provided in the imaging device 1 or may be provided outside the imaging device 1 . When the voltage generation circuit 60 is provided outside the imaging device 1, the first voltage output from the voltage generation circuit 60 is supplied to the buffer circuit 62 via wiring, connection terminals, and the like.
  • FIG. 4 is a diagram showing detailed circuit configurations of the voltage generation circuit 60 and the buffer circuit 62 shown in FIG. It should be noted that wiring and circuits related to the first power supply voltage Va1 are omitted from the drawing for convenience of explanation. The same applies to subsequent figures.
  • the buffer circuit 62 provided for each column of the pixel array is composed of a source follower circuit using an NMOS transistor.
  • the buffer circuit 62 includes an amplifying transistor 76 functioning as a source follower, which is an example of a first transistor, and a current source transistor 75 functioning as a current source, which is an example of a second transistor.
  • a voltage line 73 is an example of a second voltage line for supplying a power supply voltage, which is an example of a second voltage.
  • a voltage line 70 is an example of a third voltage line for supplying a ground voltage, which is an example of a third voltage.
  • a current source voltage for operating the current source transistor 75 as a current source is supplied from the voltage generation circuit 60 to the voltage line 71 .
  • a fixed first voltage is applied to the gate of the amplification transistor 76 from the voltage generation circuit 60 via the voltage line 72, which is an example of the first voltage line.
  • a voltage obtained by amplifying the first voltage in the buffer circuit 62 (that is, the second power supply voltage Va2) is output from the output terminal 77, which is the first node between the amplification transistor 76 and the current source transistor 75, and Via the switch 52, it can be applied to the power wiring 22, which is an example of the first wiring.
  • the first wiring is a wiring to which the output voltage amplified by the buffer circuit 62 is applied.
  • the illustrated two buffer circuits 62 are respectively connected to the first voltage line, a first amplifier circuit that amplifies the first voltage and outputs it to the first wiring, and the first voltage line. , is an example of a second amplifier circuit that amplifies the first voltage and outputs the amplified voltage to the second wiring.
  • the voltage generation circuit 60 supplies the buffer circuit 62 with the first voltage through the voltage line 72 and the current source voltage through the voltage line 71 by using the invalid pixels 10a included in the imaging device 1.
  • the invalid pixels 10a are pixels that are not used for imaging among the pixels 10 included in the imaging device 1 .
  • the voltage generation circuit 60 includes an operational amplifier 63 and NMOS transistors 64-66.
  • Transistors 65 and 66 are replica circuits having a configuration similar to that of buffer circuit 62 .
  • Transistors 64 and 65 form a current mirror.
  • a fixed reference voltage VFD (for example, 0.3 V) is input to the non-inverting input terminal of the operational amplifier 63, and the inverting input terminal of the operational amplifier 63 is connected to the power wiring 22a of the invalid pixel 10a. is connected to the gate of the transistor 66 and the amplifying transistor 76 of each buffer circuit 62 .
  • the above A is (the WL ratio of the transistor 65)/(the WL ratio of the transistor 64), and the above B is the (the WL ratio of the transistor 75)/(the WL ratio of the transistor 64).
  • the WL ratio is gate width/gate length.
  • the second power supply voltage Va2 equal to the reference voltage VFD (for example, 0.3 V) can be applied to the power supply wiring 22 of any column.
  • the second power supply voltage Va2 equal to the reference voltage VFD to the power supply wiring 22 of each column through the buffer circuit 62, the current flowing during noise cancellation flows to the voltage line 72 that transmits the first voltage. flow to the buffer circuit 62.
  • the buffer circuit 62 As a result, it is possible to suppress the voltage drop caused by the parasitic resistance in the wiring that supplies the reference voltage, which has conventionally occurred.
  • variations in the noise reduction amount of noise cancellation depending on the row position are improved, and deterioration of readout image signals is suppressed.
  • (Modification 1) 5 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Modification 1 of Embodiment 1.
  • FIG. This modification differs from the first embodiment in that the buffer circuit 62 is shared by a plurality of columns of the pixel array.
  • the output terminal 77 of one buffer circuit 62 is connected to the second switch 52 provided for each of the power supply lines 22 of the plurality of columns in the pixel array.
  • the number of buffer circuits 62 required for the imaging device can be reduced, and the buffer circuit area can be reduced, compared to the case where the buffer circuits 62 are provided for each column.
  • (Modification 2) 6 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Modification 2 of Embodiment 1.
  • FIG. This modification differs from the first embodiment in the circuit configuration for noise cancellation.
  • the imaging device has a current source switching circuit 55 as a constant current source for noise cancellation.
  • the current source switching circuit 55 includes a readout constant current source 8 connected to the voltage Vb1, a switch 56 for switching connection and disconnection between the constant current source 8 and the vertical signal line 18, and a noise current source connected to the voltage Vb2. It has a constant current source 8a for cancellation and a switch 57 for switching connection and disconnection between the constant current source 8a and the vertical signal line 18 .
  • the imaging device has a voltage switching circuit 54a instead of the voltage switching circuit 54 of the first embodiment.
  • the voltage switching circuit 54a switches connection and disconnection between the third power supply voltage Va3, which is the reference voltage for pre-resetting in noise cancellation, and the power supply wiring 22. It has a third switch 53 .
  • the voltage switching circuit 54a selects one reference voltage (that is, the first power supply voltage Va1) as a voltage for reading and two kinds of reference voltages (that is, a second power supply voltage Va2) as a voltage for noise cancellation. and a third power supply voltage Va3) are selectively supplied. That is, the first power supply voltage Va1 is applied to the power supply wiring 22 via the first switch 51 during reading.
  • the second power supply voltage Va2 is supplied to the power supply line 22 via the second switch 52 when performing a feedback operation for noise cancellation.
  • the third power supply voltage Va3 is supplied to the power supply wiring 22 via the third switch 53 when pre-resetting the potential of the FD before the feedback operation.
  • buffer circuits 62 and 62a for the second power supply voltage Va2 and the third power supply voltage Va3, which are two types of reference voltages for noise cancellation, and buffer circuits 62 and 62a for the buffer circuits 62 and 62a Voltage generation circuits 60 and 60a are provided for supplying voltages to the input terminals.
  • Buffer circuit 62 a has a circuit configuration similar to that of buffer circuit 62 .
  • the voltage generating circuit 60a basically has the same circuit configuration as the voltage generating circuit 60, but outputs a reference voltage for the third power supply voltage Va3 different from the first voltage output by the voltage generating circuit 60.
  • the imaging apparatus applies different reference voltages (that is, the second power supply voltage Va2 and the third power supply voltage Va3) to the power supply wiring 22 during pre-reset and during feedback operation in noise cancellation, Even if there are two types of reference voltages, the voltage drop due to the parasitic resistance in the wiring that supplies each of the two types of reference voltages can be suppressed, the noise reduction amount of noise cancellation depending on the column position is improved, and the deterioration of the image signal to be read is suppressed. be.
  • reference voltages that is, the second power supply voltage Va2 and the third power supply voltage Va3
  • the second power supply voltage Va2 equal to the reference voltage VFD to the power supply wiring 22 of each column through the buffer circuit 62, the current flowing from the constant current source 8a to the vertical signal line 18 during noise cancellation is , flows to the buffer circuit 62 without flowing to the voltage line 72 that transmits the reference voltage.
  • This makes it possible to suppress the voltage drop caused by parasitic resistance in the wiring that supplies the reference voltage, which has occurred in the past, improves the variation in noise reduction amount of noise cancellation depending on the column position, and suppresses deterioration of the readout image signal. be done.
  • Modification 3) 7 is a diagram schematically showing an exemplary circuit configuration of an imaging device according to Modification 3 of Embodiment 1.
  • FIG. This modification differs from modification 2 in the circuit configuration for reading.
  • the arrangement positions of the constant current source 8 for reading and the switch 56 in Modification 2 and the first power supply voltage Va1 for supplying the reference voltage for reading in Modification 2 (that is, the first power supply voltage Va1)
  • the arrangement position of the switch 51 is changed.
  • the address transistor 40 connected to one of the source and drain of the amplification transistor 34 is used as the first address transistor
  • a second address transistor 40a connected to the other of the source and drain of the amplification transistor 34 is added. It is The gate of the second address transistor 40a is connected to the vertical scanning circuit 16 via the address signal line 30a.
  • the switches and the buffer circuits 62 and 62a provided for each of the two types of reference voltages are provided at the same arrangement positions as in the second modification.
  • the vertical signal line 18 is an example of the first wiring to which the output voltages from the buffer circuits 62 and 62a are applied.
  • the noise canceling reference voltage that is, the second power supply voltage Va2 and the third power supply voltage Va3
  • the reference voltage is supplied.
  • the voltage drop due to the parasitic resistance in the wiring can be suppressed, the noise reduction amount of the noise cancellation depending on the column position is improved, and the deterioration of the image signal to be read is suppressed.
  • the current flowing from the constant current source 8a to the power supply wiring 22 during noise cancellation is , flows to the buffer circuit 62 without flowing to the voltage line 72 that transmits the reference voltage. This makes it possible to suppress the voltage drop caused by parasitic resistance in the wiring that supplies the reference voltage, which has occurred in the past, improves the variation in noise reduction amount of noise cancellation depending on the column position, and suppresses deterioration of the readout image signal. be done.
  • Embodiment 2 In the imaging apparatus 1 of Embodiment 1, as shown in FIG. 4, the first wiring of each column (that is, the power supply wiring 22 or the vertical signal line 18) and the first power supply voltage Va2 for generating the second power supply voltage Va2.
  • a buffer circuit 62 having the same configuration is arranged for each column between the voltage line 72 that transmits the voltage. This suppresses the voltage drop due to the parasitic resistance in the wiring to which the second power supply voltage Va2 is applied, thereby improving the deterioration of the image signal.
  • the buffer circuits 62 arranged in each column have the same configuration, random output offsets that do not depend on the column position generally occur due to variations in semiconductor manufacturing, voltage drop due to parasitic resistance of power supply wiring, and ground wiring. It may have an output offset dependent on the column position in the pixel array due to voltage drop due to parasitic resistance. Therefore, the second power supply voltage Va2 applied to the first wiring (that is, the power supply wiring 22 or the vertical signal line 18) is Va2_1' . Va2_n' . . . Va2_m', and this voltage variation also results in variation in the FD reset potential, which causes variation in the amount of noise reduction due to noise cancellation.
  • FIG. 8 is a diagram schematically showing an exemplary circuit configuration of the buffer circuit 62 included in the imaging device 1a according to the second embodiment.
  • the output terminals 77 of each buffer circuit 62 provided in each column of the pixel array are connected to each other. That is, an example is shown in which the output of the first amplifier circuit is connected to the output of the second amplifier circuit.
  • VaX be the first voltage input to the buffer circuit 62
  • ⁇ Vn be the output offset of the buffer circuit 62 of the Nth column (N is a natural number of 2 or more)
  • A be the gain of the buffer circuit 62.
  • the imaging apparatus 1a by connecting the output terminal 77 of the buffer circuit 62, the output offset variation of each buffer circuit 62 is averaged, and a uniform reference signal is applied to each column.
  • the voltage Va2' is applied to the power supply wiring 22 as the second power supply voltage Va2.
  • the FD reset potential (hereinafter also simply referred to as "reset potential") is made uniform, variations in the amount of noise reduction due to noise cancellation are suppressed, and deterioration of the image signal is suppressed.
  • the FD potential before being reset becomes higher than the reset potential as the amount of incident light or exposure time increases. Since the potential is high, the buffer circuit is required to have the performance of drawing the high potential of the FD to a desired lower reset potential. Further, in the stacked image sensor assumed in this embodiment, the potential for resetting the FD is lower than the power supply voltage.
  • the buffer circuit 62 including an NMOS source follower circuit as shown in FIG. Drawing charge sets the FD to a predetermined reset potential.
  • the current source of buffer circuit 62 which includes a source follower circuit, is a constant current source, and the speed at which it draws charge depends on its current capability.
  • the parasitic capacitance Cc is determined by the capacitance of the FD determined by pixel design and the wiring length of the first wiring determined by the size of the pixel array, and it is extremely difficult to conveniently change the parasitic capacitance value. .
  • increasing the current Ic of the current source results in an increase in the current consumption of the imaging device and an increase in the area of the current source transistor, and thus cannot be easily increased.
  • FIG. 9 is a diagram schematically showing an exemplary circuit configuration of each buffer circuit 62b included in the imaging device 1b according to the third embodiment.
  • the buffer circuit 62b according to the present embodiment is the same as the buffer circuit 62 according to the first embodiment, except that a control switch 80 for switching the gate of the current source transistor 75 between the bias voltage application mode and the high voltage application mode is added. with configuration. This configuration significantly shortens the time to pull the FD to the reset potential.
  • FIG. 10 is a timing chart for explaining the operation of the buffer circuit 62b included in the imaging device 1b according to the third embodiment.
  • (a) of FIG. 10 shows changes over time in the potentials of the control signal CON10 and FD for controlling the control switch 80 when the gate of the current source transistor 75 is set to the bias voltage application mode
  • (b) of FIG. FIG. 5 shows temporal changes in potentials of the control signal CON10 and FD for controlling the control switch 80 when the gate of the current source transistor 75 is set to the High voltage application mode.
  • the control signal CON10 applies a low level to the control switch 80 ("CON10" in FIG. 10(a)) to set the bias voltage application mode, thereby , the control switch 80 becomes non-conductive, so that the bias voltage applied from the voltage line 71 is applied to the gate of the current source transistor 75 .
  • the current source transistor 75 operates as a current source, and the potential of FD gradually decreases from a high potential toward the target reset potential ("FD" in (a) of FIG. 10).
  • the control signal CON10 applies a High-level pulse to the control switch 80 (“CON10” in FIG. ), thereby, the control switch 80 becomes conductive during the pulse period, and the gate of the current source transistor 75 is connected to the high level potential (here, the power supply voltage of the voltage line 73).
  • the current source transistor 75 is turned on during the pulse and functions as a switch that connects the output terminal 77 to the low level potential (eg, ground potential) of the voltage line 70 .
  • the current source transistor 75 forcibly pulls down the FD and the first wiring (that is, the power supply wiring 22 or the vertical signal line 18) connected thereto, and the current source transistor when operating as the current source of the buffer circuit 62b. 75 current capability or more is realized. As a result, the potential of the FD rapidly drops from a high potential toward the target reset potential during the pulse period (“FD” in (b) of FIG. 10).
  • the buffer circuit 62b can draw the potential of the FD to the target reset potential at high speed.
  • control switch 80 is provided for each buffer circuit 62b, but one control switch 80 shared by a plurality of buffer circuits may be provided. For example, one of the two control switches 80 in FIG. 9 may not be provided.
  • FIG. 11A is a diagram schematically showing an exemplary circuit configuration of a buffer circuit 62c according to modification 1 of the third embodiment.
  • This modification has a control switch 80a connected between the output terminal 77 and the voltage line 70 for supplying the ground voltage, instead of the control switch 80 of the third embodiment.
  • different from The same effect as in the third embodiment can also be obtained with a configuration in which the output terminal 77 is directly pulled down by the control switch 80a without the current source transistor 75 as in this modification.
  • the control switch 80a is connected between the output terminal 77 and the voltage line 70.
  • the output terminal 77 and the fourth potential are connected. It may be connected between another voltage line 70a, which is an example of a fourth voltage line to be applied.
  • FIG. 11B is a diagram schematically showing an exemplary circuit configuration of a buffer circuit 62c according to Modification 1 of Embodiment 3. As shown in FIG. A target reset potential, for example, is applied to the voltage line 70a as the fourth voltage. Even with such a configuration, the potential of the FD can be quickly drawn to the fourth potential, which is the target reset potential, as in the first modification.
  • the buffer circuit has the function of pulling down the potential of the FD.
  • the buffer circuit may be provided with a pull-up function.
  • control switch 80 shown in FIG. 9 may be connected between the gate of amplifying transistor 76 and voltage line 70 instead of the connection shown in FIG. In that case, current source transistor 75 and amplifier transistor 76 reverse their functions and function as an amplifier transistor and a current source transistor, respectively.
  • Both the current source transistor 75 and the amplification transistor 76 are preferably PMOS transistors.
  • control switch 80a shown in FIG. 11A may be connected between the voltage line 73 and the output terminal 77 instead of the connection shown in FIG. 11A.
  • the buffer circuit is equipped with a pull-up function, and the potential of the FD can be quickly pulled to the target High level.
  • FIG. 12 is a diagram schematically showing an exemplary circuit configuration of a buffer circuit 62b included in the imaging device 1c according to the fourth embodiment.
  • This embodiment combines the features of the second embodiment and the features of the third embodiment. That is, in the imaging device 1c according to the present embodiment, the output terminals 77 of the buffer circuits 62b provided in each column of the pixel array are connected to each other as in the second embodiment, and furthermore, as in the third embodiment, the output terminals 77 are connected to each other. , a control switch 80 is provided for each buffer circuit 62b.
  • the FD reset potential of each column can be made uniform, and the potential of the FDs can be drawn to the target reset potential at high speed.
  • each buffer circuit 62b may be replaced with the buffer circuit 62c according to the first modification of the third embodiment. That is, the buffer circuit 62c is provided with a control switch 80a connected between the output terminal 77 and the voltage line 70 for supplying the ground voltage as a buffer circuit in order to draw the potential of the FD to the target reset potential at high speed.
  • the second power supply voltage for FD reset is applied to the first wiring connected to one of the source and the drain of the amplification transistor of the pixel. Since a buffer circuit for supplying Va2 or the like is provided, it is possible to suppress the deviation of the reference voltage between the central column and the peripheral columns of the pixel array regardless of the wiring parasitic resistance of the reference signal and the power supply wiring of the buffer circuit. A pixel signal with good image quality performance can be obtained by suppressing column-dependent variations in the reset noise reduction amount of feedback.
  • Embodiment 5 Embodiments 1 to 4 and their modifications have described examples in which the technique of the present disclosure is applied to the voltage supply circuit that supplies the reference voltage during negative feedback operation.
  • the present disclosure is not limited to a voltage supply circuit that supplies a reference voltage during negative feedback operation.
  • an example in which the technology of the present disclosure is applied to a voltage supply circuit for supplying a reset voltage for resetting the FD will be described.
  • the same reference numerals as in Embodiment 1 are used for the same configuration as in Embodiment 1, and detailed description thereof is omitted.
  • FIG. 13 is a diagram showing an exemplary circuit configuration of the pixel 10 of the imaging device 1d according to the fifth embodiment.
  • the pixel 10 includes a photoelectric conversion section 100 that photoelectrically converts incident light, and a signal detection circuit SC that detects a signal generated by the photoelectric conversion section 100 .
  • the signal detection circuit SC included in the pixel 10 includes an amplification transistor 34 and a reset transistor 36. Unlike the first embodiment, signal detection circuit SC does not include feedback path fbl.
  • the gate of reset transistor 36 is connected to reset signal line 26 .
  • One of the source and drain of the reset transistor 36 and the gate of the amplification transistor 34 are connected to the charge accumulation region 44 . That is, they have electrical connections with the pixel electrodes 130 .
  • the other of the source and drain of reset transistor 36 is connected to reset voltage wiring 25 for supplying reset voltage Va2.
  • One of the source and drain of the amplification transistor 34 is connected to the power supply wiring 22 .
  • the other of the source and drain of the amplification transistor 34 is connected to the vertical signal line 18 which is a signal line for transmitting the electric signal output from the amplification transistor 34 .
  • a reading power supply voltage Va is applied to the power supply wiring 22 .
  • the charge storage region 44 is reset and the voltage of the charge storage region 44 becomes the reset voltage, ie the reference voltage.
  • FIG. 14 is a block diagram showing a circuit configuration for generating reset voltage Va2 in FIG.
  • a voltage generation circuit 60 that supplies a first voltage that is a fixed voltage, and a buffer circuit that amplifies the first voltage supplied from the voltage generation circuit 60 and outputs it to the reset voltage wiring 25 as a reset voltage Va2.
  • the buffer circuit 62 is an example of a first amplifier circuit that amplifies the first voltage, and is an impedance converter with a voltage gain of 1, for example.
  • the voltage generation circuit 60 may be provided in the imaging device 1d, or may be provided outside the imaging device 1d. When the voltage generation circuit 60 is provided outside the imaging device 1, the first voltage output from the voltage generation circuit 60 is supplied to the buffer circuit 62 via wiring, connection terminals, and the like.
  • the circuit configuration for generating the reference voltage Va2 is the same as the configuration described in the first to fourth embodiments and their modifications, so the description is omitted.
  • FIG. 15 is a diagram schematically showing a configuration example of a camera system 600 according to Embodiment 6.
  • a camera system 600 according to Embodiment 6 includes an imaging device according to each of the above-described embodiments or modifications (here, referred to as imaging device 1 as a representative of each embodiment).
  • imaging device 1 as a representative of each embodiment.
  • differences from each embodiment and these modifications will be mainly described, and descriptions of common points will be omitted or simplified.
  • a camera system 600 includes a lens optical system 601 , an imaging device 1 , a system controller 603 , and a camera signal processing section 604 .
  • a lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and an aperture.
  • a lens optical system 601 converges light on the imaging surface of the imaging device 1 .
  • a system controller 603 controls the entire camera system 600 .
  • System controller 603 can be realized by, for example, a microcomputer.
  • the camera signal processing unit 604 functions as a signal processing circuit that processes the output signal from the imaging device 1 .
  • a camera signal processing unit 604 performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance.
  • the camera signal processing unit 604 can be implemented by, for example, a DSP (Digital Signal Processor).
  • the imaging device 1 by using the imaging device 1 according to the above-described embodiment, noise can be reduced and a good image can be obtained.
  • the imaging device of the present disclosure has been described above based on the embodiment and modifications, the present disclosure is not limited to these embodiments and modifications. As long as it does not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can think of are applied to the embodiments and modifications, and other forms constructed by combining some components of the embodiments and modifications , are included within the scope of this disclosure.
  • the buffer circuit 62 and the like are composed of NMOS source follower circuits, but are composed of a PMOS source follower, an NMOS input source common amplifier, a PMOS input source common amplifier, a voltage follower using an operational amplifier, or the like. may be
  • first pixel and the second pixel may be located in the same column.
  • the imaging device can be used as a noise-reduced imaging device, such as a video camera, a digital still camera, a surveillance camera, and an in-vehicle camera.

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  • Engineering & Computer Science (AREA)
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  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
PCT/JP2022/047745 2022-03-03 2022-12-23 撮像装置 Ceased WO2023166832A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016127593A (ja) * 2014-12-26 2016-07-11 パナソニックＩｐマネジメント株式会社 撮像装置
JP2016152495A (ja) * 2015-02-17 2016-08-22 パナソニックＩｐマネジメント株式会社 撮像装置
WO2019167551A1 (ja) * 2018-02-28 2019-09-06 パナソニックＩｐマネジメント株式会社 撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016127593A (ja) * 2014-12-26 2016-07-11 パナソニックＩｐマネジメント株式会社 撮像装置
JP2016152495A (ja) * 2015-02-17 2016-08-22 パナソニックＩｐマネジメント株式会社 撮像装置
WO2019167551A1 (ja) * 2018-02-28 2019-09-06 パナソニックＩｐマネジメント株式会社 撮像装置

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