WO2023163531A1 - Digitizer and image display device comprising same - Google Patents

Digitizer and image display device comprising same Download PDF

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Publication number
WO2023163531A1
WO2023163531A1 PCT/KR2023/002618 KR2023002618W WO2023163531A1 WO 2023163531 A1 WO2023163531 A1 WO 2023163531A1 KR 2023002618 W KR2023002618 W KR 2023002618W WO 2023163531 A1 WO2023163531 A1 WO 2023163531A1
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Prior art keywords
layer
conductive
digitizer
conductive layer
lower conductive
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PCT/KR2023/002618
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French (fr)
Korean (ko)
Inventor
오근태
유성우
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동우 화인켐 주식회사
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Publication of WO2023163531A1 publication Critical patent/WO2023163531A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412Digitisers structurally integrated in a display
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/046Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by electromagnetic means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present invention relates to a digitizer, and more particularly, to a digitizer capable of blocking or minimizing reflection of a conductive layer of the digitizer.
  • Display Most image display devices (Display) apply a touch input method in which a user inputs by touching a screen with a finger or an electronic pen.
  • the touch input method is intuitive and convenient because the user can input by directly touching a specific location on the screen.
  • a touch input method using a pen can designate more precise coordinates than a touch input method using a finger, so it is suitable for graphic work such as CAD.
  • a touch input method using such a pen includes a digitizer.
  • FIG. 1 is a cross-sectional view of a conventional image display device having a digitizer.
  • a conventional image display device includes a display panel 100 and a digitizer 200.
  • the display panel 100 may implement color by including a pixel electrode (TFT), a pixel defining layer, a display layer, a counter electrode, an encapsulation layer, and the like on a substrate.
  • TFT pixel electrode
  • the digitizer 200 is coupled to the rear of the display panel 100 and converts the touch coordinates of the pen into digital data.
  • the digitizer 200 may include a base layer 210, an adhesive layer 220, a lower conductive layer 230, an interlayer insulating layer 240, an upper conductive layer 250, a passivation layer 260, and the like.
  • the emitted light may be reflected from the lower/upper conductive layers 230 and 250 of the digitizer 200 .
  • Such reflected light may affect the pixel electrodes of the display panel 100 and act as voltage noise on the pixel electrodes, causing screen defects.
  • the lower conductive layer 230 is patterned using FCCL (Flexible Copper Clad Laminate), and then the interlayer insulating layer 240 and the upper conductive layer 250 are sequentially laminated. do.
  • FCCL Flexible Copper Clad Laminate
  • FCCL has a structure in which copper foil, which is a conductor, is laminated on polyimide, which is an insulator.
  • the upper conductive layer 250 formed on the interlayer insulating layer 240 is formed through deposition, but the lower conductive layer 230 is mainly formed by patterning a plated copper foil layer.
  • the surface roughness (roughness) of the lower conductive layer 230 is relatively high.
  • the high surface roughness of the lower conductive layer 230 may increase the light reflection ratio more than that of the upper conductive layer 250 and may further affect the pixel electrode.
  • An object of the present invention is to block or minimize voltage noise of a pixel electrode (TFT) caused by a conductive layer by lowering light reflectivity of lower/upper conductive layers in a digitizer.
  • TFT pixel electrode
  • An object of the present invention is to reduce the difference in visibility between the lower and upper conductive layers by minimizing the difference in reflectance between the lower and upper conductive layers according to the difference in thickness and surface roughness of the lower and upper conductive layers in a digitizer.
  • the digitizer of the present invention for achieving this object may include a base layer, a lower conductive layer, a first anti-reflection layer, an interlayer insulating layer, an upper conductive layer, a second anti-reflection layer, and a contact.
  • a lower conductive layer is disposed on the upper surface of the substrate layer.
  • the first antireflection layer is formed on the lower conductive layer and has a reflectance lower than that of the lower conductive layer.
  • the interlayer insulating layer buries the lower conductive layer and the first antireflection layer.
  • An upper conductive layer is formed on the interlayer insulating layer.
  • a second antireflection layer is formed on the upper conductive layer.
  • the second antireflection layer has a reflectance lower than that of the upper conductive layer.
  • the contact penetrates the interlayer insulating layer and electrically connects the lower conductive layer and the upper conductive layer.
  • the surface roughness of the lower conductive layer may be greater than that of the upper conductive layer.
  • the first anti-reflection layer and the second anti-reflection layer may include a copper-oxygen-containing composite material.
  • the copper-oxygen-containing composite material may further contain additional metals.
  • the additional metal may be at least one selected from the group consisting of indium (In), lanthanum (La), cesium (Ce), chromium (Cr), molybdenum (Mo), tungsten (W), magnesium (Mg), and calcium (Ca).
  • the first anti-reflection layer may have a lower copper content than the second anti-reflection layer.
  • the copper-oxygen-containing composite material may include indium (In) as an additional metal.
  • the first anti-reflection layer may have a higher indium (In) content than the second anti-reflection layer.
  • the lower conductive layer and the upper conductive layer may be copper electrodes.
  • the lower conductive layer may include a plurality of first lower conductive lines and a plurality of second lower conductive lines extending in a second direction parallel to the upper surface of the base layer.
  • the upper conductive layer may include a plurality of first upper conductive lines and a plurality of second upper conductive lines extending in a first direction parallel to the top surface of the base layer and perpendicular to the second direction.
  • the contact may include first contacts and second coatacles.
  • the first contacts may electrically connect the first upper conductive lines and the second lower conductive lines to form a first conductive coil.
  • the second contacts electrically connect the first lower conductive lines and the second upper conductive lines and may form a second conductive coil.
  • the first conductive coil extends in the first direction, and a plurality of first conductive coils may be arranged along the second direction.
  • the second conductive coil extends in the second direction, and a plurality of second conductive coils may be arranged along the first direction.
  • each of the first conductive coils may include a plurality of first conductive loops.
  • Each of the second conductive coils may include a plurality of second conductive loops.
  • An image display device of the present invention may include a display panel and the above-described digitizer disposed under the display panel.
  • the digitizer of the present invention having such a configuration can reduce light reflected from the conductive layer by forming an antireflection layer on the conductive layer. As a result, the present invention can block or minimize the occurrence of voltage noise in the pixel electrode (TFT) of the display panel due to the light reflection of the conductive layer.
  • TFT pixel electrode
  • the digitizer of the present invention forms the first anti-reflection layer on the lower conductive layer
  • the copper (Cu) content is lowered and the indium (In) content is increased than the second anti-reflection layer, so that the lower conductive layer has high surface roughness and a large thickness. It is possible to minimize the difference in reflectance due to As a result, visibility of the conductive layer can be blocked or minimized.
  • FIG. 1 is a cross-sectional view of a conventional image display device having a digitizer.
  • FIG. 2 is a cross-sectional view of an image display device having a digitizer according to the present invention.
  • 3 to 6 are plan views and cross-sectional views showing specific embodiments of a digitizer according to the present invention.
  • FIG. 7 shows a result of testing the voltage of a pixel electrode in an image display device having a digitizer according to the present invention.
  • FIG. 2 is a cross-sectional view of an image display device having a digitizer according to the present invention.
  • the image display device may include a display panel 100 , a digitizer 200 , an antireflection layer 300 , and the like.
  • the display panel 100 generates an image, and may include a pixel electrode, a pixel defining layer, a display layer, a counter electrode, an encapsulation layer, and the like.
  • the pixel electrode causes the display layer to emit light by applying a voltage or current to the display layer, and may be electrically connected to the drain electrode of the thin film transistor TFT.
  • the pixel defining layer may define a pixel area by exposing a pixel electrode.
  • the display layer emits color and may include, for example, a liquid crystal layer or an organic light emitting layer.
  • the opposite electrode may be disposed on the pixel defining layer and the display layer.
  • the counter electrode may serve as, for example, a common electrode or a cathode of an image display device.
  • the encapsulation layer protects components of the lower display panel and may be stacked on the opposite electrode.
  • the display panel 100 may include a spacer or the like.
  • the image display device may include a touch panel (not shown), a window panel (not shown), and the like on top of the display panel 100 .
  • the touch panel may be coupled to the front of the display panel to sense a user's touch input through the front surface.
  • the touch panel may include sensing electrodes or sensing channels having a thickness smaller than that of the conductive layer included in the digitizer so as not to be recognized by a user.
  • the touch panel may be coupled to the display panel through an adhesive layer.
  • the window panel is coupled to the front of the touch panel, and may include, for example, a hard coating film or thin glass.
  • a light-shielding pattern may be formed on a peripheral portion of one surface of the window panel.
  • An image display device can define a bezel part or a non-display area by a light-shielding pattern.
  • an image display device may dispose a polarization layer between a window panel and a touch panel.
  • the polarization layer may include a coated polarizer or polarizer.
  • the polarization layer may be directly bonded to one surface of the window panel or attached via an adhesive layer.
  • the polarization layer may be coupled to the touch panel through an adhesive layer.
  • a window panel (not shown), a polarization layer (not shown), a touch panel (not shown), a display panel 100, and a digitizer 200 are disposed in the order from the user's viewing side.
  • the digitizer 200 may be disposed under the display panel 100 so as not to be visually recognized by a user. In this case, the digitizer 200 may be disposed between the display panel 100 and a rear cover (not shown).
  • the digitizer 200 may include a base layer 210, an adhesive layer 220, a lower conductive layer 230, an interlayer insulating layer 240, an upper conductive layer 250, a passivation layer 260, and the like.
  • the base layer 210 is a support layer for forming the lower/upper conductive layers 230 and 250 and the interlayer insulating layer 240, and may be in the form of a film.
  • the base layer 210 is a polymer material applicable to a flexible display, for example, cyclic olefin polymer (COP), polyethylene terephthalate (PET), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), cellulose acetate propionate (CAP), polyethersulfone (PES), cellulose triacetate (TAC), polycarbonate (PC), cyclic olefin copolymer (COC), polymethyl methacrylate (PMMA), and the like.
  • COP cyclic olefin polymer
  • PET polyethylene terephthalate
  • PAR polyacrylate
  • PEI polyetherimide
  • PEN polyethylene na
  • the adhesive layer 220 may be selectively included according to the type of FCCL (Flexible Copper Clad Laminate) used.
  • FCCL Flexible Copper Clad Laminate
  • FCCL usually has a structure in which copper foil, which is a conductor, is laminated on polyimide, which is an insulator.
  • FCCL has a form such as a single side FCCL (Single Side FCCL) in which copper foil exists on only one side and a double side FCCL (Double Side FCCL) in which copper foil is present on both sides.
  • Single Side FCCL Single Side FCCL
  • Double Side FCCL Double Side FCCL
  • a single side FCCL can be used.
  • Single-sided FCCL may have various laminated structures, such as a three-layer laminated FCCL with an adhesive layer between a polyimide film and copper foil, and a two-layer casting FCCL in which polyimide resin is melted and attached to copper foil.
  • the thickness may be as thick as 12 to 18 ⁇ m.
  • the digitizer 200 of the present invention may or may not include the adhesive layer 220 depending on the FCCL used.
  • the adhesive layer 220 may be composed of an insulating adhesive.
  • the insulating layer adhesive may include a thermosetting resin such as an epoxy resin, and may also include a curing agent, a binder, a flame retardant, and the like.
  • the adhesive layer 220 may have a thickness of 5 to 50 ⁇ m. If the thickness is less than 5 ⁇ m, the thickness may not be sufficient to form the circuit pattern, that is, the lower conductive layer 230 . If the thickness exceeds 50 ⁇ m, flexibility may deteriorate.
  • the lower conductive layer 230 forms, for example, a transmission electrode and may be a conductive metal layer having a circuit pattern.
  • Conductive metals include, for example, silver (Ag), gold (Au), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), chromium (Cr), titanium (Ti), tungsten (W) , Niobium (Nb), Tantalum (Ta), Vanadium (V), Iron (Fe), Manganese (Mn), Cobalt (Co), Nickel (Ni), Zinc (Zn), Tin (Sn), Molybdenum (Mo) , calcium (Ca) or an alloy containing at least two or more of these may be used, preferably copper or a copper alloy.
  • the interlayer insulating layer 240 buries and protects the lower conductive layer 230, and is an organic insulating material such as an epoxy-based resin, an acrylic-based resin, a siloxane-based resin, or a polyimide-based resin, or an inorganic material such as silicon oxide or silicon nitride. It can be composed of an insulating material or the like.
  • the interlayer insulating layer 240 is preferably formed of an organic insulating material in order to increase flexibility, and may have a thickness of 15 to 20 ⁇ m.
  • the upper conductive layer 250 is formed on the interlayer insulating layer 240 to form a receiving electrode, for example, and may be a conductive metal layer having a circuit pattern like the lower conductive layer 230 .
  • the conductive metal is silver (Ag), gold (Au), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), chromium (Cr), titanium (Ti), tungsten (W), niobium (Nb), tantalum (Ta), vanadium (V), iron (Fe), manganese (Mn), cobalt (Co), nickel (Ni), zinc (Zn), tin (Sn), molybdenum (Mo), calcium (Ca) or an alloy containing at least two or more of these, preferably copper or a copper alloy.
  • the passivation layer 260 buries and protects the upper conductive layer 250, and is an organic insulating material such as an epoxy-based resin, an acrylic-based resin, a siloxane-based resin, or a polyimide-based resin, or an inorganic insulating material such as silicon oxide or silicon nitride. can be made of matter.
  • an organic insulating material for the passivation layer 260 may have a thickness of 1.5 to 20 ⁇ m.
  • each of the interlayer insulating layer 240 and the passivation layer 260 may include an inorganic insulating material and may have a thickness of about 100 nm to about 500 nm.
  • the thickness of the lower conductive layer 230 may be greater than the thickness of the upper conductive layer 250 .
  • the thickness of the first lower conductive line 232 may be greater than that of the first upper conductive line 252 .
  • the thickness of the lower conductive layer 230 may be about 5 ⁇ m to about 30 ⁇ m, preferably about 10 ⁇ m to about 25 ⁇ m.
  • the thickness of the upper conductive layer 250 may be 6 ⁇ m or less, preferably about 1 ⁇ m to 6 ⁇ m, or 1 ⁇ m to 5 ⁇ m.
  • the antireflection layer 300 blocks or minimizes reflected light from the lower/upper conductive layers 230 and 250, and the first antireflection layer 310 formed on the lower conductive layer 230 and the second antireflection layer 310 formed on the upper conductive layer 250 2 antireflection layer 320 may be included.
  • the anti-reflection layer 300 maintains the electrical conductivity of the lower/upper conductive layers 230 and 250 while lowering the reflectance of the lower/upper conductive layers 230 and 250, and furthermore maintains a contact with the lower/upper conductive layers 230 and 250 made of copper.
  • it can be composed of a copper-oxygen-containing composite material or a copper-added metal-oxygen-containing composite material.
  • the additional metal is at least one selected from the group consisting of indium (In), lanthanum (La), cesium (Ce), chromium (Cr), molybdenum (Mo), tungsten (W), magnesium (Mg), and calcium (Ca). may contain one. It may be preferable to use indium to reduce the high surface roughness of the lower conductive layer 230 .
  • the first and second antireflection layers 310 and 320 may have different composition ratios of copper, indium, and oxygen in consideration of the high surface roughness and relatively large thickness of the lower conductive layer 230. . That is, the first anti-reflection layer 310 may have a lower copper (Cu) content and a higher indium (In) content than the second anti-reflection layer 320 .
  • the first antireflection layer 310 includes 20 to 30 parts by weight of copper, 40 to 50 parts by weight of indium, and 27 to 33 parts by weight of oxygen
  • the second antireflection layer 320 includes 40 to 45 parts by weight of copper, 15 to 20 parts by weight of indium and 37 to 43 parts by weight of oxygen may be included.
  • the first and second anti-reflection layers 310 and 320 may have a sheet resistance of 0.1 to 0.2 ⁇ / ⁇ .
  • the sheet resistance of the first and second anti-reflection layers 310 and 320 exceeds 0.2 ⁇ / ⁇ , electrical conduction characteristics may be deteriorated, and thus sensitivity may deteriorate.
  • the metal ratio may be high and the antireflection property may deteriorate.
  • the first and second anti-reflection layers 310 and 320 may be formed to a thickness of 10 to 60 nm.
  • the first and second anti-reflection layers 310 and 320 may be formed by a deposition process such as sputtering.
  • the first anti-reflection layer 310 may include, for example, 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen.
  • the sputtering process can be performed by setting the target to 30% copper, 60% indium, and 10% oxygen, setting the process conditions to 10 sccm of oxygen partial pressure and 30 sccm of argon partial pressure, and setting the plasma power to 50 W. .
  • the second anti-reflection layer 320 may include, for example, 40 parts by weight of copper, 20 parts by weight of indium, and 40 parts by weight of oxygen.
  • the sputtering process can be performed by setting the target to 50% copper, 30% indium, and 20% oxygen, setting the process conditions to 1 sccm of oxygen partial pressure and 50 sccm of argon partial pressure, and setting the plasma power to 150 W. .
  • FIG. 3 to 6 are plan views and cross-sectional views showing specific embodiments of a digitizer according to the present invention.
  • FIG. 3 is a schematic plan view illustrating a first conductive coil included in a digitizer.
  • 4 is a cross-sectional view taken in the thickness direction along line II' shown in FIG. 3 .
  • first direction and second direction are defined as a first direction and a second direction.
  • first direction and the second direction may perpendicularly cross each other.
  • the first direction may correspond to a width direction, a row direction, or an X-direction of the digitizer 100 .
  • the second direction may correspond to a longitudinal direction, a column direction, or a Y-direction of the digitizer 100 .
  • the digitizer may include a lower conductive layer 230 and an upper conductive layer 250 formed on a base layer 210 .
  • the lower conductive layer 230 and the upper conductive layer 250 may be separated into different layers with the interlayer insulating layer 240 therebetween.
  • the lower conductive layer 230 may include a first lower conductive line 232 (see FIG. 5 ) and a second lower conductive line 234 .
  • the upper conductive layer 250 may include a first upper conductive line 252 and a second upper conductive line 254 (see FIG. 5 ).
  • the first lower conductive line 232 and the second lower conductive line 234 may extend in the second direction.
  • the first upper conductive line 252 and the second upper conductive line 254 may extend in the first direction.
  • the second lower conductive line 234 and the second upper conductive line 254 may have smaller widths than the first lower conductive line 232 and the first upper conductive line 252 .
  • the digitizer may include a first conductive coil 50 .
  • the first conductive coil 50 may be provided as a first direction (or row direction) conductive coil.
  • the second lower conductive line 234 of the lower conductive layer 230 and the first upper conductive line 252 of the upper conductive layer 250 are combined by first contacts 272. can be defined.
  • the second lower conductive line 234 and the first upper conductive line 252 may be combined together to form an electromagnetic induction coil.
  • the first upper conductive line 252 and the second lower conductive line 234 together form the first conductive coil 50 and may be provided together as a sensing line for an input pen through electromagnetic induction.
  • first upper conductive line 252 and the second lower conductive line 234 may be electrically connected to each other through the first contact 272 .
  • the plurality of first upper conductive lines 252 and the plurality of second lower conductive lines 234 are electrically connected to each other through the plurality of first contacts 272 to form one first conductive coil 50
  • a plurality of conductive loops may be included therein. For example, four row direction conductive loops may be included in one first conductive coil 50 .
  • a first row-wise conductive loop 50a, a second row-wise conduction loop 50b, a third row-direction conduction loop 50c and The fourth row direction conductive loops 50d may be sequentially arranged.
  • the row direction conductive loops may have different sizes or areas in the planar direction.
  • the size of the first rowwise conductive loop 50a, the second rowwise conductive loop 50b, the third rowwise conductive loop 50c, and the fourth rowwise conductive loop 50d are sequentially increased in size. can do.
  • the first contact 272 may pass through the interlayer insulating layer 240 through the first contact hole and be substantially integrally formed with the first upper conductive line 252 .
  • a first input line 282 and a first output line 284 may be connected to any one of the row direction conductive loops.
  • the current input from the first input line 282 alternately circulates through the lower conductive layer 230 and the upper conductive layer 250 through the row direction conductive loops, and may be discharged through the first output line 284.
  • the first input line 282 may be connected to the first row conductive loop 50a
  • the first output line 284 may be connected to the fourth row conductive loop 50d.
  • the first input line 282 and the first output line 284 may be included in the lower conductive layer 230 .
  • the lower conductive layer 230 may further include a first internal connection line 234a.
  • neighboring row direction conductive loops may be connected to each other through the first inner connection line 234a.
  • the digitizer may include a second conductive coil 70 .
  • the second conductive coil 70 may be provided as a second direction (or column direction) conductive coil.
  • the first lower conductive line 232 of the lower conductive layer 230 and the second upper conductive line 254 of the upper conductive layer 250 are combined by second contacts 274 . can be defined.
  • the second upper conductive line 254 and the first lower conductive line 232 may be combined together to form an electromagnetic induction coil.
  • the first lower conductive line 232 and the second upper conductive line 254 together form the second conductive coil 70 and may be provided together as a sensing line for an input pen through electromagnetic induction.
  • first lower conductive line 232 and the second upper conductive line 254 may be electrically connected to each other through the second contact 274 .
  • the plurality of first lower conductive lines 232 and the plurality of second upper conductive lines 254 are electrically connected to each other through the plurality of second contacts 274 to form one second conductive coil 70.
  • a plurality of conductive loops may be included therein. For example, four column direction conductive loops may be included in one second conductive coil 70 .
  • a first column direction conductive loop 70a, a second column direction conductive loop 70b, a third column direction conductive loop 70c and The fourth column direction conductive loops 70d may be sequentially arranged.
  • the column direction conductive loops may have different sizes or areas in the planar direction.
  • the first column-wise conductive loop 70a, the second column-wise conductive loop 70b, the third column-wise conductive loop 70c, and the fourth column-wise conductive loop 70d sequentially increase in size. can do.
  • the second contact 274 may pass through the interlayer insulating layer 240 through the second contact hole and be substantially integrally formed with the first lower conductive line 232 .
  • a second input line 283 and a second output line 285 may be connected to any one of the column direction conductive loops.
  • the current input from the second input line 283 alternately circulates through the lower conductive layer 230 and the upper conductive layer 250 through column-direction conductive loops, and may be discharged through the second output line 285.
  • the second input line 283 may be connected to the first column direction conductive loop 70a
  • the second discharge line 285 may be connected to the fourth column direction conductive loop 70d.
  • the second input line 283 and the second output line 285 may be included in the lower conductive layer 230 .
  • the upper conductive layer 250 may further include an external connection line 254a.
  • the second input line 283 and the second output line 285 may be connected to the column direction conductive loops through the third contact by the external connection line 254a.
  • the external connection line 254a may be connected to two different second conductive coils 70 .
  • the output line 285 connected to one second conductive coil 70 may be connected to the input line 283 of another second conductive coil 70 through an external connection line 254a.
  • the upper conductive layer 250 may further include a second internal connection line.
  • a second internal connection line For example, adjacent column direction conductive loops within the second conductive coil 70 may be connected to each other by a second internal connection line.
  • 3 and 4 show that four conductive loops are included in one conductive coil, the number of conductive loops in the conductive coil may be adjusted in consideration of the size and resolution of the image display device.
  • FIG. 5 is a schematic plan view illustrating a digitizer according to example embodiments. For convenience of explanation, a detailed structure/configuration of a conductive coil is omitted in FIG. 5 .
  • a plurality of first conductive coils 50 and second conductive coils 70 may be arranged on the upper surface of the base layer 210 .
  • the first conductive coil 50 may extend in a first direction or a row direction.
  • the plurality of first conductive coils 50 may be arranged along the second direction or the column direction.
  • first conductive coils 50-1 to 50-n may be sequentially arranged in the second direction (n is a natural number).
  • the second conductive coil 70 may extend in the second direction or column direction.
  • the plurality of second conductive coils 70 may be arranged along the first direction or row direction.
  • m second conductive coils 70-1 to 70-m may be sequentially arranged along the first direction.
  • a lower conductive layer having a thickness of 12 ⁇ m is formed on a polyimide substrate by copper plating with an adhesive as a medium.
  • the lower conductive layer includes a 40 nm thick first antireflection layer made of a copper alloy composed of 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen.
  • the upper conductive layer is formed of copper to a thickness of 2 ⁇ m.
  • the upper conductive layer includes a second antireflection layer made of copper alloy having a thickness of 0.04 ⁇ m and composed of 40 parts by weight of copper, 20 parts by weight of indium, and 40 parts by weight of oxygen.
  • the lower conductive layer and the upper conductive layer included an IZO film to a thickness of 0.04 ⁇ m instead of the first anti-reflection layer and the second anti-reflection layer, and the rest of the conditions were the same as those of Example.
  • Table 1 below shows the results of measuring the cotton quality of Examples and Comparative Examples 1 and 2.
  • 'Optimap PSD' was used as the surface roughness measurement equipment, and the measurement conditions were set at 0.1 to 30.3 mm for the incident light wavelength while the distance between the non-contact sample and the measurement equipment was 1 cm.
  • the light reflected from the light source incident on the sample was detected by the CCD sensor.
  • the surface quality is high in the measured value, it indicates that light is reflected in various directions and incident to the pixel area in the panel, resulting in pixel defects (deterioration of panel quality). Looking at the surface quality measurement values in Table 1 above, / It can be seen that when an antireflection layer of copper alloy is formed on the upper conductive layer, the surface quality can be reduced by 100% or more, that is, improved compared to Comparative Examples 1 and 2.
  • the measurement equipment uses 'HP4155A Semiconductor Parameter Analyzer' to measure the electrical characteristics of TFT according to illumination stress in the voltage range of -20 ⁇ +20 (V), that is, I (current) -V (voltage) characteristics. measured.
  • a first antireflection layer 310 of a copper alloy including 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen
  • the copper alloy In the case of forming the second antireflection layer 320 (including 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen) (Cu/copper alloy, Example), the amount of change in the operating voltage (gate voltage) of the pixel electrode are showing
  • the TFT is turned on and operates normally in the region where the gate voltage is 0 V, whereas in Comparative Examples 1 and 2, the lower conductive layer 230 ) and the light reflected from the upper conductive layer 250 is incident on the TFT element, and the gate voltage changes in the negative direction of the X-axis up to the -20 V region, and it can be seen that the TFT operates unstablely. In this way, when the copper/indium alloy antireflection layer is formed on the digitizer conductive layer, voltage noise may be hardly induced in the pixel electrode of the display panel.
  • Table 2 measures the resistance and reflectance of the loop made of a combination of the lower conductive layer and the upper conductive layer after 24 hours of reliability conditions at a temperature of 60 ° C and a relative humidity of 90% for Examples and Comparative Examples 1 and 2. is a result
  • Example Comparative Example 1 Comparative Example 2 Loop Resistance ( ⁇ ) 19.5 202 22.5 Loop reflectance (%) 8.4 57.3 48.5

Abstract

This digitizer comprises: a base layer; a lower conductive layer arranged on a top surface of the base layer; a first anti-reflective layer formed on the lower conductive layer and having a reflectivity lower than that of the lower conductive layer; an interlayer insulating layer burying the lower conductive layer and the first anti-reflective layer; an upper conductive layer formed on the interlayer insulating layer; a second anti-reflective layer formed on the upper conductive layer and having a reflectivity lower than that of the upper conductive layer; and a contact electrically connecting the lower conductive layer with the upper conductive layer through the interlayer insulating layer.

Description

디지타이저 및 이를 갖는 화상 표시 장치Digitizer and image display device having the same
본 발명은 디지타이저에 관한 것으로, 상세하게는 디지타이저 도전층의 반사를 차단 내지 최소화할 수 있는 디지타이저에 관한 것이다.The present invention relates to a digitizer, and more particularly, to a digitizer capable of blocking or minimizing reflection of a conductive layer of the digitizer.
화상 표시 장치(Display)는 대부분 사용자가 손가락이나 전자 펜으로 화면을 터치하여 입력하는 터치 입력 방식을 적용하고 있다.Most image display devices (Display) apply a touch input method in which a user inputs by touching a screen with a finger or an electronic pen.
터치 입력 방식은 사용자가 화면의 특정 위치를 직접 터치하여 입력할 수 있어 직관적이고 편리하다. 특히, 펜을 이용한 터치 입력 방식은 손가락을 이용한 터치 입력보다 정밀한 좌표를 지정할 수 있어, 캐드와 같은 그래픽 작업 등에 적합하다. 이러한 펜을 이용한 터치 입력 방식에는 디지타이저가 있다.The touch input method is intuitive and convenient because the user can input by directly touching a specific location on the screen. In particular, a touch input method using a pen can designate more precise coordinates than a touch input method using a finger, so it is suitable for graphic work such as CAD. A touch input method using such a pen includes a digitizer.
도 1은 종래의 디지타이저를 갖는 화상 표시 장치의 단면도이다.1 is a cross-sectional view of a conventional image display device having a digitizer.
도 1에 도시한 바와 같이, 종래의 화상 표시 장치는 표시 패널(100), 디지타이저(200) 등을 포함하고 있다.As shown in FIG. 1, a conventional image display device includes a display panel 100 and a digitizer 200.
표시 패널(100)은 기판 상에 화소 전극(TFT), 화소 정의막, 표시층, 대향 전극, 인캡슐레이션층 등을 포함하여 색상을 구현할 수 있다.The display panel 100 may implement color by including a pixel electrode (TFT), a pixel defining layer, a display layer, a counter electrode, an encapsulation layer, and the like on a substrate.
디지타이저(200)는 표시 패널(100)의 후방에 결합하여 펜의 터치 좌표를 디지털 데이터로 바꾼다. 디지타이저(200)는 기재층(210), 접착층(220), 하부 도전층(230), 층간 절연층(240), 상부 도전층(250), 패시베이션층(260) 등을 포함할 수 있다.The digitizer 200 is coupled to the rear of the display panel 100 and converts the touch coordinates of the pen into digital data. The digitizer 200 may include a base layer 210, an adhesive layer 220, a lower conductive layer 230, an interlayer insulating layer 240, an upper conductive layer 250, a passivation layer 260, and the like.
종래의 화상 표시 장치는, 표시 패널(100)의 화소에서 광이 방출될 때, 방출 광이 디지타이저(200)의 하부/상부 도전층(230,250)에서 반사될 수 있다. 이러한 반사광은 표시 패널(100)의 화소 전극에 영향을 주어 화소 전극에 전압 노이즈로 작용하여 화면 불량을 유발할 수 있다. In a conventional image display device, when light is emitted from pixels of the display panel 100 , the emitted light may be reflected from the lower/upper conductive layers 230 and 250 of the digitizer 200 . Such reflected light may affect the pixel electrodes of the display panel 100 and act as voltage noise on the pixel electrodes, causing screen defects.
한편, 디지타이저(200)는 FCCL(Flexible Copper Clad Laminate, 연성동박 적층체)을 이용하여 하부 도전층(230)을 패턴 형성하고, 이후 층간 절연층(240)과 상부 도전층(250)을 차례로 적층한다.Meanwhile, in the digitizer 200, the lower conductive layer 230 is patterned using FCCL (Flexible Copper Clad Laminate), and then the interlayer insulating layer 240 and the upper conductive layer 250 are sequentially laminated. do.
그런데, FCCL은 절연체인 폴리이미드(Polyimide)에 도전체인 동박을 적층한 구조를 갖는다. 층간 절연층(240) 상에 형성되는 상부 도전층(250)은 증착을 통해 형성하지만, 하부 도전층(230)은 주로 도금 동박층을 패터닝하여 형성한다. 그 결과, 하부 도전층(230)의 표면 조도(거칠기)가 상대적으로 높다. 하부 도전층(230)의 높은 표면 조도는 상부 도전층(250)보다 광사반율을 더 높여 화소 전극에 더 영향을 줄 수 있다.However, FCCL has a structure in which copper foil, which is a conductor, is laminated on polyimide, which is an insulator. The upper conductive layer 250 formed on the interlayer insulating layer 240 is formed through deposition, but the lower conductive layer 230 is mainly formed by patterning a plated copper foil layer. As a result, the surface roughness (roughness) of the lower conductive layer 230 is relatively high. The high surface roughness of the lower conductive layer 230 may increase the light reflection ratio more than that of the upper conductive layer 250 and may further affect the pixel electrode.
본 발명은 디지타이저에서 하부/상부 도전층의 광반사율을 낮추어 도전층으로 인한 화소 전극(TFT)의 전압 노이즈 발생을 차단 내지 최소화하는 것을 목적으로 한다.An object of the present invention is to block or minimize voltage noise of a pixel electrode (TFT) caused by a conductive layer by lowering light reflectivity of lower/upper conductive layers in a digitizer.
본 발명은 디지타이저에서 하부/상부 도전층의 두께 및 표면 조도 차이 등에 따른 하부/상부 도전층의 반사율 차이를 최소화하여 하부/상부 도전층의 시인성 차이를 줄이는 것을 목적으로 한다.An object of the present invention is to reduce the difference in visibility between the lower and upper conductive layers by minimizing the difference in reflectance between the lower and upper conductive layers according to the difference in thickness and surface roughness of the lower and upper conductive layers in a digitizer.
이러한 목적을 달성하기 위한 본 발명의 디지타이저는 기재층, 하부 도전층, 제1 반사 방지층, 층간 절연층, 상부 도전층, 제2 반사 방지층, 및 콘택 등을 포함할 수 있다.The digitizer of the present invention for achieving this object may include a base layer, a lower conductive layer, a first anti-reflection layer, an interlayer insulating layer, an upper conductive layer, a second anti-reflection layer, and a contact.
하부 도전층은 기재층의 상면 상에 배치된다.A lower conductive layer is disposed on the upper surface of the substrate layer.
제1 반사 방지층은 하부 도전층에 형성되며 하부 도전층 보다 낮은 반사율을 갖는다.The first antireflection layer is formed on the lower conductive layer and has a reflectance lower than that of the lower conductive layer.
층간 절연층은 하부 도전층과 제1 반사 방지층을 매립한다.The interlayer insulating layer buries the lower conductive layer and the first antireflection layer.
상부 도전층은 층간 절연층에 형성된다.An upper conductive layer is formed on the interlayer insulating layer.
제2 반사 방지층은 상부 도전층에 형성된다. 제2 반사 방지층은 상부 도전층 보다 낮은 반사율을 갖는다.A second antireflection layer is formed on the upper conductive layer. The second antireflection layer has a reflectance lower than that of the upper conductive layer.
콘택은 층간 절연층을 관통하여 하부 도전층과 상부 도전층을 전기적으로 연결한다.The contact penetrates the interlayer insulating layer and electrically connects the lower conductive layer and the upper conductive layer.
본 발명의 디지타이저에서, 하부 도전층은 상부 도전층 보다 표면 조도가 클 수 있다.In the digitizer of the present invention, the surface roughness of the lower conductive layer may be greater than that of the upper conductive layer.
본 발명의 디지타이저에서, 제1 반사 방지층과 제2 반사 방지층은 구리-산소 함유 복합 물질을 포함할 수 있다.In the digitizer of the present invention, the first anti-reflection layer and the second anti-reflection layer may include a copper-oxygen-containing composite material.
본 발명의 디지타이저에서, 구리-산소 함유 복합 물질은 추가 금속을 더 함유할 수 있다. 추가 금속은 인듐(In), 란타늄(La), 세슘(Ce), 크롬(Cr), 몰리브덴(Mo), 텅스텐(W), 마그네슘(Mg) 및 칼슘(Ca)으로 구성된 그룹으로부터 선택된 적어도 하나일 수 있다.In the digitizer of the present invention, the copper-oxygen-containing composite material may further contain additional metals. The additional metal may be at least one selected from the group consisting of indium (In), lanthanum (La), cesium (Ce), chromium (Cr), molybdenum (Mo), tungsten (W), magnesium (Mg), and calcium (Ca). can
본 발명의 디지타이저에서, 제1 반사 방지층은 제2 반사 방지층 보다 구리 함유량이 낮을 수 있다.In the digitizer of the present invention, the first anti-reflection layer may have a lower copper content than the second anti-reflection layer.
본 발명의 디지타이저에서, 구리-산소 함유 복합 물질은 추가 금속으로 인듐(In)을 포함할 수 있다. 제1 반사 방지층은 제2 반사 방지층 보다 인듐(In) 함유량이 높을 수 있다.In the digitizer of the present invention, the copper-oxygen-containing composite material may include indium (In) as an additional metal. The first anti-reflection layer may have a higher indium (In) content than the second anti-reflection layer.
본 발명의 디지타이저에서, 하부 도전층과 상부 도전층은 구리 전극일 수 있다.In the digitizer of the present invention, the lower conductive layer and the upper conductive layer may be copper electrodes.
본 발명의 디지타이저에서, 하부 도전층은 기재층의 상면에 평행한 제2 방향으로 연장하는 복수의 제1 하부 도전 라인들 및 복수의 제2 하부 도전 라인들을 포함할 수 있다. 상부 도전층은 기재층의 상면에 평행하며 제2 방향과 수직한 제1 방향으로 연장하는 복수의 제1 상부 도전 라인들 및 복수의 제2 상부 도전 라인들을 포함할 수 있다.In the digitizer of the present invention, the lower conductive layer may include a plurality of first lower conductive lines and a plurality of second lower conductive lines extending in a second direction parallel to the upper surface of the base layer. The upper conductive layer may include a plurality of first upper conductive lines and a plurality of second upper conductive lines extending in a first direction parallel to the top surface of the base layer and perpendicular to the second direction.
본 발명의 디지타이저에서, 콘택은 제1 콘택들과 제2 코택들을 포함할 수 있다. 제1 콘택들은 제1 상부 도전 라인들 및 제2 하부 도전 라인들을 전기적으로 연결시키며 제1 도전 코일을 형성할 수 있다. 제2 콘택들은 제1 하부 도전 라인들 및 제2 상부 도전 라인들을 전기적으로 연결시키며, 제2 도전 코일을 형성할 수 있다.In the digitizer of the present invention, the contact may include first contacts and second coatacles. The first contacts may electrically connect the first upper conductive lines and the second lower conductive lines to form a first conductive coil. The second contacts electrically connect the first lower conductive lines and the second upper conductive lines and may form a second conductive coil.
본 발명의 디지타이저에서, 제1 도전 코일은 제1 방향으로 연장하며 제2 방향을 따라 복수의 제1 도전 코일들이 배열될 수 있다. 제2 도전 코일은 제2 방향으로 연장하며 제1 방향을 따라 복수의 제2 도전 코일들이 배열될 수 있다.In the digitizer of the present invention, the first conductive coil extends in the first direction, and a plurality of first conductive coils may be arranged along the second direction. The second conductive coil extends in the second direction, and a plurality of second conductive coils may be arranged along the first direction.
본 발명의 디지타이저에서, 제1 도전 코일들은 각각 복수의 제1 도전 루프들을 포함할 수 있다. 제2 도전 코일들은 각각 복수의 제2 도전 루프들을 포함할 수 있다.In the digitizer of the present invention, each of the first conductive coils may include a plurality of first conductive loops. Each of the second conductive coils may include a plurality of second conductive loops.
본 발명의 화상 표시 장치는 표시 패널, 및 표시 패널 아래에 배치되는 위에서 설명한 디지타이저를 포함할 수 있다.An image display device of the present invention may include a display panel and the above-described digitizer disposed under the display panel.
이러한 구성을 갖는 본 발명의 디지타이저는 도전층에 반사 방지층을 형성함으로써 도전층에서 반사되는 광을 낮출 수 있다. 그 결과, 본 발명은 도전층의 광반사로 인해 표시 패널의 화소 전극(TFT)에서 전압 노이즈가 발생하는 것을 차단 내지 최소화할 수 있다.The digitizer of the present invention having such a configuration can reduce light reflected from the conductive layer by forming an antireflection layer on the conductive layer. As a result, the present invention can block or minimize the occurrence of voltage noise in the pixel electrode (TFT) of the display panel due to the light reflection of the conductive layer.
또한, 본 발명의 디지타이저는 하부 도전층에 제1 반사 방지층을 형성할 때 제2 반사 방지층보다 구리(Cu) 함량을 낮추고 인듐(In) 함량을 높임으로써 하부 도전층의 높은 표면 조도와 큰 두께로 인한 반사율 차이를 최소화할 수 있다. 그 결과, 도전층이 시인되는 것을 차단 내지 최소화할 수 있다.In addition, when the digitizer of the present invention forms the first anti-reflection layer on the lower conductive layer, the copper (Cu) content is lowered and the indium (In) content is increased than the second anti-reflection layer, so that the lower conductive layer has high surface roughness and a large thickness. It is possible to minimize the difference in reflectance due to As a result, visibility of the conductive layer can be blocked or minimized.
도 1은 종래의 디지타이저를 갖는 화상 표시 장치의 단면도이다.1 is a cross-sectional view of a conventional image display device having a digitizer.
도 2는 본 발명에 따른 디지타이저를 갖는 화상 표시 장치의 단면도이다.2 is a cross-sectional view of an image display device having a digitizer according to the present invention.
도 3~6은 본 발명에 따른 디지타이저의 구체적 실시예를 도시하는 평면도, 단면도이다. 3 to 6 are plan views and cross-sectional views showing specific embodiments of a digitizer according to the present invention.
도 7은 본 발명에 따른 디지타이저를 갖는 화상 표시 장치에서 화소 전극의 전압을 테스트한 결과를 도시하고 있다.7 shows a result of testing the voltage of a pixel electrode in an image display device having a digitizer according to the present invention.
이하, 첨부도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 디지타이저를 갖는 화상 표시 장치의 단면도이다.2 is a cross-sectional view of an image display device having a digitizer according to the present invention.
도 2에 도시한 바와 같이, 본 발명에 따른 화상 표시 장치는 표시 패널(100), 디지타이저(200), 반사 방지층(300) 등을 포함할 수 있다.As shown in FIG. 2 , the image display device according to the present invention may include a display panel 100 , a digitizer 200 , an antireflection layer 300 , and the like.
표시 패널(100)은 화상을 생성하는 것으로, 화소 전극, 화소 정의막, 표시층, 대향 전극, 인캡슐레이션층 등을 포함할 수 있다.The display panel 100 generates an image, and may include a pixel electrode, a pixel defining layer, a display layer, a counter electrode, an encapsulation layer, and the like.
화소 전극은 표시층에 전압 또는 전류를 인가하여 표시층을 발광시키는 것으로, 박막 트랜지스터(TFT)의 드레인 전극과 전기적으로 연결될 수 있다.The pixel electrode causes the display layer to emit light by applying a voltage or current to the display layer, and may be electrically connected to the drain electrode of the thin film transistor TFT.
화소 정의막은 화소 전극을 노출시켜 화소 영역을 정의할 수 있다.The pixel defining layer may define a pixel area by exposing a pixel electrode.
표시층은 색을 방출하는 것으로, 예를 들어 액정층 또는 유기 발광층을 포함할 수 있다.The display layer emits color and may include, for example, a liquid crystal layer or an organic light emitting layer.
대향 전극은 화소 정의막 및 표시층 상에 배치될 수 있다. 대향 전극은 예를 들어 화상 표시 장치의 공통 전극 또는 캐소드로 제공될 수 있다.The opposite electrode may be disposed on the pixel defining layer and the display layer. The counter electrode may serve as, for example, a common electrode or a cathode of an image display device.
인캡슐레이션층은 하부의 표시 패널의 구성요소들을 보호하는 것으로, 대향 전극 상에 적층될 수 있다.The encapsulation layer protects components of the lower display panel and may be stacked on the opposite electrode.
그 밖에, 표시 패널(100)은 스페이서(spacer) 등을 포함할 수 있다.In addition, the display panel 100 may include a spacer or the like.
도 1에 도시하지 않았지만, 화상 표시 장치는 표시 패널(100)의 상부에 터치 패널(미도시), 윈도우 패널(미도시) 등을 포함할 수 있다.Although not shown in FIG. 1 , the image display device may include a touch panel (not shown), a window panel (not shown), and the like on top of the display panel 100 .
터치 패널은 표시 패널의 전방에 결합하여, 전방 표면을 통해 입력되는 사용자 터치를 감지할 수 있다. 터치 패널은 사용자에게 시인되지 않도록 디지타이저에 포함된 도전층보다 작은 두께의 센싱 전극 또는 센싱 채널들을 포함할 수 있다. 터치 패널은 점접착층을 통해 표시 패널과 결합될 수 있다.The touch panel may be coupled to the front of the display panel to sense a user's touch input through the front surface. The touch panel may include sensing electrodes or sensing channels having a thickness smaller than that of the conductive layer included in the digitizer so as not to be recognized by a user. The touch panel may be coupled to the display panel through an adhesive layer.
윈도우 패널은 터치 패널의 전방에 결합하는 것으로, 예를 들어 하드 코팅 필름, 박형 글래스를 포함할 수 있다. 윈도우 패널의 일면 주변부에는 차광 패턴을 형성할 수 있다. 화상 표시 장치는, 차광 패턴에 의해, 베젤부 혹은 비표시 영역을 정의할 수 있다.The window panel is coupled to the front of the touch panel, and may include, for example, a hard coating film or thin glass. A light-shielding pattern may be formed on a peripheral portion of one surface of the window panel. An image display device can define a bezel part or a non-display area by a light-shielding pattern.
도 1에 도시하지 않았지만, 화상 표시 장치는 윈도우 패널과 터치 패널 사이에 편광층을 배치할 수 있다. 편광층은 코팅형 편광자 또는 편광판을 포함할 수 있다. 편광층은 윈도우 패널의 일면과 직접 접합 또는 점접착층을 매개로 부착될 수 있다. 편광층은 터치 패널과 점접착층을 통해 결합될 수 있다.Although not shown in FIG. 1 , an image display device may dispose a polarization layer between a window panel and a touch panel. The polarization layer may include a coated polarizer or polarizer. The polarization layer may be directly bonded to one surface of the window panel or attached via an adhesive layer. The polarization layer may be coupled to the touch panel through an adhesive layer.
이러한 구성들을 포함하는 화상 표시 장치는 사용자의 시인측으로부터 윈도우 패널(미도시), 편광층(미도시), 터치 패널(미도시), 표시 패널(100), 디지타이저(200)의 순서로 배치될 수 있다. In an image display device including these configurations, a window panel (not shown), a polarization layer (not shown), a touch panel (not shown), a display panel 100, and a digitizer 200 are disposed in the order from the user's viewing side. can
디지타이저(200)는 사용자에게 시인되지 않도록 표시 패널(100) 아래에 배치할 수 있다. 이 경우, 디지타이저(200)는 표시 패널(100)과 후방 커버(미도시) 사이에 배치될 수 있다.The digitizer 200 may be disposed under the display panel 100 so as not to be visually recognized by a user. In this case, the digitizer 200 may be disposed between the display panel 100 and a rear cover (not shown).
디지타이저(200)는 기재층(210), 접착층(220), 하부 도전층(230), 층간 절연층(240), 상부 도전층(250), 패시베이션층(260) 등을 포함할 수 있다.The digitizer 200 may include a base layer 210, an adhesive layer 220, a lower conductive layer 230, an interlayer insulating layer 240, an upper conductive layer 250, a passivation layer 260, and the like.
기재층(210)은 하부/상부 도전층(230,250)과 층간 절연층(240)을 형성하기 위한 지지층으로, 필름 형태를 사용할 수 있다. 기재층(210)은 플렉서블 디스플레이에 적용할 수 있는 고분자 재질, 예를 들어 환형올레핀중합체(COP), 폴리에틸렌테레프탈레이트(PET), 폴리아크릴레이트(PAR), 폴리에테르이미드(PEI), 폴리에틸렌나프탈레이트(PEN), 폴리페닐렌설파이드(PPS), 폴리알릴레이트(polyallylate), 폴리이미드(PI), 셀룰로오스 아세테이트 프로피오네이트(CAP), 폴리에테르술폰(PES), 셀룰로오스 트리아세테이트(TAC), 폴리카보네이트(PC), 환형올레핀공중합체(COC), 폴리메틸메타크릴레이트(PMMA) 등으로 구성할 수 있다. 이들 재질 중에서, 폴리이미드가 가장 안정적인 벤딩 특성을 발휘하므로, 폴리이미드를 사용하는 것이 바람직할 수 있다.The base layer 210 is a support layer for forming the lower/upper conductive layers 230 and 250 and the interlayer insulating layer 240, and may be in the form of a film. The base layer 210 is a polymer material applicable to a flexible display, for example, cyclic olefin polymer (COP), polyethylene terephthalate (PET), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), cellulose acetate propionate (CAP), polyethersulfone (PES), cellulose triacetate (TAC), polycarbonate (PC), cyclic olefin copolymer (COC), polymethyl methacrylate (PMMA), and the like. Among these materials, since polyimide exhibits the most stable bending properties, it may be preferable to use polyimide.
접착층(220)은 사용하는 FCCL(Flexible Copper Clad Laminate, 연성동박적층체)의 형태에 따라 선택적으로 포함할 수 있다.The adhesive layer 220 may be selectively included according to the type of FCCL (Flexible Copper Clad Laminate) used.
FCCL은 보통 절연체인 폴리이미드(Polyimide)에 도전체인 동박을 적층한 구조를 갖는다. FCCL은 동박이 한쪽 면에만 존재하는 단면 FCCL(Single Side FCCL), 양쪽 면에 존재하는 양면 FCCL(Double Side FCCL) 등의 형태가 있는데, 본 발명에서는 단면 FCCL을 사용할 수 있다.FCCL usually has a structure in which copper foil, which is a conductor, is laminated on polyimide, which is an insulator. FCCL has a form such as a single side FCCL (Single Side FCCL) in which copper foil exists on only one side and a double side FCCL (Double Side FCCL) in which copper foil is present on both sides. In the present invention, a single side FCCL can be used.
단면 FCCL은 폴리이미드 필름과 동박 사이에 접착층이 있는 3층 라미네이팅 FCCL, 동박에 폴리이미드 레진(Resin)을 녹여 붙이는 2층 캐스팅 FCCL 등의 다양한 적층 구조가 있을 수 있다. 이러한 적층 구조에서, 동박은 보통 전주 도금이나 압연 방식으로 형성하므로, 두께가 12~18㎛로 두꺼울 수 있다.Single-sided FCCL may have various laminated structures, such as a three-layer laminated FCCL with an adhesive layer between a polyimide film and copper foil, and a two-layer casting FCCL in which polyimide resin is melted and attached to copper foil. In such a laminated structure, since the copper foil is usually formed by electroforming or rolling, the thickness may be as thick as 12 to 18 μm.
이와 같이, FCCL은 접착층이 존재하는 형태와 존재하지 않는 형태가 있으므로, 본 발명의 디지타이저(200)은 사용하는 FCCL에 따라 접착층(220)을 포함할 수도 있고 그렇지 않을 수도 있다.In this way, since the FCCL has a form with and without an adhesive layer, the digitizer 200 of the present invention may or may not include the adhesive layer 220 depending on the FCCL used.
접착층(220)을 포함하는 경우, 접착층(220)은 절연성 접착제로 구성할 수 있다. 절연층 접착제는 에폭시 수지 등의 열경화성 수지를 포함할 수 있고, 그 밖에 경화제, 바인더, 난연제 등도 포함할 수 있다.In the case of including the adhesive layer 220, the adhesive layer 220 may be composed of an insulating adhesive. The insulating layer adhesive may include a thermosetting resin such as an epoxy resin, and may also include a curing agent, a binder, a flame retardant, and the like.
접착층(220)은 5~50㎛ 두께로 구성할 수 있다. 두께가 5㎛ 미만이면, 회로 패턴, 즉 하부 도전층(230)을 형성하기에 두께가 충분하지 않을 수 있다. 두께가 50㎛를 초과하면, 굴곡성이 악화될 수 있다. The adhesive layer 220 may have a thickness of 5 to 50 μm. If the thickness is less than 5 μm, the thickness may not be sufficient to form the circuit pattern, that is, the lower conductive layer 230 . If the thickness exceeds 50 μm, flexibility may deteriorate.
하부 도전층(230)은 예를 들어 송신 전극을 형성하는 것으로, 회로 패턴을 갖는 도전 금속층일 수 있다. 도전 금속은 예를 들어 은(Ag), 금(Au), 구리(Cu), 알루미늄(Al), 백금(Pt), 팔라듐(Pd), 크롬(Cr), 티타늄(Ti), 텅스텐(W), 니오븀(Nb), 탄탈륨(Ta), 바나듐(V), 철(Fe), 망간(Mn), 코발트(Co), 니켈(Ni), 아연(Zn), 주석(Sn), 몰리브덴(Mo), 칼슘(Ca) 또는 이들 중 적어도 2 이상을 함유하는 합금을 사용할 수 있는데, 바람직하게는 구리 또는 구리 합금으로 구성할 수 있다.The lower conductive layer 230 forms, for example, a transmission electrode and may be a conductive metal layer having a circuit pattern. Conductive metals include, for example, silver (Ag), gold (Au), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), chromium (Cr), titanium (Ti), tungsten (W) , Niobium (Nb), Tantalum (Ta), Vanadium (V), Iron (Fe), Manganese (Mn), Cobalt (Co), Nickel (Ni), Zinc (Zn), Tin (Sn), Molybdenum (Mo) , calcium (Ca) or an alloy containing at least two or more of these may be used, preferably copper or a copper alloy.
층간 절연층(240)은 하부 도전층(230)을 매립하여 보호하는 것으로, 에폭시계 수지, 아크릴계 수지, 실록산계 수지, 폴리이미드계 수지 등과 같은 유기 절연 물질, 또는 실리콘 산화물, 실리콘 질화물 등과 같은 무기 절연 물질 등으로 구성할 수 있다.The interlayer insulating layer 240 buries and protects the lower conductive layer 230, and is an organic insulating material such as an epoxy-based resin, an acrylic-based resin, a siloxane-based resin, or a polyimide-based resin, or an inorganic material such as silicon oxide or silicon nitride. It can be composed of an insulating material or the like.
층간 절연층(240)은 플렉서블 특성을 높이기 위해서 유기 절연 물질을 사용하는 것이 바람직하고, 두께는 15~20㎛로 형성할 수 있다.The interlayer insulating layer 240 is preferably formed of an organic insulating material in order to increase flexibility, and may have a thickness of 15 to 20 μm.
상부 도전층(250)은 층간 절연층(240)에 형성되어 예를 들어 수신 전극을 형성하는 것으로, 하부 도전층(230)과 같이 회로 패턴을 갖는 도전 금속층일 수 있다. 도전 금속은, 하부 도전층(230)과 동일하게, 은(Ag), 금(Au), 구리(Cu), 알루미늄(Al), 백금(Pt), 팔라듐(Pd), 크롬(Cr), 티타늄(Ti), 텅스텐(W), 니오븀(Nb), 탄탈륨(Ta), 바나듐(V), 철(Fe), 망간(Mn), 코발트(Co), 니켈(Ni), 아연(Zn), 주석(Sn), 몰리브덴(Mo), 칼슘(Ca) 또는 이들 중 적어도 2 이상을 함유하는 합금으로 구성할 수 있고, 바람직하게는 구리 또는 구리 합금으로 구성할 수 있다.The upper conductive layer 250 is formed on the interlayer insulating layer 240 to form a receiving electrode, for example, and may be a conductive metal layer having a circuit pattern like the lower conductive layer 230 . Like the lower conductive layer 230, the conductive metal is silver (Ag), gold (Au), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), chromium (Cr), titanium (Ti), tungsten (W), niobium (Nb), tantalum (Ta), vanadium (V), iron (Fe), manganese (Mn), cobalt (Co), nickel (Ni), zinc (Zn), tin (Sn), molybdenum (Mo), calcium (Ca) or an alloy containing at least two or more of these, preferably copper or a copper alloy.
패시베이션층(260)은 상부 도전층(250)을 매립하여 보호하는 것으로, 에폭시계 수지, 아크릴계 수지, 실록산계 수지, 폴리이미드계 수지 등과 같은 유기 절연 물질, 또는 실리콘 산화물, 실리콘 질화물 등과 같은 무기 절연 물질로 구성할 수 있다.The passivation layer 260 buries and protects the upper conductive layer 250, and is an organic insulating material such as an epoxy-based resin, an acrylic-based resin, a siloxane-based resin, or a polyimide-based resin, or an inorganic insulating material such as silicon oxide or silicon nitride. can be made of matter.
패시베이션층(260)은 플렉서블 특성을 높이기 위해서 유기 절연 물질을 사용하는 것이 바람직하고, 두께는 1.5~20㎛로 형성할 수 있다.It is preferable to use an organic insulating material for the passivation layer 260 to increase flexibility, and may have a thickness of 1.5 to 20 μm.
일 실시예에 있어서, 층간 절연층(240) 및 패시베이션층(260) 각각은 무기 절연 물질을 포함할 수 있으며, 약 100nm 내지 500nm의 두께를 가질 수 있다.In one embodiment, each of the interlayer insulating layer 240 and the passivation layer 260 may include an inorganic insulating material and may have a thickness of about 100 nm to about 500 nm.
일 실시예에 있어서, 하부 도전층(230)의 두께는 상부 도전층(250)의 두께보다 클 수 있다. 예를 들면, 제1 하부 도전 라인(232)의 두께는 제 1 상부 도전 라인(252)의 두께보다 클 수 있다.In one embodiment, the thickness of the lower conductive layer 230 may be greater than the thickness of the upper conductive layer 250 . For example, the thickness of the first lower conductive line 232 may be greater than that of the first upper conductive line 252 .
일부 실시예들에 있어서, 하부 도전층(230)의 두께는 약 5㎛ 내지 30㎛일 수 있으며, 바람직하게는 10㎛ 내지 25㎛일 수 있다. 상부 도전층(250)의 두께는 6㎛ 이하일 수 있으며, 바람직하게는 약 1㎛ 내지 6㎛, 또는 1㎛ 내지 5㎛일 수 있다.In some embodiments, the thickness of the lower conductive layer 230 may be about 5 μm to about 30 μm, preferably about 10 μm to about 25 μm. The thickness of the upper conductive layer 250 may be 6 μm or less, preferably about 1 μm to 6 μm, or 1 μm to 5 μm.
반사 방지층(300)은 하부/상부 도전층(230,250)의 반사광을 차단 내지 최소화하는 것으로, 하부 도전층(230)에 형성되는 제1 반사 방지층(310)과 상부 도전층(250)에 형성되는 제2 반사 방지층(320)을 포함할 수 있다.The antireflection layer 300 blocks or minimizes reflected light from the lower/upper conductive layers 230 and 250, and the first antireflection layer 310 formed on the lower conductive layer 230 and the second antireflection layer 310 formed on the upper conductive layer 250 2 antireflection layer 320 may be included.
반사 방지층(300)은, 하부/상부 도전층(230,250)의 반사율을 낮추면서 하부/상부 도전층(230,250)의 전기 전도 특성을 유지하고 나아가 구리로 구성되는 하부/상부 도전층(230,250)과의 콘택 저항도 낮추기 위해서, 구리-산소 함유 복합 물질 또는 구리-추가 금속-산소 함유 복합 물질로 구성할 수 있다. 여기서, 추가 금속은 인듐(In), 란타늄(La), 세슘(Ce), 크롬(Cr), 몰리브덴(Mo), 텅스텐(W), 마그네슘(Mg), 칼슘(Ca)으로 구성된 그룹으로부터 선택된 적어도 하나를 포함할 수 있다. 하부 도전층(230)의 높은 표면 조도를 낮추는 데는 인듐을 사용하는 것이 바람직할 수 있다.The anti-reflection layer 300 maintains the electrical conductivity of the lower/upper conductive layers 230 and 250 while lowering the reflectance of the lower/upper conductive layers 230 and 250, and furthermore maintains a contact with the lower/upper conductive layers 230 and 250 made of copper. In order to also lower the contact resistance, it can be composed of a copper-oxygen-containing composite material or a copper-added metal-oxygen-containing composite material. Here, the additional metal is at least one selected from the group consisting of indium (In), lanthanum (La), cesium (Ce), chromium (Cr), molybdenum (Mo), tungsten (W), magnesium (Mg), and calcium (Ca). may contain one. It may be preferable to use indium to reduce the high surface roughness of the lower conductive layer 230 .
추가 금속으로 인듐을 사용하는 경우, 제1,2 반사 방지층(310,320)은 하부 도전층(230)의 높은 표면 조도와 상대적 큰 두께를 고려하여, 구리, 인듐, 산소의 구성 비율을 다르게 할 수 있다. 즉, 제1 반사 방지층(310)은 제2 반사 방지층(320)보다 구리(Cu) 함량을 낮추고, 인듐(In) 함량을 높일 수 있다. 예를 들어, 제1 반사 방지층(310)은 구리 20~30중량부, 인듐 40~50중량부, 산소 27~33중량부를 포함하고, 제2 반사 방지층(320)은 구리 40~45중량부, 인듐 15~20중량부, 산소 37~43중량부를 포함할 수 있다.When indium is used as the additional metal, the first and second antireflection layers 310 and 320 may have different composition ratios of copper, indium, and oxygen in consideration of the high surface roughness and relatively large thickness of the lower conductive layer 230. . That is, the first anti-reflection layer 310 may have a lower copper (Cu) content and a higher indium (In) content than the second anti-reflection layer 320 . For example, the first antireflection layer 310 includes 20 to 30 parts by weight of copper, 40 to 50 parts by weight of indium, and 27 to 33 parts by weight of oxygen, and the second antireflection layer 320 includes 40 to 45 parts by weight of copper, 15 to 20 parts by weight of indium and 37 to 43 parts by weight of oxygen may be included.
제1,2 반사 방지층(310,320)은 0.1~0.2 Ω/□의 면저항을 가질 수 있다. 제1,2 반사 방지층(310,320)의 면저항이 0.2 Ω/□를 초과하면, 전기 전도 특성이 저하되어 감도 등이 떨어질 수 있다. 면 저항이 0.1 Ω/□에 미치지 못하면, 금속 비율이 높아서 반사 방지 특성이 떨어질 수 있다.The first and second anti-reflection layers 310 and 320 may have a sheet resistance of 0.1 to 0.2 Ω/□. When the sheet resistance of the first and second anti-reflection layers 310 and 320 exceeds 0.2 Ω/□, electrical conduction characteristics may be deteriorated, and thus sensitivity may deteriorate. If the sheet resistance is less than 0.1 Ω/□, the metal ratio may be high and the antireflection property may deteriorate.
제1,2 반사 방지층(310,320)은 10~60 nm의 두께로 형성할 수 있다.The first and second anti-reflection layers 310 and 320 may be formed to a thickness of 10 to 60 nm.
제1,2 반사 방지층(310,320)은 스퍼터링 등의 증착 공정으로 형성할 수 있다. The first and second anti-reflection layers 310 and 320 may be formed by a deposition process such as sputtering.
제1 반사 방지층(310)은 예를 들어 구리 25중량부, 인듐 45중량부, 산소 30중량부를 포함하도록 형성할 수 있다. 이 경우, 타켓을 구리 30%, 인듐 60%, 산소 10%로 하고, 공정 조건을 산소 분압 10 sccm, 아르곤 분압 30 sccm으로 하며, 플라즈마 파워는 50 W로 설정하여, 스퍼터링 공정을 수행할 수 있다.The first anti-reflection layer 310 may include, for example, 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen. In this case, the sputtering process can be performed by setting the target to 30% copper, 60% indium, and 10% oxygen, setting the process conditions to 10 sccm of oxygen partial pressure and 30 sccm of argon partial pressure, and setting the plasma power to 50 W. .
제2 반사 방지층(320)은 예를 들어 구리 40중량부, 인듐 20중량부, 산소 40중량부를 포함하도록 형성할 수 있다. 이 경우, 타켓을 구리 50%, 인듐 30%, 산소 20%로 하고, 공정 조건을 산소 분압 1 sccm, 아르곤 분압 50 sccm으로 하며, 플라즈마 파워를 150 W로 설정하여, 스퍼터링 공정을 수행할 수 있다.The second anti-reflection layer 320 may include, for example, 40 parts by weight of copper, 20 parts by weight of indium, and 40 parts by weight of oxygen. In this case, the sputtering process can be performed by setting the target to 50% copper, 30% indium, and 20% oxygen, setting the process conditions to 1 sccm of oxygen partial pressure and 50 sccm of argon partial pressure, and setting the plasma power to 150 W. .
도 3~6은 본 발명에 따른 디지타이저의 구체적 실시예를 도시하는 평면도, 단면도이다. 예를 들어, 도 3은 디지타이저에 포함된 제1 도전 코일을 나타내는 개략적인 평면도이다. 도 4는 도 3에 표시된 I-I' 라인을 따라 두께 방향으로 절단한 단면도이다.3 to 6 are plan views and cross-sectional views showing specific embodiments of a digitizer according to the present invention. For example, FIG. 3 is a schematic plan view illustrating a first conductive coil included in a digitizer. 4 is a cross-sectional view taken in the thickness direction along line II' shown in FIG. 3 .
도 3~6에서, 디지타이저(100) 또는 기재층(105)의 상면에 평행하며 서로 교차하는 두 방향을 제1 방향 및 제2 방향으로 정의한다. 예를 들면, 제1 방향 및 제2 방향은 서로 수직하게 교차할 수 있다.In FIGS. 3 to 6 , two directions that are parallel to the upper surface of the digitizer 100 or the base layer 105 and cross each other are defined as a first direction and a second direction. For example, the first direction and the second direction may perpendicularly cross each other.
제1 방향은 디지타이저(100)의 너비 방향, 행 방향 혹은 X-방향에 대응될 수 있다. 제2 방향은 디지타이저(100)의 길이 방향, 열 방향 혹은 Y-방향에 대응될 수 있다.The first direction may correspond to a width direction, a row direction, or an X-direction of the digitizer 100 . The second direction may correspond to a longitudinal direction, a column direction, or a Y-direction of the digitizer 100 .
도 3~6과 관련하여, 용어 '행 방향', '열 방향' 등은 절대적인 방향을 지칭하는 것이 아니며, 서로 다른 방향을 지정하는 상대적인 의미로 이해되어야 한다.3 to 6, the terms 'row direction' and 'column direction' do not refer to absolute directions, but should be understood as relative meanings designating different directions.
도 3~5를 참조하면, 디지타이저는 기재층(210) 상에 형성된 하부 도전층(230) 및 상부 도전층(250)을 포함할 수 있다. 하부 도전층(230) 및 상부 도전층(250)은 층간 절연층(240)을 사이에 두고 서로 다른 층에 분리될 수 있다. Referring to FIGS. 3 to 5 , the digitizer may include a lower conductive layer 230 and an upper conductive layer 250 formed on a base layer 210 . The lower conductive layer 230 and the upper conductive layer 250 may be separated into different layers with the interlayer insulating layer 240 therebetween.
하부 도전층(230)은 제1 하부 도전 라인(232)(도 5 참조) 및 제2 하부 도전 라인(234)을 포함할 수 있다. 상부 도전층(250)은 제1 상부 도전 라인(252) 및 제2 상부 도전 라인(254)(도 5 참조)을 포함할 수 있다.The lower conductive layer 230 may include a first lower conductive line 232 (see FIG. 5 ) and a second lower conductive line 234 . The upper conductive layer 250 may include a first upper conductive line 252 and a second upper conductive line 254 (see FIG. 5 ).
제1 하부 도전 라인(232) 및 제2 하부 도전 라인(234)은 제2 방향으로 연장할 수 있다. 제1 상부 도전 라인(252) 및 제2 상부 도전 라인(254)은 제1 방향으로 연장할 수 있다.The first lower conductive line 232 and the second lower conductive line 234 may extend in the second direction. The first upper conductive line 252 and the second upper conductive line 254 may extend in the first direction.
제2 하부 도전 라인(234) 및 제2 상부 도전 라인(254)은 제1 하부 도전 라인(232) 및 제1 상부 도전 라인(252)보다 작은 너비를 가질 수 있다.The second lower conductive line 234 and the second upper conductive line 254 may have smaller widths than the first lower conductive line 232 and the first upper conductive line 252 .
도 3에 도시한 바와 같이, 디지타이저는 제1 도전 코일(50)을 포함할 수 있다. 제1 도전 코일(50)은 제1 방향(또는 행 방향) 도전 코일로서 제공될 수 있다. 제1 도전 코일(50)은 하부 도전층(230)의 제2 하부 도전 라인(234) 및 상부 도전층(250)의 제1 상부 도전 라인(252)이 제1 콘택들(272)에 의해 조합되어 정의될 수 있다. 제2 하부 도전 라인(234) 및 제1 상부 도전 라인(252)은 함께 조합되어 전자기 유도 코일을 형성할 수 있다.As shown in FIG. 3 , the digitizer may include a first conductive coil 50 . The first conductive coil 50 may be provided as a first direction (or row direction) conductive coil. In the first conductive coil 50, the second lower conductive line 234 of the lower conductive layer 230 and the first upper conductive line 252 of the upper conductive layer 250 are combined by first contacts 272. can be defined. The second lower conductive line 234 and the first upper conductive line 252 may be combined together to form an electromagnetic induction coil.
제1 상부 도전 라인(252) 및 제2 하부 도전 라인(234)은 함께 제1 도전 코일(50)을 형성하여 전자기 유도를 통한 입력 펜에 대한 센싱 라인으로 함께 제공될 수 있다.The first upper conductive line 252 and the second lower conductive line 234 together form the first conductive coil 50 and may be provided together as a sensing line for an input pen through electromagnetic induction.
예를 들어, 제1 상부 도전 라인(252) 및 제2 하부 도전 라인(234)은 제1 콘택(272)을 통해 서로 전기적으로 연결될 수 있다. 복수의 제1 상부 도전 라인들(252) 및 복수의 제2 하부 도전 라인들(234)이 복수의 제1 콘택들(272)을 통해 서로 전기적으로 연결되어, 하나의 제1 도전 코일(50) 내에 복수의 도전 루프가 포함될 수 있다. 예를 들어, 하나의 제1 도전 코일(50) 내에 4개의 행 방향 도전 루프들이 포함될 수 있다.For example, the first upper conductive line 252 and the second lower conductive line 234 may be electrically connected to each other through the first contact 272 . The plurality of first upper conductive lines 252 and the plurality of second lower conductive lines 234 are electrically connected to each other through the plurality of first contacts 272 to form one first conductive coil 50 A plurality of conductive loops may be included therein. For example, four row direction conductive loops may be included in one first conductive coil 50 .
일 실시예에 있어서, 제1 도전 코일(50)의 내측에서부터 외곽부로 순차적으로 제1 행 방향 도전 루프(50a), 제2 행 방향 도전 루프(50b), 제3 행 방향 도전 루프(50c) 및 제4 행 방향 도전 루프(50d)가 순차적으로 배치될 수 있다.In one embodiment, a first row-wise conductive loop 50a, a second row-wise conduction loop 50b, a third row-direction conduction loop 50c and The fourth row direction conductive loops 50d may be sequentially arranged.
일부 실시예들에 있어서, 행 방향 도전 루프들은 평면 방향에서 서로 다른 사이즈 혹은 면적을 가질 수 있다. 예를 들어, 제1 행 방향 도전 루프(50a), 제2 행 방향 도전 루프(50b), 제3 행 방향 도전 루프(50c) 및 제4 행 방향 도전 루프(50d) 순으로 순차적으로 사이즈가 증가할 수 있다.In some embodiments, the row direction conductive loops may have different sizes or areas in the planar direction. For example, the size of the first rowwise conductive loop 50a, the second rowwise conductive loop 50b, the third rowwise conductive loop 50c, and the fourth rowwise conductive loop 50d are sequentially increased in size. can do.
제1 콘택(272)은 제1 콘택홀을 통해 층간 절연층(240)을 관통하여 제1 상부 도전 라인(252)과 실질적으로 일체로 형성될 수 있다.The first contact 272 may pass through the interlayer insulating layer 240 through the first contact hole and be substantially integrally formed with the first upper conductive line 252 .
행 방향 도전 루프들 중 어느 하나의 도전 루프에는 제1 입력 라인(282) 및 제1 출력 라인(284)이 연결될 수 있다. 제1 입력 라인(282)으로부터 입력된 전류는 행 방향 도전 루프들을 통해 하부 도전층(230) 및 상부 도전층(250)을 교대로 순환하며, 제1 출력 라인(284)을 통해 배출될 수 있다. 예를 들어, 제1 입력 라인(282)은 제1 행 방향 도전 루프(50a)에 연결되며, 제1 출력 라인(284)은 제4 행 방향 도전 루프(50d)에 연결될 수 있다.A first input line 282 and a first output line 284 may be connected to any one of the row direction conductive loops. The current input from the first input line 282 alternately circulates through the lower conductive layer 230 and the upper conductive layer 250 through the row direction conductive loops, and may be discharged through the first output line 284. . For example, the first input line 282 may be connected to the first row conductive loop 50a, and the first output line 284 may be connected to the fourth row conductive loop 50d.
일부 실시예들에 있어서, 제1 입력 라인(282) 및 제1 출력 라인(284)은 하부 도전층(230)에 포함될 수 있다. 일부 실시예들에 있어서, 하부 도전층(230)은 제1 내부 연결 라인(234a)을 더 포함할 수 있다. 예를 들어, 이웃하는 행 방향 도전 루프들이 제1 내부 연결 라인(234a)을 통해 서로 연결될 수 있다.In some embodiments, the first input line 282 and the first output line 284 may be included in the lower conductive layer 230 . In some embodiments, the lower conductive layer 230 may further include a first internal connection line 234a. For example, neighboring row direction conductive loops may be connected to each other through the first inner connection line 234a.
도 5를 참조하면, 디지타이저는 제2 도전 코일(70)을 포함할 수 있다. 제2 도전 코일(70)은 제2 방향(또는 열 방향) 도전 코일로서 제공될 수 있다. 제2 도전 코일(70)은 하부 도전층(230)의 제1 하부 도전 라인(232) 및 상부 도전층(250)의 제2 상부 도전 라인(254)이 제2 콘택들(274)에 의해 조합되어 정의될 수 있다. 제2 상부 도전 라인(254) 및 제1 하부 도전 라인(232)은 함께 조합되어 전자기 유도 코일을 형성할 수 있다.Referring to FIG. 5 , the digitizer may include a second conductive coil 70 . The second conductive coil 70 may be provided as a second direction (or column direction) conductive coil. In the second conductive coil 70 , the first lower conductive line 232 of the lower conductive layer 230 and the second upper conductive line 254 of the upper conductive layer 250 are combined by second contacts 274 . can be defined. The second upper conductive line 254 and the first lower conductive line 232 may be combined together to form an electromagnetic induction coil.
제1 하부 도전 라인(232) 및 제2 상부 도전 라인(254)은 함께 제2 도전 코일(70)을 형성하여 전자기 유도를 통한 입력 펜에 대한 센싱 라인으로 함께 제공될 수 있다.The first lower conductive line 232 and the second upper conductive line 254 together form the second conductive coil 70 and may be provided together as a sensing line for an input pen through electromagnetic induction.
예를 들어, 제1 하부 도전 라인(232) 및 제2 상부 도전 라인(254)은 제2 콘택(274)을 통해 서로 전기적으로 연결될 수 있다. 복수의 제1 하부 도전 라인들(232) 및 복수의 제2 상부 도전 라인들(254)이 복수의 제2 콘택들(274)을 통해 서로 전기적으로 연결되어, 하나의 제2 도전 코일(70) 내에 복수의 도전 루프가 포함될 수 있다. 예를 들어, 하나의 제2 도전 코일(70) 내에 4개의 열 방향 도전 루프들이 포함될 수 있다.For example, the first lower conductive line 232 and the second upper conductive line 254 may be electrically connected to each other through the second contact 274 . The plurality of first lower conductive lines 232 and the plurality of second upper conductive lines 254 are electrically connected to each other through the plurality of second contacts 274 to form one second conductive coil 70. A plurality of conductive loops may be included therein. For example, four column direction conductive loops may be included in one second conductive coil 70 .
일 실시예에 있어서, 제2 도전 코일(70)의 내측에서부터 외곽부로 순차적으로 제1 열 방향 도전 루프(70a), 제2 열 방향 도전 루프(70b), 제3 열 방향 도전 루프(70c) 및 제4 열 방향 도전 루프(70d)가 순차적으로 배치될 수 있다.In one embodiment, a first column direction conductive loop 70a, a second column direction conductive loop 70b, a third column direction conductive loop 70c and The fourth column direction conductive loops 70d may be sequentially arranged.
일부 실시예들에 있어서, 열 방향 도전 루프들은 평면 방향에서 서로 다른 사이즈 혹은 면적을 가질 수 있다. 예를 들어, 제1 열 방향 도전 루프(70a), 제2 열 방향 도전 루프(70b), 제3 열 방향 도전 루프(70c) 및 제4 열 방향 도전 루프(70d) 순으로 순차적으로 사이즈가 증가할 수 있다.In some embodiments, the column direction conductive loops may have different sizes or areas in the planar direction. For example, the first column-wise conductive loop 70a, the second column-wise conductive loop 70b, the third column-wise conductive loop 70c, and the fourth column-wise conductive loop 70d sequentially increase in size. can do.
제2 콘택(274)은 제2 콘택홀을 통해 층간 절연층(240)을 관통하여 제1 하부 도전 라인(232)과 실질적으로 일체로 형성될 수 있다.The second contact 274 may pass through the interlayer insulating layer 240 through the second contact hole and be substantially integrally formed with the first lower conductive line 232 .
열 방향 도전 루프들 중 어느 하나의 도전 루프에는 제2 입력 라인(283) 및 제2 출력 라인(285)이 연결될 수 있다. 제2 입력 라인(283)으로부터 입력된 전류는 열 방향 도전 루프들을 통해 하부 도전층(230) 및 상부 도전층(250)을 교대로 순환하며, 제2 출력 라인(285)을 통해 배출될 수 있다. 예를 들어, 제2 입력 라인(283)은 제1 열 방향 도전 루프(70a)에 연결되며, 제2 배출 라인(285)는 제4 열 방향 도전 루프(70d)에 연결될 수 있다.A second input line 283 and a second output line 285 may be connected to any one of the column direction conductive loops. The current input from the second input line 283 alternately circulates through the lower conductive layer 230 and the upper conductive layer 250 through column-direction conductive loops, and may be discharged through the second output line 285. . For example, the second input line 283 may be connected to the first column direction conductive loop 70a, and the second discharge line 285 may be connected to the fourth column direction conductive loop 70d.
일부 실시예들에 있어서, 제2 입력 라인(283) 및 제2 출력 라인(285)은 하부 도전층(230)에 포함될 수 있다. In some embodiments, the second input line 283 and the second output line 285 may be included in the lower conductive layer 230 .
일부 실시예들에 있어서, 상부 도전층(250)은 외부 연결 라인(254a)을 더 포함할 수 있다. 예를 들어, 외부 연결 라인(254a)에 의해 제2 입력 라인(283) 및 제2 출력 라인(285)이 열 방향 도전 루프들과 제3 콘택을 통해 연결될 수 있다.In some embodiments, the upper conductive layer 250 may further include an external connection line 254a. For example, the second input line 283 and the second output line 285 may be connected to the column direction conductive loops through the third contact by the external connection line 254a.
일 실시예에 있어서, 외부 연결 라인(254a)은 2개의 서로 다른 제2 도전 코일(70)에 연결될 수도 있다. 예를 들면, 어느 하나의 제2 도전 코일(70)에 연결된 출력 라인(285)은 외부 연결 라인(254a)을 통해 다른 제2 도전 코일(70)의 입력 라인(283)에 연결될 수도 있다.In one embodiment, the external connection line 254a may be connected to two different second conductive coils 70 . For example, the output line 285 connected to one second conductive coil 70 may be connected to the input line 283 of another second conductive coil 70 through an external connection line 254a.
일부 실시예들에 있어서, 상부 도전층(250)은 제2 내부 연결 라인을 더 포함할 수도 있다. 예를 들어, 제2 내부 연결 라인에 의해 제2 도전 코일(70) 내에서 이웃하는 열 방향 도전 루프들이 서로 연결될 수 있다.In some embodiments, the upper conductive layer 250 may further include a second internal connection line. For example, adjacent column direction conductive loops within the second conductive coil 70 may be connected to each other by a second internal connection line.
도 3~5를 참조하여 설명한 바와 같이, 하부 도전층(230) 및 상부 도전층(250)을 콘택(272,274)을 통해 연결하여 도전 루프를 형성하므로, 제한된 공간 내에서의 도전 코일의 루프 개수를 효율적으로 증가시키며 전자기 유도 효율성을 향상시킬 수 있다.As described with reference to FIGS. 3 to 5 , since a conductive loop is formed by connecting the lower conductive layer 230 and the upper conductive layer 250 through the contacts 272 and 274, the number of loops of the conductive coil within the limited space can be reduced. efficiency and improve the electromagnetic induction efficiency.
도 3,4에서는 하나의 도전 코일 내에 4개의 도전 루프가 포함되는 것으로 도시하였으나, 도전 코일 내의 도전 루프의 개수는 화상 표시 장치의 사이즈 및 해상도 등을 고려하여 조절될 수 있다.3 and 4 show that four conductive loops are included in one conductive coil, the number of conductive loops in the conductive coil may be adjusted in consideration of the size and resolution of the image display device.
도 5는 예시적인 실시예들에 따른 디지타이저를 나타내는 개략적인 평면도인데, 설명의 편의를 위해, 도 5에서는 도전 코일의 상세 구조/구성의 도시는 생략되었다. 기재층(210)의 상면 상에 복수의 제1 도전 코일들(50) 및 제2 도전 코일들(70)이 배열될 수 있다.FIG. 5 is a schematic plan view illustrating a digitizer according to example embodiments. For convenience of explanation, a detailed structure/configuration of a conductive coil is omitted in FIG. 5 . A plurality of first conductive coils 50 and second conductive coils 70 may be arranged on the upper surface of the base layer 210 .
제1 도전 코일(50)은 제1 방향 혹은 행 방향으로 연장할 수 있다. 복수의 제1 도전 코일들(50)은 제2 방향 또는 열 방향을 따라 배열될 수 있다.The first conductive coil 50 may extend in a first direction or a row direction. The plurality of first conductive coils 50 may be arranged along the second direction or the column direction.
예를 들어, n개의 제1 도전 코일들(50-1 내지 50-n)이 순차적으로 제2 방향을 따라 배열될 수 있다(n은 자연수).For example, n first conductive coils 50-1 to 50-n may be sequentially arranged in the second direction (n is a natural number).
제2 도전 코일(70)은 제2 방향 혹은 열 방향으로 연장할 수 있다. 복수의 제2 도전 코일들(70)은 제1 방향 또는 행 방향을 따라 배열될 수 있다.The second conductive coil 70 may extend in the second direction or column direction. The plurality of second conductive coils 70 may be arranged along the first direction or row direction.
예를 들어, m개의 제2 도전 코일들(70-1 내지 70-m)이 순차적으로 제1 방향을 따라 배열될 수 있다.For example, m second conductive coils 70-1 to 70-m may be sequentially arranged along the first direction.
[실시예][Example]
폴리이미드 기판 상에 접착제를 매개로 구리 도금으로 하부 도전층을 12㎛ 두께로 형성한다. 하부 도전층은 상부에 구리 25중량부, 인듐 45중량부, 산소 30중량부로 구성된 구리 합금의 제1 반사 방지층을 40nm 두께로 포함한다. 또한, 층간 절연층을 형성한 후, 상부 도전층은 구리를 2㎛ 두께로 형성한다. 상부 도전층은 상부에 구리 40중량부, 인듐 20중량부, 산소 40중량부로 구성된 구리 합금의 제2 반사 방지층을 0.04㎛ 두께로 포함한다.A lower conductive layer having a thickness of 12 μm is formed on a polyimide substrate by copper plating with an adhesive as a medium. The lower conductive layer includes a 40 nm thick first antireflection layer made of a copper alloy composed of 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen. Further, after forming the interlayer insulating layer, the upper conductive layer is formed of copper to a thickness of 2 μm. The upper conductive layer includes a second antireflection layer made of copper alloy having a thickness of 0.04 μm and composed of 40 parts by weight of copper, 20 parts by weight of indium, and 40 parts by weight of oxygen.
[비교예 1][Comparative Example 1]
제1 반사 방지층 및 제2 반사 방지층을 제외하고, 실시예와 동일 조건으로 형성하였다.Except for the first antireflection layer and the second antireflection layer, it was formed under the same conditions as in the Example.
[비교예 2][Comparative Example 2]
하부 도전층 및 상부 도전층은 제1 반사 방지층 및 제2 반사 방지층 대신에 IZO 막을 0.04㎛ 두께로 포함하고, 나머지 조건은 실시예와 동일 조건으로 형성하였다.The lower conductive layer and the upper conductive layer included an IZO film to a thickness of 0.04 μm instead of the first anti-reflection layer and the second anti-reflection layer, and the rest of the conditions were the same as those of Example.
아래의 표 1은 실시예, 비교예 1,2의 면품위를 측정한 결과를 나타내었다. 여기서, 표면조도 측정장비는 'Optimap PSD'를 사용하고, 측정 조건은 비접촉식 샘플과 측정장비 간의 거리를 1㎝로 하면서 입사광 파장은 0.1~30.3㎜로 하였다. 측정 방식은 샘플에 입사된 광원이 반사되어 나오는 빛을 CCD 센서로 검출하였다.Table 1 below shows the results of measuring the cotton quality of Examples and Comparative Examples 1 and 2. Here, 'Optimap PSD' was used as the surface roughness measurement equipment, and the measurement conditions were set at 0.1 to 30.3 mm for the incident light wavelength while the distance between the non-contact sample and the measurement equipment was 1 cm. In the measurement method, the light reflected from the light source incident on the sample was detected by the CCD sensor.
하부 도전층의 면품위Surface quality of the lower conductive layer 상부 도전층의 면품위Surface quality of the upper conductive layer 평균 면품위average face
실시예Example 0.50.5 1.31.3 0.90.9
비교예1Comparative Example 1 4.24.2 5.35.3 4.74.7
비교예2Comparative Example 2 3.33.3 3.63.6 3.43.4
위의 표 1에서, 비교예 1은 하부 도전층(230)에 반사 방지층을 형성하지 않은 경우(단일 Cu), 비교예 2는 하부 도전층(230)에 반사 방지층으로 IZO 막을 형성한 경우(Cu/IZO), 그리고 실시예는 하부 도전층(230)에 구리 합금(구리 25중량부, 인듐 45중량부, 산소 30중량부를 포함)의 제1 반사 방지층(310)을 형성하고 상부 도전층(250)에 구리 합금(구리 25중량부, 인듐 45중량부, 산소 30중량부를 포함)의 제2 반사 방지층(320)을 형성한 경우이고, 표 1의 값은 각각에 대한 면품위 측정값이다. 측정값에서 면품위가 높으면 다양한 방향으로 빛이 반사되어 패널 내 화소 영역으로 입사되고 그 결과 화소 불량(패널 품질 저하)로 이어질 수 있음을 나타내는데, 위의 표 1의 면품위 측정값을 보면, 하부/상부 도전층에 구리 합금의 반사 방지층을 형성하면 면품위를 비교예 1,2와 비교하여 100% 이상 감소, 즉 개선할 수 있음을 확인할 수 있다. In Table 1 above, in Comparative Example 1, no antireflection layer is formed on the lower conductive layer 230 (single Cu), and in Comparative Example 2, an IZO film is formed as an antireflection layer on the lower conductive layer 230 (Cu /IZO), and the embodiment forms a first anti-reflection layer 310 of copper alloy (including 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen) on the lower conductive layer 230, and the upper conductive layer 250 ) in the case of forming the second antireflection layer 320 of copper alloy (including 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen), and the values in Table 1 are surface quality measurement values for each. If the surface quality is high in the measured value, it indicates that light is reflected in various directions and incident to the pixel area in the panel, resulting in pixel defects (deterioration of panel quality). Looking at the surface quality measurement values in Table 1 above, / It can be seen that when an antireflection layer of copper alloy is formed on the upper conductive layer, the surface quality can be reduced by 100% or more, that is, improved compared to Comparative Examples 1 and 2.
도 7은 본 발명에 따른 디지타이저를 갖는 화상 표시 장치에서 화소 전극의 전압을 테스트한 결과를 도시하고 있다. 측정 장비는 'HP4155A Semiconductor Parameter Analyzer'를 사용하여, -20 ~ +20(V)의 전압 범위에서 조도 스트레스(Illumination Stress)에 따른 TFT의 전기적 특성, 즉 I(전류)-V(전압) 특성을 측정하였다.7 shows a result of testing the voltage of a pixel electrode in an image display device having a digitizer according to the present invention. The measurement equipment uses 'HP4155A Semiconductor Parameter Analyzer' to measure the electrical characteristics of TFT according to illumination stress in the voltage range of -20 ~ +20 (V), that is, I (current) -V (voltage) characteristics. measured.
도 7은, 하부 도전층(230)에 반사 방지층을 형성하지 않은 경우(단일 Cu, 비교예 1), 하부 도전층(230)에 반사 방지층으로 IZO 막을 형성한 경우(Cu/IZO, 비교예 2), 그리고 하부 도전층(230)에 구리 합금(구리 25중량부, 인듐 45중량부, 산소 30중량부를 포함)의 제1 반사 방지층(310)을 형성하고 상부 도전층(250)에 구리 합금(구리 25중량부, 인듐 45중량부, 산소 30중량부를 포함)의 제2 반사 방지층(320)을 형성한 경우(Cu/구리합금, 실시예)에서, 화소 전극의 동작 전압(게이트 전압) 변화량을 보여주고 있다. 7 shows a case in which an antireflection layer is not formed on the lower conductive layer 230 (single Cu, Comparative Example 1) and a case where an IZO film is formed as an antireflection layer on the lower conductive layer 230 (Cu/IZO, Comparative Example 2). ), and a first antireflection layer 310 of a copper alloy (including 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen) is formed on the lower conductive layer 230, and the copper alloy ( In the case of forming the second antireflection layer 320 (including 25 parts by weight of copper, 45 parts by weight of indium, and 30 parts by weight of oxygen) (Cu/copper alloy, Example), the amount of change in the operating voltage (gate voltage) of the pixel electrode are showing
도 7을 보면, 구리 합금을 반사 방지층으로 사용하는 실시예에서는 게이트 전압이 0 V 영역에서 TFT가 온(ON) 상태가 되어 정상 동작하고 있음에 반해, 비교예 1,2에서는 하부 도전층(230) 및 상부 도전층(250)에서 반사된 빛이 TFT 소자에 입사되면서 게이트 전압이 -20 V 영역까지 X축의 음의 방향으로 변하면서 불안정하게 동작하고 있음을 확인할 수 있다. 이와 같이, 디지타이저 도전층에 구리/인듐 합금의 반사 방지층을 형성하면 표시 패널의 화소 전극에 전압 노이즈를 거의 유발하지 않을 수 있다.Referring to FIG. 7 , in the embodiment in which copper alloy is used as the antireflection layer, the TFT is turned on and operates normally in the region where the gate voltage is 0 V, whereas in Comparative Examples 1 and 2, the lower conductive layer 230 ) and the light reflected from the upper conductive layer 250 is incident on the TFT element, and the gate voltage changes in the negative direction of the X-axis up to the -20 V region, and it can be seen that the TFT operates unstablely. In this way, when the copper/indium alloy antireflection layer is formed on the digitizer conductive layer, voltage noise may be hardly induced in the pixel electrode of the display panel.
아래의 표 2는 실시예 및 비교예 1,2에 대해, 온도 60℃와 상대습도 90% 조건에서 24시간 신뢰성 조건 이후, 하부 도전층 및 상부 도전층의 조합으로 이루어진 루프의 저항 및 반사율을 측정한 결과이다.Table 2 below measures the resistance and reflectance of the loop made of a combination of the lower conductive layer and the upper conductive layer after 24 hours of reliability conditions at a temperature of 60 ° C and a relative humidity of 90% for Examples and Comparative Examples 1 and 2. is a result
실시예Example 비교예 1Comparative Example 1 비교예 2Comparative Example 2
루프 저항(Ω)Loop Resistance (Ω) 19.519.5 202202 22.522.5
루프 반사율(%)Loop reflectance (%) 8.48.4 57.357.3 48.548.5
위의 표 2에서 보듯이, 구리 도전층에 구리 합금의 반사 방지층을 형성하는 실시예는, 비교예 1과 비교하여 루프 저항과 루프 반사율이 현저하게 개선됨을 확인할 수 있고, 비교예 2와 비교해서는 루프 저항은 비슷하지만 루프 반사율이 현저하게 개선됨을 확인할 수 있다.As shown in Table 2 above, it can be confirmed that the example in which the antireflection layer of copper alloy is formed on the copper conductive layer has significantly improved loop resistance and loop reflectance compared to Comparative Example 1, and compared to Comparative Example 2 Although the loop resistance is similar, it can be seen that the loop reflectivity is remarkably improved.
이상, 본 발명을 실시예로서 설명하였는데, 이것은 본 발명을 예증하기 위한 것이다. 통상의 기술자라면 이러한 실시예를 다른 형태로 변형하거나 수정할 수 있을 것이다. 그러나, 본 발명의 권리범위는 아래의 특허청구범위에 의해 정해지므로, 그러한 변형이나 수정은 본 발명의 권리범위에 포함되는 것으로 해석될 수 있다.In the above, the present invention has been described as examples, which are for illustrating the present invention. Those skilled in the art will be able to change or modify these embodiments in other forms. However, since the scope of the present invention is defined by the claims below, such variations or modifications may be construed as being included in the scope of the present invention.
[부호의 설명][Description of code]
100 : 표시 패널100: display panel
200 : 디지타이저200: digitizer
210 : 기재층210: base layer
220 : 접착층220: adhesive layer
230 : 하부 도전층230: lower conductive layer
240 : 층간 절연층240: interlayer insulating layer
250 : 상부 도전층250: upper conductive layer
260 : 패시베이션층260: passivation layer
272,274 : 콘택272,274: contact
300 : 반사 방지층 300: antireflection layer
310 : 제1 반사 방지층310: first anti-reflection layer
320 : 제2 반사 방지층320: second anti-reflection layer

Claims (12)

  1. 기재층;base layer;
    상기 기재층의 상면 상에 배치된 하부 도전층;a lower conductive layer disposed on an upper surface of the base layer;
    상기 하부 도전층에 형성되며 상기 하부 도전층 보다 낮은 반사율을 갖는 제1 반사 방지층;a first antireflection layer formed on the lower conductive layer and having a reflectance lower than that of the lower conductive layer;
    상기 하부 도전층 및 제1 반사 방지층을 매립하는 층간 절연층;an interlayer insulating layer filling the lower conductive layer and the first antireflection layer;
    상기 층간 절연층에 형성되는 상부 도전층;an upper conductive layer formed on the interlayer insulating layer;
    상기 상부 도전층에 형성되며 상기 상부 도전층 보다 낮은 반사율을 갖는 제2 반사 방지층; 및a second antireflection layer formed on the upper conductive layer and having a reflectance lower than that of the upper conductive layer; and
    상기 층간 절연층을 관통하여 상기 하부 도전층과 상기 상부 도전층을 전기적으로 연결시키는 콘택을 포함하는, 디지타이저.A digitizer comprising a contact passing through the interlayer insulating layer and electrically connecting the lower conductive layer and the upper conductive layer.
  2. 청구항 1에 있어서, 상기 하부 도전층은The method according to claim 1, wherein the lower conductive layer
    상기 상부 도전층 보다 표면 조도가 큰, 디지타이저.A digitizer having a surface roughness greater than that of the upper conductive layer.
  3. 청구항 1에 있어서, 상기 제1 반사 방지층과 제2 반사 방지층은The method according to claim 1, wherein the first anti-reflection layer and the second anti-reflection layer
    구리-산소 함유 복합 물질을 포함하는, 디지타이저.A digitizer comprising a copper-oxygen containing composite material.
  4. 청구항 3에 있어서,The method of claim 3,
    상기 구리-산소 함유 복합 물질은 추가 금속을 더 함유하며,The copper-oxygen-containing composite material further contains an additional metal,
    상기 추가 금속은 인듐(In), 란타늄(La), 세슘(Ce), 크롬(Cr), 몰리브덴(Mo), 텅스텐(W), 마그네슘(Mg) 및 칼슘(Ca)으로 구성된 그룹으로부터 선택된 적어도 하나를 포함하는, 디지타이저.The additional metal is at least one selected from the group consisting of indium (In), lanthanum (La), cesium (Ce), chromium (Cr), molybdenum (Mo), tungsten (W), magnesium (Mg), and calcium (Ca) Including, digitizer.
  5. 청구항 3에 있어서, 상기 제1 반사 방지층은The method according to claim 3, wherein the first anti-reflection layer
    상기 제2 반사 방지층 보다 구리 함유량이 낮은, 디지타이저.A digitizer having a lower copper content than the second antireflection layer.
  6. 청구항 3에 있어서,The method of claim 3,
    상기 구리-산소 함유 복합 물질은 추가 금속으로 인듐(In)을 포함하고,The copper-oxygen-containing composite material includes indium (In) as an additional metal,
    상기 제1 반사 방지층은 상기 제2 반사 방지층 보다 인듐(In) 함유량이 높은, 디지타이저.The first anti-reflection layer has a higher indium (In) content than the second anti-reflection layer, the digitizer.
  7. 청구항 1에 있어서, 상기 하부 도전층과 상부 도전층은The method according to claim 1, wherein the lower conductive layer and the upper conductive layer
    구리 전극인, 디지타이저.A digitizer, which is a copper electrode.
  8. 청구항 1에 있어서,The method of claim 1,
    상기 하부 도전층은 상기 기재층의 상면에 평행한 제2 방향으로 연장하는 복수의 제1 하부 도전 라인들 및 복수의 제2 하부 도전 라인들을 포함하고, The lower conductive layer includes a plurality of first lower conductive lines and a plurality of second lower conductive lines extending in a second direction parallel to the top surface of the base layer,
    상기 상부 도전층은 상기 기재층의 상면에 평행하며 상기 제2 방향과 수직한 제1 방향으로 연장하는 복수의 제1 상부 도전 라인들 및 복수의 제2 상부 도전 라인들을 포함하는, 디지타이저.The upper conductive layer includes a plurality of first upper conductive lines and a plurality of second upper conductive lines extending in a first direction parallel to the upper surface of the base layer and perpendicular to the second direction, digitizer.
  9. 청구항 8에 있어서, 상기 콘택은,The method according to claim 8, wherein the contact,
    상기 제1 상부 도전 라인들 및 상기 제2 하부 도전 라인들을 전기적으로 연결시키며 제1 도전 코일을 형성하는 제1 콘택들; 및first contacts electrically connecting the first upper conductive lines and the second lower conductive lines and forming a first conductive coil; and
    상기 제1 하부 도전 라인들 및 상기 제2 상부 도전 라인들을 전기적으로 연결시키며 제2 도전 코일을 형성하는 제2 콘택들을 포함하는, 디지타이저.and second contacts electrically connecting the first lower conductive lines and the second upper conductive lines and forming a second conductive coil.
  10. 청구항 9에 있어서,The method of claim 9,
    상기 제1 도전 코일은 상기 제1 방향으로 연장하며, 상기 제2 방향을 따라 복수의 상기 제1 도전 코일들이 배열되고,The first conductive coil extends in the first direction, and a plurality of first conductive coils are arranged along the second direction;
    상기 제2 도전 코일은 상기 제2 방향으로 연장하며, 상기 제1 방향을 따라 복수의 상기 제2 도전 코일들이 배열되는, 디지타이저.The second conductive coil extends in the second direction, and a plurality of second conductive coils are arranged along the first direction.
  11. 청구항 10에 있어서,The method of claim 10,
    상기 제1 도전 코일들은 각각 복수의 제1 도전 루프들을 포함하고,The first conductive coils each include a plurality of first conductive loops,
    상기 제2 도전 코일들은 각각 복수의 제2 도전 루프들을 포함하는, 디지타이저.The digitizer of claim 1 , wherein the second conductive coils each include a plurality of second conductive loops.
  12. 표시 패널; 및display panel; and
    상기 표시 패널 아래에 배치된 청구항 1~11 중 어느 하나에 따른 디지타이저를 포함하는, 화상 표시 장치.An image display device comprising the digitizer according to any one of claims 1 to 11 disposed under the display panel.
PCT/KR2023/002618 2022-02-25 2023-02-23 Digitizer and image display device comprising same WO2023163531A1 (en)

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KR10-2022-0025056 2022-02-25

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120130990A (en) * 2011-05-24 2012-12-04 삼성전자주식회사 Digitizer integrated display
JP2014164757A (en) * 2013-02-22 2014-09-08 Trendon Touch Technology Corp Touch panel and manufacturing method of the same
KR20150103612A (en) * 2014-03-03 2015-09-11 엘지이노텍 주식회사 Digitizer
JP2020097143A (en) * 2018-12-17 2020-06-25 日東電工株式会社 Electroconductive film having protective film, and method for manufacturing electroconductive film
KR20210081673A (en) * 2019-12-24 2021-07-02 동우 화인켐 주식회사 Touch sensor, window stack structure including the same and image display device including the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120130990A (en) * 2011-05-24 2012-12-04 삼성전자주식회사 Digitizer integrated display
JP2014164757A (en) * 2013-02-22 2014-09-08 Trendon Touch Technology Corp Touch panel and manufacturing method of the same
KR20150103612A (en) * 2014-03-03 2015-09-11 엘지이노텍 주식회사 Digitizer
JP2020097143A (en) * 2018-12-17 2020-06-25 日東電工株式会社 Electroconductive film having protective film, and method for manufacturing electroconductive film
KR20210081673A (en) * 2019-12-24 2021-07-02 동우 화인켐 주식회사 Touch sensor, window stack structure including the same and image display device including the same

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