WO2023163156A1 - Computation device and anomaly detection device - Google Patents

Abstract

Provided is a computation device comprising a memory, a selector, a first computation unit configured to perform computation on first data read out from the memory and output of the selector, and a second computation unit configured to perform computation using output of the first computation unit. The selector is configured to output either second data read out from the memory or the previous computation result of the first computation unit.

Description

Arithmetic device and anomaly detection device

The invention disclosed in this specification relates to an arithmetic device and an anomaly detection device including the arithmetic device.

For example, machine learning is used in anomaly detection for machine health monitoring systems (see Patent Document 1). In machine learning, mathematics operations on matrices and vectors are performed. In machine learning, the REDUCE operation is also frequently used for matrices and vectors. Note that the REDUCE operation is an operation for obtaining a single value by applying the same operation to a plurality of values.

As an example of matrix operation in machine learning, there is Equation (1) described in Non-Patent Document 1. Formula (1) represents Figure 3 described in Non-Patent Document 1 as a formula. Equation (1) is an equation for estimation using learning results. α and β in equation (1) are matrices, and x, y, and b in equation (1) are vectors. And G() in equation (1) is a vector function.
y=G(x·α+b)β (1)

The formula for learning is formula (5) described in Non-Patent Document 1. P, H, and I in the formula (5) are each row.
P _i =P _i-1 -P _i-1 H _i ^T (I + H _i P _i-1 H _i ^T ) ^-1 H _i P _i-1 (5)
β _i =β _i-1 +P _i H _i ^T (t _i -H _i β _i-1 )

Examples of REDUCE calculation include Average Pooling and Max-Pooling described in Non-Patent Document 2. These are often used in Convolution Neural Networks (CNN).

WO2019/035279

In order for machine learning with complex algorithms to be implemented without delay, it is necessary to shorten the calculation execution time of the calculation device.

The computing device disclosed in this specification includes a memory, a selector, a first computing unit configured to compute first data read from the memory and an output of the selector, the first and a second computing unit configured to perform computation using the output of the computing unit. The selector is configured to output one of the second data read from the memory and the previous computation result of the first computing unit.

The anomaly detection device disclosed in this specification includes the computing device configured as described above.

According to the invention disclosed in this specification, the computation execution time can be shortened.

FIG. 1 is a diagram showing the configuration of an arithmetic unit according to a reference example. FIG. 2 is a diagram for explaining the processing flow when the first computing unit according to the reference example performs the REDUCE computation. FIG. 3 is a diagram illustrating a configuration of an arithmetic device according to the embodiment; FIG. 4 is a diagram for explaining a processing flow when the first calculator according to the embodiment performs a REDUCE calculation; FIG. 5 is a diagram showing a schematic configuration of a motor driver. FIG. 6 is a diagram showing an example of acceleration signals and abnormal values.

<Arithmetic device according to reference example>
First, before describing the embodiment, a reference example for understanding the features of the embodiment will be described. FIG. 1 is a diagram showing the configuration of an arithmetic device 100 according to a reference example.

A computing device 100 according to the reference example includes a memory 1 , a control unit 2 , a first computing unit 11 , a second computing unit 21 , and a latch 22 .

The memory 1, the control unit 2, the first calculator 11, the second calculator 21, and the latch 22 are configured to operate in synchronization with the same clock signal.

The memory 1 is configured to store data used for computation.

The control unit 2 is configured to control the memory 1. The control unit 2 is configured to output a control signal S<b>1 to the memory 1 and control data reading from the memory 1 and data writing to the memory 1 .

The first computing unit 11 is configured to compute the first data read from the memory 1 and the second data read from the memory 1 . The calculation result of the first calculator 11 is supplied to the memory 1 and the second calculator 21 .

The calculation result of the first calculator 11 is supplied to the first input terminal of the second calculator 21 , and the output of the latch 22 is supplied to the second input terminal of the second calculator 21 . The second calculator 21 is configured to calculate the calculation result of the first calculator 11 and the previous calculation result of the second calculator 21 . A calculation result of the second calculator 21 is supplied to the memory 1 and the latch 22 .

The latch 22 is provided on a feedback path from the output end of the second computing unit 21 to the second input end of the second computing unit 21 . The latch 22 is configured to latch the computation result of the second computing unit 21 . This enables the second calculator 21 to perform the REDUCE calculation.

Here, as an example, the processing flow when the first calculator 11 according to the reference example obtains the product of the data A1 to A8 by the REDUCE calculation will be described with reference to FIG.

First, data A1 and A5 are read from the memory 1 in state ST1.

Next, in state ST2, the first calculator 11 outputs data B1, which is the product of data A1 and data A5, to memory 1, and data B1 is written in memory 1.

Next, in state ST3, data A2 and A6 are read from memory 1.

Next, in state ST4, the first calculator 11 outputs data B2, which is the product of data A2 and data A6, to memory 1, and data B2 is written in memory 1.

Next, in state ST5, data A3 and A7 are read from memory 1.

Next, in state ST6, the first calculator 11 outputs data B3, which is the product of data A3 and data A6, to memory 1, and data B3 is written in memory 1.

Next, in state ST7, data A4 and A8 are read from memory 1.

Next, in state ST8, the first calculator 11 outputs data B4, which is the product of data A4 and data A8, to memory 1, and data B4 is written in memory 1.

Next, in state ST9, data B1 and B3 are read from memory 1.

Next, in state ST10, the first calculator 11 outputs data C1, which is the product of data B1 and data B3, to the memory 1, and the data C1 is written in the memory 1.

Next, in state ST11, data B2 and B4 are read from memory 1.

Next, in state ST12, the first calculator 11 outputs data C2, which is the product of data B2 and data B4, to memory 1, and data C2 is written in memory 1.

Next, in state ST13, data C1 and C2 are read from memory 1.

Finally, in state ST14, the first calculator 11 outputs data D1, which is the product of data C1 and data C2, to memory 1, and data D1 is written in memory 1. As a result, the product of the data A1 to A8 is stored in the memory 1. FIG.

The arithmetic device 100 according to the reference example needs frequent access to the memory 1 when obtaining the product of the data A1 to A8.

<Arithmetic device according to the embodiment>
Next, embodiments will be described. FIG. 3 is a diagram showing the configuration of the arithmetic device 101 according to the embodiment. Here, differences from the configuration according to the reference example shown in FIG. 1 will be mainly described.

A computing device 101 according to the embodiment includes a memory 1, a control unit 2, a first computing unit 11, a first latch 12, a selector 13, a second computing unit 21, and a second latch 22. .

The memory 1, control unit 2, first calculator 11, first latch 12, selector 13, second calculator 21, and second latch 22 are configured to operate in synchronization with the same clock signal.

The memory 1 is configured to store data used for computation.

The control unit 2 is configured to control the memory 1 and the selector 13. The control unit 2 is configured to output a control signal S<b>1 to the memory 1 and control data reading from the memory 1 and data writing to the memory 1 . Also, the control unit 2 is configured to output a control signal (selection signal) S2 to the selector 13 to cause the selector 13 to select one of the two inputs. The memory addresses of data to be read from and written to the memory 1 are not necessarily consecutive, and may be discontinuous.

The first computing unit 11 is configured to compute the first data read from the memory 1 and the output of the selector 13 . The calculation result of the first calculator 11 is supplied to the first latch 12 and the second calculator 21 .

The first calculator 11 may be, for example, a multiplier, a maximum value selection circuit, or a minimum value selection circuit. Further, in order to diversify the operations that can be executed by the arithmetic device 101 according to the embodiment, the first arithmetic unit 11 includes, for example, a multiplier, a maximum value selection circuit, and a minimum value selection circuit. The circuit may be configured to select one of the maximum value selection circuit and the minimum value selection circuit.

The first latch 12 is provided on the first feedback path from the first calculator 11 to the selector 13 . More specifically, the first latch 12 is provided on a first feedback path from the output end of the first calculator 11 to the second input end of the selector 13 . The first latch 12 is configured to latch the calculation result of the first calculator 11 .

The second data read from the memory 1 is supplied to the first input terminal of the selector 13, and the output of the first latch 12 is supplied to the first input terminal of the selector 13. The selector 13 is configured to output one of the second data read from the memory 1 and the result of the immediately previous operation of the first operator 11 .

The calculation result of the first calculator 11 is supplied to the first input terminal of the second calculator 21 , and the output of the second latch 22 is supplied to the second input terminal of the second calculator 21 . The second calculator 21 is configured to calculate the calculation result of the first calculator 11 and the previous calculation result of the second calculator 21 . The calculation result of the second calculator 21 is supplied to the memory 1 and the second latch 22 .

The second calculator 21 may be, for example, a summation calculator. For example, when the first calculator 11 is a multiplier and the second calculator 21 is a summation calculator, the calculator 101 according to the embodiment calculates the sum of products of three or more numbers (Σn[Πm (xmn )]) can be computed. Further, for example, when the first arithmetic unit 11 is a maximum value selection circuit and the second arithmetic unit 21 is a summation arithmetic unit, the arithmetic unit 101 according to the embodiment can calculate the sum of three or more maximum values ( Σn[Maxm(xmn)]) can be calculated.

The second latch 22 is provided on a second feedback path from the output end of the second computing unit 21 to the second input end of the second computing unit 21 . The second latch 22 is configured to latch the calculation result of the second calculator 21 . This enables the second calculator 21 to perform the REDUCE calculation.

Here, as an example, the processing flow when the first calculator 11 according to the present embodiment obtains the product of the data A1 to A8 by the REDUCE calculation will be described with reference to FIG.

First, data A1 and A2 are read from memory 1 in state ST21.

Next, in state ST22, the first arithmetic unit 11 outputs data E1, which is the product of data A1 and data A2, to the first latch 12.

Next, in state ST23, data A3 and data E1 are supplied to the first computing unit 11.

Next, in state ST24, the first calculator 11 outputs to the first latch 12 data E2, which is the product of data A3 and data E1.

Next, in state ST25, data A4 and data E2 are supplied to the first calculator 11.

Next, in state ST26, the first calculator 11 outputs to the first latch 12 data E3, which is the product of data A4 and data E2.

Next, in state ST27, data A5 and data E3 are supplied to the first computing unit 11.

Next, in state ST28, the first arithmetic unit 11 outputs data E4, which is the product of data A5 and data E3, to the first latch 12.

Next, in state ST29, data A6 and data E4 are supplied to the first arithmetic unit 11.

Next, in state ST30, the first arithmetic unit 11 outputs data E5, which is the product of data A6 and data E4, to the first latch 12.

Next, in state ST31, data A7 and data E5 are supplied to the first computing unit 11.

Next, in state ST32, the first computing unit 11 outputs data E6, which is the product of data A7 and data E5, to the first latch 12.

Next, in state ST33, data A8 and data E6 are supplied to the first arithmetic unit 11.

Finally, in state ST34, the first calculator 11 outputs data E7, which is the product of data A8 and data E6, to memory 1, and data E7 is written in memory 1. As a result, the product of the data A1 to A8 is stored in the memory 1. FIG.

When calculating the product of data A1 to A8, the arithmetic device 101 according to the embodiment first accesses the memory 1 once to read the data and only accesses the memory 1 last time to write the data. is enough. Therefore, the computation device 101 according to the embodiment can shorten the computation execution time.

The data A1 to A8 described above may be, for example, the elements of a vector arranged in order, or may be the elements of a matrix arranged in order, for example. That is, the arithmetic device 101 according to the embodiment can repeatedly perform vector arithmetic by using the output of the first arithmetic unit 11 as the input of the first arithmetic unit 11 .

The data A1 to A8 described above may be, for example, some time-series data, or may be, for example, data of each pixel of an image.

In the example shown in FIG. 4, the REDUCE operation in the first computing unit 11 was the product, but operations other than the product, such as maximum value selection, minimum value selection, etc., may be used.

<Application to abnormality detection device>
The computing device 101 according to the embodiment is mounted on, for example, a motor driver. FIG. 5 is a diagram showing a schematic configuration of a motor driver. The motor driver 200 includes a drive control signal generation circuit 201, a pre-driver circuit 202, a three-phase inverter circuit 203, an abnormality detection device 204, and terminals T1 to T6.

The terminal T1 is connected to the U-phase winding of the motor. Terminal T2 is connected to the V-phase winding of the motor. Terminal T3 is connected to the W-phase winding of the motor.

The terminal T4 receives the U-phase Hall signal output from the U-phase Hall sensor. A terminal T5 receives a V-phase Hall signal output from the V-phase Hall sensor. A terminal T6 receives a W-phase Hall signal output from the W-phase Hall sensor.

A drive control signal generation circuit 201 generates a drive control signal based on each phase Hall signal. The pre-driver circuit 202 controls the three-phase inverter circuit 203 according to the drive control signal. The three-phase inverter circuit 203 outputs the U-phase drive signal to the terminal T1, the V-phase drive signal to the terminal T2, and the W-phase drive signal to the terminal T3.

The abnormality detection device 204 detects motor abnormalities using machine learning based on the Hall signals of each phase. Machine learning uses the calculation result of the calculation device 101 according to the embodiment. Since the calculation execution time of the calculation device 101 according to the embodiment is short, a complicated algorithm can be adopted in machine learning. Thereby, the abnormality detection accuracy in the abnormality detection device 204 can be improved.

Although the motor driver 200 described above is configured to use Hall signals, the arithmetic device 101 according to the embodiment may be included in an abnormality detection device provided in a sensorless motor driver that does not use Hall signals. A sensorless motor driver detects the rotor position of a motor by detecting a back electromotive force generated as the rotor rotates.

Also, the arithmetic device 101 according to the embodiment may be included in an abnormality detection device that uses the output signal of the acceleration sensor. Examples of the mounting location of the acceleration sensor include a moving body, a rotating body, and the vicinity of the rotating body. Examples of mobile objects include vehicles, elevators, and transport devices in factories. Rotating bodies include, for example, rotating shafts of machines. The vicinity of the rotating body includes, for example, bearings.

FIG. 6 is a diagram showing an example of acceleration signals and abnormal values. In FIG. 6, the vertical axis indicates each value and abnormal value of the acceleration signals x, y, and z, and the horizontal axis indicates time. Acceleration signals x, y, and z are the output signals of the acceleration sensor. An acceleration signal x is an output signal of an acceleration sensor indicating acceleration in the X-axis direction. An acceleration signal y is an output signal of an acceleration sensor indicating acceleration in the Y-axis direction. The acceleration signal z is an output signal of the acceleration sensor indicating acceleration in the Z-axis direction. The X-axis, Y-axis, and Z-axis are orthogonal to each other. For example, 100 acceleration signals x in time series, 100 acceleration signals y in the same time series, and 100 acceleration signals z in the same time series are arranged in this order. By inputting , the anomaly detection device can calculate one anomaly value. The outliers shown in FIG. 6 are the outliers calculated by the anomaly detector.

For example, when the abnormality detection device 204 is an abnormality detection device that uses the output signal of an acceleration sensor, and the abnormality value calculated by the abnormality detection device 204 exceeds a preset threshold value, the drive control signal generation circuit 201 The three-phase inverter circuit 203 may be stopped.

Further, for example, the abnormality detection device 204 is an abnormality detection device that uses the output signal of an acceleration sensor, and the abnormality value calculated by the abnormality detection device 204 is equal to or greater than the preset threshold for a preset threshold time or longer. In this case, the drive control signal generation circuit 201 may stop the three-phase inverter circuit 203 .

Further, for example, when the abnormality detection device 204 is an abnormality detection device that uses the output signal of an acceleration sensor, and the abnormality value calculated by the abnormality detection device 204 exceeds a preset threshold value, the abnormality detection device 204 An abnormality may be notified to a device in which the motor driver 200 is mounted.

<Others>
Various modifications can be made to the various technical features disclosed in this specification without departing from the gist of the technical creation in addition to the above-described embodiments. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalency to the claims are included.

The arithmetic device (101) described above includes a memory (1), a selector (13), and a first arithmetic unit (11 ), and a second computing unit (21) configured to perform computation using the output of the first computing unit, wherein the selector comprises second data read from the memory and the first computation This is a configuration (first configuration) that is configured to output either one of the computation result of the unit and the one immediately before.

The computing device having the first configuration can reduce the number of times the memory is accessed. Therefore, the computing device having the first configuration can shorten the computing execution time.

The arithmetic device having the first configuration may have a configuration (second configuration) including a first latch (12) provided in a first feedback path from the first computing unit to the selector.

The computing device having the above second configuration can supply the previous computing result of the first computing unit with a simple configuration.

In the computing device having the second configuration, a configuration (third configuration ).

The computing device having the above third configuration is capable of REDUCE computation in the second computing unit.

The arithmetic device having any one of the first to third configurations may have a configuration (fourth configuration) including a control section (2) configured to control the memory and the selector.

The arithmetic device having the fourth configuration above can execute arithmetic processing without receiving a control signal from the outside.

In the arithmetic device having any one of the first to fourth configurations, the first arithmetic unit includes a multiplier, a maximum value selection circuit, and a minimum value selection circuit, and the multiplier, the maximum value selection circuit, and A configuration (fifth configuration) that is a circuit configured to select one of the minimum value selection circuits may be employed.

The computing device having the fifth configuration can diversify executable computations.

The abnormality detection device described above may have a configuration (fifth configuration) including an arithmetic device having any one of the first to fourth configurations.

In the abnormality detection device having the fifth configuration, it is possible to shorten the computation execution time of the computation device.

1 memory 2 control unit 11 first arithmetic unit 12 first latch 13 selector 21 second arithmetic unit 22 latch, second latch 100 arithmetic device according to reference example 101 arithmetic device according to embodiment 200 motor driver 201 drive control signal generation circuit 202 pre-driver circuit 203 three-phase inverter circuit 204 abnormality detection device T1 to T6 terminals

Claims (6)

1. memory;
   a selector;
   a first computing unit configured to compute first data read from the memory and the output of the selector;
   a second computing unit configured to perform computation using the output of the first computing unit;
   with
   The arithmetic device, wherein the selector is configured to output one of the second data read from the memory and the previous arithmetic result of the first arithmetic unit.
2. 2. The computing device according to claim 1, comprising a first latch provided on a first feedback path from said first computing unit to said selector.
3. 3. The computing device according to claim 1, comprising a second latch provided on a second feedback path from the output end of the second computing unit to the input end of the second computing unit.
4. The arithmetic device according to any one of claims 1 to 3, comprising a control unit configured to control said memory and said selector.
5. The first calculator includes a multiplier, a maximum value selection circuit, and a minimum value selection circuit, and can select any one of the multiplier, the maximum value selection circuit, and the minimum value selection circuit. The arithmetic device according to any one of claims 1 to 4, which is a circuit configured with:
6. An anomaly detection device comprising the arithmetic device according to any one of claims 1 to 5.

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