WO2023159451A1 - 数据模拟装置及方法 - Google Patents

数据模拟装置及方法 Download PDF

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Publication number
WO2023159451A1
WO2023159451A1 PCT/CN2022/077820 CN2022077820W WO2023159451A1 WO 2023159451 A1 WO2023159451 A1 WO 2023159451A1 CN 2022077820 W CN2022077820 W CN 2022077820W WO 2023159451 A1 WO2023159451 A1 WO 2023159451A1
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Prior art keywords
data
interface
programmable logic
sector
simulation
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PCT/CN2022/077820
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English (en)
French (fr)
Inventor
窦润江
于靖一
吴南健
刘力源
刘剑
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中国科学院半导体研究所
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Priority to PCT/CN2022/077820 priority Critical patent/WO2023159451A1/zh
Publication of WO2023159451A1 publication Critical patent/WO2023159451A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

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  • the present disclosure relates to the technical field of computer communication, in particular to a data simulation device and method.
  • the present disclosure provides a data simulation device and method for at least partially solving the above technical problems.
  • the present disclosure provides a data simulation device, including: a programmable logic device, configured to implement at least one interface protocol, so as to respectively send and receive simulation data and test data according to the interface protocol, wherein the simulation data includes first data and For the second data, the transmission rate of the first data is lower than the transmission rate of the second data; at least one first interface is used to connect the programmable logic device and at least one first device under test to transmit the first data and test data; and /or, at least one second interface, used for connecting the programmable logic device and at least one second device under test, so as to transmit the second data and test data.
  • the data simulation device further includes: a disk array, connected in communication with the programmable logic device, for storing simulation data; a cache array, connected in communication with the programmable logic device, for reading and writing data to the disk array; wherein, The disk array includes at least one disk, the disk includes at least one sending channel sector and at least one receiving channel sector, the sending channel sector is used to store the analog data sent, and the receiving channel sector is used to store the received analog data; the buffer array includes At least one buffer element, the buffer element includes at least one sending channel buffer area and at least one receiving channel buffer area, the sending channel buffer area is used to read data from the sending channel sector, and the receiving channel buffer area is used to perform data reading on the receiving channel sector Data writing: the first interface and the second interface are assigned independent sending channel sectors and receiving channel sectors.
  • the sending channel buffer area and the receiving channel buffer area use ping-pong buffering.
  • the programmable logic device includes an on-chip memory for reading and writing data to the cache array.
  • the first interface includes a low voltage differential signal interface, a universal asynchronous transceiver interface and a CANBUS interface;
  • the second interface includes a TLK2711 interface and an Ethernet interface.
  • the data simulation device also includes: a PCIe bus for connecting the programmable logic device and the client to transmit the simulated data; the programmable logic device is also used for obtaining configuration information through the PCIe bus to divide the sending channel sector and The receiving channel sector; the disk also includes: an independent configuration sector for storing configuration information; the cache element also includes: an independent buffer area for reading and writing data to the independent configuration sector.
  • a PCIe bus for connecting the programmable logic device and the client to transmit the simulated data
  • the programmable logic device is also used for obtaining configuration information through the PCIe bus to divide the sending channel sector and The receiving channel sector
  • the disk also includes: an independent configuration sector for storing configuration information
  • the cache element also includes: an independent buffer area for reading and writing data to the independent configuration sector.
  • the programmable logic device is further configured to obtain the configuration register through the PCIe bus, so as to reset the first address of the sending channel sector or the receiving channel sector.
  • the PCIe bus is connected to the client through the Thunderbolt controller.
  • the first interface or the second interface transmits analog data in any one of single-frame synchronous, single-frame asynchronous, continuous synchronous, and continuous asynchronous.
  • Another aspect of the present disclosure provides a data simulation method, including: using a programmable logic device to implement at least one interface protocol; obtaining interface configuration information according to the interface protocol; according to the interface configuration information, using at least one first interface and/or at least one The second interface transmits analog data; wherein the analog data includes first data and second data, and the transmission rate of the first data is lower than the transmission rate of the second data.
  • the present disclosure provides a data simulation device, which connects a plurality of interfaces with different data transmission rates and different data transmission protocols to a programmable logic device, and implements various data corresponding to each interface on the programmable logic device.
  • the transmission protocol can centrally realize the analog data communication with the interfaces of the external large-scale complex visual processing system, etc., which greatly improves the test efficiency of the external system.
  • the data simulation device of the present disclosure also includes a cache array and a disk array, wherein each cache element and disk are divided into independent cache areas and sectors for each interface, so that each interface can send the simulation of each custom protocol synchronously or asynchronously. data.
  • FIG. 1 schematically shows a structural diagram of a data simulation device according to an embodiment of the present disclosure
  • Fig. 2 schematically shows a storage structure diagram of a data simulation device according to an embodiment of the present disclosure
  • Fig. 3 schematically shows a flowchart of a data simulation method according to an embodiment of the present disclosure.
  • Fig. 1 schematically shows a structural diagram of a data simulation device according to an embodiment of the present disclosure.
  • the data simulation device which may also be referred to as a data simulation source, includes, for example: a programmable logic device, which is used to implement at least one interface protocol, so as to separately simulate data according to the interface protocol and test data are sent and received, wherein the simulated data includes first data and second data, and the transmission rate of the first data is lower than the transmission rate of the second data.
  • a programmable logic device which is used to implement at least one interface protocol, so as to separately simulate data according to the interface protocol and test data are sent and received, wherein the simulated data includes first data and second data, and the transmission rate of the first data is lower than the transmission rate of the second data.
  • At least one first interface is used to connect the programmable logic device and at least one first device under test to transmit the first data and test data.
  • at least one second interface is used to connect the programmable logic device and at least one second device under test, so as to transmit the second data and test data.
  • the simulation data is, for example, the data sent by the data simulation device to each device under test
  • the test data is, for example, the result data fed back to the data simulation device by each device under test.
  • the transmission rate attribute of the test data is consistent with the simulated data of the corresponding interface.
  • the first data is, for example, low-speed data
  • the first interface is, for example, a low-speed interface.
  • the low-speed interface connects the programmable logic device with an external system, such as a low-speed data interface of a large-scale and complex visual processing system.
  • the low-speed data transmission protocol can realize the mutual transmission of low-speed data of different low-speed data transmission protocols between the data simulation device and the external system.
  • the second data is, for example, high-speed data
  • the second interface is, for example, a high-speed interface.
  • the high-speed interface connects the programmable logic device with an external system, such as a high-speed data interface of a large and complex visual processing system.
  • the corresponding high-speed data transmission protocol is implemented on the chip, which can realize the mutual transmission of high-speed data of different high-speed data transmission protocols between the data simulation device and the external system.
  • programmable logic devices can implement protocols such as DDR3 controllers, PCIe 2.0 buses, SATA 3.0, 10 Gigabit Ethernet, and CANBUS 2.0B controllers and custom protocols on-chip.
  • the first device under test is, for example, a device that generates or utilizes low-speed data in the external system
  • the second device under test is, for example, a device that generates or utilizes high-speed data in the external system.
  • the programmable logic device in the present disclosure can be any programmable device that can implement a custom data transmission protocol and multi-interface data communication on-chip, such as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD). logic device.
  • FPGA field programmable gate array
  • CPLD complex programmable logic device
  • the first interface and the second interface respectively represent a type of interface, that is, the first interface is, for example, a low-speed interface that transmits low-speed data, and the second interface is, for example, a high-speed interface that transmits high-speed data. interface.
  • the first interface can be, for example, a low-voltage differential signal interface (LVDS (Low-Voltage Differential Signaling) interface), a universal asynchronous transceiver interface (UART (Universal Asynchronous Receiver/Transmitter) interface) and a CANBUS interface.
  • the second interface includes, for example, a TLK2711 interface, an Ethernet interface, and the like.
  • each interface is, for example, the working mode of the corresponding connector driven by the interface chip.
  • the LVDS interface is the low-speed data transmission between the LVDS interface chip driving the low-speed connector and the external system
  • the TLK2711 interface is the TLK2711 interface chip driving the coaxial connector.
  • the Ethernet interface for example, performs high-speed data transmission with external systems directly through optical fiber connectors.
  • the Ethernet interface is suitable for Fast Ethernet, Gigabit Ethernet, Ten Gigabit Ethernet, 40G and higher bandwidth Ethernet, for example.
  • the first interface or the second interface may transmit analog data in any one of single-frame synchronous, single-frame asynchronous, continuous synchronous, and continuous asynchronous.
  • the data simulation device includes, for example, two LVDS physical layer driving circuits, respectively implementing one three-wire LVDS interface and one two-wire LVDS interface.
  • 3 UART physical layer drive circuits respectively implement 1 external trigger signal interface, 1 synchronous RS422 and 5 asynchronous RS422 interfaces.
  • 1 CANBUS physical layer drive circuit to realize 1 CANBUS interface.
  • 3 TLK2711 drive circuits to realize 3-way 2711 high-speed serial transceiver interface.
  • the number of driving circuits and the number of interfaces can be set according to the data transmission requirements of the external system, which are not specifically limited in the present disclosure.
  • Fig. 2 schematically shows a storage structure diagram of a data simulation device according to an embodiment of the present disclosure.
  • the data simulation device further includes: a disk array, connected in communication with the programmable logic device, for storing simulation data and test data. After the system is disconnected and the power supply is stopped, due to the non-volatility of the disk array, the simulation data will not be lost and can be used for the next simulation. When simulating large amounts of data for a long time, the disk array can ensure the stability of data output simulation and input storage.
  • the cache array is connected in communication with the programmable logic device, and is used for reading and writing data to the disk array.
  • the cache array can be, for example, a DRAM array. Wherein, as shown in FIG. 2 , the disk array includes at least one disk.
  • the disk is, for example, an SSD storage, and the SSD storage may be, for example, a SATA storage or an NVME storage.
  • the disk includes at least one sending channel sector and at least one receiving channel sector.
  • the sending channel sector is used to store sent simulation data
  • the receiving channel sector is used to store received test data.
  • the cache array includes at least one cache element, and the cache element may be, for example, a DDR granule or a DDR memory stick.
  • Each buffer element includes at least one sending channel buffer area and at least one receiving channel buffer area, the sending channel buffer area is used to read data from the sending channel sector, and the receiving channel buffer area is used to write data to the receiving channel sector. Both the first interface and the second interface are assigned independent sending channel sectors and receiving channel sectors.
  • the TLK2711 interface can be divided into a sending channel and a receiving channel according to the data transmission direction.
  • the TLK2711 transmission channel corresponds to an independent transmission channel buffer area and transmission channel sector, for example, it can be a transmission channel 1 buffer area and a transmission channel 1 sector.
  • the LVDS transmission channel may correspond to the transmission channel 2 buffer area and the transmission channel 2 sector.
  • the data simulation device allocates an independent sending channel buffer area and sending channel sector for each interface.
  • the external system can provide the data to be simulated and return the test result data to the data simulation device.
  • the receiving channel of TLK2711 corresponds to the receiving channel 1 buffer area and the receiving channel 1 sector, for example.
  • the LVDS receiving channel corresponds to the receiving channel 2 buffer area and the receiving channel 2 sector.
  • the data simulation device also allocates an independent receiving channel buffer area and receiving channel sector for each interface.
  • the storage structure is such as a disk array and the cache structure is such as a cache array, the effective data transmission bandwidth of the same interface can be improved.
  • the TLK2711 transmission channel corresponds to two transmission channel 1 buffer areas and two transmission channel 1 sectors, which can Improve the effective data transmission bandwidth of the TLK2711 transmission channel.
  • the number of disks and cache elements is determined according to the requirements of the data bandwidth to be transmitted by each interface, for example.
  • the number of sending channel sectors and receiving channel sectors is determined according to the number of interfaces, for example, which is not specifically limited in the present disclosure.
  • the programmable logic device includes, for example, an on-chip memory for reading and writing data to the cache array.
  • the cache array and the on-chip memory form a two-level cache structure, which realizes the two-level cache for reading and writing data from the disk array.
  • the on-chip memory is, for example, a level 1 cache
  • the cache elements (constituting a cache array) are, for example, a DDR level 2 cache.
  • the data simulation device sends data to the external system, it can first read the data from the disk array to the DDR secondary cache, then move the data from the DDR secondary cache to the first level cache, and finally from the first level cache Read data and emit data by protocol.
  • each interface Since the data of each interface may be transmitted in the form of synchronous transmission, the complete data frame or data packet needs to be buffered in the buffer area. Therefore, the transmission timing of each data frame or data packet can be adjusted through the two-level buffer structure, thereby ensuring the data security of each interface. Send synchronously.
  • the data simulation device when the data simulation device receives data from an external system, it can first store the data in the first-level cache, then move the data from the first-level cache to the DDR second-level cache, and finally transfer the data from the DDR second-level cache stored in disk array.
  • the receiving timing of each data frame or data packet can also be adjusted through the two-level buffer structure, thereby ensuring the correct protocol analysis of the data received by each interface and the integrity of the data.
  • both the on-chip memory and the DDR secondary cache can cache data in a ping-pong cache manner, for example.
  • the ping-pong cache method is adopted to further improve the efficiency of data transmission.
  • the data simulation device further includes, for example, a PCIe (PCI-Express) bus for connecting a programmable logic device and a client to transmit simulation data.
  • PCIe PCI-Express
  • the data simulation device of the present disclosure can be directly connected to the main board of the computer independently, mounted and used through the PCIe bus, and realizes communication with the application management software.
  • the programmable logic device is also used to obtain configuration information through the PCIe bus, so as to divide the transmission channel sector and the reception channel sector.
  • the disk also includes: an independent configuration sector for storing configuration information.
  • Each cache element also includes: an independent cache area, which is used for reading and writing data of independent configuration sectors.
  • the data simulation device is connected to the client through the PCIe bus, for example, and the client sets the configuration information of each interface through application software according to each interface protocol, so that data can be transmitted through each interface according to the protocol.
  • the configuration information includes, for example, parameters such as storage partition size, starting position, data frame size, frame interval, and data delivery and uploading path of each data sending channel or receiving channel.
  • the programmable logic device has PCIe control logic, which can control the data simulation device to store these configuration information in the PCIe cache area through the PCIe bus, and then further store them in the inherent independent configuration sector of the disk.
  • the application software can automatically read back the configuration and display it through the PCIe bus. If you need to change the configuration information, after the software is set, the new configuration information will be updated into the independent configuration sector.
  • the PCIe bus can be connected to the client through the Thunderbolt controller, that is, the data simulation device of the present disclosure can also communicate with the application management software through the Thunderbolt interface.
  • the data simulation device includes, for example, a Thunderbolt controller to realize the Thunderbolt interface communication with the computer and the PCIe bus protocol conversion between the computer and the programmable logic device.
  • the data simulation device can be connected to a laptop computer through a lightning connector, which improves the portability of the device.
  • the programmable logic device is further configured to obtain the configuration register through the PCIe bus, so as to reset the first address of the sending channel sector or the receiving channel sector. Resetting the first address can determine the timing of data transfer and re-partition the sector. After the data stored in the memory sector is sent or the application software clicks to restore the first address of the sector, the control logic returns to the first address of the sector to start transferring data.
  • Fig. 3 schematically shows a flowchart of a data simulation method according to an embodiment of the present disclosure.
  • the data simulation method includes, for example:
  • the data simulation device before starting to transmit the simulated data, the data simulation device communicates with the application management software of the computer, for example, through the PCIe bus, or communicates with the computer through the Thunderbolt interface.
  • the application management software is connected to the data simulation device to check the hardware information status of the device.
  • the application management software can be used to read back or configure the first address of the sector occupied by the disk of each interface channel of the data simulation device, the size of the capacity, and the remaining space to display.
  • the interface configuration information use at least one first interface and/or at least one second interface to transmit the analog data.
  • the analog data includes first data and second data, and the transmission rate of the first data is lower than the transmission rate of the second data.
  • the data of each transmission channel is downloaded to the configured sector space.
  • the working mode of each sending channel can also be set through the software: in the external trigger activation mode, each sending channel controls the sending and stopping of data according to the working parameters set by the external trigger signal.
  • the software controls the sending and stopping of data.
  • the data sending and receiving behaviors of each interface channel are independent of each other, and the software can display the sending and receiving data information of each interface.
  • Each sending channel reads out the data in its sector and sends it out according to the set working parameters.
  • Each receiving channel receives data in real time, the data is saved in the set sector space, the software sets the format and path of the saved file, and uploads the data in the sector space to the local computer.
  • the software also supports the reset of the initial sector address of the sending and receiving interface channels respectively. After reset, the sending channel starts to send data from the first address of their respective sectors, and the receiving channel starts to store data from the first address of their respective sectors.
  • the simulated data in the present disclosure includes, for example, data to be simulated downloaded from the PC and high-speed and low-speed data input by an external system.
  • the data to be simulated can be input to the data simulation device through a client (PC), for example, and then input from the data simulation device to an external system.
  • High-speed and low-speed data can also be input from an external system to the data simulation device, and then uploaded from the data simulation device to the client.
  • the specific process of data transmission is, for example, shown in Figure 2.
  • the application software first downloads the data to be simulated through the PCIe bus, and the PCIe control logic of the data simulation device writes the data to be simulated into DDR3 (8Gb, x64, 1333M) through XDMA operations, for example. Open up the PCIe buffer (8MB), and then execute the DMA write operation from DDR to SATA, and write the data to be simulated into the SATA memory.
  • DDR3 8Gb, x64, 1333M
  • XDMA operations for example.
  • Open up the PCIe buffer (8MB) and then execute the DMA write operation from DDR to SATA, and write the data to be simulated into the SATA memory.
  • each sending channel such as the TLK2711 sending channel
  • the control logic performs a SATA DMA read operation (16MB), and reads data blocks from its sectors to its DDR buffer in sequence area (32MB), the buffer, for example, adopts a ping-pong operation mode of 16MB each, and whenever the data is full, the data will be moved to the first-level buffer (128KB) in the control logic of the programmable logic device.
  • the control logic can start a 16KB DMA operation to move the data from the DDR buffer to the primary buffer.
  • control logic reads the data from the primary buffer, and sends the data to the external system according to the protocol according to the configuration information set by the application software.
  • the control logic will stop sending data after sending a complete protocol frame data, and the sector address will keep the current value unchanged.
  • each receiving channel of the data simulation device When data is input from an external system to the data simulation device, each receiving channel of the data simulation device, such as the TLK2711 receiving channel, analyzes in real time according to the configuration information set by the application software and writes the correct data into the first level of its control logic buffer (512KB).
  • the control logic moves the data to its DDR buffer (32MB).
  • the buffer adopts the ping-pong operation mode of 16MB respectively. Start DMA to sequentially write 16MB data into its SATA sector, and alternately repeat the ping-pong buffer to write the data into the SATA memory in real time.
  • each receiving channel will write the correct data into its sector space in real-time order according to the protocol analysis. If the control logic does not detect the data, the sector write address will keep the current value unchanged. According to the need, the application The software can set the first address of the recovery sector.
  • each channel stores the data in SATA, and the application software sets the uploaded data volume and storage format. For example, to request the TLK2711 receiving channel to upload 500MB of data, you can set the number of files to 1 and the size of a single file to 500MB, or set the number of files to 5 and the size of a single file to 100MB.
  • the embodiments of the present disclosure provide a data simulation device and method.
  • the analog data communication between interfaces of large complex visual processing systems etc. greatly improves the testing efficiency of external systems.
  • the data simulation device of the present disclosure can realize data transmission, reception and real-time storage of data interfaces of various channels of different application layer protocols, and can be widely used in fields such as robotics, industrial vision, and scientific research.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include one or more of these features.
  • plural means at least two, such as two, three, etc., unless otherwise specifically defined.

Abstract

本公开提供一种数据模拟装置及方法，装置包括：可编程逻辑器件，用于实现至少一种接口协议，以根据接口协议分别对模拟数据和测试数据进行发送和接收，其中，模拟数据包括第一数据和第二数据，第一数据的传输速率小于第二数据的传输速率；至少一个第一接口，用于连接可编程逻辑器件和至少一个第一待测设备，以传输第一数据和测试数据；和/或，至少一个第二接口，用于连接可编程逻辑器件和至少一个第二待测设备，以传输第二数据和测试数据。本公开提供的数据模拟装置可以集中统一实现与外部大型复杂视觉处理系统等的各接口之间的模拟数据通信，大大提高了外部系统的测试效率。

Description

数据模拟装置及方法 技术领域
本公开涉及计算机通信技术领域，尤其涉及一种数据模拟装置及方法。
背景技术
当前工业视觉、科学研究等领域的大型复杂视觉处理系统，普遍存在不同数据协议的控制接口和数据接口，系统各组件的功能验证都需要专用的接口设备进行单独测试，导致系统的闭环验证效率很低，而且整个验证过程非常复杂且不稳定，对于有接口同步和可自定义数据协议要求的系统更是无法满足测试要求。
因此，需要一种具备丰富类型高速和低速接口的可收发自定义协议数据流的数据模拟源系统，以广泛应用于工业视觉、科学研究等领域视觉处理系统的算法、硬件以及架构验证。
发明内容
(一)要解决的技术问题
针对现有的技术问题，本公开提供一种数据模拟装置及方法，用于至少部分解决以上技术问题。
(二)技术方案
本公开提供一种数据模拟装置，包括：可编程逻辑器件，用于实现至少一种接口协议，以根据接口协议分别对模拟数据和测试数据进行发送和接收，其中，模拟数据包括第一数据和第二数据，第一数据的传输速率小于第二数据的传输速率；至少一个第一接口，用于连接可编程逻辑器件和至少一个第一待测设备，以传输第一数据和测试数据；和/或，至少一个第二接口，用于连接可编程逻辑器件和至少一个第二待测设备， 以传输第二数据和测试数据。
可选地，数据模拟装置还包括：磁盘阵列，与可编程逻辑器件通信连接，用于存储模拟数据；缓存阵列，与可编程逻辑器件通信连接，用于对磁盘阵列进行数据读写；其中，磁盘阵列包括至少一个磁盘，磁盘包括至少一个发送通道扇区和至少一个接收通道扇区，发送通道扇区用于存储发送的模拟数据，接收通道扇区用于存储接收的模拟数据；缓存阵列包括至少一个缓存元件，缓存元件包括至少一个发送通道缓存区和至少一个接收通道缓存区，发送通道缓存区用于对发送通道扇区进行数据读出，接收通道缓存区用于对接收通道扇区进行数据写入；第一接口和第二接口均分配有独立的发送通道扇区和接收通道扇区。
可选地，发送通道缓存区和接收通道缓存区采用乒乓缓存。
可选地，可编程逻辑器件包括片上存储器，用于对缓存阵列进行数据读写。
可选地，第一接口包括低电压差分信号接口，通用异步收发传输器接口和CANBUS接口；第二接口包括TLK2711接口和以太网接口。
可选地，数据模拟装置还包括：PCIe总线，用于连接可编程逻辑器件和客户端，以传输模拟数据；可编程逻辑器件还用于通过PCIe总线获取配置信息，以划分发送通道扇区和接收通道扇区；磁盘还包括：独立配置扇区，用于存储配置信息；缓存元件还包括：独立缓存区，用于对独立配置扇区进行数据读写。
可选地，可编程逻辑器件还用于通过PCIe总线获取配置寄存器，以复位发送通道扇区或接收通道扇区的首地址。
可选地，PCIe总线通过雷电控制器与客户端相连接。
可选地，第一接口或第二接口采用单帧同步、单帧异步、连续同步和连续异步中的任一种方式传输模拟数据。
本公开另一方面提供一种数据模拟方法，包括：利用可编程逻辑器件实现至少一种接口协议；根据接口协议获取接口配置信息；根据接口配置信息，采用至少一个第一接口和/或至少一个第二接口对模拟数据进行传输；其中，模拟数据包括第一数据和第二数据，第一数据的传输速 率小于第二数据的传输速率。
(三)有益效果
本公开提供一种数据模拟装置，通过将多个具有不同数据传输速率、不同数据传输协议的接口与可编程逻辑器件相连接，并在可编程逻辑器件上片上实现与各接口对应的多种数据传输协议，可以集中统一实现与外部大型复杂视觉处理系统等的各接口之间的模拟数据通信，大大提高了外部系统的测试效率。
本公开的数据模拟装置还包括缓存阵列和磁盘阵列，其中的各缓存元件和磁盘分别为各个接口划分有独立的缓存区和扇区，使得各接口可以以同步或异步方式发送各自定义协议的模拟数据。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示意性示出了根据本公开实施例的数据模拟装置的结构图；
图2示意性示出了根据本公开实施例的数据模拟装置的存储结构图；
图3示意性示出了根据本公开实施例的数据模拟方法流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
需要说明的是，在附图或说明书描述中，相似或相同的部分都使用相同的图号。说明书中示例的各个实施例中的技术特征在无冲突的前提下可以进行自由组合形成新的方案，另外每个权利要求可以单独作为一个实施例或者各个权利要求中的技术特征可以进行组合作为新的实施例，且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。再者，附图中未绘示或描述的元件或实现方式，为所属技术领域中 普通技术人员所知的形式。另外，虽然本文可提供包含特定值的参数的示范，但应了解，参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应的值。
除非存在技术障碍或矛盾，本公开的上述各种实施方式可以自由组合以形成另外的实施例，这些另外的实施例均在本公开的保护范围中。
虽然结合附图对本公开进行了说明，但是附图中公开的实施例旨在对本公开优选实施方式进行示例性说明，而不能理解为对本公开的一种限制。附图中的尺寸比例仅仅是示意性的，并不能理解为对本公开的限制。
虽然本公开总体构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离本总体公开构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。
图1示意性示出了根据本公开实施例的数据模拟装置的结构图。
根据本公开的实施例，如图1所示，数据模拟装置，也可称为数据模拟源，例如包括：可编程逻辑器件，用于实现至少一种接口协议，以根据接口协议分别对模拟数据和测试数据进行发送和接收，其中，模拟数据包括第一数据和第二数据，第一数据的传输速率小于第二数据的传输速率。至少一个第一接口，用于连接可编程逻辑器件和至少一个第一待测设备，以传输第一数据和测试数据。和/或，至少一个第二接口，用于连接可编程逻辑器件和至少一个第二待测设备，以传输第二数据和测试数据。模拟数据例如为数据模拟装置发送到各被测试设备的数据，测试数据例如为各被测试设备反馈给数据模拟装置的结果数据。测试数据的传输速率属性与对应接口的模拟数据一致。第一数据例如为低速数据，第一接口例如为低速接口，低速接口将可编程逻辑器件与外部系统，例如大型复杂视觉处理系统的低速数据接口相连接，通过在可编程逻辑器件上片上实现相应的低速数据传输协议，可以实现本数据模拟装置与外部系统的不同低速数据传输协议的低速数据的互相传输。同样的，第二数据例如为高速数据，第二接口例如为高速接口，高速接口将可编程逻辑器件与外部系统，例如大型复杂视觉处理系统的高速数据接口相连接， 通过在可编程逻辑器件上片上实现相应的高速数据传输协议，可以实现本数据模拟装置与外部系统的不同高速数据传输协议的高速数据的互相传输。可编程逻辑器件例如可以片上实现DDR3控制器、PCIe 2.0总线、SATA 3.0、万兆以太网和CANBUS 2.0B控制器等协议及自定义协议。第一待测设备例如为外部系统中，产生或利用低速数据的设备，第二测设备例如为外部系统中，产生或利用高速数据的设备。
可以理解的是，本公开中的可编程逻辑器件可以是现场可编程门阵列(FPGA)和复杂可编程逻辑器件(CPLD)等任意可片上实现自定义数据传输协议以及多接口数据通信的可编程逻辑器件。
根据本公开的实施例，如图1所示，第一接口和第二接口例如分别表示一类接口，即第一接口例如为传输低速数据的低速接口，第二接口例如为传输高速数据的高速接口。第一接口例如可以是低电压差分信号接口(LVDS(Low-Voltage Differential Signaling)接口)，通用异步收发传输器接口(UART(Universal Asynchronous Receiver/Transmitter)接口)和CANBUS接口等。第二接口例如包括TLK2711接口和以太网接口等。其中，各接口例如为接口芯片驱动相应连接器的工作方式，例如LVDS接口为LVDS接口芯片驱动低速连接器与外部系统进行低速数据传输，TLK2711接口为TLK2711接口芯片驱动同轴连接器与外部系统进行高速数据传输。而以太网接口例如直接通过光纤连接器与外部系统进行高速数据传输。以太网接口例如适用于百兆以太网、千兆以太网、万兆以太网、40G以及更高带宽以太网等。第一接口或第二接口例如可以采用单帧同步、单帧异步、连续同步和连续异步中的任一种方式传输模拟数据。
在一个实施例中，数据模拟装置例如包括2个LVDS物理层驱动电路，分别实现1路三线LVDS接口和1路两线LVDS接口。3个UART物理层驱动电路，分别实现1路外触发信号接口、1路同步RS422和5个异步RS422接口。1个CANBUS物理层驱动电路，实现1路CANBUS接口。以及3个TLK2711驱动电路，实现3路2711高速串行收发器接口。
可以理解的是，驱动电路的数量和各接口的数量可以根据外部系统的数据传输需要进行设置，本公开不作具体限定。
图2示意性示出了根据本公开实施例的数据模拟装置的存储结构图。
根据本公开的实施例，数据模拟装置例如还包括：磁盘阵列，与可编程逻辑器件通信连接，用于存储模拟数据和测试数据。在系统断开连接，停止供电后，由于磁盘阵列的非易失性，模拟数据不会丢失，可供下次模拟使用。模拟长时间大数据量数据时，磁盘阵列可保证数据输出模拟及输入存储的稳定性。缓存阵列，与可编程逻辑器件通信连接，用于对磁盘阵列进行数据读写。缓存阵列例如可以为DRAM阵列。其中，如图2所示，磁盘阵列包括至少一个磁盘，磁盘例如为SSD存储器，SSD存储器例如可以是SATA存储器或者NVME存储器。磁盘包括至少一个发送通道扇区和至少一个接收通道扇区，发送通道扇区用于存储发送的模拟数据，接收通道扇区用于存储接收的测试数据。缓存阵列包括至少一个缓存元件，缓存元件例如可以是DDR颗粒或者DDR内存条。各缓存元件包括至少一个发送通道缓存区和至少一个接收通道缓存区，发送通道缓存区用于对发送通道扇区进行数据读出，接收通道缓存区用于对接收通道扇区进行数据写入。第一接口和第二接口均分配有独立的发送通道扇区和接收通道扇区。例如TLK2711接口根据数据的传输方向，可以分为发送通道和接收通道。在从数据模拟装置发送数据时，TLK2711发送通道对应有独立的发送通道缓存区和发送通道扇区，例如可以是发送通道1缓存区和发送通道1扇区。LVDS发送通道例如可以对应发送通道2缓存区和发送通道2扇区。以此类推，数据模拟装置为每个接口均分配有独立的发送通道缓存区和发送通道扇区。外部系统例如可以提供待模拟的数据以及返回测试结果数据等到数据模拟装置，在从外部系统接收数据时，TLK2711接收通道例如对应接收通道1缓存区和接收通道1扇区。LVDS接收通道例如对应接收通道2缓存区和接收通道2扇区。以此类推，数据模拟装置也为每个接口均分配有独立的接收通道缓存区和接收通道扇区。同时，由于存储结构例如为磁盘阵列，缓存结构例如为缓存阵列，可以提升同一个接口的有效数据传输带宽，例如 TLK2711发送通道对应两个发送通道1缓存区和两个发送通道1扇区，可以提升TLK2711发送通道的有效数据传输带宽。
可以理解的是，磁盘和缓存元件的数量例如根据各接口需要传输的数据带宽的要求来确定。发送通道扇区和接收通道扇区的数量例如根据接口的数量来确定，本公开不作具体限定。
根据本公开的实施例，可编程逻辑器件例如包括片上存储器，用于对缓存阵列进行数据读写。缓存阵列和片上存储器构成两级缓存结构，实现了从磁盘阵列中读写数据的两级缓存。如图2所示，片上存储器例如为一级缓存，缓存元件(构成缓存阵列)例如为DDR二级缓存。数据模拟装置在向外部系统发送数据时，可以先将数据从磁盘阵列中读出到DDR二级缓存中，再将数据从DDR二级缓存中搬移到一级缓存中，最后从一级缓存中读取数据并按协议发出数据。由于各接口数据可能采用同步传输的方式传输，需要在缓存区中缓存完整的数据帧或数据包，因而通过两级缓存结构可以调节各数据帧或数据包的发送时序，进而保障各接口数据的同步发送。同样的，数据模拟装置在从外部系统接收数据时，可以先将数据存入一级缓存中，再将数据从一级缓存中搬移到DDR二级缓存中，最后将数据从DDR二级缓存中存入磁盘阵列。通过两级缓存结构也可以调节各数据帧或数据包的接收时序，进而保障各接口接收数据的正确协议解析以及数据的完整性。
优选地，片上存储器和DDR二级缓存例如可以均采用乒乓缓存的方式进行数据的缓存。采用乒乓缓存的方式，进一步提升了数据传输的效率。
根据本公开的实施例，数据模拟装置例如还包括：PCIe(PCI-Express)总线，用于连接可编程逻辑器件和客户端，以传输模拟数据。本公开的数据模拟装置可以单独的与计算机主板直接相连，通过PCIe总线挂载使用，实现与应用管理软件通信。可编程逻辑器件还用于通过PCIe总线获取配置信息，以划分发送通道扇区和接收通道扇区。磁盘还包括：独立配置扇区，用于存储配置信息。各缓存元件还包括：独立缓存区，用于对独立配置扇区进行数据读写。数据模拟装置例如通过PCIe总线 与客户端连接，客户端根据各接口协议，通过应用软件来设置各接口的配置信息，使得数据可以按协议通过各接口进行传输。该配置信息例如包括各数据发送通道或接收通道的存储分区大小、起始位置、数据帧大小、帧间隔和数据下发上传路径等参数。可编程逻辑器件中具有PCIe控制逻辑，可以控制数据模拟装置通过PCIe总线将这些配置信息存储在PCIe缓存区中，进而进一步存储到磁盘固有的独立配置扇区中，当数据模拟装置重新上电后，应用软件可以通过PCIe总线自动读回配置并显示。如需更改配置信息，软件设置后，新配置的信息会更新进该独立配置扇区。
优选地，PCIe总线例如可以通过雷电控制器与客户端相连接，即本公开的数据模拟装置也可以通过雷电接口实现与应用管理软件的通信。本实施例中，数据模拟装置例如包括1个雷电控制器，实现与计算机的雷电接口通信，及计算机与可编程逻辑器件之间的PCIe总线协议转换。数据模拟装置通过雷电连接器可以与笔记本电脑相连接，提升了装置的便携性。
根据本公开的实施例，可编程逻辑器件还用于通过PCIe总线获取配置寄存器，以复位发送通道扇区或接收通道扇区的首地址。复位首地址可以确定数据搬运的时机以及对扇区进行重新划分。存储器扇区中存储的数据发送完后或者应用软件点击恢复扇区首地址后，控制逻辑回到扇区首地址开始搬运数据。
图3示意性示出了根据本公开实施例的数据模拟方法流程图。
根据本公开的实施例，如图3所示，数据模拟方法例如包括：
S310，利用可编程逻辑器件实现至少一种接口协议。
根据本公开的实施例，在开始传输模拟数据之前，数据模拟装置例如通过PCIe总线与计算机的应用管理软件通信，或通过雷电接口与计算机通信。应用管理软件连接数据模拟装置，检查装置的硬件信息状态。
S320，根据接口协议获取接口配置信息。
根据本公开的实施例，根据各接口需要传输的数据类型及传输速率要求等，可以通过应用管理软件读回或配置数据模拟装置各接口通道的 磁盘占用扇区首地址、容量大小，并对剩余空间进行显示。
S330，根据接口配置信息，采用至少一个第一接口和/或至少一个第二接口对模拟数据进行传输。其中，模拟数据包括第一数据和第二数据，第一数据的传输速率小于第二数据的传输速率。
根据本公开的实施例，通过选择文件所在的路径，将各发送通道的数据下传到已经配置的扇区空间。根据协议需要，设置发送数据的接口所需的帧头、帧大小、帧间隔、模式、延迟等参数。同时，也可以通过软件设置各发送通道的工作模式：外触发激活模式下，各发送通道按照其设置的工作参数，由外触发信号控制数据的发送与停止。禁用外触发模式下，软件控制数据的发送与停止。各接口通道的数据发送与接收行为相互独立，软件可以显示各接口的发送与接收数据信息。每次启动数据发送或有数据接收，各通道数据的发送与接收例如分别是连续读取和写入定义的磁盘扇区。各发送通道将其扇区内的数据读出，按照设置的工作参数发送出去。各接收通道实时接收数据，数据保存在设置的扇区空间，软件设置保存文件的格式和路径，将扇区空间的数据上传到本地计算机。软件还分别支持发送与接收接口通道的起始扇区地址复位。复位后，发送通道从各自扇区首地址开始发送数据，接收通道从各自扇区首地址开始存储。
根据本公开的实施例，本公开中的模拟数据例如包括PC端下传的待模拟数据和外部系统输入的高速、低速数据。待模拟数据例如可以通过客户端(PC)输入到数据模拟装置，再从数据模拟装置输入到外部系统中。高速、低速数据也可以从外部系统输入到数据模拟装置，再从数据模拟装置上传到客户端。数据传输的具体过程例如如图2所示，应用软件首先通过PCIe总线下传待模拟数据，数据模拟装置的PCIe控制逻辑例如通过XDMA操作将待模拟数据写入DDR3(8Gb，x64，1333M)中开辟的PCIe缓冲区(8MB)，然后执行DDR到SATA的DMA写操作，将待模拟数据写入SATA存储器。
当数据模拟装置收到外部触发信号或者应用软件点击开始发送，各发送通道，如TLK2711发送通道，控制逻辑执行SATA DMA读操作 (16MB)，从其扇区按顺序读出数据块到其DDR缓冲区(32MB)，该缓冲区例如采用各16MB的乒乓操作模式，每当数据填满后，数据将搬移到可编程逻辑器件控制逻辑内部中的一级缓冲区(128KB)。每当一级缓冲区中的数据量低于64KB，控制逻辑可以启动16KB DMA操作从DDR缓冲区中将数据搬移到一级缓冲区。然后控制逻辑再从一级缓冲区读取数据，根据应用软件设置的配置信息，按协议发出数据到外部系统。当外触发信号消失或应用软件点击停止发送，控制逻辑会发送完一个完整的协议帧数据后，停止发送数据，扇区地址保持当前值不变。
当从外部系统输入数据到数据模拟装置时，数据模拟装置的各接收通道，如TLK2711接收通道，按照应用软件设置的配置信息，实时解析并将正确的数据首先写入其控制逻辑内的一级缓冲区(512KB)。一级缓冲区中的数据量超过16KB时，控制逻辑将数据搬移到其DDR缓冲区(32MB)中，该缓冲区采用各自16MB的乒乓操作模式，乒缓冲区内的16MB数据满后，控制逻辑启动DMA将16MB数据顺序写入其SATA扇区，乒乓缓冲区交替反复，将数据实时的写入SATA存储器。各接收通道根据应用软件设置的配置信息，按照协议解析正确的数据会实时的顺序写入其扇区空间，控制逻辑如果没有检测到数据，扇区写地址保持当前值不变，根据需要，应用软件可以设置恢复扇区首地址。
数据从数据模拟装置上传到客户端时，各通道存储在SATA中的数据，由应用软件设置上传的数据量和存储格式。比如，请求TLK2711接收通道上传500MB的数据，可以根据需要设置文件个数为1，单个文件大小为500MB，也可以设置文件个数为5，单个文件大小为100MB。
综上所述，本公开实施例提出一种数据模拟装置及方法。通过将多个具有不同数据传输速率、不同数据传输协议的接口与可编程逻辑器件相连接，并在可编程逻辑器件上片上实现与各接口对应的多种数据传输协议，可以集中统一实现与外部大型复杂视觉处理系统等的各接口之间的模拟数据通信，大大提高了外部系统的测试效率。本公开的数据模拟装置可以实现不同应用层协议的各通道数据接口的数据发送、接收以及实时存储，可广泛应用于机器人、工业视觉、科学研究等领域。
方法实施例部分未尽细节之处与装置实施例部分类似，请参见装置实施例部分，此处不再赘述。
应该明白，公开的过程中的步骤的特定顺序或层次是示例性方法的实例。基于设计偏好，应该理解，过程中的步骤的特定顺序或层次可以在不脱离本公开的保护范围的情况下得到重新安排。所附的方法权利要求以示例性的顺序给出了各种步骤的要素，并且不是要限于的特定顺序或层次。
还需要说明的是，实施例中提到的方向术语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。可能导致本公开的理解造成混淆时，将省略常规结构或构造。并且图中各部件的形状、尺寸、位置关系不反映真实大小、比例和实际位置关系。
在上述的详细描述中，各种特征一起组合在单个的实施方案中，以简化本公开。不应该将这种公开方法解释为反映了这样的意图，即，所要求保护的主题的实施方案需要比清楚地在每个权利要求中所陈述的特征更多的特征。相反，如所附的权利要求书所反映的那样，本公开处于比所公开的单个实施方案的全部特征少的状态。因此，所附的权利要求书特此清楚地被并入详细描述中，其中每项权利要求独自作为本公开单独的优选实施方案。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。因此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个、三个等，除非另有明确具体的限定。就说明书或权利要求书中使用的术语“包含”，该词的涵盖方式类似于术语“包括”，就如同“包括，”在权利要求中用作衔接词所解释的那样。使用在权利要求书的说明书中的任何一个术语“或者”是要表示“非排它性的或者”。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施 例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种数据模拟装置，其特征在于，包括：
    可编程逻辑器件，用于实现至少一种接口协议，以根据所述接口协议分别对模拟数据和测试数据进行发送和接收，其中，所述模拟数据包括第一数据和第二数据，所述第一数据的传输速率小于所述第二数据的传输速率；
    至少一个第一接口，用于连接所述可编程逻辑器件和至少一个第一待测设备，以传输所述第一数据和所述测试数据；和/或，
    至少一个第二接口，用于连接所述可编程逻辑器件和至少一个第二待测设备，以传输所述第二数据和所述测试数据。
  2. 根据权利要求1所述的数据模拟装置，其特征在于，还包括：
    磁盘阵列，与所述可编程逻辑器件通信连接，用于存储所述模拟数据和所述测试数据；
    缓存阵列，与所述可编程逻辑器件通信连接，用于对所述磁盘阵列进行数据读写；
    其中，所述磁盘阵列包括至少一个磁盘，所述磁盘包括至少一个发送通道扇区和至少一个接收通道扇区，所述发送通道扇区用于存储发送的所述模拟数据，所述接收通道扇区用于存储接收的所述测试数据；
    所述缓存阵列包括至少一个缓存元件，所述缓存元件包括至少一个发送通道缓存区和至少一个接收通道缓存区，所述发送通道缓存区用于对所述发送通道扇区进行数据读出，所述接收通道缓存区用于对所述接收通道扇区进行数据写入；
    所述第一接口和所述第二接口均分配有独立的所述发送通道扇区和所述接收通道扇区。
  3. 根据权利要求2所述的数据模拟装置，其特征在于，所述发送通道缓存区和所述接收通道缓存区采用乒乓缓存。
  4. 根据权利要求2所述的数据模拟装置，其特征在于，所述可编程逻辑器件包括片上存储器，用于对所述缓存阵列进行数据读写。
  5. 根据权利要求1所述的数据模拟装置，其特征在于，所述第一接口包括低电压差分信号接口，通用异步收发传输器接口和CANBUS接口；
    所述第二接口包括TLK2711接口和以太网接口。
  6. 根据权利要求2所述的数据模拟装置，其特征在于，所述数据模拟装置还包括：
    PCIe总线，用于连接所述可编程逻辑器件和客户端，以传输所述模拟数据；
    所述可编程逻辑器件还用于通过所述PCIe总线获取配置信息，以划分所述发送通道扇区和所述接收通道扇区；
    所述磁盘还包括：
    独立配置扇区，用于存储所述配置信息；
    所述缓存元件还包括：
    独立缓存区，用于对所述独立配置扇区进行数据读写。
  7. 根据权利要求6所述的数据模拟装置，其特征在于，所述可编程逻辑器件还用于通过所述PCIe总线获取配置寄存器，以复位所述发送通道扇区或所述接收通道扇区的首地址。
  8. 根据权利要求6所述的数据模拟装置，其特征在于，所述PCIe总线通过雷电控制器与所述客户端相连接。
  9. 根据权利要求1所述的数据模拟装置，其特征在于，所述第一接口或所述第二接口采用单帧同步、单帧异步、连续同步和连续异步中的任一种方式传输所述模拟数据。
  10. 一种数据模拟方法，包括：
    利用可编程逻辑器件实现至少一种接口协议；
    根据所述接口协议获取接口配置信息；
    根据所述接口配置信息，采用至少一个第一接口和/或至少一个第二接口对模拟数据进行传输；
    其中，所述模拟数据包括第一数据和第二数据，所述第一数据的传输速率小于所述第二数据的传输速率。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104820637A (zh) * 2015-04-17 2015-08-05 中国电子科技集团公司第四十一研究所 一种手持式usb3.0协议分析仪
US20180205621A1 (en) * 2017-01-13 2018-07-19 A.T.E. Solutions, Inc. Systems and methods for dynamically reconfiguring automatic test equipment
CN110362058A (zh) * 2018-04-11 2019-10-22 徐伟 用于多个接口进行测试的系统
CN113035267A (zh) * 2021-03-25 2021-06-25 长江存储科技有限责任公司 一种半导体测试装置、数据处理方法、设备及存储介质

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104820637A (zh) * 2015-04-17 2015-08-05 中国电子科技集团公司第四十一研究所 一种手持式usb3.0协议分析仪
US20180205621A1 (en) * 2017-01-13 2018-07-19 A.T.E. Solutions, Inc. Systems and methods for dynamically reconfiguring automatic test equipment
CN110362058A (zh) * 2018-04-11 2019-10-22 徐伟 用于多个接口进行测试的系统
CN113035267A (zh) * 2021-03-25 2021-06-25 长江存储科技有限责任公司 一种半导体测试装置、数据处理方法、设备及存储介质

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