WO2023159441A1 - 显示基板、其制作方法及显示装置 - Google Patents

显示基板、其制作方法及显示装置 Download PDF

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Publication number
WO2023159441A1
WO2023159441A1 PCT/CN2022/077762 CN2022077762W WO2023159441A1 WO 2023159441 A1 WO2023159441 A1 WO 2023159441A1 CN 2022077762 W CN2022077762 W CN 2022077762W WO 2023159441 A1 WO2023159441 A1 WO 2023159441A1
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WIPO (PCT)
Prior art keywords
conductive
layer
insulating layer
conductive pattern
hole
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PCT/CN2022/077762
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English (en)
French (fr)
Inventor
王敏
王哲
华刚
邓立广
王冬
李少波
胡锦堂
刘景昊
苏少凯
潘靓靓
白家豪
林志宁
陈鑫雨
齐梓希
张鹏曲
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/077762 priority Critical patent/WO2023159441A1/zh
Priority to CN202280000262.0A priority patent/CN117296007A/zh
Publication of WO2023159441A1 publication Critical patent/WO2023159441A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including:
  • the base substrate includes a display area, and the display area includes a plurality of pixel areas;
  • At least four conductive layers stacked on the base substrate any two adjacent conductive layers are insulated from each other, each of the conductive layers includes a conductive pattern located in each of the pixel regions, The conductive patterns of any two adjacent conductive layers in the same pixel area form a storage capacitor, and in the direction perpendicular to the base substrate, the projection of the at least four conductive layers on the base substrate overlap.
  • the at least four conductive layers include a first conductive layer, a second conductive layer, a third conductive layer and a pixel electrode layer, wherein,
  • the first conductive layer includes a first conductive pattern
  • the second conductive layer includes a second conductive pattern
  • the third conductive layer includes a third conductive pattern
  • the pixel electrode layer includes a pixel electrode
  • the first conductive pattern and the second conductive pattern constitute a first storage capacitor
  • the second conductive pattern and the third conductive pattern constitute a second storage capacitor
  • the third conductive pattern and the pixel electrode constitute a a third storage capacitor
  • the first conductive pattern is electrically connected to the third conductive pattern
  • the second conductive pattern is electrically connected to the pixel electrode.
  • the above display substrate provided by the embodiments of the present disclosure further includes a first insulating layer, a second insulating layer and a third insulating layer, wherein the first insulating layer is located on the first conductive layer between the second conductive layer, the second insulating layer is located between the second conductive layer and the third conductive layer, and the third insulating layer is located between the third conductive layer and the pixel between the electrode layers.
  • the second insulating layer and the third insulating layer include a through hole disposed through, and the pixel electrode communicates with the pixel electrode through the through hole.
  • the second conductive patterns are electrically connected.
  • the third conductive pattern includes a hollow structure, and the orthographic projection of the hollow structure on the base substrate covers the through hole on the Orthographic projection on the substrate substrate.
  • the base substrate further includes a non-display area surrounding the display area;
  • the first conductive layer further includes a first connection line, the first connection line extends along a first direction, and the first connection line is integrated with the first conductive pattern;
  • the third conductive layer further includes a second connection line, the second connection line extends along a second direction, and the second connection line is integrated with the third conductive pattern, and the second direction and the First direction cross setting;
  • the pixel electrode layer further includes a wiring located in the non-display area, the wiring surrounds the display area and is electrically connected to the first connection line and the second connection line respectively.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a transistor located in the pixel region, the gate of the transistor is located in the first conductive layer, the first electrode of the transistor, The second pole is located on the second conductive layer.
  • the third conductive layer is metal
  • the orthographic projection of the third conductive pattern on the base substrate at least covers the trench of the transistor. Orthographic projection of the track area on the base substrate.
  • the orthographic projection of the first conductive pattern on the base substrate half surrounds the orthographic projection of the transistor on the base substrate.
  • the orthographic projection of the second conductive pattern on the base substrate is the same as the orthographic projection of the first conductive pattern on the base substrate.
  • the projections overlap, and the second conductive pattern is integrally arranged with the first pole of the transistor.
  • the orthographic projection of the pixel electrode on the base substrate completely covers the orthographic projection of the transistor on the base substrate.
  • an embodiment of the present disclosure provides a display device, including a display substrate and a counter substrate facing each other, and a dimming layer located between the display substrate and the counter substrate, wherein the display substrate
  • a display substrate including a display substrate and a counter substrate facing each other, and a dimming layer located between the display substrate and the counter substrate, wherein the display substrate
  • the opposite substrate includes a common electrode, and the common electrode, the first conductive pattern and the third conductive pattern are loaded with the same electrical signal .
  • the light-adjusting layer is an electrophoretic layer or a liquid crystal layer.
  • an embodiment of the present disclosure provides a method for manufacturing the above display substrate, including:
  • a base substrate is provided, the base substrate includes a display area, and the display area includes a plurality of pixel areas;
  • At least four conductive layers stacked are formed on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each of the pixel regions, any The conductive patterns of two adjacent conductive layers in the same pixel area form a storage capacitor, and in the direction perpendicular to the base substrate, the projections of the at least four conductive layers on the base substrate overlap stack.
  • At least four conductive layers stacked are formed on the base substrate, and any two adjacent conductive layers are insulated from each other,
  • Each of the conductive layers includes a conductive pattern located in each of the pixel regions, and the conductive patterns of any two adjacent conductive layers in the same pixel region form a storage capacitor.
  • the projections of the at least four conductive layers on the base substrate overlap, specifically including:
  • the first conductive layer including a first conductive pattern located in the pixel region;
  • a second conductive layer is formed on the first inorganic insulating layer, the second conductive layer includes a second conductive pattern located in the pixel area, and the second conductive pattern and the first conductive pattern constitute a first memory capacitance;
  • a third conductive layer is formed on the second inorganic insulating layer, the third conductive layer includes a third conductive pattern located in the pixel area, and the third conductive pattern and the second conductive pattern form a second memory capacitance;
  • a pixel electrode layer is formed on the third inorganic insulating layer, the pixel electrode layer includes a pixel electrode located in the pixel area, the pixel electrode and the third conductive pattern form a third storage capacitor, and the pixel The electrodes are electrically connected to the second conductive patterns through the first through holes.
  • Also includes:
  • An organic insulating layer is formed on the second conductive layer, the organic insulating layer includes a second through hole located in the pixel region, and the second through hole is connected to the first through hole.
  • the first conductive pattern located in the pixel area on the base substrate while forming the first conductive pattern located in the pixel area on the base substrate, it also includes: forming a pattern on the first conductive layer a first connection line extending along a first direction and integrally provided with the first conductive pattern;
  • Forming a first inorganic insulating layer on the first conductive layer specifically includes: forming a third through hole penetrating through the first inorganic insulating layer in a non-display area;
  • While forming the second conductive pattern located in the pixel area on the first inorganic insulating layer it also includes: forming a second conductive layer on the second conductive layer extending along the second direction and integrally arranged with the second conductive pattern a second connecting line, the second direction intersects the first direction;
  • first through hole penetrating through the third inorganic insulating layer and the second inorganic insulating layer in the pixel area it also includes: forming a through hole penetrating through the third inorganic insulating layer and the second inorganic insulating layer in the non-display area.
  • the fourth through hole of the second inorganic insulating layer, and the fifth through hole only penetrating through the third inorganic insulating layer in the non-display area, wherein the fourth through hole is connected to the third through hole Pass;
  • While forming the pixel electrode in the pixel region on the third inorganic insulating layer it also includes: forming a wiring in the pixel electrode layer in the non-display area, the wiring passing through the third The through hole and the fourth through hole are electrically connected to the first connection line, and the trace is electrically connected to the second connection line through the fifth through hole.
  • Also includes:
  • An organic insulating layer is formed on the second conductive layer, the organic insulating layer includes a second through hole located in the pixel area, and a sixth through hole located in the non-display area, the second through hole The sixth through hole is connected to the first through hole, and the sixth through hole is connected to the third through hole and the fourth through hole.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • Fig. 2 is a schematic diagram along the four pixel areas in Fig. 1;
  • Fig. 3 is a schematic structural view of the first conductive layer in Fig. 2;
  • Fig. 4 is the structural representation of the second conductive layer in Fig. 2;
  • Fig. 5 is a schematic structural view of the third conductive layer in Fig. 2;
  • FIG. 6 is a schematic structural diagram of a pixel electrode layer in FIG. 2;
  • FIG. 7 is a schematic structural diagram of the active layer and the insulating layer in FIG. 2;
  • Fig. 8 is a kind of sectional schematic diagram along I-I line in Fig. 2;
  • Fig. 9 is another kind of sectional schematic view along I-I line in Fig. 2;
  • FIG. 10 is a schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure in a non-display area;
  • FIG. 11 is another schematic cross-sectional view of a display substrate in a non-display area provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic cross-sectional view of a display substrate in the related art
  • FIG. 13 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 14 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIG. 1 to FIG. 8 , including:
  • a first base substrate 101, the first base substrate 101 includes a display area AA, and a plurality of pixel areas P are arranged in the display area AA;
  • At least four conductive layers (such as the first conductive layer 102, the second conductive layer 103, the third conductive layer 104 and the pixel electrode layer 105) that are stacked are located on the first base substrate 101, and any two adjacent conductive layers
  • the layers are insulated from each other, and each conductive layer includes a conductive pattern (such as a first conductive pattern 1021, a second conductive pattern 1031, a third conductive pattern 1041 and a pixel electrode 1051) located in each pixel area P, and any two adjacent
  • the conductive pattern of the conductive layer in the same pixel region P constitutes a storage capacitor (such as the first storage capacitor Cst 1 , the second storage capacitor Cst 2 , and the third storage capacitor Cst 3 ), and in the direction Z perpendicular to the substrate, the above-mentioned Projections of at least four conductive layers on the first base substrate 101 overlap.
  • conductive patterns are provided in at least four conductive layers, and the conductive patterns of any two adjacent conductive layers are arranged to overlap each other to form a storage capacitor, so that each pixel area P
  • Each has at least three storage capacitors, so that the capacitance value of each pixel region P can be effectively increased, which is beneficial to maintain voltage stability.
  • the first conductive layer 102 includes a first conductive pattern 1021
  • the second conductive layer 103 includes a second conductive pattern 1031
  • the third conductive layer 104 includes a third conductive pattern 1041
  • the pixel electrode layer 105 includes Pixel electrode 1051
  • the area surrounded by a thick solid line frame in Figure 2 represents a pixel electrode 1051
  • the first conductive pattern 1021 and the second conductive pattern 1031 constitute the first storage capacitor Cst 1
  • the conductive pattern 1041 forms the second storage capacitor Cst 2
  • the third conductive pattern 1041 and the pixel electrode 1051 form the third storage capacitor Cst 3
  • the first conductive pattern 1021 is electrically connected to the third conductive pattern 1041
  • the second conductive pattern 1031 is connected to the pixel
  • the electrodes 1051 forms the second storage capacitor Cst 2
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may further include a first insulating layer 106, a second insulating layer 107, and a third insulating layer 108, wherein, The first insulating layer 106 is located between the first conductive layer 102 and the second conductive layer 103, the second insulating layer 107 is located between the second conductive layer 103 and the third conductive layer 104, and the third insulating layer 108 is located in the third conductive layer.
  • the third conductive layer 104 is insulated from the pixel electrode layer 105 through the third insulating layer 108 .
  • the first insulating layer 106 is a first inorganic insulating layer
  • the second insulating layer 107 is a second inorganic insulating layer 1071
  • the third insulating layer 108 is a third inorganic insulating layer; or, the first insulating layer 106 is a second inorganic insulating layer.
  • An inorganic insulating layer, the third insulating layer 108 is the third inorganic insulating layer
  • the second insulating layer 107 includes a second inorganic insulating layer 1071 and an organic insulating layer 1072 stacked, and the second inorganic insulating layer 1071 is located on the organic insulating layer 1072 and the third insulating layer 108 .
  • the second insulating layer 107 and the third insulating layer 108 may include through holes disposed through.
  • the through hole is the first through hole h 1 penetrating through the second inorganic insulating layer 1071 and the third insulating layer 108 .
  • FIG. 8 the through hole is the first through hole h 1 penetrating through the second inorganic insulating layer 1071 and the third insulating layer 108 .
  • the through hole is composed of a first through hole h1 and a second through hole h2 which are provided in a conductive manner, wherein the first through hole h1 penetrates the second inorganic insulating layer 1071 and the third insulating layer 108, and the second through hole h1 penetrates through the second inorganic insulating layer 1071 and the third insulating layer 108.
  • the via hole h 2 penetrates through the organic insulating layer 1072 .
  • the pixel electrode 1051 is electrically connected to the second conductive pattern 1031 through a through hole (such as the first through hole h 1 in FIG. 8 , or the first through hole h 1 and the second through hole h 2 in FIG. 9 ).
  • the first pattern penetrating through the second inorganic insulating layer 1071 and the third insulating layer 108 can be formed at the same time through a patterning (mask) process.
  • a patterning process For the through hole h 1 , compared with the solution of patterning the second inorganic insulating layer 1071 and the third insulating layer 108 to form the through hole, one patterning process can be saved, which is beneficial to improve production efficiency and reduce production cost.
  • the hollow structure K is set in the center, and the orthographic projection of the hollow structure K on the first base substrate 101 covers the through hole (for example, the first through hole h 1 in FIG. 8 , or the first through hole h 1 in FIG. 9 and the orthographic projection of the second through hole h 2 ) on the first base substrate 101 .
  • the first conductive layer 102 may further include a first connection line 1022 extending along the first direction X, and the first connection line 1022 is integrally provided with the first conductive pattern 1021; the third conductive
  • the layer 104 may further include a second connection line 1042 extending along the second direction Y, and the second connection line 1042 is integrally provided with the third conductive pattern 1041, and the second direction Y crosses the first direction X.
  • the pixel electrode layer 105 can also include a wiring 1052 located in the non-display area BB.
  • the wiring 1052 surrounds the display area AA and is electrically connected to the first connection line 1022 and the second connection line 1042 respectively.
  • the wiring 1052 realizes the jumper connection between the first connecting wire 1022 and the second connecting wire 1042 , and further realizes the electrical connection between the first conductive pattern 1021 and the third conductive pattern 1041 .
  • a third via hole h3 penetrating through the first insulating layer 106 may be firstly formed in the non-display area BB. Then, while forming the first through hole h 1 penetrating through the second inorganic insulating layer 1071 and the third insulating layer 108 in the display area AA, a hole h1 penetrating the second inorganic insulating layer 1071 and the third insulating layer is formed in the non-display area BB.
  • an insulating layer penetrating through the first insulating layer 106 can be formed first in the non-display area BB.
  • the third through hole h 3 in the non-display area BB is then formed in the non-display area BB to penetrate the organic insulating layer 1072 and form the sixth through hole h 6 conducting with the third through hole h 3 ;
  • a hole that penetrates the second inorganic insulating layer 1071 and the third insulating layer 108 and conducts with the sixth through hole h6 is formed.
  • the fourth through hole h 4 , and the fifth through hole h 5 that only penetrates the third insulating layer 108 , so that the wire 1052 passes through the third through hole h 3 , the sixth through hole h 6 , and the fourth through hole h 5 .
  • the hole h4 is electrically connected to the first connection line 1022
  • the trace 1052 is electrically connected to the second connection line 1042 through the fifth through hole h5 .
  • the first electrode d and the second electrode s of the transistor TFT may be located in the second conductive layer 103 .
  • the first conductive layer 102 to prepare the gate g and the first conductive pattern 1021, it is avoided to separately increase the film layer of the first conductive pattern 1021, and the preparation of the gate g and the first conductive pattern 1021 can be completed through one patterning process, The patterning process of separately adding the first conductive pattern 1021 is avoided, therefore, it is beneficial to simplify the manufacturing process and realize the light and thin design.
  • the second conductive layer 103 to prepare the first pole d, the second pole s and the second conductive pattern 1031 , it is also beneficial to simplify the manufacturing process and realize a light and thin design.
  • the transistor TFT mentioned in the embodiments of the present disclosure may be a thin film transistor or a metal oxide semiconductor field effect transistor, which is not limited herein.
  • the transistor TFT may be a P-type transistor or an N-type transistor.
  • the transistor TFT may be a top-gate transistor or a bottom-gate transistor.
  • the first pole d and the second pole s of the transistor TFT are source and drain respectively. In practical applications, the functions of the first pole d and the second pole s can be interchanged depending on the type of transistor and the input signal. make specific distinctions.
  • a gate line GL extending along the first direction X may be provided in the first conductive layer 102
  • a data line DL extending along the second direction Y may be provided in the second conductive layer 103
  • the gate line GL and the data line The intersection of DL defines a pixel region P
  • the conductive patterns of each conductive layer (such as the first conductive pattern 1021 , the second conductive pattern 1031 , the third conductive pattern 1041 and the pixel electrode 1051 ) may be at least partially located in the pixel region P.
  • the conductive patterns (such as the first conductive pattern 1021, the second conductive pattern 1031, the third conductive pattern 1041 and the pixel electrode 1051) from overlapping with the gate line GL and/or the data line DL to form an electric field influence
  • the electrophoretic layer and the conductive patterns of each conductive layer should all be located in the pixel region P, as shown in FIG. 2 .
  • the orthographic projection on can at least cover the orthographic projection of the channel region of the transistor TFT (ie the region of the active layer a between the first pole d and the second pole s) on the first substrate 101 .
  • the material of the third conductive layer 104 may be a light-shielding metal (TPM), so that the orthographic projection of the third conductive pattern 1041 on the first base substrate 101 covers at least the channel region of the transistor TFT (that is, the active In the case of the orthographic projection of layer a (the area between the first pole d and the second pole s) on the first base substrate 101, it can effectively block light, and prevent light from irradiating the channel region of the transistor TFT to cause leakage. current, thereby ensuring the stability of the transistor TFT.
  • TPM light-shielding metal
  • the orthographic projection on the base substrate 101 can ensure that the area of the first conductive pattern 1021 is larger, so that the capacitance value of the first storage capacitor Cst1 formed by the first conductive pattern 1021 and the second conductive pattern 1031 is larger On the other hand, it avoids coupling capacitance caused by overlapping of the first conductive pattern 1021 and the transistor TFT, so that the signal on the first conductive pattern 1021 and the signal of the transistor TFT interfere with each other.
  • the orthographic projection of the second conductive pattern 1031 on the first base substrate 101 is the The orthographic projections on the first base substrate 101 overlap, so that a second storage capacitor Cst 2 can be formed between the first conductive pattern 1021 and the second conductive pattern 1031 .
  • the orthographic projection of the second conductive pattern 1031 on the first base substrate 101 can be compared with that of the first conductive pattern 1021 on the first base substrate 101.
  • the orthographic projection roughly coincides, that is, the two coincide exactly or are within the error range caused by factors such as production and measurement.
  • the second conductive pattern 1031 can be integrated with the first electrode d of the transistor, so that the signal of the transistor TFT is transmitted to the pixel electrode 1051 through the second conductive pattern 1031 .
  • the orthographic projection of the pixel electrode 1051 on the first substrate 101 can completely cover the Orthographic projection on the base substrate 101, so that the pixel electrode 1051 and the third conductive pattern 1041 have a sufficiently large facing area to form a third storage capacitor Cst 3 with a larger capacitance value; meanwhile, the pixel electrode 1051 with a larger area can also Better control of the electrophoretic layer improves display quality.
  • the above display substrate provided by the embodiments of the present disclosure may further include a buffer layer 109 and the like.
  • Other essential components of the display substrate should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.
  • the storage capacitor of each pixel area P is composed of a fourth storage capacitor Cst 4 and a fifth storage capacitor Cst 5 , wherein the fourth storage capacitor Cst 4 is connected with the gate g of the transistor TFT
  • the fourth conductive pattern C 1 arranged in the same layer, and the fifth conductive pattern C 2 arranged in the same layer as the first pole d and the second pole s of the transistor TFT, and the fourth conductive pattern C 1 and the fifth conductive pattern C
  • the fifth storage capacitor Cst 5 is formed by the fifth conductive pattern C 2 set on the same layer as the first pole d and the second pole s of the transistor TFT, and the third conductive layer 104 and the pixel
  • the electrode layer 105 is formed by the sixth conductive pattern C3 , and there is a second inorganic insulating layer 1071 and an organic insulating layer 1072 between the fifth conductive pattern C2 and the sixth conductive pattern C3 .
  • the present disclosure also provides related data of the storage capacitor of the display substrate shown in FIG. 9 and the storage capacitor of the related art shown in FIG. 12 .
  • Table 1 shows the parameters of each insulating layer, where GI represents the first insulating layer 106 , PVX1 represents the second inorganic insulating layer 1071 , PVX2 represents the third insulating layer 108 , and Resin represents the organic insulating layer 1072 .
  • Table 2 shows the comparative data of the storage capacitors.
  • the total capacitance value of a pixel region P in the present disclosure is 0.7186pF, which is within the range of 0.6pF-1pF required to maintain the voltage. And compared with the total capacitance value of 0.1746pF in the related art, it is increased by about 311.6%. Therefore, the structure shown in FIG. 9 of the present disclosure can effectively meet the requirement of holding voltage.
  • an embodiment of the present disclosure provides a manufacturing method of the above-mentioned display substrate. Since the principle of solving the problem of the manufacturing method is similar to the principle of solving the problem of the above-mentioned display substrate, the manufacturing method provided by the embodiment of the present disclosure For the implementation, reference may be made to the implementation of the above-mentioned display substrate provided by the embodiments of the present disclosure, and repeated descriptions will not be repeated.
  • a method for manufacturing the above-mentioned display substrate includes the following steps:
  • a base substrate is provided, the base substrate includes a display area, and the display area includes a plurality of pixel areas;
  • At least four conductive layers stacked are formed on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each pixel area, any two adjacent conductive layers are in the same
  • the conductive pattern in the pixel area forms a storage capacitor, and in a direction perpendicular to the base substrate, projections of at least four conductive layers overlap on the base substrate.
  • At least four conductive layers stacked are formed on the base substrate, any two adjacent conductive layers are insulated from each other, and each conductive layer Including the conductive patterns located in each pixel area, the conductive patterns of any two adjacent conductive layers in the same pixel area form a storage capacitor. Overlapping can be achieved in the following ways:
  • first conductive layer on the base substrate, the first conductive layer including a first conductive pattern located in the pixel area;
  • the second conductive layer includes a second conductive pattern located in the pixel area, the second conductive pattern and the first conductive pattern form a first storage capacitor;
  • the third conductive layer includes a third conductive pattern located in the pixel area, the third conductive pattern and the second conductive pattern form a second storage capacitor;
  • a pixel electrode layer is formed on the third inorganic insulating layer, the pixel electrode layer includes a pixel electrode located in the pixel region, the pixel electrode and the third conductive pattern constitute a third storage capacitor, and the pixel electrode is electrically connected to the second conductive pattern through the first through hole connect.
  • An organic insulating layer is formed on the second conductive layer, the organic insulating layer includes a second through hole located in the pixel area, and the second through hole is connected to the first through hole so that the pixel electrode passes through the first through hole, the second through hole, and the second through hole.
  • the hole is electrically connected with the second conductive pattern.
  • the present disclosure no matter the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer or the organic insulating layer are all for the purpose of insulation, therefore, in some embodiments, the present disclosure
  • the inorganic insulating layer can be replaced by an organic insulating layer, and the organic insulating layer can also be replaced by an inorganic insulating layer, which is not specifically limited here.
  • inorganic insulating materials can be used for both, or they can be replaced with organic insulating materials.
  • the first conductive layer can also be formed to extend along the first direction and a first connecting line integrally provided with the first conductive pattern
  • Forming the first inorganic insulating layer on the first conductive layer may specifically be achieved in the following manner: forming a third through hole penetrating through the first inorganic insulating layer in the non-display area;
  • a second connection line extending along the second direction and integrally arranged with the second conductive pattern may also be formed on the second conductive layer, and the second direction is in line with the second conductive pattern.
  • a fourth through hole penetrating through the third inorganic insulating layer and the second inorganic insulating layer may also be formed in the non-display area, and In the non-display area, only the fifth through hole penetrates the third inorganic insulating layer, wherein the fourth through hole is connected to the third through hole;
  • the An organic insulating layer is formed on the second conductive layer.
  • the organic insulating layer includes a second through hole located in the pixel area and a sixth through hole located in the non-display area.
  • the second through hole is connected to the first through hole.
  • the through hole conducts the third through hole and the fourth through hole, so that the wiring is electrically connected to the first connecting line through the third through hole, the sixth through hole, and the fourth through hole, and the wiring is connected to the first connecting line through the fifth through hole.
  • the second connecting wire is electrically connected.
  • an embodiment of the present disclosure provides a display device. Since the problem-solving principle of the display device is similar to that of the above-mentioned display substrate, the implementation of the display device provided by the embodiment of the present disclosure can be found in this The implementation of the above-mentioned display substrate provided by the disclosed embodiments will not be repeated here.
  • a display device provided by an embodiment of the present disclosure, as shown in FIG. 12 and FIG. 13 , includes a display substrate 001 and a counter substrate 002 facing each other, and a display substrate between the display substrate 001 and the counter substrate 002 The light-adjusting layer 003, wherein the display substrate 001 is the above-mentioned display substrate provided by the embodiment of the present disclosure.
  • the opposite substrate 002 may include a second base substrate 201, and a common electrode 202 located on the side of the second base substrate 201 facing the dimming layer 003 , optionally, the common electrode 202 can be electrically connected to the first conductive pattern 1021 and the third conductive pattern 1041 through conductive silver glue, so that the common electrode 202, the first conductive pattern 1021 and the third conductive pattern 1041 are loaded with the same common Voltage electrical signal (Vcom).
  • Vcom Voltage electrical signal
  • the light-adjusting layer 003 may be an electrophoretic layer (as shown in FIG. 13 and FIG. 14 ) or a liquid crystal layer.
  • the light-adjusting layer 003 is an electrophoretic layer as an example for illustration.
  • the electrophoretic layer 003 may include: a plurality of electrophoretic particles 301, each electrophoretic particle 301 may include: a particle body, and electrophoretic fluid and charged particles located in the particle body, the charged particles Particles can include: black particles, white particles and colored particles, etc.
  • the driving of electrophoretic particles includes: reverse phase, up and down shaking phase and writing phase.
  • the purpose of the reverse phase is to maintain charge conservation.
  • the up and down shaking phase is to eliminate the influence of the previous frame on the next frame.
  • the writing phase is based on the picture to be written, such as a black picture.
  • the writing voltage is 15V, then the common voltage Generally around 0V, the scan signal on the gate line DL gives a turn-on voltage of 20V, and the data signal on the data line DL gives 15V, which is transmitted to the pixel electrode 1051 through the transistor TFT, so that the pixel electrode 1051 and the common electrode 202 form an electric field to drive black particles.
  • it generally requires multi-frame driving to make the electrophoretic particles 301 display uniform and stable black.
  • the storage capacitor plays a role in maintaining the pixel voltage.
  • the conference affects the charging of pixels, so the reader (Reader) products are generally between 0.1pF and 1.2pF.
  • the electrophoretic particles 301 can maintain the original position through the buoyancy and viscous force in the electrophoretic fluid, thereby saving power and using ambient light to display eye protection.
  • the above-mentioned display device provided in the embodiments of the present disclosure may also include but not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a user input unit, an interface unit, a memory, a processor, and power supply and other components.
  • a radio frequency unit a radio frequency unit
  • a network module a network module
  • an audio output & input unit a sensor
  • a user input unit e.g., a user input unit
  • an interface unit e.g., a memory
  • a processor e.g., a processor, and power supply and other components.
  • the above-mentioned structure does not constitute a limitation on the above-mentioned display device provided by the embodiment of the present disclosure.
  • the above-mentioned display device provided by the embodiment of the present disclosure may include more or less of the above components, or combinations of certain components, or different arrangements of components.

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Abstract

一种显示基板，包括衬底基板（101），衬底基板（101）包括显示区（AA），显示区（AA）包括多个像素区（P）；层叠设置的至少四个导电层（102、103、104和105），位于衬底基板（101）之上，任意相邻两个导电层之间相互绝缘设置，每个导电层（102、103、104和105）包括位于各像素区（P）的导电图案，任意相邻两个导电层在同一像素区（P）的导电图案构成一个存储电容（如Cst 1、Cst 2、Cst 3），在垂直于衬底基板（101）的方向上，至少四层导电层（102、103、104和105）在衬底基板（101）的投影交叠。还提供显示基板的制作方法及显示装置。

Description

显示基板、其制作方法及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、其制作方法及显示装置。
背景技术
近年来，以电泳显示为代表的反射式显示器作为阅读器，以其具有护眼、低功耗、日光下可读、灵活性好等优势，在教育市场得到了极大的应用。
发明内容
本公开提供的显示基板、其制作方法及显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，所述衬底基板包括显示区，所述显示区包括多个像素区；
层叠设置的至少四个导电层，位于所述衬底基板之上，任意相邻两个所述导电层之间相互绝缘设置，每个所述导电层包括位于各所述像素区的导电图案，任意相邻两个所述导电层在同一所述像素区的导电图案构成一个存储电容，在垂直于所述衬底基板的方向上，所述至少四层导电层在所述衬底基板的投影交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述至少四个导电层包括第一导电层、第二导电层、第三导电层和像素电极层，其中，
所述第一导电层包括第一导电图案，所述第二导电层包括第二导电图案，所述第三导电层包括第三导电图案，所述像素电极层包括像素电极；
所述第一导电图案和所述第二导电图案构成第一存储电容，所述第二导电图案和所述第三导电图案构成第二存储电容，所述第三导电图案和所述像素电极构成第三存储电容，且所述第一导电图案与所述第三导电图案电连接，所述第二导电图案与所述像素电极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括第一绝缘层、第二绝缘层和第三绝缘层，其中，所述第一绝缘层位于所述第一导电层与所述第二导电层之间，所述第二绝缘层位于所述第二导电层与所述第三导电层之间，所述第三绝缘层位于所述第三导电层与所述像素电极层之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二绝缘层和所述第三绝缘层包括贯穿设置的通孔，所述像素电极经由所述通孔与所述第二导电图案电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第三导电图案包括镂空结构，所述镂空结构在所述衬底基板上的正投影覆盖所述通孔在所述衬底基板上的正投影。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述衬底基板还包括包围所述显示区的非显示区；
所述第一导电层还包括第一连接线，所述第一连接线沿第一方向延伸，且所述第一连接线与所述第一导电图案一体设置；
所述第三导电层还包括第二连接线，所述第二连接线沿第二方向延伸，且所述第二连接线与所述第三导电图案一体设置，所述第二方向与所述第一方向交叉设置；
所述像素电极层还包括位于所述非显示区的走线，所述走线包围所述显示区且与所述第一连接线、所述第二连接线分别电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述像素区的晶体管，所述晶体管的栅极位于所述第一导电层，所述晶体管的第一极、第二极位于所述第二导电层。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第三导电层为金属，所述第三导电图案在所述衬底基板上的正投影至少覆盖所述晶体管的沟道区在所述衬底基板上的正投影。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一导电图案在所述衬底基板上的正投影半包围所述晶体管在所述衬底基板上的正 投影。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二导电图案在所述衬底基板上的正投影与所述第一导电图案在所述衬底基板上的正投影交叠，且所述第二导电图案与所述晶体管的第一极一体设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述像素电极在所述衬底基板上的正投影完全覆盖所述晶体管在所述衬底基板上的正投影。
另一方面，本公开实施例提供了一种显示装置，包括相对而置的显示基板和对向基板，以及位于所述显示基板和对向基板之间的调光层，其中，所述显示基板为本公开实施例提供的上述显示基板。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述对向基板包括公共电极，所述公共电极、所述第一导电图案和所述第三导电图案加载相同的电信号。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述调光层为电泳层或液晶层。
另一方面，本公开实施例提供了一种上述显示基板的制作方法，包括：
提供一个衬底基板，所述衬底基板包括显示区，所述显示区包括多个像素区；
在所述衬底基板上形成层叠设置的至少四个导电层，任意相邻两个所述导电层之间相互绝缘设置，每个所述导电层包括位于各所述像素区的导电图案，任意相邻两个所述导电层在同一所述像素区的导电图案构成一个存储电容，在垂直于所述衬底基板的方向上，所述至少四层导电层在所述衬底基板的投影交叠。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述衬底基板上形成层叠设置的至少四个导电层，任意相邻两个所述导电层之间相互绝缘设置，每个所述导电层包括位于各所述像素区的导电图案，任意相邻两个所述导电层在同一所述像素区的导电图案构成一个存储电容，在垂直于所 述衬底基板的方向上，所述至少四层导电层在所述衬底基板的投影交叠，具体包括：
在所述衬底基板上形成第一导电层，所述第一导电层包括位于所述像素区的第一导电图案；
在所述第一导电层上形成第一无机绝缘层；
在所述第一无机绝缘层上形成第二导电层，所述第二导电层包括位于所述像素区的第二导电图案，所述第二导电图案和所述第一导电图案构成第一存储电容；
在所述第二导电层上形成第二无机绝缘层；
在所述第二无机绝缘层上形成第三导电层，所述第三导电层包括位于所述像素区的第三导电图案，所述第三导电图案和所述第二导电图案构成第二存储电容；
在所述第三导电层上形成第三无机绝缘层，并采用一次构图工艺，在所述像素区形成贯穿所述第三无机绝缘层和所述第二无机绝缘层的第一通孔；
在所述第三无机绝缘层上形成像素电极层，所述像素电极层包括位于所述像素区的像素电极，所述像素电极和所述第三导电图案构成第三存储电容，且所述像素电极通过所述第一通孔与所述第二导电图案电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述第一无机绝缘层上形成第二导电层之后，且在所述第二导电层上形成第二无机绝缘层之前，还包括：
在所述第二导电层上形成包括有机绝缘层，所述有机绝缘层包括位于所述像素区的第二通孔，所述第二通孔与所述第一通孔导通设置。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述衬底基板上形成位于所述像素区的第一导电图案的同时，还包括：在所述第一导电层形成沿第一方向延伸且与所述第一导电图案一体设置的第一连接线；
在所述第一导电层上形成第一无机绝缘层，具体包括：在非显示区形成贯穿第一无机绝缘层的第三通孔；
在所述第一无机绝缘层上形成位于所述像素区的第二导电图案的同时，还包括：在所述第二导电层形成沿第二方向延伸且与所述第二导电图案一体设置的第二连接线，所述第二方向与所述第一方向交叉设置；
在所述像素区形成贯穿所述第三无机绝缘层和所述第二无机绝缘层的第一通孔的同时，还包括：在所述非显示区形成贯穿所述第三无机绝缘层和所述第二无机绝缘层的第四通孔，以及在所述非显示区仅贯穿所述第三无机绝缘层的第五通孔，其中，所述第四通孔与所述第三通孔导通；
在所述第三无机绝缘层上形成位于所述像素区的像素电极的同时，还包括：在所述非显示区形成位于所述像素电极层的走线，所述走线通过所述第三通孔和所述第四通孔与所述第一连接线电连接，所述走线通过所述第五通孔与所述第二连接线电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述第一无机绝缘层上形成第二导电层之后，且在所述第二导电层上形成第二无机绝缘层之前，还包括：
在所述第二导电层上形成包括有机绝缘层，所述有机绝缘层包括位于所述像素区的第二通孔，以及位于所述非显示区的第六通孔，所述第二通孔与所述第一通孔导通设置，所述第六通孔导通所述第三通孔与所述第四通孔。
附图说明
图1为本公开实施例提供的显示基板的结构示意图；
图2为沿图1中四个像素区的示意图；
图3为图2中第一导电层的结构示意图；
图4为图2中第二导电层的结构示意图；
图5为图2中第三导电层的结构示意图；
图6为图2中像素电极层的结构示意图；
图7为图2中有源层及绝缘层的结构示意图；
图8为沿图2中I-I线的一种截面示意图；
图9为沿图2中I-I线的又一种截面示意图；
图10为本公开实施例提供的显示基板在非显示区的一种截面示意图；
图11为本公开实施例提供的显示基板在非显示区的又一种截面示意图；
图12为相关技术中的显示基板的截面示意图；
图13为本公开实施例提供的显示装置的一种结构示意图；
图14为本公开实施例提供的显示装置的又一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，市场对高分辨率(PPI)、全彩电子纸(EPD)的需求越来越强烈。然而，随着分辨率的提高，像素的尺寸越来越小，那么存储电容的交叠面积越来越小，因此存储电容越来越小，相关技术中采用两个存储电容，依然无法满足EPD产品对保持电压的需求。
为了解决相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图1至图8所示，包括：
第一衬底基板101，该第一衬底基板101包括显示区AA，在显示区AA内设置有多个像素区P；
层叠设置的至少四个导电层(例如第一导电层102、第二导电层103、第三导电层104和像素电极层105)，位于第一衬底基板101之上，任意相邻两个导电层之间相互绝缘设置，每个导电层包括位于各像素区P的导电图案(例如第一导电图案1021、第二导电图案1031、第三导电图案1041和像素电极1051)，任意相邻两个导电层在同一像素区P的导电图案构成一个存储电容(例如第一存储电容Cst 1、第二存储电容Cst 2、第三存储电容Cst 3)，在垂直于衬底基板的方向Z上，上述至少四层导电层在第一衬底基板101的投影交叠。
在本公开实施例提供的上述显示基板中，通过在至少四个导电层中设置导电图案，并设置任意相邻两个导电层的导电图案相互交叠构成一个存储电容，使得每个像素区P内均具有至少三个存储电容，从而可有效增大每个像素区P的电容值，利于维持电压稳定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2至图8所示，上述至少四个导电层可以包括第一导电层102、第二导电层103、第三导电层104和像素电极层105，其中，第一导电层102包括第一导电图案1021，第二导电层103包括第二导电1031，第三导电层104包括第三导电图案1041，像素电极层105包括像素电极1051，图2中一个粗实线框所围成的区域表示一个像素电极1051；第一导电图案1021和第二导电图案1031构成第一存储电容Cst 1，第二导电图案1031和第三导电图案1041构成第二存储电容Cst 2，第三导电图案1041和像素电极1051构成第三存储电容Cst 3，且第一导电图案1021与第三导电图案1041电连接，第二导电图案1031与像素电极1051电连接，使得第一存储电容Cst 1、第二存储电容Cst 2、第三存储电容Cst 3三者并联，每个像素区P内的电容值为第一存储电容Cst 1的电容值、第二存储电容Cst 2的电容值、以及第三存储电容Cst 3的电容值加和，有效增大了每个像素区P的电容值。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图8和图9 所示，还可以包括第一绝缘层106、第二绝缘层107和第三绝缘层108，其中，第一绝缘层106位于第一导电层102与第二导电层103之间，第二绝缘层107位于第二导电层103与第三导电层104之间，第三绝缘层108位于第三导电层104与像素电极层105之间，这样可以保证第一导电层102与第二导电层103通过第一绝缘层106实现绝缘，第二导电层103与第三导电层104通过第二绝缘层107实现绝缘，第三导电层104与像素电极层105通过第三绝缘层108实现绝缘。
可选地，第一绝缘层106为第一无机绝缘层，第二绝缘层107为第二无机绝缘层1071，第三绝缘层108为第三无机绝缘层；或者，第一绝缘层106为第一无机绝缘层，第三绝缘层108为第三无机绝缘层，第二绝缘层107包括层叠设置的第二无机绝缘层1071和有机绝缘层1072，且第二无机绝缘层1071位于有机绝缘层1072与第三绝缘层108之间。电容值C的计算公式为C＝ε*s/d，其中，ε表示绝缘层的介电常数，S表示存储电容中两个电极的正对面积，d为绝缘层的厚度。由电容的计算公式可知，绝缘层的厚度越小，存储电容的电容值越大，因此，第二存储电容Cst 2的电容值，在第二绝缘层107仅包括第二无机绝缘层1071的情况下，比第二绝缘层107包括第二无机绝缘层1071和有机绝缘层1072的情况下大。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图8和图9所示，第二绝缘层107和第三绝缘层108可以包括贯穿设置的通孔。例如在图8中通孔为贯穿第二无机绝缘层1071和第三绝缘层108的第一通孔h 1。在图9中通孔由导通设置的第一通孔h 1和第二通孔h 2组成，其中，第一通孔h 1贯穿第二无机绝缘层1071和第三绝缘层108，第二通孔h 2贯穿有机绝缘层1072。像素电极1051经由通孔(例如图8中的第一通孔h 1，或者图9中的第一通孔h 1和第二通孔h 2)与第二导电图案1031电连接。由于第二无机绝缘层1071和第三绝缘层108的材料均为无机绝缘材料，因此，可通过一次构图(mask)工艺，同时形成贯穿第二无机绝缘层1071和第三绝缘层108的第一通孔h 1，相较于分别对第二无机绝缘层1071和第三绝缘层108进行构图制作 通孔的方案，可以节省一道构图工艺，利于提高生产效率，降低制作成本。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图8和图9所示，为了便于实现像素电极1051与第二导电图案1031的电连接，可以在第三导电图案1041中设置镂空结构K，且使得该镂空结构K在第一衬底基板101上的正投影覆盖通孔(例如图8中的第一通孔h 1，或者图9中的第一通孔h 1和第二通孔h 2)在第一衬底基板101上的正投影。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1至图3、图5、图10和图11所示，第一衬底基板101还可以包括包围显示区AA的非显示区BB；第一导电层102还可以包括第一连接线1022，该第一连接线1022沿第一方向X延伸，且第一连接线1022与第一导电图案1021一体设置；第三导电层104还可以包括第二连接线1042，该第二连接线1042沿第二方向Y延伸，且第二连接线1042与第三导电图案1041一体设置，第二方向Y与第一方向X交叉设置；像素电极层105还可以包括位于非显示区BB的走线1052，走线1052包围显示区AA且与第一连接线1022、第二连接线1042分别电连接，如此则通过在像素电极层105的走线1052实现第一连接线1022与第二连接线1042的跳线连接，进而实现了第一导电图案1021与第三导电图案1041的电连接。
可选地，如图10所示，在第二绝缘层107仅包括第二无机绝缘层1071的情况下，可先在非显示区BB内形成贯穿第一绝缘层106的第三通孔h 3；然后在形成显示区AA内贯穿第二无机绝缘层1071和第三绝缘层108的第一通孔h 1的同时，在非显示区BB内形成贯穿第二无机绝缘层1071和第三绝缘层108并与第三通孔h 3导通的第四通孔h 4、以及仅贯穿第三绝缘层108的第五通孔h 5，从而使得走线1052通过导通的第三通孔h 3和第四通孔h 4与第一连接线1022电连接，走线1052通过第五通孔h 5与第二连接线1042电连接。
可选地，如图11所示，在第二绝缘层107包括层叠设置的有机绝缘层1072和第二无机绝缘层1071的情况下，可先在非显示区BB内形成贯穿第一绝缘层106的第三通孔h 3；然后在非显示区BB内形成贯穿有机绝缘层1072且与 第三通孔h 3导通的第六通孔h 6；随后在形成显示区AA内贯穿第二无机绝缘层1071和第三绝缘层108的第一通孔h 1的同时，在非显示区BB内形成贯穿第二无机绝缘层1071和第三绝缘层108并与第六通孔h 6导通的第四通孔h 4、以及仅贯穿第三绝缘层108的第五通孔h 5，从而使得走线1052通过导通的第三通孔h 3、第六通孔h 6、以及第四通孔h 4与第一连接线1022电连接，走线1052通过第五通孔h 5与第二连接线1042电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4、图8和图9所示，还可以包括位于像素区P的晶体管TFT，晶体管TFT的栅极g可以位于第一导电层102，晶体管TFT的第一极d、第二极s可以位于第二导电层103。通过采用第一导电层102制备栅极g和第一导电图案1021，避免了单独增加第一导电图案1021的膜层，且可通过一次构图工艺完成栅极g和第一导电图案1021的制备，避免了单独增加第一导电图案1021的构图工艺，因此，利于简化制作工艺，实现轻薄化设计。基于相似的理由，通过采用第二导电层103制备第一极d、第二极s和第二导电图案1031，也利于简化制作工艺，实现轻薄化设计。
此外，本公开实施例中提到的晶体管TFT可以是薄膜晶体管，也可以是金属氧化物半导体场效应管，在此不做限定。并且，晶体管TFT可以为P型晶体管或N型晶体管。晶体管TFT可以为顶栅型晶体管，也可以为底栅型晶体管。晶体管TFT的第一极d和第二极s分别为源极和漏极，在实际应用中，根据晶体管类型以及输入信号的不同，第一极d和第二极s的功能可以互换，不做具体区分。
可选地，在第一导电层102中可以设置沿第一方向X延伸的栅线GL，并在第二导电层103中设置沿第二方向Y延伸的数据线DL，栅线GL和数据线DL交叉限定出像素区P，各导电层的导电图案(例如第一导电图案1021、第二导电图案1031、第三导电图案1041和像素电极1051)可以至少部分位于像素区P内。在一些实施例中，为避免导电图案(例如第一导电图案1021、第二导电图案1031、第三导电图案1041和像素电极1051)与栅线GL和/或 数据线DL交叠而形成电场影响电泳层，各导电层的导电图案(例如第一导电图案1021、第二导电图案1031、第三导电图案1041和像素电极1051)宜全部位于像素区P内，如图2所示。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2至图9所示，第三导电层104的材料可以为金属，第三导电图案1041在第一衬底基板101上的正投影可以至少覆盖晶体管TFT的沟道区(即有源层a在第一极d和第二极s之间的区域)在第一衬底基板101上的正投影。可选地，第三导电层104的材料可以为遮光金属(TPM)，从而使得在第三导电图案1041在第一衬底基板101上的正投影至少覆盖晶体管TFT的沟道区(即有源层a在第一极d和第二极s之间的区域)在第一衬底基板101上的正投影的情况下，可以有效阻挡光线，避免光线照射至晶体管TFT的沟道区而产生漏电流，从而保证了晶体管TFT的稳定性。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图2至图9所示，第一导电图案1021在第一衬底基板101上的正投影半包围晶体管TFT在第一衬底基板101上的正投影，这样一方面可以保证第一导电图案1021的面积较大，从而使得第一导电图案1021与第二导电图案1031构成的第一存储电容Cst 1的电容值较大；另一方面，避免了第一导电图案1021与晶体管TFT相互交叠而造成耦合电容，而使得第一导电图案1021上的信号与晶体管TFT的信号相互干扰。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2至图9所示，第二导电图案1031在第一衬底基板101上的正投影与第一导电图案1021在第一衬底基板101上的正投影交叠，以使得第一导电图案1021与第二导电图案1031之间可形成第二存储电容Cst 2。可选地，为使得第二存储电容Cst 2的电容值较大，第二导电图案1031在第一衬底基板101上的正投影可以与第一导电图案1021在第一衬底基板101上的正投影大致重合，即二者恰好重合或在因制作、测量等因素造成的误差范围内。在一些实施例中，第二导电图案1031可以与晶体管的第一极d一体设置，以便于晶体管TFT的信号经 第二导电图案1031传输至像素电极1051。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2至图9所示，像素电极1051在第一衬底基板101上的正投影可以完全覆盖晶体管TFT在第一衬底基板101上的正投影，以使得像素电极1051与第三导电图案1041具有足够大的正对面积，形成电容值较大的第三存储电容Cst 3；同时较大面积的像素电极1051还可以更好地控制电泳层，提高显示质量。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图8和图9所示，还可以包括缓冲层109等。对于显示基板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
如图12所示，在相关技术中每个像素区P的存储电容由第四存储电容Cst 4和第五存储电容Cst 5构成，其中，第四存储电容Cst 4由与晶体管TFT的栅极g同层设置的第四导电图案C 1、以及与晶体管TFT的第一极d、第二极s同层设置的第五导电图案C 2构成，且第四导电图案C 1和第五导电图案C 2之间具有第一绝缘层106；第五存储电容Cst 5由与晶体管TFT的第一极d、第二极s同层设置的第五导电图案C 2、以及位于第三导电层104及像素电极层105的第六导电图案C 3构成，且第五导电图案C 2与第六导电图案C 3之间具有第二无机绝缘层1071和有机绝缘层1072。
另外，以像素区P的尺寸(pitch)为60μm为例，本公开还提供了图9所示显示基板的存储电容与图12所示相关技术中存储电容的相关数据。具体地，表1示出了各绝缘层的参数，其中，GI表示第一绝缘层106，PVX1表示第二无机绝缘层1071，PVX2表示第三绝缘层108，Resin表示有机绝缘层1072。表2示出了存储电容的对比数据，由表2可以看出，本公开中一个像素区P的总电容值为0.7186pF，在保持电压所需的0.6pF～1pF的范围内。且相较于相关技术中的总电容值0.1746pF，增大了约311.6％，因此，本公开图9所示结构能够有效满足保持电压的需求。
表1
Figure PCTCN2022077762-appb-000001
表2
Figure PCTCN2022077762-appb-000002
基于同一发明构思，本公开实施例提供了一种上述显示基板的制作方法，由于该制作方法解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
具体地，本公开实施例提供的一种上述显示基板的制作方法，包括以下步骤：
提供一个衬底基板，衬底基板包括显示区，显示区包括多个像素区；
在衬底基板上形成层叠设置的至少四个导电层，任意相邻两个导电层之间相互绝缘设置，每个导电层包括位于各像素区的导电图案，任意相邻两个导电层在同一像素区的导电图案构成一个存储电容，在垂直于衬底基板的方向上，至少四层导电层在衬底基板的投影交叠。
在一些实施例中，在本公开实施例提供的上述制作方法中，在衬底基板 上形成层叠设置的至少四个导电层，任意相邻两个导电层之间相互绝缘设置，每个导电层包括位于各像素区的导电图案，任意相邻两个导电层在同一像素区的导电图案构成一个存储电容，在垂直于衬底基板的方向上，至少四层导电层在衬底基板的投影交叠，具体可以通过以下方式进行实现：
在衬底基板上形成第一导电层，第一导电层包括位于像素区的第一导电图案；
在第一导电层上形成第一无机绝缘层；
在第一无机绝缘层上形成第二导电层，第二导电层包括位于像素区的第二导电图案，第二导电图案和第一导电图案构成第一存储电容；
在第二导电层上形成第二无机绝缘层；
在第二无机绝缘层上形成第三导电层，第三导电层包括位于像素区的第三导电图案，第三导电图案和第二导电图案构成第二存储电容；
在第三导电层上形成第三无机绝缘层，并采用一次构图工艺，在像素区形成贯穿第三无机绝缘层和第二无机绝缘层的第一通孔；
在第三无机绝缘层上形成像素电极层，像素电极层包括位于像素区的像素电极，像素电极和第三导电图案构成第三存储电容，且像素电极通过第一通孔与第二导电图案电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在第一无机绝缘层上形成第二导电层之后，且在第二导电层上形成第二无机绝缘层之前，还可以执行以下步骤：
在第二导电层上形成包括有机绝缘层，有机绝缘层包括位于像素区的第二通孔，第二通孔与第一通孔导通设置，使得像素电极通过第一通孔、第二通孔与第二导电图案电连接。
需要说明的是，本公开中无论第一无机绝缘层、第二无机绝缘层、第三无机绝缘层还是有机绝缘层都是为了起到绝缘作用，因此，在一些实施例中，本公开中的无机绝缘层可以采用有机绝缘层替代，有机绝缘层也可以采用无机绝缘层替代，在此不做具体限定。并且，为了减少掩膜次数，需要保证第 三无机绝缘层和第二无机绝缘层的材质相同，例如可以均采用无机绝缘材料，或者可以均替换为有机绝缘材料。
在一些实施例中，在本公开实施例提供的上述制作方法中，在衬底基板上形成位于像素区的第一导电图案的同时，还可以在第一导电层形成沿第一方向延伸且与第一导电图案一体设置的第一连接线；
在第一导电层上形成第一无机绝缘层，具体可以通过以下方式实现：在非显示区形成贯穿第一无机绝缘层的第三通孔；
在第一无机绝缘层上形成位于像素区的第二导电图案的同时，还可以在第二导电层形成沿第二方向延伸且与第二导电图案一体设置的第二连接线，第二方向与第一方向交叉设置；
在像素区形成贯穿第三无机绝缘层和第二无机绝缘层的第一通孔的同时，还可以在非显示区形成贯穿第三无机绝缘层和第二无机绝缘层的第四通孔，以及在非显示区仅贯穿第三无机绝缘层的第五通孔，其中，第四通孔与第三通孔导通；
在第三无机绝缘层上形成位于像素区的像素电极的同时，还可以在非显示区形成位于像素电极层的走线，走线通过第三通孔和第四通孔与第一连接线电连接，走线通过第五通孔与第二连接线电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在第一无机绝缘层上形成第二导电层之后，且在第二导电层上形成第二无机绝缘层之前，还可以在第二导电层上形成包括有机绝缘层，有机绝缘层包括位于像素区的第二通孔，以及位于非显示区的第六通孔，第二通孔与第一通孔导通设置，第六通孔导通第三通孔与第四通孔，使得走线通过第三通孔、第六通孔、以及第四通孔与第一连接线电连接，且走线通过第五通孔与第二连接线电连接。
基于同一发明构思，本公开实施例提供了一种显示装置，由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
具体地，本公开实施例提供的一种显示装置，如图12和图13所示，包括相对而置的显示基板001和对向基板002，以及位于显示基板001和对向基板002之间的调光层003，其中，显示基板001为本公开实施例提供的上述显示基板。
在一些实施例中，在本公开实施例提供的上述显示装置中，对向基板002可以包括第二衬底基板201，以及位于第二衬底基板201面向调光层003一侧的公共电极202，可选地，公共电极202可通过导电银胶实现与第一导电图案1021、第三导电图案1041的电连接，使得公共电极202、第一导电图案1021和第三导电图案1041加载相同的公共电压电信号(Vcom)。
在一些实施例中，在本公开实施例提供的上述显示装置中，调光层003可以为电泳层(如图13和图14所示)或为液晶层。本公开中以调光层003为电泳层为例进行说明。具体地，如图13和图14所示，电泳层003可以包括：多个电泳粒子301，每个电泳粒子301可以包括：粒子本体，以及位于该粒子本体内的电泳液和带电粒子，该带电粒子可以包括：黑粒子、白粒子和彩色粒子等。电泳粒子的驱动包括：反向阶段、上下摇动阶段和写入阶段。反向阶段的目的是保持电荷守恒，上下摇动阶段是消除上一帧画面对下一帧画面的影响，写入阶段是根据要写的画面，比如黑色画面，写入电压是15V，那么公共电压一般在0V左右，栅线DL上的扫描信号给开启电压20V，数据线DL上的数据信号给15V，通过晶体管TFT传输到像素电极1051上，使像素电极1051与公共电极202形成电场驱动黑色粒子移动到上方，一般需要多帧驱动使电泳粒子301显示均匀稳定的黑色，在多帧驱动之间，存储电容起到使像素电压保持的作用，一般存储电容越大保持越好，但存储电容过大会影响像素充电，所以阅读器(Reader)产品一般在0.1pF～1.2pF之间。当几帧写完后断电，电泳粒子301通过电泳液中的浮力、粘滞力能保持原来的位置不变，从而节约电源，并且利用环境光显示护眼。
在一些实施例中，在本公开实施例提供的上述显示装置还可以包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、用户输入单元、 接口单元、存储器、处理器、以及电源等部件。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种显示基板，其中，包括：
    衬底基板，所述衬底基板包括显示区，所述显示区包括多个像素区；
    层叠设置的至少四个导电层，位于所述衬底基板之上，任意相邻两个所述导电层之间相互绝缘设置，每个所述导电层包括位于各所述像素区的导电图案，任意相邻两个所述导电层在同一所述像素区的导电图案构成一个存储电容，在垂直于所述衬底基板的方向上，所述至少四层导电层在所述衬底基板的投影交叠。
  2. 如权利要求1所述的显示基板，其中，所述至少四个导电层包括第一导电层、第二导电层、第三导电层和像素电极层，其中，
    所述第一导电层包括第一导电图案，所述第二导电层包括第二导电图案，所述第三导电层包括第三导电图案，所述像素电极层包括像素电极；
    所述第一导电图案和所述第二导电图案构成第一存储电容，所述第二导电图案和所述第三导电图案构成第二存储电容，所述第三导电图案和所述像素电极构成第三存储电容，且所述第一导电图案与所述第三导电图案电连接，所述第二导电图案与所述像素电极电连接。
  3. 如权利要求2所述的显示基板，其中，还包括第一绝缘层、第二绝缘层和第三绝缘层，其中，所述第一绝缘层位于所述第一导电层与所述第二导电层之间，所述第二绝缘层位于所述第二导电层与所述第三导电层之间，所述第三绝缘层位于所述第三导电层与所述像素电极层之间。
  4. 如权利要求3所述的显示基板，其中，所述第二绝缘层和所述第三绝缘层包括贯穿设置的通孔，所述像素电极经由所述通孔与所述第二导电图案电连接。
  5. 如权利要求4所述的显示基板，其中，所述第三导电图案包括镂空结构，所述镂空结构在所述衬底基板上的正投影覆盖所述通孔在所述衬底基板上的正投影。
  6. 如权利要求2～5任一项所述的显示基板，其中，所述衬底基板还包括包围所述显示区的非显示区；
    所述第一导电层还包括第一连接线，所述第一连接线沿第一方向延伸，且所述第一连接线与所述第一导电图案一体设置；
    所述第三导电层还包括第二连接线，所述第二连接线沿第二方向延伸，且所述第二连接线与所述第三导电图案一体设置，所述第二方向与所述第一方向交叉设置；
    所述像素电极层还包括位于所述非显示区的走线，所述走线包围所述显示区且与所述第一连接线、所述第二连接线分别电连接。
  7. 如权利要求2～6任一项所述的显示基板，其中，还包括位于所述像素区的晶体管，所述晶体管的栅极位于所述第一导电层，所述晶体管的第一极、第二极位于所述第二导电层。
  8. 如权利要求7所述的显示基板，其中，所述第三导电层为金属，所述第三导电图案在所述衬底基板上的正投影至少覆盖所述晶体管的沟道区在所述衬底基板上的正投影。
  9. 如权利要求7或8所述的显示基板，其中，所述第一导电图案在所述衬底基板上的正投影半包围所述晶体管在所述衬底基板上的正投影。
  10. 如权利要求7～9任一项所述的显示基板，其中，所述第二导电图案在所述衬底基板上的正投影与所述第一导电图案在所述衬底基板上的正投影交叠，且所述第二导电图案与所述晶体管的第一极一体设置。
  11. 如权利要求7～10任一项所述的显示基板，其中，所述像素电极在所述衬底基板上的正投影完全覆盖所述晶体管在所述衬底基板上的正投影。
  12. 一种显示装置，其中，包括相对而置的显示基板和对向基板，以及位于所述显示基板和对向基板之间的调光层，其中，所述显示基板为如权利要求1～11任一项所述的显示基板。
  13. 如权利要求12所述的显示装置，其中，所述对向基板包括公共电极，所述公共电极、所述第一导电图案和所述第三导电图案加载相同的电信号。
  14. 如权利要求12或13所述的显示装置，其中，所述调光层为电泳层或液晶层。
  15. 一种如权利要求1～11任一项所述显示基板的制作方法，其中，包括：
    提供一个衬底基板，所述衬底基板包括显示区，所述显示区包括多个像素区；
    在所述衬底基板上形成层叠设置的至少四个导电层，任意相邻两个所述导电层之间相互绝缘设置，每个所述导电层包括位于各所述像素区的导电图案，任意相邻两个所述导电层在同一所述像素区的导电图案构成一个存储电容，在垂直于所述衬底基板的方向上，所述至少四层导电层在所述衬底基板的投影交叠。
  16. 如权利要求15所述的制作方法，其中，在所述衬底基板上形成层叠设置的至少四个导电层，任意相邻两个所述导电层之间相互绝缘设置，每个所述导电层包括位于各所述像素区的导电图案，任意相邻两个所述导电层在同一所述像素区的导电图案构成一个存储电容，在垂直于所述衬底基板的方向上，所述至少四层导电层在所述衬底基板的投影交叠，具体包括：
    在所述衬底基板上形成第一导电层，所述第一导电层包括位于所述像素区的第一导电图案；
    在所述第一导电层上形成第一无机绝缘层；
    在所述第一无机绝缘层上形成第二导电层，所述第二导电层包括位于所述像素区的第二导电图案，所述第二导电图案和所述第一导电图案构成第一存储电容；
    在所述第二导电层上形成第二无机绝缘层；
    在所述第二无机绝缘层上形成第三导电层，所述第三导电层包括位于所述像素区的第三导电图案，所述第三导电图案和所述第二导电图案构成第二存储电容；
    在所述第三导电层上形成第三无机绝缘层，并采用一次构图工艺，在所述像素区形成贯穿所述第三无机绝缘层和所述第二无机绝缘层的第一通孔；
    在所述第三无机绝缘层上形成像素电极层，所述像素电极层包括位于所述像素区的像素电极，所述像素电极和所述第三导电图案构成第三存储电容，且所述像素电极通过所述第一通孔与所述第二导电图案电连接。
  17. 如权利要求16所述的制作方法，其中，在所述第一无机绝缘层上形成第二导电层之后，且在所述第二导电层上形成第二无机绝缘层之前，还包括：
    在所述第二导电层上形成包括有机绝缘层，所述有机绝缘层包括位于所述像素区的第二通孔，所述第二通孔与所述第一通孔导通设置。
  18. 如权利要求16所述的制作方法，其中，在所述衬底基板上形成位于所述像素区的第一导电图案的同时，还包括：在所述第一导电层形成沿第一方向延伸且与所述第一导电图案一体设置的第一连接线；
    在所述第一导电层上形成第一无机绝缘层，具体包括：在非显示区形成贯穿第一无机绝缘层的第三通孔；
    在所述第一无机绝缘层上形成位于所述像素区的第二导电图案的同时，还包括：在所述第二导电层形成沿第二方向延伸且与所述第二导电图案一体设置的第二连接线，所述第二方向与所述第一方向交叉设置；
    在所述像素区形成贯穿所述第三无机绝缘层和所述第二无机绝缘层的第一通孔的同时，还包括：在所述非显示区形成贯穿所述第三无机绝缘层和所述第二无机绝缘层的第四通孔，以及在所述非显示区仅贯穿所述第三无机绝缘层的第五通孔，其中，所述第四通孔与所述第三通孔导通；
    在所述第三无机绝缘层上形成位于所述像素区的像素电极的同时，还包括：在所述非显示区形成位于所述像素电极层的走线，所述走线通过所述第三通孔和所述第四通孔与所述第一连接线电连接，所述走线通过所述第五通孔与所述第二连接线电连接。
  19. 如权利要求18所述的制作方法，其中，在所述第一无机绝缘层上形成第二导电层之后，且在所述第二导电层上形成第二无机绝缘层之前，还包括：
    在所述第二导电层上形成包括有机绝缘层，所述有机绝缘层包括位于所述像素区的第二通孔，以及位于所述非显示区的第六通孔，所述第二通孔与所述第一通孔导通设置，所述第六通孔导通所述第三通孔与所述第四通孔。
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