WO2023157719A1

WO2023157719A1 - Circuit structure

Info

Publication number: WO2023157719A1
Application number: PCT/JP2023/003991
Authority: WO
Inventors: 慎司澤井; 功徳本; 亮平寺西; 拓也飯田; 卓展川口
Original assignee: 住友電装株式会社
Priority date: 2022-02-17
Filing date: 2023-02-07
Publication date: 2023-08-24

Abstract

This circuit structure is provided with a multilayer substrate and an electronic component mounted on the multilayer substrate. In the present invention, the multilayer substrate comprises a first surface layer having a surface-side pattern on which the electronic component is mounted; a second surface layer provided on the opposite side to the first surface layer with respect to a stacking direction; one or a plurality of inner layers provided between the first surface layer and the second surface layer and having an inside pattern; and a via that connects the surface-side pattern and the inside pattern. The first surface layer includes, on the surface of the first surface layer, a first portion that is a region in which the surface-side pattern is formed, and a second portion outside the region in which the surface-side pattern is formed. The inside pattern includes a pattern body portion that is in communication with the surface-side pattern through the via, and a pattern extension portion provided inside the second portion with respect to the stacking direction and extending from the pattern body portion.

Description

circuit construct

The present disclosure relates to circuit constructs. This application claims priority based on Japanese Application No. 2022-022550 filed on February 17, 2022, and incorporates all the descriptions described in the Japanese Application.

For example, in a car, an electric connection box is used in its electrical system. The electrical connection box may have functional parts for signal input/output with equipment mounted on the vehicle body, CAN, Gateway, and the like. To that end, the junction box has a printed circuit board on which electronic components such as processors, relays and fuses are mounted. Patent Literature 1 discloses a printed wiring board for an electric junction box mounted on an automobile.

JP 2011-66083 A

A circuit structure of the present disclosure is a circuit structure comprising a multilayer substrate, an electronic component mounted on the multilayer substrate, and a connector connection portion provided on the multilayer substrate and connected to a mating connector. The multilayer substrate includes a first surface layer having a front pattern on which the electronic component is placed, a second surface layer provided on the opposite side of the first surface layer in a stacking direction, and the first surface layer. One or more inner layers provided between the second surface layer and having an inner pattern, and vias connecting the front pattern and the inner pattern, wherein the first surface layer is provided with the second surface layer The surface of one surface layer has a first part that is an area in which the front pattern is formed and a second part that is outside the formation area of the front pattern, and the inner pattern includes the front pattern and the It has a pattern body portion connected through vias, and a pattern extension portion provided inside the second portion in the stacking direction and extending from the pattern body portion.

FIG. 1 is an exploded perspective view showing an outline of an electric connection box. FIG. 2 is a plan view showing an outline of the circuit structure. 3 is a cross-sectional view showing part of the circuit structure shown in FIG. 2. FIG. FIG. 4 is a plan view of the first surface layer. FIG. 5 is a plan view for explaining an inner layer having inner patterns. FIG. 6 is a cross-sectional view showing a modification of the heat dissipation structure. 7 is a plan view of the first surface layer of the circuit structure shown in FIG. 6. FIG. 8 is a plan view for explaining an inner layer having an inner pattern in the circuit structure shown in FIG. 6. FIG.

[Problems to be Solved by the Present Disclosure]
In the above printed wiring board, when it becomes difficult to secure the area for heat dissipation due to the reduction of the waste board for cost reduction or the layout change of the connector connection part to which the mating connector is connected. There is In particular, when an electronic component through which a relatively large current flows is mounted on a printed wiring board, improvement of heat dissipation performance becomes a problem.

Therefore, an object of the present disclosure is to improve the heat dissipation performance of a circuit structure including a printed wiring board.

[Effect of the present disclosure]
According to the present disclosure, it is possible to improve the heat dissipation performance of the circuit structure.

<Outline of Embodiment of Present Disclosure>
An outline of the embodiments of the present disclosure will be listed and described below.
(1) A circuit structure according to a first embodiment is a circuit structure including a multilayer substrate and an electronic component mounted on the multilayer substrate, wherein the electronic component is mounted on the multilayer substrate. a first surface layer having a front pattern, a second surface layer provided on the opposite side of the first surface layer in the stacking direction, and an inner pattern provided between the first surface layer and the second surface layer and a via that connects the front pattern and the inner pattern, and the first surface layer has the front pattern formed on the surface of the first surface layer and a second portion outside the forming region of the front-side pattern, and the inner pattern includes a pattern body portion connected to the front-side pattern through the via, and the second portion. and a pattern extension portion provided inside in the stacking direction and extending from the pattern body portion.

According to the circuit structure according to the first embodiment, heat generated in the electronic component is transferred from the front side pattern of the first surface layer to the inner side pattern through the via. The inner pattern has a pattern extension part in addition to the pattern body part, and the heat dissipation area is enlarged. The heat of the pattern extension can be dissipated from the second portion outside the formation area of the front-side pattern. As described above, the heat dissipation performance is improved.

(2) In the circuit construction body of (1) above, preferably, the first surface layer has a sub-pattern on the second part on which the electronic component is not placed and is not connected to the front pattern, and The pattern extension portion is provided inside the sub-pattern in the stacking direction. In this case, the heat of the pattern extension is transmitted to the sub-pattern of the first surface layer and radiated.

(3) In the circuit structure of (2) above, preferably, the multilayer substrate has sub-vias connected to the sub-patterns, and the inner layer has sub-inner patterns connected to the sub-vias. and the pattern extension is provided between the sub-pattern and the sub-inner pattern. In this case, the heat of the pattern extension is transferred to the sub-pattern and the sub-inner pattern. Heat from the sub-inner pattern is radiated from the sub-pattern through the sub-via.

(4) In the circuit constructing body of (1), the second portion is provided with a prohibited surface on which pattern formation is prohibited, and the pattern extension portion extends inside the prohibited surface in the stacking direction. is provided. In this case, the heat of the pattern extension is dissipated from the forbidden surface.

(5) In the circuit structures of (1) to (4) above, when the heat generation of the electronic parts is relatively large, a wide wiring pattern is formed on the multilayer board for such electronic parts. preferable. Therefore, the circuit structure further includes a plurality of connector connection portions to which mating connectors are connected in the multilayer board, and the multilayer board includes a first mounting area in which the electronic components are mounted and a mounting area from the electronic components. a second mounting area on which components that generate less heat are mounted, wherein the first mounting area is provided between the plurality of connector connection portions, and the plurality of connector connection portions and the first mounting area are The second mounting area is provided next to the lined range.

In this case, the first mounting area where electronic components that generate relatively large heat are mounted is adjacent to the connector connecting portion. In order to electrically connect the electronic component and the connector connecting portion, it is possible to shorten the wide wiring pattern formed on the multilayer substrate for the electronic component as much as possible. As a result, the space of the multilayer substrate can be effectively used. On the other hand, for components that generate less heat, the wiring pattern may be narrower, and such a wiring pattern may be slightly longer in order to be electrically connected to the connector connecting portion. No need to occupy space.

<Details of the embodiment of the present disclosure>
Hereinafter, details of embodiments of the present disclosure will be described with reference to the drawings. At least part of the embodiments described below may be combined arbitrarily.

[Regarding the circuit structure]
FIG. 1 is an exploded perspective view showing an outline of the electrical junction box 5. FIG. The electrical connection box 5 shown in FIG. 1 includes a resin upper cover 6 , a resin lower cover 7 , and a circuit structure 10 . The upper cover 6 and the lower cover 7 can be combined. Circuit component 10 is accommodated in a space formed between upper cover 6 and lower cover 7 . An opening 8 for connecting the mating connector 9 to the circuit structure 10 is formed in the upper cover 6 . In the form shown in FIG. 1, two openings 8, 8 are formed in the upper cover 6 for connecting two

mating connectors

9, 9. As shown in FIG. The circuit structure 10 has a connector connection portion 13 to which the mating connector 9 is connected. The number of mating connectors 9 can be changed, and the circuit structure 10 has the same number of connector connecting portions 13 as the mating connectors 9 .

The circuit structure 10 includes a multilayer board 11 that is a printed wiring board, and electronic components 12 mounted on the multilayer board 11 . FIG. 2 is a plan view showing an outline of the circuit structure 10. FIG. The circuit structure 10 includes a multilayer substrate 11 having a plurality of (two in the figure) connector connection portions 13 to which a mating connector 9 (see FIG. 1) is connected. The multilayer substrate 11 has a first mounting area K1 on which an electronic component 12 that generates relatively large heat is mounted, and a second mounting area K2 on which a component 80 that generates less heat than the electronic component 12 is mounted. Examples of electronic components 12 that generate relatively large heat are transistors, power devices, and the like. Examples of components (electronic components) 80 that generate relatively little heat are resistors, ceramic capacitors, and the like. The electronic component 12 and the component 80 are electrically connected to the connector connection portion 13 by wiring patterns formed on the multilayer substrate 11 .

A first mounting area K<b>1 is provided between the two

connector connection portions

13 and 13 on the surface of the multilayer substrate 11 . A second mounting area K2 is provided next to the range K0 in which the two

connector connection portions

13, 13 and the first mounting area K1 are arranged. In FIG. 2, the range K0 is a range indicated by a two-dot chain line.
The circuit structure 10 has a heat dissipation structure for improving heat dissipation performance. The heat dissipation structure will be described below.

[First Embodiment of Heat Dissipation Structure]
FIG. 3 is a cross-sectional view showing part of the circuit structure 10 shown in FIG. 2 (the part indicated by symbol A). A multilayer substrate 11 shown in FIG. and vias 19 . The multilayer substrate 11 shown in FIG. 3 has four inner layers 18, but the number of layers of the inner layers 18 can be changed. The multilayer substrate 11 may have one or more inner layers 18 .

The first surface layer 16 has a front pattern 21 on which the heat-generating electronic component 12 is placed. The first surface layer 16 has a first resin layer 31 on which the front pattern 21 is formed. The front pattern 21 is made of metal foil and is also called a land. The front pattern 21 is thermally and electrically directly connected to the electronic component 12 . The first surface layer 16 has a first portion 41 and a second portion 42 as regions on its surface 16a. The first part 41 is a region where the front pattern 21 is formed. The second portion 42 is an area outside the formation area of the front-side pattern 21 .

The first surface layer 16 has a first sub-pattern 24 on its second portion 42 . The first sub-pattern 24 is not mounted with the electronic component 12 and is not connected to the front pattern 21 . The first sub-pattern 24 is made of metal foil. In this embodiment, the first sub-pattern 24 is used as a ground pattern and connected to the reference potential point. The first subpattern 24 and the front pattern 21 are formed on the common surface 16a, but are not physically and electrically connected.

The second surface layer 17 has a back pattern 22 . The second surface layer 17 has a second resin layer 32 on which the back pattern 22 is formed. The back pattern 22 is made of metal foil. The backside pattern 22 may be a wiring pattern for electrically connecting the electronic component 12 mounted on the first surface layer 16 and the terminals of the connector connecting portion 13 or components not shown.

The second surface layer 17 has a second sub-pattern 25 . The second sub-pattern 25 is not connected to the back pattern 22 . The second sub-pattern 25 is made of metal foil. In this embodiment, the second sub-pattern 25 is used as a ground pattern and connected to the reference potential point. The second sub-pattern 25 and the back pattern 22 are formed on the common surface 17a, but are not physically and electrically connected. The second sub-pattern 25 is provided on the side opposite to the first sub-pattern 24 in the stacking direction.

The inner layer 18 has an inner pattern 23 . In the form shown in FIG. 3, two layers of inner patterns 23 are provided. A layer (inner layer 18 ) adjacent to the first surface layer 16 has one layer of inner pattern 23 . A layer (inner layer 18 ) adjacent to the second surface layer 17 has one layer of inner pattern 23 . Note that the number and arrangement of the inner patterns 23 can be changed. The inner layer 18 has an inner resin layer 33 on which the inner pattern 23 is formed. The inner pattern 23 is made of metal foil. The two layers of the inner pattern 23 are arranged between the front pattern 21 and the back pattern 22 so as to overlap each other in the stacking direction with the resin portion interposed therebetween.

A plurality of vias 19 are provided. The vias 19 are holes coated with a conductive film, and thermally and electrically connect the patterns of each layer. The via 19 is a thermal via that connects the front pattern 21 and the inner pattern 23 . In the form shown in FIG. 3 , the via 19 connects the front pattern 21 , the

inner patterns

23 and 23 in two layers, and the back pattern 22 . At least one via 19 may be provided. In other words, one or a plurality of vias 19 may be provided.

The inner layer 18 has sub-inner patterns 26 . In the form shown in FIG. 3, four layers of sub-inner patterns 26 are provided. Note that the number of sub-inner patterns 26 can be changed. The sub-inner pattern 26 is formed on the inner resin layer 33 . The sub inner pattern 26 is made of metal foil. The inner layer 18 next to the first surface layer 16 has a sub-inner pattern 26a that is one layer narrower. The inner layer 18 next to the second surface layer 17 has a sub-inner pattern 26b that is one layer narrower. The remaining inner layer 18 has sub-inner patterns 26c that are wider than sub-inner patterns 26a (26b) that are narrower. The plurality of inner sub-patterns 26 are arranged between the first sub-pattern 24 and the second sub-pattern 25 so as to overlap each other in the stacking direction via the resin portion.

The multilayer substrate 11 has sub-vias 20 connected to the first sub-patterns 24 . The sub-vias 20 are formed by holes coated with a conductive film, and thermally and electrically connect the patterns of each layer. The sub-via 20 is a thermal via that connects the first sub-pattern 24 and the sub-inner pattern 26 . In the form shown in FIG. 3 , the sub-via 20 connects the first sub-pattern 24 , the four-layer inner sub-pattern 26 and the second sub-pattern 25 . As described above, the inner layer 18 has sub-inner patterns 26 connected to the sub-vias 20 .

4 is a plan view of the first surface layer 16. FIG. FIG. 5 is a plan view for explaining the inner layer 18 having the inner pattern 23. FIG. As shown in FIGS. 3, 4 and 5, the inner pattern 23 has a pattern body 27 and pattern extensions 28 . The pattern body portion 27 is a portion provided inside the front pattern 21 in the stacking direction. The pattern body portion 27 is thermally and electrically connected to the front side pattern 21 and the back side pattern 22 through the vias 19 . The pattern extension portion 28 is a portion extended from the pattern body portion 27 . The pattern extension part 28 is provided inside the second part 42 in the stacking direction, which is outside the forming area of the front-side pattern 21 . If the direction in which the pattern extension portion 28 extends is defined as the width direction, the pattern extension portion 28 makes the inner pattern 23 wider in the width direction than the front side pattern 21 (becomes wider).

In this embodiment, the pattern extension portion 28 is provided inside the first sub-pattern 24 in the stacking direction via the resin portion. More specifically, in the inner layer 18 adjacent to the first surface layer 16, the pattern extension 28 is provided between the first sub-pattern 24 and the wide sub-inner pattern 26c via the resin portion. The pattern extension 28 and the narrow sub-inner pattern 26a are provided in the same layer.
In the inner layer 18 next to the second surface layer 17, the pattern extension part 28 is provided between the second sub-pattern 25 and the wide sub-inner pattern 26c via the resin part. The pattern extension 28 and the narrow sub-inner pattern 26b are provided in the same layer.

As described above, according to the heat dissipation structure according to the first embodiment, heat generated in the electronic component 12 is transferred from the front pattern 21 of the first surface layer 16 to the inner pattern 23 through the vias 19 . The inner pattern 23 has a pattern extension portion 28 in addition to the pattern body portion 27 to increase the heat dissipation area. The heat of the pattern extension portion 28 can be radiated from the second portion 42 outside the forming area of the front-side pattern 21 through the resin portion.

In the form shown in FIG. 3, the second portion 42 is provided with the first sub-pattern 24 . That is, the first surface layer 16 has the first sub-pattern 24 on the second portion 42 on which the electronic component 12 is not placed and which is not connected to the front side pattern 21 . A pattern extension portion 28 is provided inside the first sub-pattern 24 in the stacking direction. Therefore, the heat of the pattern extension portion 28 is transmitted to the first sub-pattern 24 of the first surface layer 16 via the resin portion and radiated.

Furthermore, in the form shown in FIG. 3 , the multilayer substrate 11 has sub-vias 20 connected to the first sub-patterns 24 . The inner layer 18 has sub-inner patterns 26 connected with the sub-vias 20 . The pattern extension 28 is provided between the first sub-pattern 24 and the sub-inner pattern 26 (26c). Therefore, the heat of the pattern extension portion 28 is transmitted to the first sub-pattern 24 and the sub-inner pattern 26 (26c) through the resin portion. The heat of the inner sub-pattern 26 (26c) is radiated from the first sub-pattern 24 through the sub-via 20 .

Furthermore, a second sub-pattern 25 is provided on the second surface layer 17 side. Another pattern extension 28 is provided inside the second sub-pattern 25 in the stacking direction. Therefore, the heat of the pattern extension portion 28 is transferred to the second sub-pattern 25 of the second surface layer 17 via the resin portion and radiated.

The inner layer 18 on the second surface layer 17 side has sub-inner patterns 26 connected to the sub-vias 20 . The sub inner pattern 26 and the second sub pattern 25 are connected through the sub via 20 . The pattern extension 28 of the inner layer 18 on the second surface layer 17 side is provided between the second sub-pattern 25 and the sub-inner pattern 26 (26c). Therefore, the heat of the pattern extension portion 28 is transmitted to the second sub-pattern 25 and the sub-inner pattern 26 (26c) through the resin portion. The heat of the inner sub-pattern 26 (26c) is radiated from the second sub-pattern 25 through the sub-via 20 .

[Modified example of heat dissipation structure]
In the embodiment shown in FIGS. 3, 4 and 5 (hereinafter referred to as "first embodiment"), the second portion 42 of the multilayer substrate 11 and the

subpatterns

24, 24 and 24 25, sub-inner patterns 26, and sub-vias 20 are provided.
FIG. 6 is a cross-sectional view showing a modification of the heat dissipation structure according to the first embodiment. FIG. 7 is a plan view of the first surface layer 16 of the circuit construction 10 shown in FIG. 8 is a plan view for explaining the inner layer 18 having the inner pattern 23 in the circuit structure 10 shown in FIG. 6. FIG.

In the modified example, sub-patterns 24 and 25, sub-inner pattern 26, and sub-via 20 are omitted compared to the first embodiment. Other configurations are the same. In each figure showing a modification, the same reference numerals are given to the same configurations as in the first embodiment, and the description of the same configurations will be omitted.

A modified circuit structure 10 includes a multilayer substrate 11 and electronic components 12 mounted on the multilayer substrate 11 . The multilayer substrate 11 includes a first surface layer 16 having a front pattern 21 on which the electronic component 12 is placed, a second surface layer 17 provided on the opposite side of the first surface layer 16 in the stacking direction, and the first surface layer 16. It has one or a plurality of inner layers 18 provided between the second surface layer 17 and having an inner pattern 23 , and vias 19 connecting the front pattern 21 and the inner pattern 23 . The first surface layer 16 has, on its surface 16a, a first portion 41, which is an area where the front-side pattern 21 is formed, and a second portion 42, which is outside the area where the front-side pattern 21 is formed. The inner pattern 23 has a pattern body portion 27 connected to the front pattern 21 through the vias 19 and a pattern extension portion 28 provided inside the second portion 42 in the lamination direction and extending from the pattern body portion 27 . The above points are the same as those of the first embodiment.

In the modified example, the second portion 42 is provided with a prohibited surface 45 on which pattern formation is prohibited. The pattern extension 28 is provided inside the prohibition surface 45 in the stacking direction. In this case, the heat of the pattern extension portion 28 is radiated from the prohibition surface 45 via the resin portion.

As described above, according to the circuit structure 10 having the heat dissipation structure according to the first embodiment including the first form and the modification, the heat dissipation performance is improved. In the multilayer substrate 11, it becomes possible to effectively utilize the ground pattern space such as the sub-pattern 24 (FIG. 3) or the dead space such as the prohibition surface 45 (see FIG. 6) for heat dissipation. .

[Regarding the circuit structure 10]
As described above (see FIG. 2), the multilayer substrate 11 has a first mounting area K1 in which the electronic components 12 that generate relatively large heat are mounted, and a second mounting area K1 in which the components 80 that generate less heat than the electronic components 12 are mounted. and the mounting area K2. The circuit structure 10 includes two (plural) connector connecting portions 13 .

Here, in the circuit structure 10 , if the electronic components 12 generate relatively large heat, it is preferable to form a wide wiring pattern on the multilayer substrate 11 for such electronic components 12 . Therefore, as shown in FIG. 2, the circuit structure 10 is provided with a first mounting area K1 between the two

connector connection portions

13,13. A second mounting area K2 is provided next to the range K0 in which the two

connector connection portions

13, 13 and the first mounting area K1 are arranged.

In this case, the first mounting area K1 where the electronic component 12 that generates relatively large heat is mounted and the connector connecting portion 13 are adjacent to each other. In order to electrically connect the electronic component 12 and the connector connection part 13, a wide wiring pattern (for example, a back side pattern 22) formed on the multilayer substrate 11 for the electronic component 12 is made as short as possible. becomes possible. As a result, the space of the multilayer substrate 11 can be effectively used. On the other hand, the width of the wiring pattern may be narrow for the component 80 that generates less heat, and such a wiring pattern may be slightly longer in order to be electrically connected to the connector connection portion 13 . does not occupy space unnecessarily.

Note that the number of connector connection portions 13 can be changed, and may be three or more. In this case also, the first mounting area K1 is provided between the adjacent

connector connecting portions

13, 13, and the second mounting area K2 is provided next to the range in which the connector connecting portions 13 and the first mounting area K1 are arranged. It is good if it is

〔others〕
In the circuit structure 10 shown in FIG. 3, the case where the first sub-pattern 24 is provided on the first surface layer 16 and the second sub-pattern 25 is provided on the second surface layer 17 has been described. and the second sub-pattern 25 or both may be omitted.

In the circuit structure 10 shown in FIG. 6, a second portion 42 is provided on the surface 16a of the first surface layer 16 as a region outside the formation region of the front side pattern 21, and the pattern is formed on the second portion 42. A forbidden face 45 is provided. The inner layer 18 shown in FIG. 6 does not have the sub-inner pattern 26 as shown in FIG. 3, but may have the sub-inner pattern 26 .

The above embodiments are illustrative in all respects and are not restrictive. The scope of rights of the present invention is indicated by the scope of claims rather than the above embodiments, and includes all modifications within the range equivalent to the structure described in the scope of claims.

5 electrical connection box 6 upper cover 7 lower cover 8 opening 9 mating connector 10 circuit structure 11 multilayer substrate 12 electronic component 13 connector connecting portion 16 first surface layer 16a surface 17 second surface layer 17a surface 18 inner layer 19 via 20 sub-via 21 front pattern 22 back side pattern 23 inner pattern 24 first sub-pattern 25 second sub-pattern 26 sub-inner pattern 26a sub-inner pattern 26b sub-inner pattern 26c sub-inner pattern 27 pattern body 28 pattern extension 31 first resin layer 32 second resin layer 33 Inner Resin Layer 41 First Part 42 Second Part 45 Prohibited Surface 80 Components with Small Heat Generation K1 First Mounting Area K2 Second Mounting Area

Claims

A circuit structure comprising a multilayer substrate and an electronic component mounted on the multilayer substrate,
The multilayer substrate is
a first surface layer having a front pattern on which the electronic component is placed;
a second surface layer provided on the side opposite to the first surface layer in the stacking direction;
one or more inner layers provided between the first surface layer and the second surface layer and having an inner pattern;
a via that connects the front side pattern and the inner side pattern;
has
The first surface layer has, on the surface of the first surface layer,
a first part, which is a region where the front-side pattern is formed;
and a second portion outside the formation area of the front-side pattern,
The inner pattern is
a pattern body portion connected to the front side pattern through the via;
a pattern extension portion provided inside the second portion in the stacking direction and extending from the pattern body portion;
A circuit construct having
The first surface layer has, in the second part, a sub-pattern on which the electronic component is not placed and which is not connected to the front-side pattern,
2. The circuit structure according to claim 1, wherein said pattern extension portion is provided inside said sub-pattern in the stacking direction.
The multilayer substrate has sub-vias connected to the sub-patterns,
The inner layer has a sub-inner pattern connected to the sub-via,
3. The circuit construct according to claim 2, wherein said pattern extension is provided between said sub-pattern and said sub-inner pattern.
The second portion is provided with a prohibited surface on which pattern formation is prohibited,
2. The circuit structure according to claim 1, wherein said pattern extension portion is provided inside said prohibition surface in the stacking direction.
The multi-layer substrate is provided with a plurality of connector connection portions to which mating connectors are connected,
The multilayer board has a first mounting area where the electronic component is mounted and a second mounting area where a component that generates less heat than the electronic component is mounted,
The first mounting area is provided between the plurality of connector connection parts,
5. The circuit structure according to any one of claims 1 to 4, wherein said second mounting area is provided next to a range in which said plurality of connector connection portions and said first mounting area are arranged.