WO2023155422A1 - 一种提升led芯片光取出效率的芯片制造方法及led芯片 - Google Patents

一种提升led芯片光取出效率的芯片制造方法及led芯片 Download PDF

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WO2023155422A1
WO2023155422A1 PCT/CN2022/117778 CN2022117778W WO2023155422A1 WO 2023155422 A1 WO2023155422 A1 WO 2023155422A1 CN 2022117778 W CN2022117778 W CN 2022117778W WO 2023155422 A1 WO2023155422 A1 WO 2023155422A1
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layer
led chip
sapphire substrate
gallium nitride
chip
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French (fr)
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林潇雄
曹玉飞
褚志强
黄文光
王帅
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聚灿光电科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the invention relates to the technical field of LEDs, in particular to a chip manufacturing method and an LED chip for improving the light extraction efficiency of an LED chip.
  • LED Light-Emitting Diode
  • LEDs are widely used in various indications, displays, decorations, backlights, general lighting and other fields due to their advantages in energy saving, environmental protection, long life, and low power consumption.
  • the core component of semiconductor lighting products is the LED chip. Its research and production technology has developed rapidly, and the brightness and reliability of the chip have been continuously improved. In the process of R&D and production of LED chips, the improvement of the external quantum efficiency of the device has always been the core content. Therefore, the improvement of the light extraction efficiency is very important.
  • the light extraction efficiency of LED refers to: inside the LED, the photons generated by electric energy excitation are not all emitted, only some photons can leave the device through refraction, and other photons are continuously reflected inside and finally absorbed. In traditional LED devices, due to the existence of factors such as substrate absorption, electrode blocking, and total reflection of the light-emitting surface, the light extraction efficiency is usually less than 10%.
  • the structure of the LED chip usually includes a sapphire substrate, an N-GaN layer, an active region and a P-GaN layer arranged in sequence, and the N-GaN layer is exposed by etching the LED chip to form steps.
  • a sapphire substrate an N-GaN layer, an active region and a P-GaN layer arranged in sequence
  • the N-GaN layer is exposed by etching the LED chip to form steps.
  • an N-type electrode layer on the N-GaN layer form a current blocking layer on the P-GaN layer, form a transparent conductive layer on the current blocking layer, and set an insulating protective layer on the transparent conductive layer.
  • a P-type electrode layer is formed on the layer.
  • the refractive index of GaN is about 2.3, while that of air is 1, so the side light at the step surface will be totally reflected at the interface of GaN, while The lateral light cannot be emitted, resulting in low extraction efficiency of the lateral light.
  • the invention provides a chip manufacturing method and an LED chip for improving the light extraction efficiency of the LED chip, so as to solve the problem of low light extraction efficiency of the LED chip due to large differences in refractive index during the manufacturing process of the LED chip.
  • the first aspect of the embodiment of the present application provides a chip manufacturing method for improving the light extraction efficiency of LED chips, the method includes:
  • Patterned sapphire substrate grows LED chip epitaxial wafers by metal organic compound chemical vapor deposition method
  • N-type gallium nitride is etched on the LED chip epitaxial wafer by inductively coupled plasma method, so that the N-type gallium nitride is exposed;
  • the sapphire substrate is deposited with silicon oxide by plasma enhanced chemical vapor deposition, and the silicon oxide covers the entire surface of the LED chip epitaxial wafer;
  • the isolation groove is formed after laser cutting or photolithography plus etching for the LED chip epitaxial wafer;
  • the isolation tank is corroded one or more times with phosphoric acid, sulfuric acid and hydrofluoric acid solutions to form a preset shape, it also includes:
  • a specific via hole is etched on the insulating protective layer for connecting the pad electrode and the extended electrode under the insulating protective layer.
  • the oxide layer has a thickness of 0.5 ⁇ m to 5 ⁇ m.
  • the material of the oxide layer includes one, two or a combination of single-layer silicon oxide, single-layer titanium oxide or niobium oxide.
  • the material of the transparent conductive layer is ITO, GZO, AZO or NiAu, and the thickness is 10 nm to 300 nm.
  • the material of the metal electrode includes chromium, titanium, aluminum, nickel, platinum and gold, and the thickness of the metal electrode is between 1 ⁇ m and 5 ⁇ m.
  • the material of the insulating protection layer is SiO 2 or Si 3 N 4 .
  • the patterned sapphire substrate is periodically arranged, and the pattern period is 2 ⁇ m to 8 ⁇ m.
  • the preset shape is multi-layered triangular cone, semicircle or sphere.
  • etching includes using a dry method or a wet method.
  • the second aspect of the embodiment of the present application provides an LED chip, including: a patterned sapphire substrate, the patterned sapphire substrate includes a sapphire substrate and an oxide layer arranged on the sapphire substrate; an LED chip epitaxial wafer, arranged on the patterned sapphire substrate On the sapphire substrate, and the outer periphery of the LED chip epitaxial wafer is provided with isolation grooves; wherein, the LED chip epitaxial wafer includes an N-type gallium nitride layer and a P-type gallium nitride layer, and the N-type gallium nitride layer is arranged on the patterned sapphire On the substrate, the P-type gallium nitride layer is arranged on the N-type gallium nitride layer, and the isolation groove is multi-layered triangular cone, semicircular or spherical.
  • the LED chip also includes: a current blocking layer disposed on the P-type gallium nitride layer; a transparent conductive layer disposed on the P-type gallium nitride layer and covering the current blocking layer; and the transparent layer is provided with positive and negative metal An electrode; an insulating protection layer, which is arranged on the N-type gallium nitride layer and covers the transparent conductive layer and the P-type gallium nitride layer; the insulating protection layer is provided with an etching through hole, and the etching through hole is used to connect the pad electrode and the P-type gallium nitride layer.
  • the electrode is extended under the insulating protective layer.
  • the etched through hole includes a first through hole and a second through hole; the first through hole is located above the transparent conductive layer, and the second via hole is located above the N-type gallium nitride; the LED chip also includes: a P-type electrode layer, It is arranged in the first through hole; the N-type electrode layer is arranged in the second through hole.
  • the oxide layer has a thickness of 0.5 ⁇ m to 5 ⁇ m.
  • the thickness of the transparent conductive layer is 10 nm to 300 nm.
  • the thickness of the metal electrode is 1 ⁇ m to 5 ⁇ m.
  • the patterned sapphire substrate is periodically arranged, and the pattern period is 2 ⁇ m to 8 ⁇ m. It can be seen from the above technical solutions that the present application provides a chip manufacturing method and an LED chip for improving the light extraction efficiency of LED chips.
  • the method includes: depositing a lithographic oxide layer on a sapphire substrate by plasma-enhanced chemical vapor deposition.
  • a patterned sapphire substrate is obtained by photolithography and etching of the oxide layer.
  • the patterned sapphire substrate grows the LED chip epitaxial wafer through the metal organic compound chemical vapor deposition method.
  • N-type gallium nitride is etched on the epitaxial wafer of the LED chip by an inductively coupled plasma method, so that the N-type gallium nitride is exposed to the outside.
  • the sapphire substrate is deposited with silicon oxide by plasma enhanced chemical vapor deposition, and the silicon oxide covers the entire surface of the epitaxial wafer of the LED chip. After laser cutting or photolithography and etching are used for the LED chip epitaxial wafer, isolation grooves are formed. Use phosphoric acid, sulfuric acid and hydrofluoric acid solutions to corrode the isolation tank one or more times to form a preset shape.
  • the LED chip includes: a patterned sapphire substrate, the patterned sapphire substrate includes a sapphire substrate and an oxide layer arranged on the sapphire substrate; an LED chip epitaxial sheet is arranged on a patterned sapphire substrate, and the LED chip epitaxial sheet
  • the periphery of the LED chip is provided with isolation grooves; wherein, the LED chip epitaxial wafer includes an N-type GaN layer and a P-type GaN layer, the N-type GaN layer is set on a patterned sapphire substrate, and the P-type GaN layer is set On the N-type gallium nitride layer, the isolation groove is multi-layered triangular cone, semicircular or spherical.
  • the technical solution of the present application forms a multi-layer triangular cone, semicircle or spherical shape around the LED chip that is conducive to light output, so that the light emitted by the active area of the LED chip will be emitted with a greater probability, thereby improving the light output. Take out efficiency.
  • FIG. 1 is a schematic flowchart of a chip manufacturing method for improving the light extraction efficiency of an LED chip provided by an embodiment of the present application;
  • Fig. 2 is a schematic cross-sectional structure diagram of a conventional LED chip provided by the embodiment of the present application;
  • FIG. 3 is a schematic diagram of a cross-sectional structure of an LED chip provided by an embodiment of the present application.
  • Figure 4 is a schematic electron microscope diagram of the cross-sectional structure of the LED chip provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of an electron microscope showing an inclined 45° angle of the LED chip cross-sectional structure provided by the embodiment of the present application;
  • sapphire substrate 101 sapphire substrate 101, oxide layer 102, N-type gallium nitride 201, P-type gallium nitride 202, current blocking layer 301, transparent conductive layer 302, N-type electrode layer 401, P-type electrode layer 402, insulation protection Layer 501.
  • Patterned sapphire substrate that is, a mask for dry etching is grown on a sapphire substrate, and the mask is patterned with a standard photolithography process, and etched by an inductively coupled plasma ICP (Inductive Coupled Plasma) etching technology. etch the sapphire and remove the mask. GaN material is then grown on it, so that the vertical epitaxy of the GaN material becomes lateral epitaxy.
  • ICP Inductive Coupled Plasma
  • the output brightness of the LED grown on the patterned sapphire substrate is greatly improved compared with the traditional LED, while the reverse leakage current is reduced, and the life of the LED is also extended.
  • GaN GaN
  • Gallium Nitride An inorganic substance, a compound of nitrogen and gallium, commonly used in light-emitting diodes.
  • Gallium nitride is very hard and has a wide energy gap, which can be used in high-power, high-speed optoelectronic components.
  • gallium nitride can be used in violet laser diodes, which can generate laser light without the use of nonlinear semiconductor-pumped solid-state lasers.
  • PECVD Plasma Enhanced Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition method
  • Plasma Enhanced Chemical Vapor Deposition method refers to the separation of gas containing thin film component atoms by means of microwave or radio frequency, etc., and the formation of plasma locally, and the plasma chemical activity is very strong, and it is easy to occur reaction to deposit the desired film on the substrate.
  • Dry etching It is a technology of thin film etching with plasma.
  • the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that under normal conditions. React with the material to achieve the purpose of etching and removal; on the other hand, the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy.
  • the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy.
  • it bombards the surface of the etched object it will be etched The atoms of the object material are knocked out, so as to achieve the purpose of etching by physical energy transfer.
  • the refractive index of GaN is about 2.3, while the refractive index of air is 1, so the side light at the step surface will be totally reflected at the interface of GaN , so that the side light cannot be emitted, resulting in low light extraction efficiency of the LED chip.
  • the present application aims to solve the problem of low light extraction efficiency of the LED chip due to large differences in refractive index during the manufacturing process of the LED chip.
  • the present application provides a chip manufacturing method for improving the light extraction efficiency of an LED chip and an LED chip.
  • FIG. 1 it is a schematic flowchart of a chip manufacturing method for improving the light extraction efficiency of an LED chip provided by an embodiment of the present application.
  • a chip manufacturing method for improving the light extraction efficiency of LED chips includes:
  • a lithographic oxide layer is deposited on the sapphire substrate 101 by PECVD or vapor deposition.
  • the lithographic oxide layer is deposited by PECVD, and the total thickness of the oxide layer is 0.5 ⁇ m to 5 ⁇ m.
  • the oxide layer includes one, two or a combination of a single layer of silicon oxide, a single layer of titanium oxide or niobium oxide.
  • the photolithographic oxide layer may be deposited by PECVD or evaporation method, which may be one of the three materials, or a combination of two materials, or all three materials.
  • the oxide layer is photolithographically and etched to obtain a patterned sapphire substrate.
  • the patterned sapphire substrate forms a periodic arrangement, and the pattern period is 2 ⁇ m to 8 ⁇ m.
  • the patterned sapphire substrate grows the LED chip epitaxial wafer by metal organic compound chemical vapor deposition method.
  • a GaN thin film with complex structure is grown on the patterned sapphire substrate, and this thin film is the epitaxial wafer.
  • N-type gallium nitride is etched on the LED chip epitaxial wafer by inductively coupled plasma method, so that the N-type gallium nitride is exposed.
  • the inductively coupled plasma ICP method to etch away part of the P-type GaN and quantum wells on the LED chip epitaxial wafer including N-type GaN, quantum well and P-type GaN, so that the N-type GaN is exposed to the outside , In this way, the exposed N-type gallium nitride can be reserved for the fabrication of the metal negative electrode.
  • the sapphire substrate deposits silicon oxide by plasma enhanced chemical vapor deposition, and the silicon oxide covers the entire surface of the LED chip epitaxial wafer.
  • Silicon oxide is mainly used to protect the LED chip epitaxial wafer and prevent the LED chip epitaxial wafer from being corroded. Silicon oxide covers the entire surface of the LED chip epitaxial wafer, that is, covers the entire surface of the thin film wafer.
  • a circle of isolation grooves will be formed, and the method of photolithography and etching can also be used. Most of them are laser cut, and after cutting, a circle of thin grooves, that is, isolation grooves, will be formed.
  • step S6 after laser cutting, some carbides will be produced on the isolation groove, and the carbides in the isolation groove are etched once or more times by using one solution in phosphoric acid, sulfuric acid and hydrofluoric acid solution or a mixed solution of the three solutions, A variety of shapes are formed, which may be multilayered triangular pyramids, semicircles, or spheres.
  • FIG. 2 it is a schematic diagram of a cross-sectional structure of a conventional LED chip provided by an embodiment of the present application.
  • the structure of a conventional LED chip usually includes a sapphire substrate 101, an N-GaN layer 201, an active region, and a P-GaN layer 202 arranged in sequence. Steps are formed by etching the LED chip, and the N-GaN layer 201 is exposed, an N-type electrode layer 401 is formed on the N-GaN layer 201, a current blocking layer 301 is formed on the P-GaN layer 202, a transparent conductive layer 302 is formed on the current blocking layer 301, and the transparent conductive layer 302 is set An insulating protection layer 501 , and a P-type electrode layer 402 is formed on the insulating protection layer 501 .
  • the conventional LED chip structure has a large difference in refractive index between the inside and outside of the etched step, the refractive index of GaN is about 2.3, and the refractive index of air is 1, so the side light at the step surface will be at Total reflection is formed at the interface of GaN, so that the side light cannot be emitted, resulting in low extraction efficiency of the side light.
  • FIG. 3 it is a schematic diagram of a cross-sectional structure of an LED chip provided by an embodiment of the present application.
  • the LED chip structure of the present application includes a sapphire substrate 101 .
  • a lithographic oxide layer 102 is deposited on the sapphire substrate 101 by PECVD or evaporation method, and the lithographic oxide layer 102 is deposited by PECVD method.
  • the total thickness of the oxide layer 102 is 0.5 ⁇ m to 5 ⁇ m.
  • the material of the oxide layer 102 includes one, two or a combination of single-layer silicon oxide, single-layer titanium oxide or niobium oxide.
  • the oxide layer 102 is deposited by PECVD or vapor deposition, and may be one of the three materials, or a combination of the two materials, or all three materials.
  • the advantage of PECVD is the ability to lower the process temperature while maintaining or increasing the deposition rate. Then photoetching and etching the oxide layer 102 to obtain a patterned sapphire substrate.
  • the patterned sapphire substrate forms a periodic arrangement, and the pattern period is 2 ⁇ m to 8 ⁇ m.
  • Etching mainly adopts dry method or wet method.
  • the so-called dry etching is to expose the surface of the silicon wafer to the plasma generated in the air.
  • the plasma passes through the window opened in the photoresist and reacts physically or chemically with the silicon wafer, thereby Remove exposed display material.
  • Wet etching is the chemical removal of material from the surface of silicon wafers with liquid chemicals.
  • the purpose of forming a patterned sapphire substrate is to effectively reduce the dislocation density of the GaN epitaxial material on the one hand, thereby reducing the non-radiative recombination of the active region, reducing the reverse leakage current, and improving the life of the LED; on the other hand, the active
  • the light emitted by the region is scattered multiple times by the interface between GaN and sapphire substrate, which changes the exit angle of total reflection light and increases the probability of light exiting from the sapphire substrate, thereby improving the light extraction efficiency.
  • the output brightness of the LED grown on the patterned sapphire substrate is greatly improved compared with the traditional LED, while the reverse leakage current is reduced, and the life of the LED is also extended.
  • the LED chip epitaxial wafer is grown by MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition) or MOVPE (Metal-organic Vapor Phase Epitaxy, metal organic compound vapor phase epitaxy) .
  • MOCVD Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition
  • MOVPE Metal-organic Vapor Phase Epitaxy, metal organic compound vapor phase epitaxy
  • LED chip epitaxial wafer refers to a semiconductor thin film grown on a single crystal material with a matching crystal structure.
  • a GaN thin film with a complex structure is grown on a patterned sapphire substrate.
  • the GaN thin film includes: N-GaN, quantum well, and P-GaN, this thin film is called epitaxial wafer.
  • MOCVD technology has unique advantages in the growth of thin-film crystals: it can prepare high-purity thin-film materials at lower temperatures, reducing the thermal defects and intrinsic impurity content of materials; it can control the thickness of thin-films with atomic-level precision; it adopts mass flow
  • the meter is easy to control the composition and doping amount of the compound; through the rapid switching of the gas source without dead zone, the type or proportion of the reactant can be flexibly changed to achieve a sudden change in the composition of the film growth interface.
  • the interface is steep; it can achieve large-area, uniform and high-repeatability film growth.
  • the N-type GaN 201 is etched on the LED chip epitaxial wafer by using the inductively coupled plasma ICP method, and part of the P-type GaN 202 and the quantum well are etched away, so that the N-type GaN 201 is exposed to the outside, so that it can be
  • the exposed N-type gallium nitride 201 is reserved for the fabrication of the metal negative electrode.
  • ICP Inductively coupled plasma
  • the ICP method has the advantages of fast analysis speed, stable time distribution, and wide linear range. Quantitative and qualitative analysis of multiple elements.
  • the analytical sensitivity is high, the analytical accuracy and precision are high and the determination range is wide. It can measure almost all spectral lines in the ultraviolet and visible light regions, and the range of elements to be measured is large, and dozens of elements can be measured at a time.
  • the sapphire substrate 101 is deposited with 100nm to 5000nm silicon oxide by PECVD or evaporation method. Silicon oxide is mainly used to protect LED chip epitaxial wafers. Silicon oxide has high melting point, wear resistance and corrosion resistance, strong protection ability, and light scattering absorption. Small light with excellent performance.
  • laser cutting After laser cutting or photolithography and etching are used for the LED chip epitaxial wafer, a circle of isolation grooves is formed; laser cutting has the characteristics of fast cutting speed, high cutting efficiency and good cutting quality, and laser cutting can obtain better cutting quality.
  • FIG. 4 and FIG. 5 there are schematic electron microscope schematic diagrams of the cross-sectional structure of the LED chip provided in the embodiment of the present application and a schematic electron microscopic schematic diagram of the cross-sectional structure of the LED chip inclined at an angle of 45°.
  • the pre-set shape is formed by corroding the isolation tank one or more times with one solution of phosphoric acid, sulfuric acid and hydrofluoric acid solution or a mixed solution of the three solutions. As shown in Figures 4 and 5, it can be seen that according to the number and degree of corrosion, the formed shapes are different. A platform structure will be formed first, and then a double-layered triangular cone, semicircle or spherical shape will appear on the platform structure. The shape formed after etching is also related to the material of the oxide layer 102. Different materials of the oxide layer 102 have different shapes. The more the material of the oxide layer 102, the more triangular pyramidal layers are formed.
  • the oxide layer 102 is deposited on the sapphire substrate 101 by PECVD or evaporation method, the deposited oxide layer 102 may be a composite material, or a single layer of silicon oxide, single layer of titanium oxide or niobium oxide, so after etching The resulting preset shapes are different.
  • the light in the embodiment of the present application will be refracted multiple times when passing through these preset shapes, so that part of the light that cannot be refracted can pass through the LED chip continuously. The refraction of the light emits it, thereby improving the light extraction efficiency.
  • the preset shape After forming the preset shape, it also includes: forming a current blocking layer 301 by directly photolithography and etching silicon oxide, and then removing silicon oxide and then depositing silicon oxide again by PECVD. Make a layer of transparent conductive layer 302 on the P-GaN 4 0 2 of the LED epitaxial wafer; make positive and negative metal electrodes on the transparent conductive layer 302 to obtain a P-type electrode layer; coat the entire surface of the P-type electrode layer to obtain insulation Protective layer 501 : performing specific via hole etching on the insulating protective layer 501 for connecting the pad electrode and the extended electrode under the insulating protective layer 501 .
  • the positive and negative metal electrodes can be formed by using electron beam evaporation.
  • the materials of the metal electrodes include chromium Cr, titanium Ti, aluminum Al, nickel Ni, platinum Pt and gold Au, and the thickness of the metal electrodes is between 1 ⁇ m and 5 ⁇ m. between.
  • the material of the transparent conductive layer 302 is selected from indium tin oxide ITO, zinc gallium oxide GZO, AZO or NiAu, and the thickness is 10 nm to 300 nm.
  • the transparent conductive layer 302 is made of ITO material.
  • Indium tin oxide ITO is a transparent layer, a mixture, transparent brown film or yellowish gray block, mainly used for ohmic contact and current conduction diffusion of P-type gallium nitride , can also be used in liquid crystal displays, flat panel displays, plasma displays, touch screens, electronic paper, organic light-emitting diodes, solar cells, antistatic coatings, transparent conductive coatings for EMI shielding, various optical coatings, etc.
  • the thickness of ITO may be between 10 nm and 300 nm.
  • AZO is the abbreviation of Aluminum Doped Zinc Oxide Transparent Conductive Glass.
  • the insulating protection layer 501 is made of SiO 2 or Si 3 N 4 .
  • the insulating protection layer 501 insulates and protects the side edges and the entire surface.
  • Silicon nitride Si 3 N 4 has the characteristics of high hardness, high strength, high temperature resistance, and corrosion resistance.
  • the present application provides a chip manufacturing method for improving the light extraction efficiency of LED chips.
  • the method includes: depositing an oxide layer on a sapphire substrate by plasma-enhanced chemical vapor deposition.
  • a patterned sapphire substrate is obtained by photolithography and etching of the oxide layer.
  • the patterned sapphire substrate grows the LED chip epitaxial wafer through the metal organic compound chemical vapor deposition method.
  • N-type gallium nitride is etched on the epitaxial wafer of the LED chip by an inductively coupled plasma method, so that the N-type gallium nitride is exposed to the outside.
  • the sapphire substrate is deposited with silicon oxide by plasma enhanced chemical vapor deposition, and the silicon oxide covers the entire surface of the LED chip epitaxial wafer. After laser cutting or photolithography and etching are used for the LED chip epitaxial wafer, isolation grooves are formed. Use phosphoric acid, sulfuric acid and hydrofluoric acid solutions to corrode the isolation tank one or more times to form a preset shape.
  • the technical solution of the present application forms a multi-layer triangular cone, semicircle or spherical shape around the LED chip that is conducive to light output, so that the light emitted by the active area of the LED chip will be emitted with a greater probability, thereby improving the light output. Take out efficiency.
  • the embodiment of the present application also provides an LED chip, the LED chip includes a patterned sapphire substrate, the patterned sapphire substrate includes a sapphire substrate 101 and an oxide layer 102 arranged on the sapphire substrate; the LED chip epitaxial wafer is arranged on On a patterned sapphire substrate, and the outer periphery of the LED chip epitaxial wafer is provided with isolation grooves; wherein, the LED chip epitaxial wafer includes an N-type gallium nitride layer 201 and a P-type gallium nitride layer 202, and the N-type gallium nitride layer 201 is set On the patterned sapphire substrate, the P-type GaN layer 202 is disposed on the N-type GaN layer 201, and the isolation grooves are in the shape of multi-layered triangular cones, semicircles or spheres.
  • the LED chip further includes: a current blocking layer 301 disposed on the P-type GaN layer 402; a transparent conductive layer 302 disposed on the P-type GaN layer 402 and covering the current blocking layer 301; and
  • the transparent conductive layer 302 is provided with positive and negative metal electrodes;
  • the insulating protective layer 501 is arranged on the N-type gallium nitride layer 201 and covers the transparent conductive layer 302 and the P-type gallium nitride layer 402; the insulating protective layer 501 is provided with engraved The etched through hole is used to connect the pad electrode and the extended electrode under the insulating protection layer.
  • the etched via hole includes a first via hole and a second via hole; the first via hole is located above the transparent conductive layer, and the second via hole is located above the N-type gallium nitride 201; the LED chip further includes: P The N-type electrode layer 402 is arranged in the first through hole; the N-type electrode layer 401 is arranged in the second through hole.
  • the present application deposits the lithographic oxide layer 102 on the sapphire substrate 101 by PECVD or evaporation method, and uses the PECVD method to deposit the lithographic oxide layer 102, the total thickness of the oxide layer 102 0.5 ⁇ m to 5 ⁇ m.
  • the material of the oxide layer 102 includes one, two or a combination of single-layer silicon oxide, single-layer titanium oxide or niobium oxide.
  • the oxide layer 102 is deposited by PECVD or vapor deposition, and may be one of the three materials, or a combination of two materials, or all three materials.
  • the advantage of PECVD is the ability to lower the process temperature while maintaining or increasing the deposition rate. Then photoetching and etching the oxide layer 102 to obtain a patterned sapphire substrate.
  • the thickness of the transparent conductive layer 302 is 10 nm to 300 nm.
  • the material of the transparent conductive layer 302 is selected from indium tin oxide ITO, zinc gallium oxide GZO, AZO or NiAu, and the thickness is 10 nm to 300 nm. In most cases, the transparent conductive layer 302 is made of ITO material.
  • ITO Indium tin oxide
  • ITO is a transparent layer, a mixture, transparent brown film or yellowish gray block, mainly used for ohmic contact and current conduction diffusion of P-type gallium nitride , can also be used in liquid crystal displays, flat panel displays, plasma displays, touch screens, electronic paper, organic light-emitting diodes, solar cells, antistatic coatings, transparent conductive coatings for EMI shielding, various optical coatings, etc.
  • the thickness of ITO may be between 10 nm and 300 nm.
  • AZO is the abbreviation of Aluminum Doped Zinc Oxide Transparent Conductive Glass.
  • the positive and negative metal electrodes can be formed by using electron beam evaporation.
  • the materials of the metal electrodes include chromium Cr, titanium Ti, aluminum Al, nickel Ni, platinum Pt and gold Au, and the thickness of the metal electrodes is between 1 ⁇ m and 5 ⁇ m. between.
  • the LED chip structure of the present application includes a sapphire substrate 101 .
  • a lithographic oxide layer 102 is deposited on the sapphire substrate 101 by PECVD or evaporation method, and the lithographic oxide layer 102 is deposited by PECVD method.
  • the total thickness of the oxide layer 102 is 0.5 ⁇ m to 5 ⁇ m.
  • the material of the oxide layer 102 includes one, two or a combination of single-layer silicon oxide, single-layer titanium oxide or niobium oxide.
  • the oxide layer 102 is deposited by PECVD or vapor deposition, and may be one of the three materials, or a combination of the two materials, or all three materials.
  • the advantage of PECVD is the ability to lower the process temperature while maintaining or increasing the deposition rate. Then photoetching and etching the oxide layer 102 to obtain a patterned sapphire substrate.
  • the patterned sapphire substrate forms a periodic arrangement, and the pattern period is 2 ⁇ m to 8 ⁇ m.
  • Etching mainly adopts dry method or wet method.
  • the so-called dry etching is to expose the surface of the silicon wafer to the plasma generated in the air.
  • the plasma passes through the window opened in the photoresist and reacts physically or chemically with the silicon wafer, thereby Remove exposed display material.
  • Wet etching is the chemical removal of material from the surface of silicon wafers with liquid chemicals.

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Abstract

本申请公开了一种提升LED芯片光取出效率的芯片制造方法及LED芯片，LED芯片包括：图形化蓝宝石衬底，图形化蓝宝石衬底包括蓝宝石衬底和设置在蓝宝石衬底上的氧化物层；LED芯片外延片，设置在图形化蓝宝石衬底上，且LED芯片外延片的外周设有隔离槽；其中，LED芯片外延片包括N型氮化镓层和P型氮化镓层，N型氮化镓层设置在图形化蓝宝石衬底上，P型氮化镓层设置在N型氮化镓层上，隔离槽为多层三角锥形、半圆形或球形。本申请技术方案通过在LED芯片周围形成一圈有利于出光的多层三角锥形、半圆形或球形，这样LED芯片有源区发出的光就会以更大的概率出射，进而可提升光取出效率。

Description

一种提升LED芯片光取出效率的芯片制造方法及LED芯片 技术领域
本发明涉及LED技术领域，尤其涉及一种提升LED芯片光取出效率的芯片制造方法及LED芯片。
背景技术
发光二极管(Light-Emitting Diode，LED)是一种常用发光器件。随着半导体照明的不断深入发展，LED以其节能、环保、寿命长、低功耗等优势，广泛应用于各种指示、显示、装饰、背光源、普通照明等领域。半导体照明产品中的核心组成部分是LED芯片，其研究与生产技术有了飞速的发展，芯片亮度和可靠性不断提高。在LED芯片的研发和生产过程中，器件外量子效率的提高一直是核心内容，因此，光提取效率的提高显得至关重要。
LED的光提取效率是指：在LED内部，由电能激发产生的光子没有全部发射出去，只有部分光子才能通过折射离开器件，其他光子在内部不断反射，最终被吸收。在传统LED器件中，由于衬底吸收、电极阻挡、出光面的全反射等因素的存在，光提取效率通常不到10％。
目前为了提高LED的光提取效率，LED芯片的结构通常包括依次设置的蓝宝石衬底、N-GaN层、有源区和P-GaN层，通过刻蚀LED芯片形成台阶，将N-GaN层裸露出来，在N-GaN层上形成N型电极层，在P-GaN层上形成电流阻挡层，在电流阻挡层上形成透明导电层，在透明导电层上设置一层绝缘保护层，在绝缘保护层上形成P型电极层。但该结构由于蚀刻台阶处的内外折射率相差过大，GaN的折射率在2.3左右，而空气的折射率为1，因此台阶面处的侧向光将在GaN的界面处形成全反射，而使侧向光无法射出，导致侧向光的取出效率偏低。
发明内容
本发明提供一种提升LED芯片光取出效率的芯片制造方法及LED芯片，以解决在LED芯片制作过程中，由于折射率差异较大，造成LED芯片光取出效率低的问题。
本申请实施例第一方面提供了一种提升LED芯片光取出效率的芯片制造方法，方法包括：
在蓝宝石衬底上沉积可光刻的氧化物层；
通过对氧化物层光刻和腐蚀，得到图形化蓝宝石衬底；
图形化蓝宝石衬底通过金属有机化合物化学气相沉积法，生长出LED芯片外延片；
通过电感耦合等离子体法在LED芯片外延片上刻蚀出来N型氮化镓，使N型氮化镓暴露在外；
蓝宝石衬底通过等离子增强化学气相沉积法，沉积氧化硅，氧化硅覆盖在LED芯片外延片整个表面；
对LED芯片外延片采用激光切割或光刻加刻蚀的方式后，形成隔离槽；
采用磷酸、硫酸和氢氟酸溶液对隔离槽一次或多次腐蚀，形成预设形状。
进一步地，在采用磷酸、硫酸和氢氟酸溶液对隔离槽一次或多次腐蚀，形成预设形状之后还包括：
对氧化硅直接光刻和腐蚀，形成电流阻挡层；
在LED芯片外延片的P-GaN上制作一层透明导电层；
在透明导电层上制作正负金属电极，得到P型电极层；
在P型电极层上整面镀膜，得到绝缘保护层；
在绝缘保护层上进行特定通孔刻蚀，用于焊盘电极和绝缘保护层下方扩展电极连接。
进一步地，氧化物层的厚度为0.5μm至5μm。
进一步地，氧化物层的材料包括单层氧化硅、单层氧化钛或氧化铌中的一种、两种或三种结合。
进一步地，透明导电层的材料为ITO、GZO、AZO或NiAu，厚度为10nm至300nm。
进一步地，金属电极的材质包括铬、钛、铝、镍、铂金和金，金属电极的厚度在1μm至5μm之间。
进一步地，绝缘保护层的材料为SiO 2或Si 3N 4。
进一步地，图形化蓝宝石衬底为周期性排布，图形周期为2μm至8μm。
进一步地，预设形状为多层三角锥形、半圆形或球形。
进一步地，腐蚀包括采用干法或湿法。
本申请实施例第二方面提供一种LED芯片，包括：图形化蓝宝石衬底，图形化蓝宝石衬底包括蓝宝石衬底和设置在蓝宝石衬底上的氧化物层；LED芯片外延片，设置在图形化蓝宝石衬底上，且LED芯片外延片的外周设有隔离槽；其中，LED芯片外延片包括N型氮化镓层和P型氮化镓层，N型氮化镓层设置在图形化蓝宝石衬底上，P型氮化镓层设置在N型氮化镓层上，隔离槽为多层三角锥形、半圆形或球形。
进一步地，LED芯片还包括：电流阻挡层，设置在P型氮化镓层上；透明导电层，设置在P型氮化镓层上，覆盖电流阻挡层；且透明层上设有正负金属电极；绝缘保护层，设置在N型氮化镓层上，且覆盖透明导电层和P型氮化镓层；绝缘保护层设有刻蚀通孔，刻蚀通孔用于连接焊盘电极和绝缘保护层下方扩展电极。
进一步地，刻蚀通孔包括第一通孔和第二通孔；第一通孔位于透明导电层上方，第二通孔位于N型氮化镓上方；LED芯片还包括：P型电极层，设置在第一通孔内；N型电极层，设置在第二通孔内。
进一步地，氧化物层的厚度为0.5μm至5μm。
进一步地，透明导电层的厚度为10nm至300nm。
进一步地，金属电极的厚度为1μm至5μm。
进一步地，图形化蓝宝石衬底为周期性排布，图形周期为2μm至8μm。由上述技术方案可知，本申请提供一种提升LED芯片光取出效率的芯片制造方法及LED芯片，方法包括：在蓝宝石衬底上通过等离子体增强化学气相沉积法沉积可光刻的氧化物层。通过对氧化物层光刻和腐蚀，得到图形化蓝宝石衬底。图形化蓝宝石衬底通过金属有机化合物化学气相沉积法，生长出LED芯片外延片。通过电感耦合等离子体法在LED芯片外延片上刻蚀出来N型氮化镓，使N型氮化镓暴露在外。蓝宝石衬底通过等离子增强化学气相沉积法， 沉积氧化硅，氧化硅覆盖在LED芯片外延片整个表面。对LED芯片外延片采用激光切割或光刻加刻蚀的方式后，形成隔离槽。采用磷酸、硫酸和氢氟酸溶液对隔离槽一次或多次腐蚀，形成预设形状。LED芯片包括：图形化蓝宝石衬底，图形化蓝宝石衬底包括蓝宝石衬底和设置在蓝宝石衬底上的氧化物层；LED芯片外延片，设置在图形化蓝宝石衬底上，且LED芯片外延片的外周设有隔离槽；其中，LED芯片外延片包括N型氮化镓层和P型氮化镓层，N型氮化镓层设置在图形化蓝宝石衬底上，P型氮化镓层设置在N型氮化镓层上，隔离槽为多层三角锥形、半圆形或球形。本申请技术方案通过在LED芯片周围形成一圈有利于出光的多层三角锥形、半圆形或球形，这样LED芯片有源区发出的光就会以更大的概率出射，进而可提升光取出效率。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种提升LED芯片光取出效率的芯片制造方法的流程示意图；
图2为本申请实施例提供的一种常规LED芯片横截面结构示意图；
图3为本申请实施例提供的LED芯片横截面结构示意图；
图4为本申请实施例提供的LED芯片横截面结构的电子显微镜示意图；
图5为本申请实施例提供的LED芯片横截面结构倾斜45°角的电子显微镜示意图；
其中：蓝宝石衬底101，氧化物层102，N型氮化镓201，P型氮化镓202，电流阻挡层301，透明导电层302，N型电极层401，P型电极层402，绝缘保护层501。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。以下结合附图，详细说明本申请实施例提供的技术方案。
为便于理解本申请实施例的技术方案，在对本申请实施例的具体实施方式进行阐述说明之前，首先对本申请实施例所属技术领域的一些技术术语进行简单解释说明。
图形化蓝宝石衬底：也就是在蓝宝石衬底上生长干法刻蚀用掩膜，用标准的光刻工艺将掩膜刻出图形，利用电感耦合等离子体ICP(Inductive Coupled Plasma)刻蚀技术刻蚀蓝宝石，并去掉掩膜。再在其上生长GaN材料，使GaN材料的纵向外延变为横向外延。一方面可以有效减少GaN外延材料的位错密度，从而减小有源区的非辐射复合，减小反向漏电流，提高LED的寿命；另一方面有源区发出的光，经GaN和蓝宝石衬底界面多次散射，改变了全反射光的出射角，增加了倒装LED的光从蓝宝石衬底出射的几率，从而提高了光的提取效率。综合这两方面的原因，使在图形化蓝宝石衬底上生长的LED的出射光亮度比传统的LED大大提高，同时反向漏电流减小，LED的寿命也得到了延长。
GaN(氮化镓)：一种无机物，是氮和镓的化合物，常用在发光二极管中。氮化镓硬度很高，能隙很宽，可以用在高功率、高速的光电元件中。例如氮化镓可以用在紫光的激光 二极管，可以在不使用非线性半导体泵浦固体激光器的条件下，产生激光。
PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)，是指借助微波或射频等使含有薄膜成分原子的气体分离，在局部形成等离子体，而等离子体化学活性很强，很容易发生反应，在基片上沉积出所期望的薄膜。
干法刻蚀：是用等离子体进行薄膜刻蚀的技术。当气体以等离子体形式存在时，它具备两个特点：一方面等离子体中的这些气体化学活性比常态下时要强很多，根据被刻蚀材料的不同，选择合适的气体，就可以更快地与材料进行反应，实现刻蚀去除的目的；另一方面，还可以利用电场对等离子体进行引导和加速，使其具备一定能量，当其轰击被刻蚀物的表面时，会将被刻蚀物材料的原子击出，从而达到利用物理上的能量转移来实现刻蚀的目的。
对本申请实施例所属技术领域的一些技术术语进行简单解释说明后，下面对本申请实施例提供的一种提升LED芯片光取出效率的芯片制造方法进行详细描述。
传统的LED芯片结构由于蚀刻台阶处的内外折射率相差过大，GaN的折射率在2.3左右，而空气的折射率为1，因此台阶面处的侧向光将在GaN的界面处形成全反射，而使侧向光无法射出，导致LED芯片的光取出效率偏低。本申请为解决在LED芯片制作过程中，由于折射率差异较大，造成LED芯片光取出效率低的问题。本申请提供一种提升LED芯片光取出效率的芯片制造方法及一种LED芯片。
参见图1，为本申请实施例提供的一种提升LED芯片光取出效率的芯片制造方法的流程示意图。
由图1所示，本申请实施例提供的一种提升LED芯片光取出效率的芯片制造方法包括：
S1：在蓝宝石衬底上沉积可光刻的氧化物层。
本申请在蓝宝石衬底101上通过PECVD或者蒸镀的方法沉积可光刻的氧化物层，采用PECVD方法沉积可光刻的氧化物层，氧化物层的总厚度为0.5μm至5μm。氧化物层包括单层氧化硅、单层氧化钛或氧化铌中的一种、两种或三种结合。具体的，通过PECVD或蒸镀方法沉积可光刻的氧化物层，可能是三种材料中的一种，也有可能是两种材料的结合，亦或者可能三种材料都有。
S2：通过对氧化物层光刻和腐蚀，得到图形化蓝宝石衬底。
然后通过对氧化物层光刻和腐蚀，进而得到图形化蓝宝石衬底，图形化蓝宝石衬底形成周期性排布，图形周期为2μm至8μm。
S3：图形化蓝宝石衬底通过金属有机化合物化学气相沉积法，生长出LED芯片外延片。
通过金属有机化合物化学气相沉淀方法或者金属有机化合物气相外延方法，在图形化蓝宝石衬底上成长一层结构复杂的GaN薄膜，这层薄膜就是外延片。
S4：通过电感耦合等离子体法在LED芯片外延片上刻蚀出来N型氮化镓，使N型氮化镓暴露在外。
采用电感耦合等离子体ICP方法在LED芯片外延片包括N型氮化镓、量子阱和P型氮化镓，将部分P型氮化镓和量子阱刻蚀掉，使N型氮化镓暴露在外，这样，可以将暴露的N型氮化镓留作金属负电极制作使用。
S5：蓝宝石衬底通过等离子增强化学气相沉积法，沉积氧化硅，氧化硅覆盖在LED芯片外延片整个表面。
通过等离子增强化学气相沉积法，沉积100nm至5000nm的氧化硅，氧化硅主要用于保护LED芯片外延片，防止LED芯片外延片被腐蚀。氧化硅覆盖在LED芯片外延片整个表面也就是覆盖在薄膜晶圆的整个表面。
S6：对LED芯片外延片采用激光切割或光刻加刻蚀的方式后，形成隔离槽。
对LED芯片外延片采用激光切割后，会形成一圈隔离槽，也可以选用光刻加刻蚀的方式。大多数都是采用激光切割的方式，切割后会形成一圈细细的沟槽也就是隔离槽。
S7：采用磷酸、硫酸和氢氟酸溶液对隔离槽一次或多次腐蚀，形成预设形状。
步骤S6激光切割后会隔离槽上会产生一些碳化物，通过采用磷酸、硫酸和氢氟酸溶液中的一种溶液或其三种溶液的混合溶液对隔离槽的碳化物一次或多次腐蚀，会形成多种形状，可能是多层三角锥形、半圆形或球形。
参见图2，为本申请实施例提供的一种常规LED芯片横截面结构示意图。
由图2所示，常规LED芯片的结构通常包括依次设置的蓝宝石衬底101、N-GaN层201、有源区和P-GaN层202，通过刻蚀LED芯片形成台阶，将N-GaN层201裸露出来，在N-GaN层201上形成N型电极层401，在P-GaN层202上形成电流阻挡层301，在电流阻挡层301上形成透明导电层302，在透明导电层302上设置一层绝缘保护层501，在绝缘保护层501上形成P型电极层402。由图2可以看出，常规的LED芯片结构由于蚀刻台阶处的内外折射率相差过大，GaN的折射率在2.3左右，而空气的折射率为1，因此台阶面处的侧向光将在GaN的界面处形成全反射，而使侧向光无法射出，导致侧向光的取出效率偏低。
参见图3，为本申请实施例提供的LED芯片横截面结构示意图。
由图3所示，本申请LED芯片结构包括蓝宝石衬底101。本申请在蓝宝石衬底101上通过PECVD或蒸镀方法沉积可光刻的氧化物层102，采用PECVD方法沉积可光刻的氧化物层102，氧化物层102的总厚度为0.5μm至5μm。氧化物层102的材料包括单层氧化硅、单层氧化钛或氧化铌中的一种、两种或三种结合。通过PECVD或蒸镀方法沉积氧化物层102，可能是三种材料中的一种，也有可能是两种材料的结合，亦或者可能三种材料都有。PECVD的优势在于能够在保持或提高沉积速率的同时降低工艺温度。然后通过对氧化物层102光刻和腐蚀，进而得到图形化蓝宝石衬底。图形化蓝宝石衬底形成周期性排布，图形周期为2μm至8μm。腐蚀主要采用干法或者湿法，所谓干法刻蚀是把硅片表面暴露于空气中产生的等离子体，等离子体通过光刻胶中开出的窗口，与硅片发生物理或化学反应，从而去掉暴露的表明材料。湿法腐蚀是以液体化学试剂以化学方式去除硅片表面的材料。
形成图形化蓝宝石衬底的目的是一方面可以有效减少GaN外延材料的位错密度，从而减小有源区的非辐射复合，减小反向漏电流，提高LED的寿命；另一方面有源区发出的光，经GaN和蓝宝石衬底界面多次散射，改变了全反射光的出射角，增加了光从蓝宝石衬底出射的几率，从而提高了光的提取效率。综合这两方面的原因，使在图形化蓝宝石衬底上生长的LED的出射光亮度比传统的LED大大提高，同时反向漏电流减小，LED的寿命也得到了延长。
得到图形化蓝宝石衬底之后，再通过MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉淀)或MOVPE(Metal-organic Vapor Phase Epitaxy，金属有机化合物气相外延)方法，生长出LED芯片外延片。
LED芯片外延片指的是在晶体结构匹配的单晶材料上生长出来的半导体薄膜，在图形 化蓝宝石衬底上成长一层结构复杂的GaN薄膜，GaN薄膜包括：N-GaN、量子阱、和P-GaN，这层薄膜就叫做外延片。
MOCVD技术在薄膜晶体生长中具有独特优势：能在较低的温度下制备高纯度的薄膜材料，减少了材料的热缺陷和本征杂质含量；能达到原子级精度控制薄膜的厚度；采用质量流量计易于控制化合物的组分和掺杂量；通过气源的快速无死区切换，可灵活改变反应物的种类或比例，达到薄膜生长界面成份突变。实现界面陡峭；能够实现大面积、均匀、高重复性地完成薄膜生长。
采用电感耦合等离子体ICP方法在LED芯片外延片上刻蚀出来N型氮化镓201，将部分P型氮化镓202和量子阱刻蚀掉，使N型氮化镓201暴露在外，这样，可以将暴露的N型氮化镓201留作金属负电极制作使用。
电感耦合等离子体ICP是以电感耦合等离子为激发光源的一类光谱分析方法，ICP方法具有分析速度快、时间分布稳定、线性范围宽，能够一次同时读出多种被测元素的特征光谱，同时对多种元素进行定量和定性分析。分析灵敏度高，分析准确度、精密度较高和测定范围广。可以测定几乎所有紫外和可见光区的谱线，被测元素的范围大，一次可以测定几十个元素。
蓝宝石衬底101通过PECVD或蒸镀方法，沉积100nm至5000nm的氧化硅，氧化硅主要用于保护LED芯片外延片，氧化硅具有熔点高、抗磨耐腐蚀、保护能力强、对光的散射吸收小灯优良性能。
对LED芯片外延片采用激光切割或光刻加刻蚀的方式后，形成一圈隔离槽；激光切割具有切割速度快、切割效率高和切割质量好的特点，采用激光切割能够获得较好的切割质量。
参见图4和图5，为本申请实施例提供的LED芯片横截面结构的电子显微镜示意图和LED芯片横截面结构倾斜45°角的电子显微镜示意图。
通过采用磷酸、硫酸和氢氟酸溶液中的一种溶液或其三种溶液的混合溶液对隔离槽一次或多次腐蚀，形成预设形状。如图4和5所示可知，根据腐蚀的次数和程度不同，形成的形状是不同的，会先形成平台结构，然后在平台结构上出现双层的三角锥形、半圆形或者球形。腐蚀后所形成的形状还和氧化物层102的材料有关，不同的氧化物层102材料，形成的形状也是不同，氧化物层102的材料越多，形成的三角锥形层数越多。由于在蓝宝石衬底101上通过PECVD或蒸镀方法沉积氧化物层102，沉积的氧化物层102可能是复合材料，也可能是单层氧化硅、单层氧化钛或氧化铌，因此经过腐蚀后所形成的预设形状不同。
经过腐蚀后会形成三角锥形、半圆形或者球形，本申请实施例中的光在通过这些预设形状时会发生多次折射，使得部分原本无法折射出去的光线，能够从LED芯片经过不断的折射，将其射出，进而提升光取出效率。
在形成预设形状之后还包括：通过对氧化硅直接光刻和腐蚀，形成电流阻挡层301，还可以将氧化硅去掉之后重新通过PECVD方法沉积氧化硅。在LED外延片的P-GaN 40 2上制作一层透明导电层302；在透明导电层302上制作正负金属电极，得到P型电极层；在P型电极层上整面镀膜，得到绝缘保护层501；在绝缘保护层501上进行特定通孔刻蚀，用于焊盘电极和绝缘保护层501下方扩展电极连接。
在一些实施例中，正负金属电极可以通过使用电子束蒸发方式形成，金属电极的材质包括铬Cr、钛Ti、铝Al、镍Ni、铂金Pt和金Au，金属电极的厚度在1μm至5μm之间。
在一些实施例中，透明导电层302的材料选为氧化铟锡ITO、氧化锌镓GZO、AZO或NiAu，厚度为10nm至300nm。大多数情况透明导电层302选用ITO材料，氧化铟锡ITO是透明层，是一种混合物，透明茶色薄膜或黄偏灰色块状，主要用来做P型氮化镓的欧姆接触和电流传导扩散，还可以用于液晶显示器、平板显示器、等离子显示器、触摸屏、电子纸、有机发光二极管、太阳能电池、抗静电镀膜、EMI屏蔽的透明传导镀、各种光学镀膜等。在本申请实施例中，氧化铟锡ITO厚度可以在10nm-300nm之间。AZO是铝掺杂的氧化锌透明导电玻璃的简称。
在一些实施例中，绝缘保护层501的材料为SiO 2或Si 3N 4。绝缘保护层501对侧边缘和整面进行绝缘保护。氮化硅Si 3N 4具有高硬度、高强度、耐高温、耐腐蚀等特性。
由上述技术方案可知，本申请提供一种提升LED芯片光取出效率的芯片制造方法，方法包括：在蓝宝石衬底上通过等离子体增强化学气相沉积法沉积氧化物层。通过对氧化物层光刻和腐蚀，得到图形化蓝宝石衬底。图形化蓝宝石衬底通过金属有机化合物化学气相沉积法，生长出LED芯片外延片。通过电感耦合等离子体法在LED芯片外延片上刻蚀出来N型氮化镓，使N型氮化镓暴露在外。蓝宝石衬底通过等离子增强化学气相沉积法，沉积氧化硅，氧化硅覆盖在LED芯片外延片整个表面。对LED芯片外延片采用激光切割或光刻加刻蚀的方式后，形成隔离槽。采用磷酸、硫酸和氢氟酸溶液对隔离槽一次或多次腐蚀，形成预设形状。本申请技术方案通过在LED芯片周围形成一圈有利于出光的多层三角锥形、半圆形或球形，这样LED芯片有源区发出的光就会以更大的概率出射，进而可提升光取出效率。
本申请实施例还提供一种LED芯片，LED芯片包括图形化蓝宝石衬底，图形化蓝宝石衬底包括蓝宝石衬底101和设置在蓝宝石衬底上的氧化物层102；LED芯片外延片，设置在图形化蓝宝石衬底上，且LED芯片外延片的外周设有隔离槽；其中，LED芯片外延片包括N型氮化镓层201和P型氮化镓层202，N型氮化镓层201设置在图形化蓝宝石衬底上，P型氮化镓层202设置在所N型氮化镓层201上，隔离槽为多层三角锥形、半圆形或球形。
在一些实施例中，LED芯片还包括：电流阻挡层301，设置在P型氮化镓层402上；透明导电层302，设置在P型氮化镓层402上，覆盖电流阻挡层301；且透明导电层302上设有正负金属电极；绝缘保护层501，设置在N型氮化镓层201上，且覆盖透明导电层302和P型氮化镓层402；绝缘保护层501设有刻蚀通孔，刻蚀通孔用于连接焊盘电极和绝缘保护层下方扩展电极。
在一些实施例中，刻蚀通孔包括第一通孔和第二通孔；第一通孔位于透明导电层上方，第二通孔位于N型氮化镓201上方；LED芯片还包括：P型电极层402，设置在第一通孔内；N型电极层401，设置在第二通孔内。
在一些实施例中，本申请在蓝宝石衬底101上通过PECVD或蒸镀方法沉积可光刻的氧化物层102，采用PECVD方法沉积可光刻的氧化物层102，氧化物层102的总厚度为0.5μm至5μm。氧化物层102的材料包括单层氧化硅、单层氧化钛或氧化铌中的一种、两种或三种结合。通过PECVD或蒸镀方法沉积氧化物层102，可能是三种材料中的一种，也有 可能是两种材料的结合，亦或者可能三种材料都有。PECVD的优势在于能够在保持或提高沉积速率的同时降低工艺温度。然后通过对氧化物层102光刻和腐蚀，进而得到图形化蓝宝石衬底。
在一些实施例中，透明导电层302的厚度为10nm至300nm。透明导电层302的材料选为氧化铟锡ITO、氧化锌镓GZO、AZO或NiAu，厚度为10nm至300nm。大多数情况透明导电层302选用ITO材料，氧化铟锡ITO是透明层，是一种混合物，透明茶色薄膜或黄偏灰色块状，主要用来做P型氮化镓的欧姆接触和电流传导扩散，还可以用于液晶显示器、平板显示器、等离子显示器、触摸屏、电子纸、有机发光二极管、太阳能电池、抗静电镀膜、EMI屏蔽的透明传导镀、各种光学镀膜等。在本申请实施例中，氧化铟锡ITO厚度可以在10nm-300nm之间。AZO是铝掺杂的氧化锌透明导电玻璃的简称。
在一些实施例中，正负金属电极可以通过使用电子束蒸发方式形成，金属电极的材质包括铬Cr、钛Ti、铝Al、镍Ni、铂金Pt和金Au，金属电极的厚度在1μm至5μm之间。
在一些实施例中，本申请LED芯片结构包括蓝宝石衬底101。本申请在蓝宝石衬底101上通过PECVD或蒸镀方法沉积可光刻的氧化物层102，采用PECVD方法沉积可光刻的氧化物层102，氧化物层102的总厚度为0.5μm至5μm。氧化物层102的材料包括单层氧化硅、单层氧化钛或氧化铌中的一种、两种或三种结合。通过PECVD或蒸镀方法沉积氧化物层102，可能是三种材料中的一种，也有可能是两种材料的结合，亦或者可能三种材料都有。PECVD的优势在于能够在保持或提高沉积速率的同时降低工艺温度。然后通过对氧化物层102光刻和腐蚀，进而得到图形化蓝宝石衬底。图形化蓝宝石衬底形成周期性排布，图形周期为2μm至8μm。腐蚀主要采用干法或者湿法，所谓干法刻蚀是把硅片表面暴露于空气中产生的等离子体，等离子体通过光刻胶中开出的窗口，与硅片发生物理或化学反应，从而去掉暴露的表明材料。湿法腐蚀是以液体化学试剂以化学方式去除硅片表面的材料。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本发明的其它实施方案。本申请旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本发明的一般性原理并包括本发明未公开的本技术领域中的公知常识或惯用技术手段。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。

Claims (17)

  1. 一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述方法包括：
    在蓝宝石衬底上沉积可光刻的氧化物层；
    通过对所述氧化物层光刻和腐蚀，得到图形化蓝宝石衬底；
    所述图形化蓝宝石衬底通过金属有机化合物化学气相沉积法，生长出LED芯片外延片；
    通过电感耦合等离子体法在所述LED芯片外延片上刻蚀出来N型氮化镓，使所述N型氮化镓暴露在外；
    所述蓝宝石衬底通过等离子体增强化学气相沉积法，沉积氧化硅，所述氧化硅覆盖在所述LED芯片外延片整个表面；
    对所述LED芯片外延片采用激光切割或光刻加刻蚀的方式后，形成隔离槽；
    采用磷酸、硫酸和氢氟酸溶液对所述隔离槽一次或多次腐蚀，形成预设形状。
  2. 根据权利要求1所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，采用磷酸、硫酸和氢氟酸溶液对所述隔离槽一次或多次腐蚀，形成预设形状之后还包括：
    对所述氧化硅直接光刻和腐蚀，形成电流阻挡层；
    在所述LED芯片外延片的P-GaN上制作一层透明导电层；
    在所述透明导电层上制作正负金属电极，得到P型电极层；
    在所述P型电极层上整面镀膜，得到绝缘保护层；
    在所述绝缘保护层上进行特定通孔刻蚀，用于焊盘电极和所述绝缘保护层下方扩展电极连接。
  3. 根据权利要求1所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述氧化物层的厚度为0.5μm至5μm。
  4. 根据权利要求1所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述氧化物层包括单层氧化硅、单层氧化钛或氧化铌中的一种、两种或三种结合。
  5. 根据权利要求2所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述透明导电层的材料为ITO、GZO、AZO或NiAu，厚度为10nm至300nm。
  6. 根据权利要求2所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述金属电极的材质包括铬、钛、铝、镍、铂金和金，所述金属电极的厚度为1μm至5μm。
  7. 根据权利要求2所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述绝缘保护层的材料为SiO 2或Si 3N 4。
  8. 根据权利要求1所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述图形化蓝宝石衬底为周期性排布，图形周期为2μm至8μm。
  9. 根据权利要求1所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述预设形状为多层三角锥形、半圆形或球形。
  10. 根据权利要求1所述的一种提升LED芯片光取出效率的芯片制造方法，其特征在于，所述腐蚀包括采用干法或湿法。
  11. 一种LED芯片，其特征在于，所述芯片包括：
    图形化蓝宝石衬底，所述图形化蓝宝石衬底包括蓝宝石衬底和设置在所述蓝宝石衬底上的氧化物层；
    LED芯片外延片，设置在所述图形化蓝宝石衬底上，且所述LED芯片外延片的外周设有隔离槽；
    其中，所述LED芯片外延片包括N型氮化镓层和P型氮化镓层，所述N型氮化镓层设置在所述图形化蓝宝石衬底上，所述P型氮化镓层设置在所述N型氮化镓层上，所述隔离槽为多层三角锥形、半圆形或球形。
  12. 根据权利要求11所述的芯片，其特征在于，还包括：
    电流阻挡层，设置在所述P型氮化镓层上；
    透明导电层，设置在所述P型氮化镓层上，覆盖所述电流阻挡层；且所述透明导电层上设有正负金属电极；
    绝缘保护层，设置在所述N型氮化镓层上，且覆盖所述透明导电层和所述P型氮化镓层；所述绝缘保护层设有刻蚀通孔，所述刻蚀通孔用于连接焊盘电极和所述绝缘保护层下方扩展电极。
  13. 根据权利要求12所述的芯片，其特征在于，
    所述刻蚀通孔包括第一通孔和第二通孔；所述第一通孔位于所述透明导电层上方，所述第二通孔位于所述N型氮化镓上方；
    所述LED芯片还包括：P型电极层，设置在所述第一通孔内；
    N型电极层，设置在所述第二通孔内。
  14. 根据权利要求11所述的芯片，其特征在于，还包括：
    所述氧化物层的厚度为0.5μm至5μm。
  15. 根据权利要求12所述的芯片，其特征在于，还包括：
    所述透明导电层的厚度为10nm至300nm。
  16. 根据权利要求12所述的芯片，其特征在于，还包括：
    所述金属电极的厚度为1μm至5μm。
  17. 根据权利要求11所述的芯片，其特征在于，还包括：
    所述图形化蓝宝石衬底为周期性排布，图形周期为2μm至8μm。
PCT/CN2022/117778 2022-02-16 2022-09-08 一种提升led芯片光取出效率的芯片制造方法及led芯片 WO2023155422A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740692A (zh) * 2009-12-24 2010-06-16 上海蓝光科技有限公司 提高led芯片亮度的方法
US20200243714A1 (en) * 2019-01-25 2020-07-30 Epistar Corporation Light-emitting device and manufacturing method thereof
CN112236873A (zh) * 2020-03-13 2021-01-15 厦门三安光电有限公司 一种半导体发光元件及其制作方法
CN114464714A (zh) * 2022-02-16 2022-05-10 聚灿光电科技（宿迁）有限公司 一种提升led芯片光取出效率的芯片制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740692A (zh) * 2009-12-24 2010-06-16 上海蓝光科技有限公司 提高led芯片亮度的方法
US20200243714A1 (en) * 2019-01-25 2020-07-30 Epistar Corporation Light-emitting device and manufacturing method thereof
CN112236873A (zh) * 2020-03-13 2021-01-15 厦门三安光电有限公司 一种半导体发光元件及其制作方法
CN114464714A (zh) * 2022-02-16 2022-05-10 聚灿光电科技（宿迁）有限公司 一种提升led芯片光取出效率的芯片制造方法

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