WO2023155314A1 - 串扰分析方法和装置 - Google Patents

串扰分析方法和装置 Download PDF

Info

Publication number
WO2023155314A1
WO2023155314A1 PCT/CN2022/093460 CN2022093460W WO2023155314A1 WO 2023155314 A1 WO2023155314 A1 WO 2023155314A1 CN 2022093460 W CN2022093460 W CN 2022093460W WO 2023155314 A1 WO2023155314 A1 WO 2023155314A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
risk
nodes
circuit
connection relationship
Prior art date
Application number
PCT/CN2022/093460
Other languages
English (en)
French (fr)
Inventor
黄克琴
范玉鹏
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2023155314A1 publication Critical patent/WO2023155314A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/373—Design optimisation

Definitions

  • This application relates to but is not limited to a crosstalk analysis method and device.
  • the chip is composed of circuits, and there is crosstalk between the electrical signals between adjacent lines in the circuit. If the burrs generated by the crosstalk are too large, the circuit may fail, and the chip may be scrapped. In order to reduce the scrap rate of the chip, crosstalk analysis can be performed on the chip before tape-out of the chip, so as to determine a node in the circuit of the chip that may cause circuit failure, and the node is a connection in the circuit.
  • crosstalk analysis is usually performed by designers based on experience. Specifically, the designer observes and analyzes the design layout of the circuit to determine nodes that may cause circuit failure, that is, nodes that have crosstalk, based on experience.
  • An embodiment of the present disclosure provides a crosstalk analysis method, the method comprising:
  • connection relationship including at least one node connecting the units, one node connecting at least two units;
  • the determining the connection relationship of each unit in the target circuit includes:
  • connection relationship of each unit in the target circuit is determined from the circuit netlist.
  • each unit includes at least one of the following: a circuit device and a module, and the module includes at least one interconnected circuit device.
  • the method before determining at least one high-risk node from the at least one node according to the standard parasitic format file of the at least one node, the method further includes:
  • the standard parasitic format file includes equivalent capacitance information between the nodes, and the equivalent capacitance information includes: a total equivalent coupling capacitance value between the node and related nodes of the node , the sub-equivalent coupling capacitance value between the node and each of the related nodes;
  • the determining at least one high-risk node from the at least one node according to the standard parasitic format file of the at least one node includes:
  • Determining at least one node whose ratio meets a preset condition as a high-risk node includes at least one of the following: the ratio is greater than or equal to a preset threshold, and the nodes ranked in the front position in descending order according to the ratio node.
  • the relevant node includes an adjacent node separated from the node by one cell, and a ground node.
  • the determining the simulation model of each high-risk node according to the connection relationship of the various units includes:
  • a simulation model of the high-risk node is determined according to the target connection relationship.
  • the determining the simulation model of the high-risk node according to the target connection relationship includes:
  • a simulation model of the high-risk node is generated according to the simulation capacitance and the driving circuit.
  • the simulation model further includes: a load circuit of the high-risk node, and the generation of the simulation model of the high-risk node according to the simulation capacitance and the driving circuit includes:
  • a simulation model of the high-risk node is generated according to the load circuit, the simulation capacitor and the driving circuit.
  • the simulating the simulation model of each of the high-risk nodes to determine whether there is a crosstalk node in the at least one high-risk node includes:
  • the high-risk node is determined as a node with crosstalk.
  • the target circuit is a circuit of a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • An embodiment of the present disclosure also provides a crosstalk analysis device, the device comprising:
  • a connection relationship determining module configured to determine the connection relationship of each unit in the target circuit, the connection relationship includes at least one node connecting the units, and one node connects at least two units;
  • a high-risk node determination module configured to determine at least one high-risk node from the at least one node according to the standard parasitic format file of the at least one node;
  • a simulation model determination module configured to determine a simulation model of each of the high-risk nodes according to the connection relationship of the various units
  • the simulation module is configured to simulate the simulation model of each of the high-risk nodes, so as to determine whether there is a crosstalk node in the at least one high-risk node.
  • connection relationship determining module is also used for:
  • connection relationship of each unit in the target circuit is determined from the circuit netlist.
  • the unit includes at least one of the following: a circuit device and a module, and the module includes at least one interconnected circuit device.
  • the device also includes:
  • a parasitic file obtaining module configured to obtain the target by simulating the target circuit before determining at least one high-risk node from the at least one node according to the standard parasitic format file of the at least one node Standard parasitic format files for each node in the circuit.
  • the standard parasitic format file includes equivalent capacitance information between the nodes, and the equivalent capacitance information includes: a total equivalent coupling capacitance value between the node and related nodes of the node , the sub-equivalent coupling capacitance value between the node and each of the related nodes;
  • the high-risk node determination module is also used for:
  • Determining at least one node whose ratio meets a preset condition as a high-risk node includes at least one of the following: the ratio is greater than or equal to a preset threshold, and the nodes ranked in the front position in descending order according to the ratio node.
  • the relevant node includes an adjacent node separated from the node by one cell, and a ground node.
  • simulation model determination module is also used for:
  • the target connection relationship between the high-risk node and each unit is obtained from the connection relationship of each unit of the target circuit.
  • a simulation model of the high-risk node is determined according to the target connection relationship.
  • simulation model determination module is also used for:
  • a simulation model of the high-risk node is generated according to the simulation capacitance and the driving circuit.
  • the simulation model also includes: a load circuit of the high-risk node, and the simulation model determination module is also used for:
  • a simulation model of the high-risk node is generated according to the load circuit, the simulation capacitor and the driving circuit.
  • simulation module is also used for:
  • the high-risk node is determined as a node with crosstalk.
  • the target circuit is a circuit of a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the crosstalk analysis method and device can determine the connection relationship of each unit in the target circuit, the connection relationship includes at least one node connecting the units, and one node connects at least two units; according to the standard parasitic of at least one node format file, determine at least one high-risk node from at least one node; determine the simulation model of each high-risk node according to the connection relationship of each unit; simulate the simulation model of each high-risk node to obtain from at least one high-risk node Identify nodes with crosstalk in .
  • the embodiment of the present disclosure does not require subjective judgment by human beings through this solution, thereby effectively improving crosstalk analysis efficiency.
  • the embodiments of the present disclosure screen out high-risk nodes first, so as to reduce the number of nodes that need to be simulated, and help improve the efficiency of crosstalk analysis.
  • the embodiment of the present disclosure is obtained by simulating the structure and data of the circuit, there is no need for human subjective judgment in the middle, so that the missed detection caused by human judgment error can be reduced, and it is helpful to improve the determination of nodes with crosstalk the accuracy.
  • FIG. 1 is a flow chart of the steps of a crosstalk analysis method provided in an embodiment of the present application
  • Figure 2 and Figure 3 are schematic diagrams of two connection relationships between a resistor and a capacitor provided by the embodiment of the present application;
  • Figure 4 and Figure 5 are schematic diagrams of the connection relationship of each unit in the circuit netlist provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an SPF file provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a subcircuit corresponding to a simulation model provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a crosstalk analysis device provided in an embodiment of the present application.
  • the prior art is performed by designers based on experience, but the prior art has the problems of low crosstalk analysis efficiency and low accuracy.
  • the inventor finds that one of the reasons for this problem is that the crosstalk analysis in the prior art is performed manually.
  • manual analysis may also result in low accuracy in determining nodes with crosstalk due to human errors.
  • the embodiment of the present application considers simulating the simulation model of the high-risk nodes to determine the nodes with crosstalk among the high-risk nodes.
  • the high-risk nodes here are first screened out through standard parasitic format files, which represent nodes that are likely to have crosstalk. Compared with the subjective determination of nodes with crosstalk, the embodiment of the present application does not require human subjective judgment through this solution, so that crosstalk analysis efficiency can be effectively improved. Further, in the embodiment of the present application, high-risk nodes are screened out first, so as to reduce the number of nodes that need to be simulated, and help to improve the efficiency of crosstalk analysis.
  • FIG. 1 is a flowchart of steps of a crosstalk analysis method provided in an embodiment of the present application. Referring to Figure 1, the above methods include:
  • S101 Determine the connection relationship of each unit in the target circuit, the connection relationship includes at least one node connecting the units, and one node connects at least two units.
  • the target circuit is any circuit that needs to detect crosstalk, which is not limited in this embodiment of the present application.
  • the target circuit may be a dynamic random access memory (DRAM, dynamic random accessing memory) circuit.
  • DRAM dynamic random access memory
  • the unit of the target circuit includes at least one of the following: a circuit device and a module.
  • the circuit device here may include any device constituting a circuit, for example, a capacitor, an inductor, a resistor, a transistor, a power amplifier, and the like.
  • the module here may include at least one interconnected circuit device, for example, a sub-circuit with a certain function formed by capacitors and inductors, and this sub-circuit may be artificially a virtual unit in the target circuit.
  • each circuit is composed of at least one kind of unit connection described above.
  • Each cell may have one or more terminals, and each terminal may be connected to one terminal of another cell through a node.
  • FIG. 2 and FIG. 3 are schematic diagrams of two connection relationships of a resistor and a capacitor provided in the embodiment of the present application. 2 and 3, the resistor has two terminals T1 and T2, and the capacitor has two terminals T3 and T4.
  • the T2 terminal of the resistor can be connected to the T3 terminal of the capacitor through a node N1, and the T1 terminal of the resistor and the T4 terminal of the capacitor are respectively connected to other units, so as to realize the series connection of the resistor and the capacitor.
  • the T1 end of the resistor can be connected to the T3 end of the capacitor through a node N2, the T2 end of the resistor can be connected to the T4 end of the capacitor through a node N3, and N2 and N3 can be connected to other units respectively, so as to realize the resistance and Parallel connection of capacitors.
  • the above connection relationship can be extracted from a file describing the structure of the target circuit.
  • the file describing the structure of the target circuit can be a circuit netlist (netlist). Therefore, the implementation of S101 can be implemented according to the following steps: first, obtain the circuit netlist of the target circuit; then, determine the connection relationship of each unit in the target circuit from the circuit netlist.
  • each record is used to describe the nodes connected to each end of a unit.
  • the order of each end in different records is the same, so that the nodes connected to each end of the unit of this type can be determined according to this order.
  • the number of terminals corresponding to different types of units may be different, and the types of terminals may also be different.
  • a transistor it may include four terminals: a gate node, a source node, a drain node, and a substrate node.
  • a resistor it may include two terminals, and there is no difference between the two terminals.
  • an inverter has an input terminal and an output terminal.
  • connection relationship of different units is essentially the connection relationship between terminals of different units.
  • FIG. 4 and FIG. 5 are schematic diagrams of the connection relationship of each unit in the circuit netlist provided by the embodiment of the present application.
  • the circuit netlist may be generated according to the target circuit after the design of the target circuit is completed.
  • the circuit netlist usually includes the connection relationship of each unit in the target circuit, and may include the connection relationship of various units. It should be noted that the formats of connection relationships corresponding to different types of units are different, and the format is related to the number of terminals of the type of units.
  • FIG. 4 is a schematic diagram of the connection relationship corresponding to each transistor in the circuit netlist provided by the embodiment of the present application.
  • the circuit netlist includes five columns: C1 to C5.
  • column C1 is used to store the identifier of the transistor, and four transistors labeled xmm1 to xmm4 are stored in the circuit netlist in FIG. 4 .
  • Column C2 is used to store the node to which the first terminal T1 of the transistor is connected. It can be seen that the nodes connected to the T1 terminals of xmm1 to xmm4 in FIG. 4 are N01 , N05 , N03 and N11 respectively.
  • Column C3 is used to store the node to which the second terminal T2 of the transistor is connected. It can be seen that the nodes connected to the T2 terminals of xmm1 to xmm4 in FIG. 4 are N02, N03, N08 and N12 respectively.
  • Column C4 is used to store the node to which the third terminal T3 of the transistor is connected. It can be seen that the nodes connected to the T3 terminals of xmm1 to xmm4 in FIG. 4 are N03, N06, N09 and N13 respectively.
  • Column C5 is used to store the node connected to the fourth terminal T4 of the transistor. It can be seen that the nodes connected to the T3 terminals of xmm1 to xmm4 in FIG. 4 are N04, N07, N10 and N03 respectively.
  • each transistor in FIG. 4 corresponds to the same node, it means that the different ends of the two transistors are connected through the node.
  • the T3 terminal of xmm1, the T2 terminal of xmm2, the T1 terminal of xmm3 and the T4 terminal of xmm4 are all connected to the node N03, then it means that the T3 terminal of xmm1, the T2 terminal of xmm2, the T1 terminal of xmm3 and the T4 terminal of xmm4 pass through the node N03 is connected together, thus realizing the connection of xmm1, xmm2, xmm3 and xmm4.
  • FIG. 5 is a schematic diagram of the connection relationship corresponding to each resistor in the circuit netlist provided by the embodiment of the present application.
  • the circuit netlist includes three columns: C1 to C3.
  • the C1 column is used to store the identifiers of the resistors, and three resistors labeled R1 to R3 are stored in the circuit netlist in FIG. 5 .
  • Column C2 is used to store the node to which the first terminal T1 of each resistor is connected. It can be seen that the nodes connected to the T1 terminals of R1 to R3 in FIG. 5 are N01, N02 and N01 respectively.
  • Column C3 is used to store the node connected to the second terminal T2 of each resistor. It can be seen that the nodes connected to the T2 terminals of R1 to R3 in FIG. 5 are N0, N02 and N04 respectively.
  • each resistor in FIG. 5 corresponds to the same node, then these different ends representing the two resistors are connected through this node.
  • the T1 terminal of R1, the T1 terminal of R2 and the T1 terminal of R3 are all connected to the node N01, it means that the T1 terminal of R1, the T1 terminal of R2 and the T1 terminal of R3 are connected together through the node N01.
  • the T2 terminal of R1 and the T2 terminal of R2 are both connected to the node N02, which means that the T2 terminal of R1 and the T2 terminal of R2 are connected together through the node N02, thereby realizing the parallel connection of R1 and R2.
  • the T2 end of R3 is connected with other units through N03.
  • the embodiment of the present application can generate the circuit netlist of the target circuit after the target circuit is designed, so that each time it is possible to identify whether there is a crosstalk node in the target circuit, it is only necessary to obtain from the circuit netlist The connection relationship is sufficient, and there is no need to re-determine the connection relationship according to the structure of the target circuit. In this way, the time required for determining the connection relationship can be shortened, so as to further improve the analysis efficiency of determining crosstalk.
  • the above-mentioned unit includes at least one of the following: a circuit device and a module, and the module includes at least one interconnected circuit device.
  • the embodiment of the present application can take the modules without internal crosstalk as a whole, so that not only can it be identified whether there is crosstalk between the nodes between the circuit devices, but also whether there is crosstalk between the nodes between these modules, and the relationship between these modules and Whether there is crosstalk at the nodes between other circuit devices.
  • the module can be regarded as a whole, so that there is no need to identify whether there is crosstalk between interconnected circuit devices inside the module.
  • the number of identified nodes can be effectively reduced, which in turn helps to further improve the efficiency of crosstalk analysis.
  • step S102 is executed.
  • S102 Determine at least one high-risk node from at least one node according to the standard parasitic format file of at least one node.
  • the equivalent capacitance information between any two nodes is stored in the standard parasitic format file (SPF, standard parasitic format), and the equivalent capacitance information may include: between each node and each related node of the node Sub-equivalent coupling capacitance value, the total equivalent coupling capacitance value between each node and all related nodes of that node.
  • SPF standard parasitic format file
  • the sub-equivalent coupling capacitance value may include at least one of the following capacitance values: a parasitic capacitance value between the node and a related node, and a capacitance value of a real capacitance connecting the node and the related node.
  • the total equivalent coupling capacitance value may be the sum of the sub-equivalent coupling capacitance values between the node and all related nodes, so that the total equivalent coupling capacitance value may also include the parasitic capacitance value and the capacitance value of the real capacitance .
  • FIG. 6 is a schematic structural diagram of an SPF file provided by an embodiment of the present application.
  • Fig. 6 shows the equivalent capacitance information for the three nodes N01 to N03 in the circuit netlist shown in Fig. 5, the principle of the 13 nodes shown in Fig. 4 is the same, and will not be repeated here repeat.
  • CT1 ct1 is used to represent the total equivalent coupling capacitance ct1 of the total equivalent coupling capacitance CT1 of the node N01 and all related nodes N02 and N03.
  • C1 N01 N02 c1 is used to represent the sub-equivalent coupling capacitance C1 between N01 and its related node N02.
  • the sub-equivalent coupling capacitance value of the effective coupling capacitance C2 is c2.
  • ct1 is the sum of c1 and c2.
  • N02:CT2 ct2 is used to represent the total equivalent coupling capacitance CT2 of the node N02 and all its related nodes N01 and N03.
  • the total equivalent coupling capacitance CT2 is ct2.
  • C3 N02 N01 c3 is used to represent the sub-equivalent coupling capacitance C3 between N02 and its related node N01.
  • the sub-equivalent coupling capacitance value of the effective coupling capacitance C4 is c4.
  • ct2 is the sum of c3 and c4.
  • N03:CT3 ct3 is used to represent the total equivalent coupling capacitance CT3 of the node N03 and all its related nodes N01 and N02.
  • the total equivalent coupling capacitance CT3 is ct3.
  • C5 N03 N01 c5 is used to represent the sub-equivalent coupling capacitance C5 between N03 and its related node N01.
  • the sub-equivalent coupling capacitance value of the effective coupling capacitance C6 is c6.
  • ct3 is the sum of c5 and c6.
  • the above-mentioned standard parasitic format files may be pre-generated.
  • the standard parasitic format file of each node in the target circuit can be obtained by simulating the target circuit. It can be seen that in the simulation process, it is necessary to obtain the sub-equivalent coupling capacitance value between each node in the target circuit and related nodes, so as to determine the total equivalent coupling capacitance of each node according to the sub-equivalent coupling capacitance value Capacitance value, finally, according to the sub-equivalent coupling capacitance value between each node and related nodes, and the total equivalent coupling capacitance value of each node, generate an SPF file with the same or similar format as shown in Figure 6 above.
  • the embodiment of the present application can generate the SPF file through the simulation process, thereby ensuring that the equivalent capacitance information in the SPF file is the current equivalent capacitance information of the target circuit, and the obtained equivalent capacitance information is consistent with the current state of the target circuit, which is helpful Improve the accuracy of equivalent capacitance information, thereby improving the accuracy of judging high-risk nodes.
  • high-risk nodes can be selected from one or more nodes of the target circuit.
  • the high-risk nodes may be nodes whose sub-equivalent coupling capacitance values are greater than a preset threshold, or may be several nodes with higher sub-equivalent coupling capacitance values.
  • high-risk nodes can be selected according to the ratio between each sub-equivalent coupling capacitance value of each node and the total equivalent coupling capacitance value. Specifically, at least one node whose ratio meets a preset condition is determined as a high-risk node, and the preset condition includes at least one of the following: the ratio is greater than or equal to a preset threshold, and the nodes are arranged in the front position in descending order of the ratio.
  • the preset threshold corresponding to the ratio here may be 30%.
  • the preset threshold may be set according to an actual application scenario, which is not limited in the embodiments of the present disclosure.
  • the node can obtain such a ratio for each related node. If at least one of the ratios of the node is greater than or equal to a preset threshold, or is ranked at the top, then it can be determined that the node is a high-risk node.
  • the embodiment of the present application can more accurately describe the probability of each node being a high-risk node through the above ratio, so that the larger the ratio, the greater the probability that the node is a high-risk node.
  • the sub-equivalent coupling capacitance value of some nodes is too small relative to the sub-equivalent coupling capacitance value of other nodes, high-risk nodes can be accurately screened out, and these nodes with too small sub-equivalent coupling capacitance values can be avoided. node.
  • the related nodes of the node may include at least one of the following nodes: an adjacent node separated from the node by one unit, and a ground node.
  • an adjacent node separated from the node by one unit may be identified whether various types of nodes are nodes with crosstalk, avoid missing some nodes, and help to further improve the accuracy of crosstalk analysis on the target circuit.
  • S103 Determine the simulation model of each high-risk node according to the connection relationship of each unit.
  • the simulation model may include units directly or indirectly connected to the high-risk node, the simulation model can be understood as a sub-circuit composed of these units, the connection relationship of these units in the simulation model and the connection relationship of these units in the target circuit unanimous.
  • the target connection relationship between the high-risk node and each unit is obtained from the connection relationship of each unit of the target circuit.
  • the target connection relationship is that among all the connection relationships of each unit of the target circuit, the connection relationship of the high-risk node is included.
  • the target connection relationship can include: xmm1 N01 N02 N03 N04, xmm2 N05 N03 N06 N07, xmm3 N03 N08 N09 N10, xmm4 N11 N12 N13 N03 .
  • the simulation model of the high-risk node is determined according to the target connection relationship.
  • the above-mentioned simulation model may not only include a driving circuit connected to a high-risk node, but may also include a simulation capacitor whose capacitance value is a sub-equivalent coupling capacitance value between the high-risk node and the relevant node . Therefore, when determining the simulation model of the high-risk node according to the target connection relationship, the following sub-steps may be included: first, determine the driving circuit connected to the high-risk node from the target connection relationship. Then, the related nodes of the high-risk nodes are determined according to the target connection relationship. Then, a simulated capacitance whose capacitance value is a sub-equivalent coupling capacitance value between the relevant node and the high-risk node is constructed. Finally, a simulation model of the high-risk nodes is generated based on the simulated capacitance and drive circuit.
  • the simulation model can be generated by simulating the capacitor and the driving circuit, so that the simulation process of the simulation model can not only be realized by relying on the driving capability of the driving circuit, but also the sub-components between the high-risk node and related nodes can be considered in the simulation process.
  • the equivalent coupling capacitance value helps to improve the accuracy of the simulation, thereby improving the accuracy of determining the nodes with crosstalk.
  • the above simulation model may also include: load circuits of high-risk nodes.
  • this load circuit can reduce the current in the sub-circuit corresponding to the simulation model, avoiding damage to the sub-circuit due to excessive current, and helping to ensure the smooth progress of the simulation.
  • the load circuit can also make the simulation model more accurately simulate the real state of the high-risk node in the target circuit, thereby helping to further improve the accuracy of determining the node with crosstalk.
  • the following sub-steps may be included: first, determine the load circuit of the high-risk node from the target connection relationship; then, according to the load circuit, simulated capacitance and driving circuit The circuit generates simulation models of high-risk nodes.
  • each connection relationship is used to represent the nodes connected to each end of a unit.
  • Each high-risk node may correspond to multiple target connection relationships, so that the load circuit can be determined from the units of the multiple target connection relationships, and the load circuit is composed of load units in the multiple target connection relationship units.
  • FIG. 7 is a schematic structural diagram of a subcircuit corresponding to a simulation model provided by an embodiment of the present application.
  • node N01 is a high-risk node, and its related nodes include N02 and N03.
  • the sub-equivalent coupling capacitance between N01 and N02 is cc1
  • the sub-equivalent coupling capacitance between N01 and N03 is cc2.
  • VDD and VCC in Figure 7 are power supply voltages
  • VSS is the negative pole or ground of the power supply.
  • the node N01 is used to connect the input terminal of the inverter cg2, one terminal of the capacitor c1, the drain node of the transistor m2, the drain node of the transistor m3, the drain node of the transistor m7 and the transistor m8
  • the drain node, node N01 can be understood as connecting the input terminal of the inverter cg2, one terminal of the capacitor c1, the drain node of the transistor m2, the drain node of the transistor m3, the drain node of the transistor m7 and the drain node of the transistor m8 of a line.
  • the source node of the transistor m2 is connected to the drain node of the transistor m1, and the other end of C1 is grounded.
  • the node N02 is used to connect the input terminal of the inverter cg1, one terminal of the capacitor c2, and the substrate node of the transistor m5, and the node N02 can be understood as connecting the input terminal of the inverter cg1 and the terminal of the capacitor c2 One terminal, a line at the substrate node of transistor m5. Also, the other end of C2 is grounded.
  • the node N03 is used to connect the input terminal of the inverter cg3, one terminal of the capacitor c3, and the substrate node of the transistor m6, and the node N03 can be understood as connecting the input terminal of the inverter cg3 and the terminal of the capacitor c3 One terminal, a line from the substrate node of transistor m6. Also, the other end of C3 is grounded.
  • the simulation model of the above-mentioned node N01 may include but not limited to: the driving circuit D1 of the high-risk node N01, the load circuit cg2 of the high-risk node, the related nodes N02 and N03 of the high-risk node N01, the high-risk node The sub-equivalent coupling capacitance cc1 between N01 and the relevant node N02, and the sub-equivalent coupling capacitance cc2 between the high-risk node N01 and the relevant node N03.
  • the driving circuit D1 includes: m1, m2, m3, m4, m7 and m8.
  • the driving circuit D1 is the power supply of N01, the power supply voltage of D1 is vcc1, the negative pole of the power supply of D1 is vss1, and provides electrical signals for the N01 node.
  • the simulation model of node N01 may also include: drive circuit m5 and load circuit cg1 of N02, drive circuit m6 and load circuit cg3 of N03 .
  • m5 is the power supply of N02
  • the power supply voltage of m5 is vdd2
  • the negative pole of the power supply of m5 is vss2, which provides electrical signals for N02.
  • M6 is the power supply of N03
  • the power supply voltage of m6 is vdd3
  • the negative pole of the power supply of m6 is vss3, which provides electrical signals for N02.
  • the driving circuit of the high-risk node provides an electrical signal to the high-risk node
  • the driving circuit of the related node provides an electrical signal to the related node, so that it can be judged whether the related node will cause An excessive burr is generated at a high-risk node, that is, it is determined whether the high-risk node is a node with crosstalk.
  • S104 Simulate the simulation model of each high-risk node, so as to determine a node with crosstalk from at least one high-risk node.
  • the simulation models of the high-risk nodes may be simulated one by one in series, or the simulation models of multiple high-risk nodes may be simulated in parallel. It can be understood that, compared with serial simulation, the simulation time of each simulation model overlaps partially or completely during parallel simulation, so that the time required for simulation can be saved, and the efficiency of crosstalk analysis can be improved.
  • the process of simulating the simulation model of each high-risk node may include the following sub-steps: First, obtain the glitch of the high-risk node in the simulation model under the condition that the electrical signal provided by the driving circuit of the simulation model changes Then, determine whether the glitch peak value is greater than or equal to the preset glitch threshold value, if the glitch peak value is greater than or equal to the preset glitch threshold value, then determine the high-risk node as a node with crosstalk, if the glitch peak value is less than the preset glitch peak value, Then the high-risk node is determined as a node without crosstalk.
  • the electrical signal provided by the driving circuit can be understood as a driving signal, so that the embodiment of the present application can use the simulation model to simulate the size of the glitch generated by the target circuit at the high-risk circuit when the driving signal changes, so that based on the size of the glitch Nodes with crosstalk can be accurately identified. Therefore, developers can analyze and process nodes with crosstalk to eliminate the crosstalk, ensure that there is no crosstalk in the target circuit, and improve the accuracy of electrical signal processing of the target circuit.
  • the embodiment of the present application combines two methods to determine nodes with crosstalk.
  • the high-risk nodes determined in S102 may be understood as nodes with crosstalk determined initially, and the nodes with crosstalk determined in S104 are nodes with crosstalk finally determined based on the result of S102.
  • S102 what is used in S102 is the static information of the target circuit, and the simulation process of S104 can be understood as a dynamic process. That is to say, the embodiment of the present application realizes crosstalk analysis by combining dynamic and static methods through S102 and S104. Compared with static crosstalk analysis or dynamic crosstalk analysis alone, this dynamic and static combination helps to improve the accuracy of crosstalk analysis.
  • FIG. 8 is a schematic structural diagram of a crosstalk analysis device provided in an embodiment of the present application.
  • the crosstalk analysis apparatus 200 includes: a connection relationship determination module 201 , a high-risk node determination module 202 , a simulation model determination module 203 and a simulation module 204 .
  • connection relationship determination module 201 is configured to determine the connection relationship of each unit in the target circuit, the connection relationship includes at least one node connecting the units, and one node connects at least two units.
  • the high-risk node determination module 202 is configured to determine at least one high-risk node from the at least one node according to the standard parasitic format file of the at least one node.
  • the simulation model determining module 203 is configured to determine a simulation model of each high-risk node according to the connection relationship of the various units.
  • the simulation module 204 is configured to simulate the simulation model of each of the high-risk nodes, so as to determine whether there is a crosstalk node in the at least one high-risk node.
  • connection relationship determining module is also used for:
  • connection relationship of each unit in the target circuit is determined from the circuit netlist.
  • the unit includes at least one of the following: a circuit device and a module, and the module includes at least one interconnected circuit device.
  • the device also includes:
  • a parasitic file obtaining module configured to obtain the target by simulating the target circuit before determining at least one high-risk node from the at least one node according to the standard parasitic format file of the at least one node Standard parasitic format files for each node in the circuit.
  • the standard parasitic format file includes equivalent capacitance information between the nodes, and the equivalent capacitance information includes: a total equivalent coupling capacitance value between the node and related nodes of the node , the sub-equivalent coupling capacitance value between the node and each of the related nodes.
  • the high-risk node determination module is also used for:
  • a ratio of each sub-equivalent coupling capacitance value corresponding to the node to the total equivalent coupling capacitance value corresponding to the node is determined.
  • Determining at least one node whose ratio meets a preset condition as a high-risk node includes at least one of the following: the ratio is greater than or equal to a preset threshold, and the nodes ranked in the front position in descending order according to the ratio node.
  • the relevant node includes an adjacent node separated from the node by one cell, and a ground node.
  • simulation model determination module is also used for:
  • the target connection relationship between the high-risk node and each unit is obtained from the connection relationship of each unit of the target circuit.
  • a simulation model of the high-risk node is determined according to the target connection relationship.
  • simulation model determination module is also used for:
  • a simulation model of the high-risk node is generated according to the simulation capacitance and the driving circuit.
  • the simulation model also includes: a load circuit of the high-risk node, and the simulation model determination module is also used for:
  • the load circuit of the high-risk node is determined from the target connection relationship.
  • a simulation model of the high-risk node is generated according to the load circuit, the simulation capacitor and the driving circuit.
  • simulation module is also used for:
  • the high-risk node is determined as a node with crosstalk.
  • the target circuit is a circuit of a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the above device embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effect as the method embodiment.
  • the device embodiment reference may be made to the detailed description of the foregoing method embodiment, and details are not repeated here.
  • An embodiment of the present application also provides an electronic device, where the electronic device includes: at least one processor and a memory.
  • the memory stores computer-executable instructions.
  • the at least one processor executes the computer-executed instructions stored in the memory, so that the electronic device implements the aforementioned method.
  • the embodiment of the present application also provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the processor executes the computer-executable instructions, the computing device is enabled to implement the foregoing method.
  • An embodiment of the present application further provides a computer program, the computer program is used to implement the foregoing method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

本申请提供一种串扰分析方法和装置，该方法包括：确定目标电路中单元的连接关系，包括连接单元的节点，一个节点连接至少两个单元；根据节点的标准寄生格式文件确定高风险节点；根据连接关系确定高风险节点的仿真模型；对仿真模型进行仿真以判断是否存在有串扰的节点。相对于人为主观确定存在串扰的节点，本申请通过该方案不需要人为主观判断，从而可以有效提高串扰分析效率。进一步地，本申请先筛选出来高风险节点，以减少需要仿真的节点的数量，有助于提高串扰分析效率。此外，由于本申请是通过电路的结构和数据进行仿真得到的，中间不需要有人为主观判断，从而可以减少由于人为判断错误而导致的漏检，有助于提高确定的存在串扰的节点的准确度。

Description

串扰分析方法和装置
本申请要求于2022年02月17日提交中国专利局、申请号为2022101483719、申请名称为“串扰分析方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种串扰分析方法和装置。
背景技术
芯片是由电路构成的，电路中相邻连线的之间的电信号存在串扰，该串扰产生的毛刺过大时可能导致电路失效，进而导致芯片报废。为了降低芯片的报废率，可以在对芯片进行流片之前，对芯片进行串扰分析，以确定芯片的电路中可能导致电路失效的节点，该节点是电路中的连线。
现有技术中，串扰分析通常是由设计人员根据经验进行的。具体地，设计人员对电路的设计版图进行观察和分析，以根据经验确定可能导致电路失效的节点，也就是存在串扰的节点。
发明内容
本公开实施例提供一种串扰分析方法，所述方法包括：
确定目标电路中各个单元的连接关系，所述连接关系中包括连接所述单元的至少一个节点，一个所述节点连接至少两个所述单元；
根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点；
根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型；
对各个所述高风险节点的所述仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点。
可选地，所述确定目标电路中各个单元的连接关系，包括：
获取目标电路的电路网表；
从所述电路网表中确定所述目标电路中各个单元的连接关系。
可选地，所述各个单元包括以下至少一种：电路器件和模块，所述模块包括至少一个相互连接的所述电路器件。
可选地，所述根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点之前，还包括：
通过对所述目标电路的仿真，获取所述目标电路中各个节点的标准寄生格式文件。
可选地，所述标准寄生格式文件中包括所述节点之间的等效电容信息，所述等效电容信息包括：所述节点与所述节点的相关节点之间的总等效耦合电容值，所述节点与每个所述相关节点之间的子等效耦合电容值；
所述根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点，包括：
对于每个所述节点，确定所述节点对应的各所述子等效耦合电容值与所述节点对应的所述总等效耦合电容值的比值；
将至少一个所述比值满足预设条件的节点确定为高风险节点，所述预设条件包括以下至少一种：所述比值大于或等于预设阈值、按照所述比值降序排列在靠前位置的节点。
可选地，所述相关节点包括与所述节点相隔一个单元的相邻节点，以及地线节点。
可选地，所述根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型，包括：
针对每个所述高风险节点，从所述目标电路的各个单元的连接关系中获取所述高风险节点与所述各个单元的目标连接关系；
针对每个所述高风险节点，根据所述目标连接关系确定所述高风险节点的仿真模型。
可选地，所述根据所述目标连接关系确定所述高风险节点的仿真模型，包括：
从所述目标连接关系中确定与所述高风险节点连接的驱动电路；
根据所述目标连接关系确定所述高风险节点的相关节点；
构建电容值为所述相关节点和所述高风险节点之间的子等效耦合电容值的仿真电容；
根据所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
可选地，所述仿真模型中还包括：所述高风险节点的负载电路，所述根据所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型，包括：
从所述目标连接关系中确定所述高风险节点的负载电路；
根据所述负载电路、所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
可选地，所述对各个所述高风险节点的仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点，包括：
获取在所述驱动电路提供的电信号发生变化的情况下，所述仿真模型中的所述高风险节点的毛刺峰值；
若所述毛刺峰值大于或等于预设毛刺阈值，则将所述高风险节点确定为存在串扰的节点。
可选地，所述目标电路是动态随机存取存储器DRAM的电路。
本公开实施例还提供一种串扰分析装置，所述装置包括：
连接关系确定模块，用于确定目标电路中各个单元的连接关系，所述连接关系中包括连接所述单元的至少一个节点，一个所述节点连接至少两个所述单元；
高风险节点确定模块，用于根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点；
仿真模型确定模块，用于根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型；
仿真模块，用于对各个所述高风险节点的所述仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点。
可选地，所述连接关系确定模块还用于：
获取目标电路的电路网表；
从所述电路网表中确定所述目标电路中各个单元的连接关系。
可选地，所述单元包括以下至少一种：电路器件和模块，所述模块包括至少一个相互连接的所述电路器件。
可选地，所述装置还包括：
寄生文件获取模块，用于在所述根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点之前，通过对所述目标电路的仿真，获取所述目标电路中各个节点的标准寄生格式文件。
可选地，所述标准寄生格式文件中包括所述节点之间的等效电容信息，所述等效电容信息包括：所述节点与所述节点的相关节点之间的总等效耦合电容值，所述节点与每个所述相关节点之间的子等效耦合电容值；
所述高风险节点确定模块还用于：
对于每个所述节点，确定所述节点对应的各所述子等效耦合电容值与所述节点对应的所述总等效耦合电容值的比值；
将至少一个所述比值满足预设条件的节点确定为高风险节点，所述预设条件包括以下至少一种：所述比值大于或等于预设阈值、按照所述比值降序排列在靠前位置的节点。
可选地，所述相关节点包括与所述节点相隔一个单元的相邻节点，以及地线节点。
可选地，所述仿真模型确定模块还用于：
针对每个所述高风险节点，从所述目标电路的各个单元的连接关系中获取所述高风险节点与所述各个单元的目标连接关系。
针对每个所述高风险节点，根据所述目标连接关系确定所述高风险节点的仿真模型。
可选地，所述仿真模型确定模块还用于：
在根据所述目标连接关系确定所述高风险节点的仿真模型时，从所述目标连接关系中确定与所述高风险节点连接的驱动电路；
根据所述目标连接关系确定所述高风险节点的相关节点；
构建电容值为所述相关节点和所述高风险节点之间的子等效耦合电容值的仿真电容；
根据所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
可选地，所述仿真模型中还包括：所述高风险节点的负载电路，所述仿真模型确定模块还用于：
从所述目标连接关系中确定所述高风险节点的负载电路；
根据所述负载电路、所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
可选地，所述仿真模块还用于：
获取在所述驱动电路提供的电信号发生变化的情况下，所述仿真模型中的所述高风险节点的毛刺峰值；
若所述毛刺峰值大于或等于预设毛刺阈值，则将所述高风险节点确定为存在串扰的节点。
可选地，所述目标电路是动态随机存取存储器DRAM的电路。
本公开实施例提供的串扰分析方法和装置，可以确定目标电路中各个单元的连接关系，该连接关系中包括连接单元的至少一个节点，一个节点连接至少两个单元；根据至少一个节点的标准寄生格式文件，从至少一个节点中确定至少一个高风险节点；根据各个单元的 连接关系，确定每个高风险节点的仿真模型；对各个高风险节点的仿真模型进行仿真，以从至少一个高风险节点中确定存在串扰的节点。相对于人为主观确定存在串扰的节点，本公开实施例通过该方案不需要人为主观判断，从而可以有效提高串扰分析效率。进一步地，本公开实施例先筛选出来高风险节点，以减少需要仿真的节点的数量，有助于提高串扰分析效率。此外，由于本公开实施例是通过电路的结构和数据进行仿真得到的，中间不需要有人为主观判断，从而可以减少由于人为判断错误而导致的漏检，有助于提高确定的存在串扰的节点的准确度。
附图说明
图1是本申请实施例提供的一种串扰分析方法的步骤流程图；
图2和图3是本申请实施例提供的一种电阻和电容的两种连接关系示意图；
图4和图5是本申请实施例提供的电路网表中的各个单元的连接关系示意图；
图6是本申请实施例提供的一种SPF文件的结构示意图；
图7是本申请实施例提供的一种仿真模型对应的子电路结构示意图；
图8是本申请实施例提供的一种串扰分析装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
如背景技术所述，现有技术通过设计人员根据经验进行，然而现有技术存在串扰分析效率较低和准确度较低的问题。发明人对现有技术进行分析之后发现，出现该问题的原因之一在于，现有技术中进行串扰分析是人工进行的。此外，人工分析也会由于人为失误而导致确定的存在串扰的节点的准确度较低。
为了解决上述技术问题，本申请实施例考虑通过对高风险节点的仿真模型进行仿真，以从高风险节点中确定存在串扰的节点。这里的高风险节点是先通过标准寄生格式文件筛选出来的，代表很有可能为存在串扰的节点。相对于人为主观确定存在串扰的节点，本申请实施例通过该方案不需要人为主观判断，从而可以有效提高串扰分析效率。进一步地，本申请实施例先筛选出来高风险节点，以减少需要仿真的节点的数量，有助于提高串扰分析效率。此外，由于本申请实施例是通过电路的结构和数据进行仿真得到的，中间不需要 有人为主观判断，从而可以减少由于人为判断错误而导致的漏检，有助于提高确定的存在串扰的节点的准确度。
图1是本申请实施例提供的一种串扰分析方法的步骤流程图。请参照图1，上述方法包括：
S101：确定目标电路中各个单元的连接关系，该连接关系中包括连接单元的至少一个节点，一个节点连接至少两个单元。
其中，目标电路是需要检测串扰的任意电路，本申请实施例对其不加以限制。例如，目标电路可以是动态随机存取存储器(DRAM，dynamic random accessing memory)的电路。
其中，目标电路的单元包括以下至少一种：电路器件和模块。这里的电路器件可以包括构成电路的任意器件，例如，电容、电感、电阻、晶体管、功率放大器等。这里的模块可以包括至少一个相互连接的电路器件，例如，电容和电感构成的具有某种功能的子电路，该子电路可以人为是该目标电路中的一个虚拟单元。
可以理解的是，在实际应用中，每个电路都是由上述至少一种单元连接构成的。每个单元可能有一个或多个端，每个端可以通过一个节点与另一个单元的一端连接。图2和图3是本申请实施例提供的一种电阻和电容的两种连接关系示意图。参照图2和图3所示，电阻有两个端T1和T2，电容有两个端T3和T4。
参照图2所示，电阻的T2端可以通过一个节点N1与电容的T3端连接，电阻的T1端和电容的T4端与其余单元分别连接，从而实现电阻和电容的串联。
参照图3所示，电阻的T1端可以通过一个节点N2与电容的T3端连接，电阻的T2端与电容的T4端通过节点N3连接，N2和N3可以与其余单元分别连接，从而实现电阻和电容的并联。上述连接关系可以从描述目标电路的结构的文件中提取出来。通常情况下，描述目标电路的结构的文件可以是电路网表(netlist)。从而执行S101时可以按照以下步骤实现：首先，获取目标电路的电路网表；然后，从电路网表中确定目标电路中各个单元的连接关系。
上述网表中通常存在多条记录，每条记录用于描述一个单元的各个端连接的节点。对于同一种类型的单元，其各个端在不同记录中的顺序是相同的，从而可以按照该顺序确定该类型的单元的各个端所连接的节点是什么。不同类型的单元对应的端数量可能不同，端类型也可能不同。例如，对于晶体管，其可以包括四个端：栅极节点、源极节点、漏极节点和衬底节点。又例如，对于电阻，其可以包括两个端，两个端无区别。再例如，对于反向器，其具有输入端和输出端。
可以理解的是，不同单元的连接关系实质上是不同单元的端之间的连接关系。
图4和图5是本申请实施例提供的电路网表中的各个单元的连接关系示意图，电路网表可以是在完成目标电路的设计之后根据目标电路生成的。电路网表中通常包括目标电路中的各个单元的连接关系，可以包括多种单元的连接关系。需要说明的是，不同种类的单元对应的连接关系的格式不同，其格式与该类型的单元的端数量有关。
图4是本申请实施例提供的电路网表中的各个三极管对应的连接关系示意图。参照图4所示，电路网表中包括五列：C1至C5。
其中，C1列用于存储晶体管的标识，图4中的电路网表中存储有四个标识为xmm1至xmm4的晶体管。
C2列用于存储晶体管的第一端T1连接的节点。可以看出，图4中的xmm1至xmm4的T1端连接的节点分别是N01、N05、N03和N11。
C3列用于存储晶体管的第二端T2连接的节点。可以看出，图4中的xmm1至xmm4的T2端连接的节点分别是N02、N03、N08和N12。
C4列用于存储晶体管的第三端T3连接的节点。可以看出，图4中的xmm1至xmm4的T3端连接的节点分别是N03、N06、N09和N13。
C5列用于存储晶体管的第四端T4连接的节点。可以看出，图4中的xmm1至xmm4的T3端连接的节点分别是N04、N07、N10和N03。
需要说明的是，图4中的每个晶体管的不同端如果对应同一个节点，那么代表这两个晶体管的这些不同端通过该节点连接。例如，xmm1的T3端、xmm2的T2端、xmm3的T1端和xmm4的T4端均与节点N03连接，那么代表xmm1的T3端、xmm2的T2端、xmm3的T1端和xmm4的T4端通过节点N03连接在一起，从而实现了xmm1、xmm2、xmm3和xmm4的连接。
图5是本申请实施例提供的电路网表中的各个电阻对应的连接关系示意图。参照图5所示，电路网表中包括三列：C1至C3。
其中，C1列用于存储电阻的标识，图5中的电路网表中存储有三个标识为R1至R3的电阻。
C2列用于存储各电阻的第一端T1连接的节点。可以看出，图5中的R1至R3的T1端连接的节点分别是N01、N02和N01。
C3列用于存储各电阻的第二端T2连接的节点。可以看出，图5中的R1至R3的T2端连接的节点分别是N0、N02和N04。
同样地，图5中的每个电阻的不同端如果对应同一个节点，那么代表这两个电阻的这些不同端通过该节点连接。例如，R1的T1端、R2的T1端和R3的T1端均与节点N01连接，那么代表R1的T1端、R2的T1端和R3的T1端通过节点N01连接在一起。此外，R1的T2端和R2的T2端均与节点N02连接，那么代表R1的T2端和R2的T2端通过节点N02连接在一起，从而实现了R1和R2的并联。R3的T2端通过N03与其余单元连接。
可以理解的是，本申请实施例可以在目标电路完成设计之后生成该目标电路的电路网表，从而可以在每次识别该目标电路是否存在串扰的节点时，只需要从该电路网表中获取连接关系即可，不需要重新根据目标电路的结构确定连接关系。如此，可以缩短确定连接关系所需要的时长，以进一步提高确定串扰分析效率。
此外，上述单元包括以下至少一种：电路器件和模块，模块包括至少一个相互连接的电路器件。基于模块，本申请实施例可以内部不存在串扰的模块作为一个整体，这样，不仅可以识别电路器件之间的节点是否存在串扰，还可以识别这些模块之间的节点是否存在串扰，以及这些模块与其余电路器件之间的节点是否存在串扰。
可以看出，本申请实施例可以将模块作为一个整体，从而可以不需要识别模块内部相互连接的电路器件之间是否存在串扰。在已知该模块内部不存在串扰的情况下，可以有效减少识别的节点数量，进而有助于进一步提高串扰分析效率。
在通过上述S101获取到上述单元的连接关系之后，可以从中确定目标电路中用于连接单元的所有节点，从而可以获取这些节点的标准寄生格式文件，并执行步骤S102。
S102：根据至少一个节点的标准寄生格式文件，从至少一个节点中确定至少一个高风险节点。
其中，标准寄生格式文件(SPF，standard parasitic format)中存储有任意两个节点之间的等效电容信息，该等效电容信息可以包括：每个节点与该节点的每个相关节点之间的子等效耦合电容值、每个节点与该节点的所有相关节点之间的总等效耦合电容值。
上述子等效耦合电容值可以包括以下至少一种电容值：该节点与相关节点之间的寄生电容值、连接该节点与该相关节点的真实电容的电容值。
可以理解的是，总等效耦合电容值可以是该节点与所有相关节点之间的子等效耦合电容值的总和，从而总等效耦合电容值也可以包括寄生电容值和真实电容的电容值。
图6是本申请实施例提供的一种SPF文件的结构示意图。为了简化起见，图6示出了针对图5所示的电路网表中的三个节点N01至N03的等效电容信息，图4所示的13个节点的原理与之相同，在此不再赘述。
参照图6所示，N01：CT1 ct1用于表示节点N01和其所有相关节点N02、N03的总等效耦合电容CT1的总等效耦合电容值ct1。C1 N01 N02 c1用于表示N01和其相关节点N02之间的子等效耦合电容C1的子等效耦合电容值为c1，C2 N01 N03 c2用于表示N01和其相关节点N03之间的子等效耦合电容C2的子等效耦合电容值为c2。其中，ct1为c1和c2之和。
参照图6所示，N02：CT2 ct2用于表示节点N02和其所有相关节点N01、N03的总等效耦合电容CT2的总等效耦合电容值为ct2。C3 N02 N01 c3用于表示N02和其相关节点N01之间的子等效耦合电容C3的子等效耦合电容值为c3，C4 N02 N03 c4用于表示N02和其相关节点N03之间的子等效耦合电容C4的子等效耦合电容值为c4。其中，ct2为c3和c4之和。
参照图6所示，N03：CT3 ct3用于表示节点N03和其所有相关节点N01、N02的总等效耦合电容CT3的总等效耦合电容值为ct3。C5 N03 N01 c5用于表示N03和其相关节点N01之间的子等效耦合电容C5的子等效耦合电容值为c5，C6 N03 N02 c6用于表示N03和其相关节点N02之间的子等效耦合电容C6的子等效耦合电容值为c6。其中，ct3为c5和c6之和。
需要说明的是，图6中的C1和C3均为N01和N02之间的子等效耦合电容，从而C1＝C3。同理，图6中的C2和C5均为N01和N03之间的子等效耦合电容，从而C2＝C5，图6中的C4和C6均为N02和N03之间的子等效耦合电容，从而C4＝C6。
上述标准寄生格式文件可以是预先生成的。具体地，可以通过对目标电路的仿真，获取目标电路中各个节点的标准寄生格式文件。可以看出，在该仿真过程中，需要获取到目标电路中的每个节点和相关节点之间的子等效耦合电容值，从而根据子等效耦合电容值确定每个节点的总等效耦合电容值，最后，按照每个节点和相关节点之间的子等效耦合电容值、每个节点的总等效耦合电容值，生成与上述图6所示格式相同或相似的SPF文件。
本申请实施例可以通过仿真过程生成SPF文件，从而可以保证SPF文件中的等效电容信息是目标电路的当前等效电容信息，得到的等效电容信息是符合目标电路的当前状态，有助于提高等效电容信息的准确度，进而提高判断高风险节点的准确度。
基于上述等效电容信息，可以从目标电路的一个或多个节点中选取高风险节点。其中， 高风险节点可以是子等效耦合电容值大于预设阈值的节点，也可以是子等效耦合电容值较高的若干节点。
为了提高判断高风险节点的准确度，可以根据每个节点的各子等效耦合电容值和总等效耦合电容值之间的比值，选取高风险节点。具体地，将至少一个该比值满足预设条件的节点确定为高风险节点，该预设条件包括以下至少一种：该比值大于或等于预设阈值、按照比值降序排列在靠前位置的节点。
其中，这里的比值对应的预设阈值可以为30％。当然，该预设阈值可以按照实际应用场景设置，本公开实施例对其不加限制。
需要说明的是，由于一个节点可以对应有多个相关节点，从而该节点针对每个该相关节点均可以得到一个这样的比值。如果该节点的至少一个该比值大于或等于预设阈值，或排序在靠前位置，那么就可以确定该节点是高风险节点。
可以看出，本申请实施例可以通过上述比值更加准确的描述每个节点为高风险节点的概率，从而该比值越大，代表该节点为高风险节点的概率越大。这样，可以在某些节点的子等效耦合电容值相对于其余节点的子等效耦合电容值过小时，准确的筛选出来高风险的节点，避免遗漏掉这些子等效耦合电容值过小的这些节点。
可选地，对于每个节点，该节点的相关节点可以包括以下至少一种节点：与该节点相隔一个单元的相邻节点、地线节点。这样，本申请实施例就可以识别出各种类型的节点是否为存在串扰的节点，避免遗漏掉部分节点，有助于进一步提高对目标电路的串扰分析准确度。
S103：根据各个单元的连接关系，确定每个高风险节点的仿真模型。
其中，仿真模型中可以包括与该高风险节点直接连接或间接连接的单元，仿真模型可以理解为这些单元构成的子电路，该仿真模型中这些单元的连接关系与目标电路中这些单元的连接关系一致。
具体地，在执行S103时，可以包括以下子步骤：首先，针对每个高风险节点，从目标电路的各个单元的连接关系中获取该高风险节点与各个单元的目标连接关系。其中，目标连接关系也就是目标电路的各个单元的所有连接关系中，包括该高风险节点的连接关系。例如，对于图4所示的电路网表，如果一个高风险节点为N03，那么目标连接关系可以包括：xmm1 N01 N02 N03 N04、xmm2 N05 N03 N06 N07、xmm3 N03 N08 N09 N10、xmm4 N11 N12 N13 N03。然后，针对每个高风险节点，根据目标连接关系确定该高风险节点的仿真模型。
可选地，上述仿真模型中不仅可以包括高风险节点连接的驱动电路，还可以包括一个仿真电容，该仿真电容的电容值为该高风险节点和该相关节点之间的子等效耦合电容值。从而，在根据目标连接关系确定该高风险节点的仿真模型时，可以包括以下子步骤：首先，从目标连接关系中确定与该高风险节点连接的驱动电路。然后，根据目标连接关系确定高风险节点的相关节点。再然后，构建电容值为该相关节点和该高风险节点之间的子等效耦合电容值的仿真电容。最后，根据仿真电容和驱动电路生成高风险节点的仿真模型。
本申请实施例可以通过仿真电容和驱动电路生成仿真模型，从而不仅可以依赖驱动电路的驱动能力实现仿真模型的仿真过程，还可以使该仿真过程考虑了该高风险节点和相关节点之间的子等效耦合电容值，有助于提高仿真的准确度，进而提高确定的存在串扰的节 点的准确度。
当然，上述仿真模型中还可以包括：高风险节点的负载电路。一方面，这个负载电路可以减小仿真模型对应的子电路中的电流大小，避免电流过大而导致子电路被损坏，有助于保证仿真的顺利进行。另一方面，这个负载电路还可以使仿真模型更加准确的模拟该高风险节点在目标电路中的真实状态，从而有助于进一步提高确定的存在串扰的节点的准确度。具体地，在根据仿真电容和驱动电路生成高风险节点的仿真模型时，可以包括以下子步骤：首先，从目标连接关系中确定高风险节点的负载电路；然后，根据负载电路、仿真电容和驱动电路生成高风险节点的仿真模型。
依据前述图4或图5对连接关系的说明，每个连接关系用于表示一个单元的各个端连接的节点。每个高风险节点可以对应有多个目标连接关系，从而可以从这多个目标连接关系的单元中确定负载电路，负载电路是由这多个目标连接关系的单元中的负载单元构成的。
图7是本申请实施例提供的一种仿真模型对应的子电路结构示意图。参照图7所示，节点N01为高风险节点，其相关节点包括N02和N03。N01和N02之间的子等效耦合电容为cc1，N01和N03之间的子等效耦合电容为cc2。图7中的VDD和VCC是电源电压，VSS是电源负极或地。
从图7中可以看出，节点N01用于连接反相器cg2的输入端、电容c1的一端、晶体管m2的漏极节点、晶体管m3的漏极节点、晶体管m7的漏极节点和晶体管m8的漏极节点，节点N01可以理解为连接反相器cg2的输入端、电容c1的一端、晶体管m2的漏极节点、晶体管m3的漏极节点、晶体管m7的漏极节点和晶体管m8的漏极节点的一条线。此外，晶体管m2的源极节点与晶体管m1的漏极节点连接，C1的另一端接地。
从图7中可以看出，节点N02用于连接反相器cg1的输入端、电容c2的一端、晶体管m5的衬底节点，节点N02可以理解为连接反相器cg1的输入端、电容c2的一端、晶体管m5的衬底节点的一条线。此外，C2的另一端接地。
从图7中可以看出，节点N03用于连接反相器cg3的输入端、电容c3的一端、晶体管m6的衬底节点，节点N03可以理解为连接反相器cg3的输入端、电容c3的一端、晶体管m6的衬底节点的一条线。此外，C3的另一端接地。
根据上述说明可以看出，上述节点N01的仿真模型可以包括但不限于：高风险节点N01的驱动电路D1、高风险节点的负载电路cg2、高风险节点N01的相关节点N02和N03、高风险节点N01与相关节点N02之间的子等效耦合电容cc1、高风险节点N01与相关节点N03之间的子等效耦合电容cc2。其中，驱动电路D1包括：m1、m2、m3、m4、m7和m8。驱动电路D1是N01的电源，D1的电源电压为vcc1，D1的电源负极为vss1，为N01节点提供电信号。
此外，为了使高风险节点的相关节点处也产生电信号，参照图7所示，节点N01的仿真模型还可以包括：N02的驱动电路m5和负载电路cg1、N03的驱动电路m6和负载电路cg3。m5为N02的电源，m5的电源电压为vdd2，m5的电源负极为vss2，为N02提供电信号。M6为N03的电源，m6的电源电压为vdd3，m6的电源负极为vss3，为N02提供电信号。这样，在对高风险节点的仿真模型进行仿真的过程中，高风险节点的驱动电路向高风险节点提供电信号，相关节点的驱动电路向相关节点提供电信号，从而可以判断相关节点是否会导致在高风险节点处产生过大的毛刺，也就是确定该高风险节点是否为存在串扰 的节点。
S104：对各个高风险节点的仿真模型进行仿真，以从至少一个高风险节点中确定存在串扰的节点。
具体地，可以逐个对高风险节点的仿真模型进行串行仿真，也可以对多个高风险节点的仿真模型进行并行仿真。可以理解的是，相对于串行仿真，并行仿真时各个仿真模型的仿真时间存在部分或全部重叠，从而可以节约仿真所需要的时长，进而提高串扰分析效率。
在对每个高风险节点的仿真模型进行仿真的过程可以包括以下子步骤：首先，获取在该仿真模型的驱动电路提供的电信号发生变化的情况下，该仿真模型中的高风险节点的毛刺峰值；然后，确定该毛刺峰值是否大于或等于预设毛刺阈值，若毛刺峰值大于或等于预设毛刺阈值，则将该高风险节点确定为存在串扰的节点，若毛刺峰值小于预设毛刺峰值，则将该高风险节点确定为不存在串扰的节点。
其中，驱动电路提供的电信号可以理解为驱动信号，从而本申请实施例也就可以通过仿真模型仿真在驱动信号变化的情况下，目标电路在高风险电路处产生的毛刺大小，从而基于毛刺大小可以准确的识别存在串扰的节点。从而，开发人员可以对存在串扰的节点进行分析并处理，以消除该串扰，保证目标电路不存在串扰，提高了目标电路的电信号处理准确度。
综上所述，本申请实施例结合两种方法确定存在串扰的节点。S102确定的高风险节点可以理解为初步确定的存在串扰的节点，S104确定的存在串扰的节点是基于S102的结果最终确定的存在串扰的节点。
其中，S102中使用的是目标电路的静态信息，S104的仿真过程可以理解为动态过程。也就是说，本申请实施例通过S102和S104实现了动态和静态结合的方法进行串扰分析。相对于单独进行静态串扰分析或单独进行动态串扰分析，这种动静结合的方式有助于提高串扰分析的准确度。
对应于上述方法实施例，图8是本申请实施例提供的一种串扰分析装置的结构示意图。请参照图8，上述串扰分析装置200，包括：连接关系确定模块201、高风险节点确定模块202、仿真模型确定模块203和仿真模块204。
其中，连接关系确定模块201，用于确定目标电路中各个单元的连接关系，所述连接关系中包括连接所述单元的至少一个节点，一个所述节点连接至少两个所述单元。
高风险节点确定模块202，用于根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点。
仿真模型确定模块203，用于根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型。
仿真模块204，用于对各个所述高风险节点的所述仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点。
可选地，所述连接关系确定模块还用于：
获取目标电路的电路网表。
从所述电路网表中确定所述目标电路中各个单元的连接关系。
可选地，所述单元包括以下至少一种：电路器件和模块，所述模块包括至少一个相互连接的所述电路器件。
可选地，所述装置还包括：
寄生文件获取模块，用于在所述根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点之前，通过对所述目标电路的仿真，获取所述目标电路中各个节点的标准寄生格式文件。
可选地，所述标准寄生格式文件中包括所述节点之间的等效电容信息，所述等效电容信息包括：所述节点与所述节点的相关节点之间的总等效耦合电容值，所述节点与每个所述相关节点之间的子等效耦合电容值。
所述高风险节点确定模块还用于：
对于每个所述节点，确定所述节点对应的各所述子等效耦合电容值与所述节点对应的所述总等效耦合电容值的比值。
将至少一个所述比值满足预设条件的节点确定为高风险节点，所述预设条件包括以下至少一种：所述比值大于或等于预设阈值、按照所述比值降序排列在靠前位置的节点。
可选地，所述相关节点包括与所述节点相隔一个单元的相邻节点，以及地线节点。
可选地，所述仿真模型确定模块还用于：
针对每个所述高风险节点，从所述目标电路的各个单元的连接关系中获取所述高风险节点与所述各个单元的目标连接关系。
针对每个所述高风险节点，根据所述目标连接关系确定所述高风险节点的仿真模型。
可选地，所述仿真模型确定模块还用于：
在根据所述目标连接关系确定所述高风险节点的仿真模型时，从所述目标连接关系中确定与所述高风险节点连接的驱动电路。
根据所述目标连接关系确定所述高风险节点的相关节点。
构建电容值为所述相关节点和所述高风险节点之间的子等效耦合电容值的仿真电容。
根据所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
可选地，所述仿真模型中还包括：所述高风险节点的负载电路，所述仿真模型确定模块还用于：
从所述目标连接关系中确定所述高风险节点的负载电路。
根据所述负载电路、所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
可选地，所述仿真模块还用于：
获取在所述驱动电路提供的电信号发生变化的情况下，所述仿真模型中的所述高风险节点的毛刺峰值。
若所述毛刺峰值大于或等于预设毛刺阈值，则将所述高风险节点确定为存在串扰的节点。
可选地，所述目标电路是动态随机存取存储器DRAM的电路。
上述装置实施例是与前述方法实施例对应的实施例，具有与方法实施例相同的技术效果。该装置实施例的详细说明可以参照前述方法实施例的详细说明，在此不再赘述。
本申请实施例还提供一种电子设备，该电子设备包括：至少一个处理器和存储器。
其中，所述存储器存储计算机执行指令。
所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述电子设备实现如前述的方法。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，使计算设备实现如前述的方法。
本申请实施例还提供一种计算机程序，所述计算机程序用于实现如前述的方法。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。
为了方便解释，已经结合具体的实施方式进行了上述说明。但是，上述示例性的讨论不是意图穷尽或者将实施方式限定到上述公开的具体形式。根据上述的教导，可以得到多种修改和变形。上述实施方式的选择和描述是为了更好的解释原理以及实际的应用，从而使得本领域技术人员更好的使用所述实施方式以及适于具体使用考虑的各种不同的变形的实施方式。

Claims (15)

  1. 一种串扰分析方法，所述方法包括：
    确定目标电路中各个单元的连接关系，所述连接关系中包括连接所述单元的至少一个节点，一个所述节点连接至少两个所述单元；
    根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点；
    根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型；
    对各个所述高风险节点的仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点。
  2. 根据权利要求1所述的方法，其中，所述确定目标电路中各个单元的连接关系，包括：
    获取目标电路的电路网表；
    从所述电路网表中确定所述目标电路中各个单元的连接关系。
  3. 根据权利要求2所述的方法，其中，所述各个单元包括以下至少一种：电路器件和模块，所述模块包括至少一个相互连接的所述电路器件。
  4. 根据权利要求1所述的方法，其中，所述根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点之前，还包括：
    通过对所述目标电路的仿真，获取所述目标电路中各个节点的标准寄生格式文件。
  5. 根据权利要求4所述的方法，其中，所述标准寄生格式文件中包括所述节点之间的等效电容信息，所述等效电容信息包括：所述节点与所述节点的相关节点之间的总等效耦合电容值，所述节点与每个所述相关节点之间的子等效耦合电容值；
    所述根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点，包括：
    对于每个所述节点，确定所述节点对应的各所述子等效耦合电容值与所述节点对应的所述总等效耦合电容值的比值；
    将至少一个所述比值满足预设条件的节点确定为高风险节点，所述预设条件包括以下至少一种：所述比值大于或等于预设阈值、按照所述比值降序排列在靠前位置的节点。
  6. 根据权利要求5所述的方法，其中，所述相关节点包括与所述节点相隔一个单元的相邻节点，以及地线节点。
  7. 根据权利要求5所述的方法，其中，所述根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型，包括：
    针对每个所述高风险节点，从所述目标电路的各个单元的连接关系中获取所述高风险节点与所述各个单元的目标连接关系；
    针对每个所述高风险节点，根据所述目标连接关系确定所述高风险节点的仿真模型。
  8. 根据权利要求7所述的方法，其中，所述根据所述目标连接关系确定所述高风险节点的仿真模型，包括：
    从所述目标连接关系中确定与所述高风险节点连接的驱动电路；
    根据所述目标连接关系确定所述高风险节点的相关节点；
    构建电容值为所述相关节点和所述高风险节点之间的子等效耦合电容值的仿真电容；
    根据所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
  9. 根据权利要求8所述的方法，其中，所述仿真模型中还包括：所述高风险节点的负载电路，所述根据所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型，包括：
    从所述目标连接关系中确定所述高风险节点的负载电路；
    根据所述负载电路、所述仿真电容和所述驱动电路生成所述高风险节点的仿真模型。
  10. 根据权利要求8或9所述的方法，其中，所述对各个所述高风险节点的仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点，包括：
    获取在所述驱动电路提供的电信号发生变化的情况下，所述仿真模型中的所述高风险节点的毛刺峰值；
    若所述毛刺峰值大于或等于预设毛刺阈值，则将所述高风险节点确定为存在串扰的节点。
  11. 根据权利要求1所述的方法，其中，所述目标电路是动态随机存取存储器DRAM的电路。
  12. 一种串扰分析装置，所述装置包括：
    连接关系确定模块，用于确定目标电路中各个单元的连接关系，所述连接关系中包括连接所述单元的至少一个节点，一个所述节点连接至少两个所述单元；
    高风险节点确定模块，用于根据所述至少一个节点的标准寄生格式文件，从所述至少一个节点中确定至少一个高风险节点；
    仿真模型确定模块，用于根据所述各个单元的连接关系，确定每个所述高风险节点的仿真模型；
    仿真模块，用于对各个所述高风险节点的仿真模型进行仿真，以判断所述至少一个高风险节点中是否存在串扰的节点。
  13. 一种电子设备，所述电子设备包括：至少一个处理器和存储器；
    所述存储器存储计算机执行指令；
    所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述电子设备实现如权利要求1至11任一项所述的方法。
  14. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，使计算设备实现如权利要求1至11任一项所述的方法。
  15. 一种计算机程序，所述计算机程序用于实现如权利要求1至11任一项所述的方法。
PCT/CN2022/093460 2022-02-17 2022-05-18 串扰分析方法和装置 WO2023155314A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210148371.9A CN116663473A (zh) 2022-02-17 2022-02-17 串扰分析方法和装置
CN202210148371.9 2022-02-17

Publications (1)

Publication Number Publication Date
WO2023155314A1 true WO2023155314A1 (zh) 2023-08-24

Family

ID=87577426

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/093460 WO2023155314A1 (zh) 2022-02-17 2022-05-18 串扰分析方法和装置

Country Status (2)

Country Link
CN (1) CN116663473A (zh)
WO (1) WO2023155314A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030121012A1 (en) * 2001-12-21 2003-06-26 Mitsubishi Denki Kabushiki Kaisha Crosstalk verifying device
JP2008020986A (ja) * 2006-07-11 2008-01-31 Renesas Technology Corp クロストーク解析方法
CN106066914A (zh) * 2016-06-02 2016-11-02 复旦大学 考虑串扰效应的静态时序分析方法
CN110717310A (zh) * 2019-10-10 2020-01-21 中国科学院微电子研究所 一种电路布图的调整方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030121012A1 (en) * 2001-12-21 2003-06-26 Mitsubishi Denki Kabushiki Kaisha Crosstalk verifying device
JP2008020986A (ja) * 2006-07-11 2008-01-31 Renesas Technology Corp クロストーク解析方法
CN106066914A (zh) * 2016-06-02 2016-11-02 复旦大学 考虑串扰效应的静态时序分析方法
CN110717310A (zh) * 2019-10-10 2020-01-21 中国科学院微电子研究所 一种电路布图的调整方法及装置

Also Published As

Publication number Publication date
CN116663473A (zh) 2023-08-29

Similar Documents

Publication Publication Date Title
US6405348B1 (en) Deep sub-micron static timing analysis in the presence of crosstalk
US20220067264A1 (en) Chip design method, design device, computer device and storage medium
US11288431B2 (en) Method and system for establishing metal interconnection layer capacitance prediction model
CN104765902A (zh) 使用考虑不同电路拓扑结构生成的输入波形特征化单元
US8281268B2 (en) Method and system detecting metal line failure
US8719760B1 (en) Validating integrated circuit simulation results
US8306804B2 (en) System, an apparatus and a method for performing chip-level electrostatic discharge simulations
JP2004185374A (ja) クロストークチェック方法
TWI775299B (zh) 在電子設計自動化平台上進行電壓規則檢查的電腦實施方法
WO2023155314A1 (zh) 串扰分析方法和装置
CN113723045A (zh) 数字集成电路的设计方法
US6484297B1 (en) 4K derating scheme for propagation delay and setup/hold time computation
US7007252B2 (en) Method and apparatus for characterizing the propagation of noise through a cell in an integrated circuit
US20030018949A1 (en) Method and apparatus for laying out wires on a semiconductor integrated circuit
US10922456B1 (en) Circuit modification for efficient electro-static discharge analysis of integrated circuits
US20140282333A1 (en) Design support apparatus and design support method
US8924911B2 (en) Equation based transient circuit optimization
US20220327269A1 (en) Computing device and method for detecting clock domain crossing violation in design of memory device
US20070219770A1 (en) Simulation method
JP2009301366A (ja) ノイズ解析装置
JP4390728B2 (ja) ネットリスト生成装置
US7263676B2 (en) Method and apparatus for detecting and analyzing the propagation of noise through an integrated circuit
US6536021B2 (en) Method and system for representing hierarchical extracted resistance-capacitance files of a circuit model
US20240070361A1 (en) Circuit analysis method, circuit analysis device, and circuit analysis system
US20220327273A1 (en) Circuit simulation method and device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22926626

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE