WO2023155050A1 - 近场通信系统及其控制方法、电子设备 - Google Patents

近场通信系统及其控制方法、电子设备 Download PDF

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Publication number
WO2023155050A1
WO2023155050A1 PCT/CN2022/076380 CN2022076380W WO2023155050A1 WO 2023155050 A1 WO2023155050 A1 WO 2023155050A1 CN 2022076380 W CN2022076380 W CN 2022076380W WO 2023155050 A1 WO2023155050 A1 WO 2023155050A1
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Prior art keywords
input terminal
transistor
coupled
signal
signal input
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PCT/CN2022/076380
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English (en)
French (fr)
Inventor
于宝亮
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华为技术有限公司
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Priority to CN202280091469.3A priority Critical patent/CN118696527A/zh
Priority to PCT/CN2022/076380 priority patent/WO2023155050A1/zh
Publication of WO2023155050A1 publication Critical patent/WO2023155050A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits

Definitions

  • the present application relates to the technical field of near field communication, and in particular to a near field communication system, a control method thereof, and electronic equipment.
  • Near field communication also known as near-field communication
  • NFC near field communication
  • NFC near-field communication
  • Contactless data transmission and exchange is a near-field communication technology that enables information exchange between two or more devices.
  • a near field communication system for realizing near field communication mainly includes a rectifier (rectifier), a demodulator (demodulator), a power management unit (power management unit, PMU) and other parts.
  • the rectifier is used to convert the radio frequency signal received by the antenna into a direct current signal for use by other modules in the near field communication system such as a demodulator.
  • the demodulator is used to demodulate the received modulated signal into a digital signal.
  • signals with low modulation depth cannot be demodulated, for example, 6.8 Mbps signals in the VHBR (very-high-bit-rates, very high-speed bit rate) protocol cannot be demodulated.
  • Embodiments of the present application provide a near field communication system, its control method, and electronic equipment, which can improve the problem of low sensitivity of the demodulator.
  • a near field communication system includes: a rectifier, a demodulator and a power management unit;
  • the demodulator includes: a transconductance circuit, a first current source, a signal source, a load module, a second A signal input terminal, a second signal input terminal, a third signal input terminal and a signal output terminal; wherein, the first signal input terminal and the second signal input terminal are used to receive radio frequency signals, and the first signal input terminal and the second signal input terminal
  • the radio frequency signal received by the input end is a pair of differential signals
  • the signal output end of the rectifier is coupled with the power management unit, and the power management unit is coupled with the power input end of the demodulator to supply power for the demodulator;
  • the signal output end of the rectifier is also coupled It is coupled with the third signal input terminal of the demodulator, and is used to provide a DC signal for the third signal input terminal
  • the bias terminal of the transconductance circuit is coupled with the first current source, and the second terminal of the
  • the first signal input end and the second signal input end of the demodulator usually receive the radio frequency signal transmitted by the antenna, and the third signal input end of the demodulator is usually coupled with the output end of the rectifier,
  • the rectifier is used to convert the radio frequency signal received from the antenna into a DC signal, so the peak value of the radio frequency signal received by the first signal input terminal, the peak value of the radio frequency signal received by the second signal input terminal and the third signal input terminal The values of the received DC signals are relatively close.
  • the demodulator provided by the present application since the voltage at the third signal input terminal is used as a reference, the voltage at the first signal input terminal and the voltage at the second signal input terminal are compared, and the first The peak value of the radio frequency signal received at the signal input end, the peak value of the radio frequency signal received at the second signal input end, and the value of the DC signal received at the third signal input end are relatively close, so the demodulator provided by the application can demodulate Only the useful signal is quantized, so that the demodulator has a higher sensitivity.
  • the transconductance circuit is used to pass the current signal provided by the third signal input terminal through the transconductance when the voltage at the first signal input terminal or the voltage at the second signal input terminal is greater than the voltage at the third signal input terminal.
  • the first end of the circuit flows to a first current source.
  • the transconductance circuit is used to pass the current signal provided by the third signal input end through the transconductance when the voltage at the first signal input end and the voltage at the second signal input end are both lower than the voltage at the third signal input end
  • the second end of the conductive circuit flows to the first current source.
  • the demodulator further includes a comparator; the first input end of the comparator is coupled to the first end of the transconductance circuit, and the first input end of the comparator is also connected to the third signal input through the load module terminal coupling, the second input terminal of the comparator is coupled to the signal source, the output terminal of the comparator is coupled to the signal output terminal, the comparator is used to compare the signal at the first input terminal with the signal at the second input terminal, and output the comparison result. For example, when the signal at the first input terminal is greater than the signal at the second input terminal, the comparator outputs a first digital signal; when the signal at the first input terminal is smaller than the signal at the second input terminal, it outputs a second digital signal.
  • the signal source is a second current source
  • the comparator is a current comparator
  • the load module includes: a first current mirror, a first input terminal of the first current mirror and a first terminal of a transconductance circuit Coupling, the second input end of the first current mirror is coupled with the third signal input end, the output end of the first current mirror is coupled with the first input end of the current comparator; the first current mirror is used for the first transconductance circuit The current mirror at the terminal is amplified, and the amplified current is output to the output terminal of the first current mirror.
  • the demodulator includes a first current mirror
  • the first current mirror can amplify the current image at the first end of the transconductance circuit and output it to the first input end of the current comparator, the first current mirror of the current comparator When the currents at the first input terminal and the second input terminal are compared, the requirements on the sensitivity of the current comparator can be reduced.
  • the transconductance circuit includes a first transistor, a second transistor, and a third transistor; the gate and the second pole of the first transistor are both coupled to the third signal input terminal, and the first pole is coupled to the first Current source coupling; one of the first pole and the second pole of the first transistor is a source, and the other is a drain; the gate of the second transistor is coupled to the first signal input terminal, and the first pole is coupled to the first current source, The second pole is coupled to the first input terminal of the comparator; one of the first pole and the second pole of the second transistor is a source, and the other is a drain; the gate of the third transistor is coupled to the second signal input terminal, and the second transistor is coupled to the second signal input terminal.
  • One pole is coupled with the first current source, and the second pole is coupled with the first input terminal of the comparator; one of the first pole and the second pole of the third transistor is a source, and the other is a drain.
  • the first signal input end when the voltage of the first signal input end is greater than the voltage of the third signal input end, the third transistor is turned off, the first transistor is turned off, the second transistor is turned on, and the third signal input end provides The current signal flows to the first current source through the second transistor (that is, the first end of the transconductance circuit), and flows to the ground terminal through the first current source; when the voltage at the first signal input terminal is lower than the voltage at the third signal input terminal, the third The transistor is turned off, the second transistor is turned off, the first transistor is turned on, and the current signal provided by the third signal input end flows to the first current source through the first transistor (that is, the second end of the transconductance circuit), and passes through the first current source flows to ground.
  • the transconductance circuit further includes a fourth transistor; the gate of the fourth transistor is coupled to the third signal input terminal, the first pole is coupled to the first current source, and the second pole is coupled to the first current source of the comparator.
  • An input terminal is coupled; one of the first pole and the second pole of the fourth transistor is a source, and the other is a drain.
  • a current source and flows to the ground terminal through the first current source; the current signal provided by the third signal input terminal also flows to the first current source through the fourth transistor (ie, the first end of the transconductance circuit), and flows through the first current source Based on this, it can be seen that the addition of the fourth transistor can maintain a continuous current on the first end of the transconductance circuit and speed up the response speed of the operational amplifier.
  • the current comparator includes: a voltage comparator, a first resistor and a second resistor; the first input terminal of the voltage comparator is coupled to the first terminal of the transconductance circuit, and the second terminal of the voltage comparator The input terminal is coupled to the second current source, the output terminal of the voltage comparator is coupled to the signal output terminal; the first resistor is coupled between the first input terminal of the voltage comparator and the ground terminal, and the second resistor is coupled between the first input terminal of the voltage comparator and the first terminal of the voltage comparator. Between the two input terminals and the ground terminal.
  • the voltage comparator is used to compare the voltage of the first input terminal of the voltage comparator with the voltage of the second input terminal of the voltage comparator, so as to output the first digital signal or the second digital signal at the output terminal of the voltage comparator.
  • the first digital signal is output; when the voltage at the first input terminal of the voltage comparator is lower than the voltage at the second input terminal of the voltage comparator, the second digital signal is output Digital signal.
  • the voltage at the first input terminal of the voltage comparator is equal to the current at the first input terminal of the voltage comparator multiplied by the first resistor
  • the voltage at the second input terminal of the voltage comparator is equal to the current at the second input terminal of the voltage comparator multiplied by the second resistance
  • the current comparator further includes: a fifth transistor and a sixth transistor; the fifth transistor and the first resistor are connected in series between the first input terminal and the ground terminal of the voltage comparator, and the fifth transistor Both the gate and the first pole are coupled to the first input terminal of the voltage comparator, and the second pole of the fifth transistor is coupled to the ground terminal; one of the first pole and the second pole of the fifth transistor is a source, and the other is a drain pole; the sixth transistor and the second resistor are connected in series between the second input terminal of the voltage comparator and the ground terminal, the gate and the first pole of the sixth transistor are coupled with the second input terminal of the voltage comparator, and the sixth transistor The second pole of the sixth transistor is coupled to the ground terminal; one of the first pole and the second pole of the sixth transistor is a source, and the other is a drain.
  • the current comparator includes a fifth transistor
  • the fifth transistor can act as a resistor, thereby increasing the voltage of the first input terminal of the voltage comparator, and under the same resistance value, the occupied area of the fifth transistor is smaller than that of a pure resistor. In other words, the area is small.
  • the current comparator includes a sixth transistor
  • the sixth transistor can act as a resistor, thereby increasing the voltage of the second input terminal of the voltage comparator, and under the same resistance value, the occupied area of the sixth transistor is relatively In terms of pure resistance, the area is small.
  • the first current mirror includes a seventh transistor and an eighth transistor; the gate and the first pole of the seventh transistor are coupled to the first end of the transconductance circuit, and the second pole of the seventh transistor is coupled to the first terminal of the transconductance circuit.
  • the third signal input terminal is coupled; one of the first pole and the second pole of the seventh transistor is a source, and the other is a drain; the gate of the eighth transistor is coupled with the gate of the seventh transistor, and the first pole of the eighth transistor
  • the pole is coupled to the first input terminal of the current comparator, and the second pole of the eighth transistor is coupled to the third signal input terminal VE; one of the first pole and the second pole of the eighth transistor is a source, and the other is a drain.
  • the image magnification of the first current mirror can be adjusted by adjusting the aspect ratio of the seventh transistor and the eighth transistor.
  • the current comparator includes: a second current mirror; the input end of the second current mirror is coupled to the second current source, and the output end and the signal output end of the second current mirror are connected to the eighth transistor The first pole is coupled; the second current mirror is used to amplify the current mirror image of the second current source, and output the amplified current to the output terminal of the second current mirror.
  • the current comparator includes the second current mirror, the circuit structure of the current comparator is simpler, the area is smaller, and the cost is lower.
  • the second current mirror includes: a ninth transistor and a tenth transistor; the gate and the first pole of the ninth transistor are coupled to the second current source, and the second pole of the ninth transistor is connected to the ground One of the first pole and the second pole of the ninth transistor is a source, and the other is a drain; the gate of the tenth transistor is coupled with the second current source, and the first pole of the tenth transistor and the signal output end are both It is coupled with the first pole of the eighth transistor; the second pole of the tenth transistor is coupled with the ground terminal; one of the first pole and the second pole of the tenth transistor is a source, and the other is a drain.
  • the current output by the second current source is amplified by the second current mirror and compared with the current output by the first pole of the eighth transistor to generate a corresponding digital signal.
  • the signal output terminal outputs the first digital signal; when the current output by the first pole of the eighth transistor is less than
  • the signal output end outputs a second digital signal.
  • the demodulator further includes: an eleventh transistor, the gate and the first pole of the eleventh transistor are coupled to the second end of the transconductance circuit, and the second pole of the eleventh transistor is coupled to the second end of the transconductance circuit.
  • the third signal input terminal is coupled; one of the first pole and the second pole of the eleventh transistor is a source, and the other is a drain.
  • the eleventh transistor When the eleventh transistor is set in the demodulator, for the first transistor, the fourth transistor, the second transistor and the third transistor in the transconductance circuit, since the second pole of the first transistor is connected to the first transistor through the eleventh transistor
  • the third signal input terminal is coupled, the second pole of the fourth transistor, the second pole of the second transistor and the second pole of the third transistor are coupled with the third signal input terminal through the seventh transistor, so it can be considered that the first transistor of the first transistor is coupled to the third signal input terminal.
  • the voltages of the two poles, the second pole of the fourth transistor, the second pole of the second transistor and the second pole of the third transistor are the same or similar, and the first pole of the first transistor, the first pole of the fourth transistor, the first pole of the third transistor Both the first pole of the second transistor and the first pole of the third transistor are coupled with the first current source, so it can be considered that the first pole of the first transistor, the first pole of the fourth transistor, the first pole of the second transistor and the first pole of the second transistor
  • the voltages of the first poles of the three transistors are the same, so that the Vds of the first transistor, the Vds of the fourth transistor, the Vds of the second transistor and the Vds of the third transistor are the same or similar, so the channel length can be reduced The influence of the modulation effect.
  • the demodulator further includes a filter, and the filter is connected in series between the third signal input end and the ground end. Since the filter can play a role of voltage stabilization, the filter is coupled to the third signal input end, which can ensure that the voltage provided by the third signal input end is stable, thereby improving the performance of the demodulator.
  • the filter includes a capacitor and a third resistor; the capacitor and the third resistor are coupled between the third signal input terminal and the ground terminal.
  • the capacitor and the third resistor can form a filter.
  • the load module includes an impedance
  • the signal source is a reference voltage source
  • the comparator is a voltage comparator
  • the second input terminal of the voltage comparator is coupled to the reference voltage source.
  • the impedance includes a twelfth transistor, the gate and first pole of the twelfth transistor are coupled to the first end of the transconductance circuit, and the second pole of the twelfth transistor is coupled to the third signal input Terminal coupling, wherein, one of the first pole and the second pole of the twelfth transistor is a source, and the other is a drain; or, the impedance includes a resistance, one end of the resistance is coupled to the third signal input end, and the other end is coupled to the transconductance The first end of the circuit is coupled.
  • the near field communication system further includes an antenna, the first signal input end and the second signal input end of the demodulator are both coupled to the antenna, and the antenna transmits the received radio frequency signal to the first signal input terminal and the second signal input terminal.
  • the antenna can provide radio frequency signals to the first signal input terminal and the second signal input terminal.
  • a control method of a near field communication system includes: a rectifier, a demodulator, and a power management unit;
  • the demodulator includes: a transconductance circuit, a first current source, a signal source, and a load module , the first signal input end, the second signal input end, the third signal input end and the signal output end;
  • the signal output end of the rectifier is coupled with the power management unit, the power management unit is coupled with the power input end of the demodulator, and the signal of the rectifier
  • the output terminal is also coupled with the third signal input terminal of the demodulator;
  • the bias terminal of the transconductance circuit is coupled with the first current source, the second terminal of the transconductance circuit is coupled with the third signal input terminal, and the control terminal of the transconductance circuit It is coupled with the first signal input end, the second signal input end and the third signal input end;
  • the above-mentioned control method includes: first, the first signal input end and the second signal input end of the demodul
  • the demodulator further includes a comparator; the first input end of the comparator is coupled to the first end of the transconductance circuit, and the first input end of the comparator is also connected to the third signal input through the load module terminal coupling, the second input terminal of the comparator is coupled to the signal source, and the output terminal of the comparator is coupled to the signal output terminal; the above control method also includes: the comparator compares the signal at the first input terminal with the signal at the second input terminal, and Output the comparison result. For example, when the signal at the first input terminal is greater than the signal at the second input terminal, the first digital signal is output; when the signal at the first input terminal is smaller than the signal at the second input terminal, the second digital signal is output.
  • a near field communication system includes: a rectifier, a demodulator, and a power management unit;
  • the demodulator includes: a transconductance circuit, a first current source, a signal source, a load module, a second A signal input terminal, a third signal input terminal and a signal output terminal; wherein, the first signal input terminal is used to receive radio frequency signals, the signal output terminal of the rectifier is coupled with the power management unit, and the power management unit is connected to the power input terminal of the demodulator Coupling is used to supply power to the demodulator; the signal output end of the rectifier is also coupled with the third signal input end of the demodulator to provide a DC signal for the third signal input end; the bias end of the transconductance circuit is connected to the first Current source coupling, the second terminal of the transconductance circuit is coupled to the third signal input terminal, the control terminal of the transconductance circuit is coupled to both the first signal input terminal and the third signal input terminal;
  • the transconductance circuit is used to flow the current signal provided by the third signal input terminal to the second signal input terminal through the first terminal of the transconductance circuit when the voltage at the first signal input terminal is greater than the voltage at the third signal input terminal. a current source.
  • the transconductance circuit is used to flow the current signal provided by the third signal input terminal to the second terminal through the second terminal of the transconductance circuit when the voltage at the first signal input terminal is lower than the voltage at the third signal input terminal. a current source.
  • the demodulator further includes a comparator; the first input end of the comparator is coupled to the first end of the transconductance circuit, and the first input end of the comparator is also connected to the third signal input through the load module terminal coupling, the second input terminal of the comparator is coupled to the signal source, the output terminal of the comparator is coupled to the signal output terminal, the comparator is used to compare the signal at the first input terminal with the signal at the second input terminal, and output the comparison result.
  • a control method of a near field communication system includes: a rectifier, a demodulator, and a power management unit;
  • the demodulator includes: a transconductance circuit, a first current source, a signal source, a load module, a first signal input terminal, a third signal input terminal and a signal output terminal;
  • the signal output terminal of the rectifier is coupled with the power management unit, and the power management unit is coupled with the power input terminal of the demodulator;
  • the signal output terminal of the rectifier is also coupled with the demodulator
  • the third signal input end of the regulator is coupled;
  • the bias end of the transconductance circuit is coupled with the first current source, the second end of the transconductance circuit is coupled with the third signal input end, and the control end of the transconductance circuit is coupled with the first signal input end and the third signal input end are all coupled;
  • the above-mentioned control method includes: first, the first signal input end of the demodulator receives the radio frequency signal, and the third
  • the demodulator further includes a comparator; the first input end of the comparator is coupled to the first end of the transconductance circuit, and the first input end of the comparator is also connected to the third signal input through the load module terminal coupling, the second input terminal of the comparator is coupled to the signal source, and the output terminal of the comparator is coupled to the signal output terminal; the above control method also includes: the comparator compares the signal at the first input terminal with the signal at the second input terminal, and Output the comparison result.
  • an electronic device in a fifth aspect, includes a printed circuit board and the near field communication system provided in the first aspect or the third aspect.
  • the electronic device has the same technical effect as that of the near field communication system provided by the first aspect above, and reference may be made to relevant descriptions of the first aspect above, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a near field communication system provided by an embodiment of the present application.
  • FIG. 3a is a schematic structural diagram of a demodulator provided by the related art
  • FIG. 3b is a schematic structural diagram of a demodulator provided by another related technology
  • FIG. 4 is a schematic structural diagram of a demodulator provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a demodulator provided in another embodiment of the present application.
  • FIG. 6 is a graph corresponding to each voltage terminal, current terminal, and signal output terminal in the demodulator shown in FIG. 5;
  • Fig. 7a is a schematic structural diagram of a demodulator provided by another embodiment of the present application.
  • FIG. 7b is a schematic structural diagram of a demodulator provided in another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a demodulator provided in another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a demodulator provided in another embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a demodulator provided in another embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a demodulator provided in another embodiment of the present application.
  • Fig. 12a is a schematic structural diagram of a demodulator provided by another embodiment of the present application.
  • Fig. 12b is a schematic structural diagram of a demodulator provided by another embodiment of the present application.
  • FIG. 13 is a schematic flowchart of a demodulator control method provided by an embodiment of the present application.
  • Fig. 14 is a schematic structural diagram of a demodulator provided by another embodiment of the present application.
  • first, second and the like are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • Coupled may be a direct electrical connection or an indirect electrical connection through an intermediary.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • Embodiments of the present application provide an electronic device, which can be, for example, a mobile phone, a tablet computer (pad), a personal digital assistant (personal digital assistant, PDA), a TV, a smart wearable product (for example, a smart watch) , smart bracelet), virtual reality (virtual reality, VR) electronic equipment, augmented reality (augmented reality, AR) electronic equipment, charging small household appliances (such as soybean milk machine, sweeping robot), drones, radar, aerospace equipment and different types of user equipment or electronic equipment such as vehicle equipment; the electronic equipment may also be network equipment such as base stations.
  • the embodiment of the present application does not specifically limit the specific form of the electronic device.
  • FIG. 1 is a schematic structural diagram of an electronic device exemplarily provided in an embodiment of the present application.
  • the electronic device 1 includes components such as a wireless communication system 10 , a processor 11 , a power supply 12 , a memory 13 , an input unit 14 , a display device 15 , and an audio circuit 16 .
  • the structure shown in FIG. 1 does not constitute a specific limitation on the electronic device 1 .
  • the electronic device 1 may include more or fewer components than shown in the illustration, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • processor 11 is the control center of this electronic equipment 1, utilizes various interfaces and lines to connect various parts of the whole electronic equipment, by running or executing the software programs and/or modules stored in the memory 13, and calling the software programs and/or modules stored in the memory 13 Perform various functions of electronic equipment and process data, so as to monitor the electronic equipment as a whole.
  • the processor 11 may include one or more processing units; in some examples, the processor 11 may integrate an application processor (application processor, AP) and a modem processor, wherein the application processor mainly handles operations systems, user interfaces, and applications, etc., the modem processor mainly handles near-field communication. It can be understood that the foregoing modem processor may not be integrated into the processor 11 .
  • the above-mentioned wireless communication system 10 can be used for sending and receiving information or receiving and sending signals during a call.
  • the downlink information from the base station it is processed by the processor 11; in addition, the uplink data is sent to the base station.
  • the wireless communication system 10 above includes a near-field communication system and a far-field communication system.
  • the wireless communication system 10 can communicate with a network and other devices through near-field communication or far-field communication.
  • Near field communication can use any communication standard or protocol, including but not limited to global system of mobile communication (GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access (CDMA), wideband code division multiple access (WCDMA), long term evolution (LTE), e-mail, short message service (short messaging service, SMS), etc.
  • GSM global system of mobile communication
  • general packet radio service general packet radio service
  • GPRS general packet radio service
  • code division multiple access code division multiple access
  • WCDMA wideband code division multiple access
  • LTE long term evolution
  • e-mail short message service
  • SMS short message service
  • the above-mentioned power supply 12 may include a battery, for example, and the power supply 12 may supply power to various components.
  • the power supply 12 may be logically connected to the processor 11 through a power management unit, so as to manage charging, discharging, and power consumption management through the power management unit. Function.
  • the above-mentioned memory 13 may be used to store software programs and modules, and the processor 11 executes various functional applications and data processing of the electronic device by running the software programs and modules stored in the memory 13 .
  • the memory 13 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playback function, an image playback function, etc.); The created data (such as audio data, image data, phone book, etc.) etc.
  • the memory 13 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.
  • the above-mentioned input unit 14 can be used to receive input numbers or character information, and generate key signal input related to user settings and function control of the electronic device.
  • the input unit 14 may include a touch screen 141 and other input devices 142 .
  • the touch screen 141 also referred to as a touch panel, can collect touch operations of the user on or near the touch screen (for example, the user uses any suitable object or accessory such as a finger or a stylus on the touch screen 141 or near the touch screen 141), and according to The preset programs drive the corresponding connected electronic devices.
  • Other input devices 142 may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control keys, power switch keys, etc.), trackballs, mice, and joysticks.
  • the above-mentioned display device 15 can be used to display information input by the user or provided to the user, as well as various menus of the electronic device.
  • the display device 15 may include a display panel 151, and the display panel 151 may be a liquid crystal display (liquid crystal display, LCD) panel, an organic light emitting diode (organic light emitting diode, OLED) display panel, or a Micro-LED (miniature light emitting diode) display panel.
  • the touch screen 141 can cover the display panel 151.
  • the touch screen 141 When the touch screen 141 detects a touch operation on or near the touch screen 141, it is sent to the processor 11 to determine the type of the touch event, and then the processor 11 displays a touch event on the display panel according to the type of the touch event. Corresponding visual output is provided on 151 .
  • the touch screen 141 and the display panel 151 are used as two independent components to realize the input and output functions of the device, in some embodiments, the touch screen 141 and the display panel 151 can be integrated to realize the input of the device. and output functions.
  • the audio circuit 16, the speaker 161 and the microphone 162 are used to provide an audio interface between the user and the electronic device.
  • the audio circuit 16 can transmit the electrical signal converted from the received audio data to the loudspeaker 161, and the loudspeaker 161 converts it into a sound signal output; After being received, it is converted into audio data, and then the audio data is output to the near field communication system to be sent to another electronic device, or the audio data is output to the memory 13 for further processing.
  • the electronic device shown in FIG. 1 may also include various sensors.
  • a gyro sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc. which will not be repeated here.
  • the electronic device shown in Figure 1 may also include a wireless fidelity (wireless fidelity, WiFi) module, a bluetooth module, etc., which will not be repeated here.
  • the above-mentioned electronic device 1 may also include printed circuit boards (printed circuit boards, PCB), and some chips or electronic devices in the electronic device 1 such as processor 11, memory 13, etc. may be arranged on the PCB.
  • PCB printed circuit boards
  • Embodiments of the present application also provide a near field communication (near field communication, NFC) system, which can be used as a kind of wireless communication system 10 and applied to the above-mentioned electronic device 1 .
  • the near field communication system 10A may include a rectifier (rectifier) 100, a demodulator (demodulator) 200, a load modulator (load modulator) 300, a clock data recovery (clock and data recovery, CDR) circuit 400 , power management unit (power management unit, PMU) 500, digital (digital) processing circuit 600, and other modules 700 and other parts, other modules can include radio frequency limiter (radio frequency limiter, RF limiter) module, field monitoring (filed detector) module, security module (secure element, SE), etc.
  • radio frequency limiter radio frequency limiter
  • RF limiter field monitoring
  • SE secure element
  • the near field communication system 10A may further include an antenna (antenna) 800 , a matching network (match) and/or a filter (filter) 900 and other parts.
  • the antenna 800 may be coupled with the rectifier 100, the demodulator 200, the load modulator 300, the clock data recovery circuit 400, etc. through a matching network and/or a filter 900.
  • the rectifier 100, demodulator 200, load modulator 300, clock data recovery circuit 400, power management unit 500, digital processing circuit 600, and other modules 700 such as radio frequency limiting module, field monitoring module, security module etc.
  • the rectifier 100, demodulator 200, load modulator 300, clock data recovery circuit 400, power management unit 500, digital processing circuit 600, and other modules 700 can be integrated on the same radio frequency chip, or can be integrated on different radio frequency chips.
  • 2 is integrated with a rectifier 100, a demodulator 200, a load modulator 300, a clock data recovery circuit 400, a power management unit 500, a digital processing circuit 600, and other modules 700 such as a radio frequency limiting module, a field monitoring module, and a security module.
  • the radio frequency chip can be arranged on the printed circuit board.
  • the radio frequency chip can include a plurality of input and output ports (input output pad, IO pad) 10a, and the antenna 800 can be connected with the input and output ports on the radio frequency chip through a matching network and/or filter 900 10a coupling, the rectifier 100, demodulator 200, load modulator 300, clock data recovery circuit 400, etc. on the radio frequency chip can be coupled with the input and output port 10a, and then receive the signal received by the antenna 800, or transmit a signal to the antenna 800.
  • the radio frequency chip may further include a port 10b coupled to the ground terminal. In some examples, as shown in FIG. 2 , the port 10b coupled to the ground terminal may be coupled to the ground terminal GND through a capacitor C.
  • the rectifier 100 is coupled with the antenna 800, and is used to convert the radio frequency signal received by the antenna 800 into DC energy for use by other modules or other chips inside the radio frequency chip.
  • the signal output terminal of the rectifier 100 is coupled with the power management unit 500, and the power management unit 500 is coupled with other modules inside the chip or power input terminals of other chips, such as the demodulator 200, the load modulator 300, the clock data recovery circuit 400,
  • the power input terminals of the digital processing circuit 600, the radio frequency limiting module, the field monitoring module, the safety module, etc. or other chips are coupled, and the power management unit 500 is used to supply power to other modules or other chips, such as for the solution in the radio frequency chip.
  • the demodulator 200 is coupled to the antenna 800 and to the digital processing circuit 600 for demodulating the received modulated signal into a digital signal and transmitting the digital signal to the digital processing circuit 600 for further demodulation.
  • the load modulator 300 is coupled with the digital processing circuit 600 and the antenna 800, and the load modulator 300 is used as a transmitting module for load-modulating the digital signal output by the digital processing circuit 600 and outputting it to the antenna 800, and then transmitting the signal through the antenna 800 .
  • the clock data recovery circuit 400 is coupled with the antenna 800 and the digital processing circuit 600, and is used to convert the radio frequency signal received by the antenna 800 into a clock signal of the same frequency, and then transmit the clock signal to the digital processing circuit 600, so that the digital processing circuit 600 work with a clock signal.
  • the digital processing circuit 600 is used for demodulation and radio frequency chip control.
  • the radio frequency limiting module is coupled with the antenna 800, and is used to prevent the signal of the antenna 800 from being too large, exceeding the withstand voltage capability of the chip and breaking down the chip.
  • the field monitoring module is used to monitor whether the antenna 800 has a signal.
  • this demodulator 200 In low-speed communication, such as below 848kbps, the unidirectional conduction characteristics of diodes are now commonly used to realize envelope detection and demodulation. However, the sensitivity of this demodulator 200 is very low, usually only the signal with a modulation depth of about 8% can be demodulated.
  • the demodulator 200 includes a programmable gain amplifier (programmable gain amplifier, PGA) and analog Digital converter (analog-to-digital converter, ADC).
  • VAC in Figure 3a represents the antenna
  • the programmable gain amplifier PGA is coupled with the antenna VAC
  • the antenna VAC provides a radio frequency signal to the programmable gain amplifier PGA
  • the programmable gain amplifier PGA is coupled with the analog-to-digital converter ADC
  • the analog-to-digital converter ADC is used to output digital signals.
  • the demodulator 200 includes an envelope detector (envelope detector), a source follower (source follower), a differentiator (differentiators), a comparator ( comparators) and control logic circuit (ctrl logic), the first signal input terminal VC, the second signal input terminal VD and the signal output terminal Dout; wherein, the first signal input terminal VC and the second signal input terminal VD are used for receiving the antenna
  • the radio frequency signal received, and the radio frequency signal received by the first signal input terminal VC and the radio frequency signal received by the second signal input terminal VD are a pair of differential signals, the first signal input terminal VC and the second signal input terminal VD are connected with the package Coupling of envelope detector, coupling of envelope detector and source follower, coupling of source follower and differentiator, coupling of differentiator and comparator, coupling of comparator and control logic circuit, coupling of control logic circuit and signal output terminal Dout, first The signal input terminal VC and the second signal input terminal
  • the demodulator 200 provided in Figure 3b is composed of an envelope detector, a source follower, a differentiator, a comparator, and a control logic circuit
  • the envelope detector, a source follower, a differentiator, and a comparator can all be It is composed of a simple circuit, so compared with the demodulator 200 provided in FIG. 3a, the demodulator 200 provided in FIG. 3b occupies a smaller area and has lower cost.
  • the sensitivity of the demodulator 200 provided in Figure 3b of the related art has been improved, the demodulator 200 still cannot demodulate signals with low modulation depth, for example, cannot demodulate 6.8Mbps signals in the VHBR protocol, that is to say The sensitivity of the demodulator 200 is still not high enough.
  • an embodiment of the present application provides a near field communication system 10A.
  • the near field communication system 10A includes a demodulator 200, such as As shown in FIG.
  • the demodulator 200 in the near field communication system 10A includes: a transconductance circuit 201, a first current source Iref1, a signal source Ref, a comparator 202, a load module 203, a first signal input terminal VC, a second The signal input terminal VD, the third signal input terminal VE and the signal output terminal Dout; wherein, the first signal input terminal VC and the second signal input terminal VD are used to receive radio frequency signals, and the first signal input terminal VC and the second signal input terminal The radio frequency signal received by terminal VD is a pair of differential signals.
  • the signal output end of the rectifier 100 is also coupled to the third signal input end VE of the demodulator 200 for providing a DC signal to the third signal input end VE.
  • the radio frequency signal received by the first signal input terminal VC and the second signal input terminal VD contains communication information, the peak value of the radio frequency signal received by the first signal input terminal VC, the peak value of the radio frequency signal received by the second signal input terminal VD
  • the peak value of the received radio frequency signal is greater than the value of the DC signal received by the third signal input terminal VE, and the peak value of the radio frequency signal received by the first signal input terminal VC, the peak value of the radio frequency signal received by the second signal input terminal VD
  • the value is relatively close to the value of the DC signal received by the third signal input terminal VE.
  • both the first signal input terminal VC and the second signal input terminal VD of the demodulator 200 are coupled to the antenna 800, and the antenna 800 can transmit the received radio frequency The signal is transmitted to the first signal input VC and the second signal input VD.
  • the function of the rectifier 100 is to convert the radio frequency signal (for example, the radio frequency signal received from the antenna 800) into a DC signal
  • the third signal input terminal VE of the demodulator 200 is connected with the signal output of the rectifier 100 terminal coupling for receiving the DC signal output from the signal output terminal of the rectifier 100 .
  • the first signal input terminal VC and the second signal input terminal VD of the demodulator 200 receive the radio frequency signal transmitted by the antenna 800, and the rectifier 100 converts the radio frequency signal received from the antenna 800 into a DC signal , and then provided to the third signal input terminal VE of the demodulator 200, so the peak value of the radio frequency signal received by the first signal input terminal VC, the peak value of the radio frequency signal received by the second signal input terminal VD and the third signal input terminal The value of the DC signal received by the VE is relatively close.
  • the bias terminal of the above-mentioned transconductance circuit 201 is coupled with the first current source Iref1
  • the first terminal of the transconductance circuit 201 is coupled with the first input terminal a of the comparator 202
  • the second terminal of the transconductance circuit 201 terminal is coupled to the third signal input terminal VE
  • the control terminal of the transconductance circuit 201 is coupled to the first signal input terminal VC, the second signal input terminal VD and the third signal input terminal VE.
  • one end of the first current source Iref1 is coupled to the bias end of the transconductance circuit 201 , and the other end may be coupled to the ground end GND.
  • the first terminal of the transconductance circuit 201 may be directly coupled to the first input terminal a of the comparator 202; the first terminal of the transconductance circuit 201 may also be indirectly coupled to the first input terminal a of the comparator 202 , that is, the first terminal of the transconductance circuit 201 and the first input terminal a of the comparator 202 are coupled together through other circuit structures.
  • the transconductance circuit 201 is used to select whether to use the current signal provided by the third signal input terminal VE according to the comparison result of the voltage of the first signal input terminal VC or the voltage of the second signal input terminal VD and the voltage of the third signal input terminal VE
  • the first current source Iref1 flows through the first end of the transconductance circuit 201 or the second end of the transconductance circuit 201 .
  • the transconductance circuit 201 is used to convert the current provided by the third signal input terminal VE to The signal flows to the first current source Iref1 through the first terminal of the transconductance circuit 201 , and flows to the ground terminal GND through the first current source Iref1 .
  • the transconductance circuit 201 is used to convert the voltage provided by the third signal input terminal VE to The current signal flows to the first current source Iref1 through the second terminal of the transconductance circuit 201 , and flows to the ground terminal GND through the first current source Iref1 .
  • the current signal provided by the third signal input terminal VE may also flow to the first current source Iref1 through the first terminal of the transconductance circuit 201 , and flow to the ground terminal GND through the first current source Iref1 .
  • the first input terminal a of the comparator 202 is also coupled to the third signal input terminal VE through the load module 203, the second input terminal b of the comparator 202 is coupled to the signal source Ref, and the output terminal of the comparator 202 is coupled to To the signal output terminal Dout, the comparator 202 is used to compare the signal at the first input terminal a with the signal at the second input terminal b, and output the comparison result.
  • the comparator 202 is used to compare the signal at the first input terminal a with the signal at the second input terminal b, and output the first input terminal b when the signal at the first input terminal a is greater than the signal at the second input terminal b.
  • a digital signal such as "1”; when the signal at the first input terminal a is smaller than the signal at the second input terminal b, a second digital signal such as "0" is output.
  • the first digital signal is "1" and the second digital signal is "0".
  • the demodulator 200 is exemplarily described below through several embodiments.
  • the load module 203 includes a first current mirror 203A, the signal source Ref is a second current source Iref2, the comparator 202 is a current comparator 202A, and the second current mirror of the current comparator 202A
  • the input terminal b is coupled to the second current source Iref2, and the current comparator 202A is used to compare the current of the first input terminal a with the current of the second input terminal b, and output the comparison result.
  • the current comparator 202A is used to compare the current of the first input terminal a with the current of the second input terminal b, and when the current of the first input terminal a is greater than the current of the second input terminal b, output the second A digital signal "1"; when the current at the first input terminal a is smaller than the current at the second input terminal b, a second digital signal "0" is output.
  • the signal source Ref is the second current source Iref2
  • one end of the second current source Iref2 is coupled to the second input terminal b of the current comparator 202A, and the other end may be coupled to the third signal input terminal VE coupling.
  • the first input end c of the first current mirror 203A is coupled to the first end of the transconductance circuit 201
  • the second input end d of the first current mirror 203A is coupled to the third signal input end VE
  • the first The output terminal e of a current mirror 203A is coupled with the first input terminal a of the current comparator 202A
  • the first current mirror 203A is used to amplify the current image of the first terminal of the transconductance circuit 201, and output the amplified current to
  • the output terminal e of the first current mirror 203A outputs the amplified current to the first input terminal a of the current comparator 202A.
  • the first terminal of the transconductance circuit 201 is coupled to the first input terminal a of the current comparator 202A through the first current mirror 203A.
  • the current at the first input terminal a of the current comparator 202A is a multiple of the current at the first terminal of the transconductance circuit 201 .
  • the load module 203 includes a first current mirror 203A
  • the first current mirror 203A can amplify the current image at the first end of the transconductance circuit 201 and output it to the first input terminal a of the current comparator 202A
  • this can reduce the requirement on the sensitivity of the current comparator 202A.
  • the above-mentioned first current mirror 203A includes a seventh transistor M7 and an eighth transistor M8; the gate and the first pole of the seventh transistor M7 are coupled to the first end of the transconductance circuit 201, The second pole of the seventh transistor M7 is coupled to the third signal input terminal VE; one of the first pole and the second pole of the seventh transistor M7 is a source, and the other is a drain; the gate of the eighth transistor M8 is connected to the seventh The gate of the transistor M7 is coupled, the first pole of the eighth transistor M8 is coupled to the first input terminal a of the current comparator 202A, the second pole of the eighth transistor M8 is coupled to the third signal input terminal VE; the eighth transistor M8 One of the first pole and the second pole is a source, and the other is a drain.
  • the gate of the seventh transistor M7 is coupled to the first pole, and the gate of the eighth transistor M8 is used as the first input terminal c of the first current mirror 203A, the second pole of the seventh transistor M7, and the gate of the eighth transistor M8 are coupled together.
  • the second poles of the eight transistors M8 are coupled together to serve as the second input terminal d of the first current mirror 203A, and the first poles of the eighth transistor M8 are used as the output terminal e of the first current mirror 203A.
  • the mirror magnification of the first current mirror 203A can be adjusted by adjusting the aspect ratio of the seventh transistor M7 and the eighth transistor M8.
  • the seventh transistor M7 and the eighth transistor M8 may be, for example, MOS transistors.
  • the seventh transistor M7 and the eighth transistor M8 are P-type transistors. Taking the seventh transistor M7 as an example, for a P-type transistor, when a low level signal is provided to the gate of the seventh transistor M7, the seventh transistor M7 is turned on.
  • the current I Gm*(VC-VE) of the first end of the transconductance circuit 201; the voltage at the second signal input terminal VD was greater than
  • the magnitude of the current of the first input terminal a of the current comparator 202A is the same as that of the first terminal a of the transconductance circuit 201. related to the size of the current. Since the second input terminal b of the current comparator 202A is coupled to the second current source Iref2, the current of the second input terminal b of the current comparator 202A is related to the current of the second current source Iref2.
  • the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is greater than the voltage at the third signal input terminal VE, and the voltage at the first signal input terminal VC Or when the difference between the voltage of the second signal input terminal VD and the voltage of the third signal input terminal VE is greater than or equal to the threshold voltage, the current of the first input terminal a of the current comparator 202A is greater than the current of the second input terminal of the current comparator 202A b current.
  • the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is greater than the voltage at the third signal input terminal VE, and the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is consistent with the third signal
  • the first signal of the current comparator 202A The current at the first input terminal a is smaller than the current at the second input terminal b of the current comparator 202A.
  • the threshold voltage can be set as required.
  • the voltage of the first signal input terminal VC and the voltage of the second signal input terminal VD are both lower than the voltage of the third signal input terminal VE, since the current signal provided by the third signal input terminal VE mainly passes through the transconductance
  • the second terminal of the circuit 201 flows to the first current source Iref1, or, the current signal provided by the third signal input terminal VE partly flows to the first current source Iref1 through the second terminal of the transconductance circuit 201, and partly passes through the second terminal of the transconductance circuit 201.
  • One end flows to the first current source Iref1, so the current at the first end of the transconductance circuit 201 is relatively small, and the first end of the transconductance circuit 201 is coupled with the first input terminal a of the current comparator 202A, so the current comparator 202A
  • the current at the first input terminal a of the current comparator 202A is smaller than the current at the second input terminal b of the current comparator 202A, and at this time, the output terminal Dout of the current comparator 202A outputs a second digital signal "0".
  • the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is greater than the voltage at the third signal input terminal VE
  • the voltage at the first signal input terminal VC is greater than the voltage at the third signal input terminal VE as
  • the first one the difference between the voltage of the first signal input terminal VC and the voltage of the third signal input terminal VE is greater than or equal to the threshold voltage
  • the current signal provided by the third signal input terminal VE mainly passes through
  • Fig. 6 comprises three graphs of relation, is respectively upper graph, middle graph and lower graph;
  • the relationship diagram of the voltage of the signal input terminal VE the middle diagram shows the current Iout of the first input terminal a of the current comparator 202A, and the current of the second input terminal b of the current comparator 202A, that is, the current of the second current source Iref2;
  • the figure shows the output result of the input terminal Dout of the current comparator 202A, where the output result is represented by a digital signal.
  • the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is greater than the voltage at the third signal input terminal VE, and the voltage at the first signal input terminal VC or the second signal input terminal
  • the difference between the voltage of VD and the voltage of the third signal input terminal VE is greater than or equal to the threshold voltage
  • the current Iout of the first input terminal a of the current comparator 202A is greater than the current Iref2 of the second input terminal b of the current comparator 202A
  • the output terminal Dout of the current comparator 202A outputs the first digital signal “1”.
  • the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is greater than the voltage at the third signal input terminal VE, and the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD is consistent with the third signal
  • the first signal of the current comparator 202A The current Iout of the first input terminal a is smaller than the current Iref2 of the second input terminal b of the current comparator 202A, and the output terminal Dout of the current comparator 202A outputs the second digital signal “0”.
  • the first signal input terminal VC and the second signal input terminal VD of the demodulator 200 receive the radio frequency signal transmitted by the antenna 800
  • the third signal input terminal VE of the demodulator 200 is coupled with the output terminal of the rectifier 100, and is used to receive the DC signal converted by the rectifier 100 from the radio frequency signal received from the antenna 800, so it can be seen with reference to FIG. 6 that the first The peak value of the radio frequency signal received by the first signal input terminal VC, the peak value of the radio frequency signal received by the second signal input terminal VD and the value of the DC signal received by the third signal input terminal VE are relatively close.
  • the demodulator 200 provided in the embodiment of the present application since the voltage of the third signal input terminal VE is used as a reference, the voltage of the first signal input terminal VC, and the voltage of the second signal input terminal The voltage of VD is compared, and the peak value of the radio frequency signal received by the first signal input terminal VC, the peak value of the radio frequency signal received by the second signal input terminal VD and the value of the DC signal received by the third signal input terminal VE are relatively close , so the demodulator 200 provided in the embodiment of the present application only quantizes the useful signal during demodulation, so that the demodulator 200 can have a higher sensitivity.
  • the demodulator 200 can quantize the For example, the 6.8 Mbps signal in the VHBR protocol can be demodulated.
  • the demodulator 200 provided in the embodiment of the present application has higher sensitivity.
  • the demodulator 200 provided by the embodiment of the present application is mainly composed of the transconductance circuit 201 and the current comparator 202A, etc.
  • the demodulator 200 provided by the embodiment of the present application occupies a smaller area and lowers the cost.
  • the demodulator 200 provided in the embodiment of the present application occupies a smaller area and lower cost.
  • the above-mentioned transconductance circuit 201 may include the following implementation manners as an example:
  • the above-mentioned transconductance circuit 201 includes a first transistor M1, a second transistor M2 and a third transistor M3; the gate and the second pole of the first transistor M1 are connected to the third signal input terminal VE coupling, the first pole of the first transistor M1 is coupled to the first current source Iref1; one of the first pole and the second pole of the first transistor M1 is a source, and the other is a drain; the gate of the second transistor M2 is connected to The first signal input terminal VC is coupled, the first pole of the second transistor M2 is coupled to the first current source Iref1, the second pole of the second transistor M2 is coupled to the first input terminal a of the comparator 202; the second pole of the second transistor M2 is coupled to the first input terminal a of the comparator 202; One of the first pole and the second pole is a source, and the other is a drain; the gate of the third transistor M3 is coupled to the second signal input terminal VD, the
  • the above-mentioned transconductance circuit 201 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; the gate and the second pole of the first transistor M1 are connected to The third signal input terminal VE is coupled, the first pole of the first transistor M1 is coupled to the first current source Iref1; one of the first pole and the second pole of the first transistor M1 is a source, and the other is a drain; the second transistor The gate of M2 is coupled to the first signal input terminal VC, the first pole of the second transistor M2 is coupled to the first current source Iref1, and the second pole of the second transistor M2 is coupled to the first input terminal a of the comparator 202; One of the first pole and the second pole of the second transistor M2 is a source, and the other is a drain; the gate of the third transistor M3 is coupled to the second signal input terminal VD, and the first pole of the third transistor M3 is connected to the first
  • the difference between the above-mentioned first method and the second method is that the second method has a fourth transistor M4 more than the first method, and the transconductance circuit 201 is used as the second method below, namely
  • the transconductance circuit 201 includes the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 as an example to introduce the transconductance circuit 201.
  • the circuit 201 is an introduction of the second mode.
  • the second pole of the second transistor M2, the second pole of the third transistor M3 and the second pole of the fourth transistor M4 are coupled together to serve as the first terminal of the transconductance circuit 201;
  • the first transistor The first pole of M1, the first pole of the second transistor M2, the first pole of the third transistor M3 and the first pole of the fourth transistor M4 are coupled together to serve as the bias terminal of the transconductance circuit 201;
  • the first The second terminal of the transistor M1 is used as the second terminal of the transconductance circuit 201 .
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be, for example, metal-oxide-semiconductor field-effect transistors, referred to as metal-oxide-semiconductor field-effect transistors (metal-oxide-semiconductor field-effect transistor, MOSFET), also known as MOS tube.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 are N-type transistors.
  • the first transistor M1 for an N-type transistor, when a high level signal is provided to the gate of the first transistor M1, the first transistor M1 is turned on.
  • the transconductance circuit 201 includes but is not limited to the above first and second methods, and may also include a series or parallel connection with the first transistor M1, the fourth transistor M4, the second transistor M2 and the third transistor M3 other one or more transistors.
  • the transconductance circuit 201 including the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 as an example, the working process of the transconductance circuit 201 will be described below: the voltage at the first signal input terminal VC is greater than When the voltage of the third signal input terminal VE is high, the third transistor M3 is turned off, the first transistor M1 and the fourth transistor M4 are turned off, the second transistor M2 is turned on, and the current signal provided by the third signal input terminal VE passes through the second transistor M2 (that is, the first end of the transconductance circuit 201) flows to the first current source Iref1, and flows to the ground terminal GND through the first current source Iref1; when the voltage of the first signal input terminal VC is lower than the voltage of the third signal input terminal VE , the third transistor M3 is turned off, the second transistor M2 is turned off, the first transistor M1 and the fourth transistor M4 are turned on, and the current signal provided by the third signal input terminal VE passes through the first transistor M
  • the current signal provided by the third signal input terminal VE flows to the first current source Iref1 through the second transistor M2 (that is, the first terminal of the transconductance circuit 201), and flows to the ground terminal GND through the first current source Iref1,
  • the voltage difference between the first signal input terminal VC and the third signal input terminal VE is greater than or equal to the threshold voltage
  • the current of the first input terminal a of the current comparator 202A is greater than the current of the second input terminal b of the current comparator 202A; the difference between the voltage of the first signal input terminal VC and the voltage of the third signal input terminal VE is less than the threshold voltage , the current at the first input terminal a of the current comparator 202A is smaller than the current at the second input terminal b of the current comparator 202A.
  • the current signal provided at the third signal input end VE flows to the first current source Iref1 through the first transistor M1 (that is, the second end of the transconductance circuit 201), and flows to the ground terminal GND through the first current source Iref1; the third signal input
  • the current signal provided by terminal VE also flows to the first current source Iref1 through the fourth transistor M4 (that is, the first terminal of the transconductance circuit 201), and flows to the ground terminal GND through the first current source Iref1, the first current comparator 202A
  • the current at the input terminal a is smaller than the current at the second input terminal b of the current comparator 202A.
  • the second transistor M2 is turned off, the first transistor M1 and the fourth transistor M4 are turned off, the third transistor M3 is turned on, and the second transistor M2 is turned off.
  • the current signal provided by the three-signal input terminal VE flows to the first current source Iref1 through the third transistor M3 (ie, the first terminal of the transconductance circuit 201), and flows to the ground terminal GND through the first current source Iref1; at the second signal input terminal
  • the second transistor M2 is turned off, the third transistor M3 is turned off, the first transistor M1 and the fourth transistor M4 are turned on, and the current signal provided by the third signal input terminal VE
  • Flow to the first current source Iref1 through the first transistor M1 that is, the second end of the transconductance circuit 201
  • the current signal provided by the third signal input terminal VE also passes through the fourth transistor M4 (that is, the first terminal of the transconductance circuit 201 ) flows to the first current source Iref1 , and flows to the ground terminal GND through the first current source Iref
  • the transconductance circuit 201 since the transconductance circuit 201 includes the first transistor M1, the second transistor M2 and the third transistor M3, and does not include the fourth transistor M4, the first signal input terminal VC
  • the current signal provided by the third signal input terminal VE flows to the first current source Iref1 through the first transistor M1 (that is, the second terminal of the transconductance circuit 201), and passes through the first current The source Iref1 flows to the ground terminal GND;
  • the transconductance circuit 201 includes the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, the voltage at the first signal input terminal VC is smaller than the third signal input
  • the current signal provided by the third signal input terminal VE flows to the first current source Iref1 through the first transistor M1 (that is, the second terminal of the transconductance circuit 201), and flows to the ground terminal GND through the first current source Ire
  • the transconductance circuit 201 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, and the first current mirror 203A includes a seventh transistor M7 and an eighth transistor M8, the first transistor M1
  • the gate of the gate and the gate of the fourth transistor M4 are coupled with the third signal input terminal VE
  • the gate of the second transistor M2 is coupled with the first signal input terminal VC
  • the gate of the third transistor M3 is coupled with the second signal input terminal VD Coupling, based on the above, it can be seen that the voltages of the first signal input terminal VC, the second signal input terminal VD and the third signal input terminal VE are similar, that is, it can be roughly considered that the first transistor M1, the fourth transistor M4, the second transistor M2 and the third The gate voltages of the three transistors M3 are the same.
  • the first pole of the first transistor M1, the first pole of the fourth transistor M4, the first pole of the second transistor M2 and the first pole of the third transistor M3 are all coupled with the first current source Iref1, it can be considered that The voltages of the first electrodes of the first transistor M1, the first electrodes of the fourth transistor M4, the first electrodes of the second transistor M2 and the first electrodes of the third transistor M3 are the same.
  • the fourth transistor M4 since the second pole of the fourth transistor M4, the second pole of the second transistor M2 and the second pole of the third transistor M3 are coupled with the third signal input terminal VE through the seventh transistor M7, it can be considered that the fourth transistor M4
  • the voltages of the second pole of the second transistor M2 and the second pole of the third transistor M3 are the same, considering that if the second pole of the first transistor M1 is directly coupled with the third signal input terminal VE, then The voltage of the second pole of the first transistor M1 will be different from the voltage of the second pole of the fourth transistor M4, the second pole of the second transistor M2 and the voltage of the second pole of the third transistor M3, that is to say, the voltage of the second pole of the first transistor M1
  • the Vds of the fourth transistor M4, the Vds of the second transistor M2 and the Vds of the third transistor M3 will be different, which will lead to channel length modulation effect.
  • the second terminal of the transconductance circuit 201 is coupled, in the case that the transconductance circuit 201 includes the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, that is, the gate of the eleventh transistor M11 and the first transistor M11 One pole is coupled to the second pole of the first transistor M1, and the second pole of the eleventh transistor M11 is coupled to the third signal input terminal VE; wherein, one of the first pole and the second pole of the eleventh transistor M11 is a source pole and one drain.
  • the eleventh transistor M11 may be, for example, a MOS transistor.
  • the eleventh transistor M11 is a P-type transistor.
  • the eleventh transistor M11 is provided in the demodulator 200, for the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 in the transconductance circuit 201, since the first transistor M1 The two poles are coupled with the third signal input terminal VE through the eleventh transistor M11, the second pole of the fourth transistor M4, the second pole of the second transistor M2 and the second pole of the third transistor M3 are connected with the first pole through the seventh transistor M7.
  • the three-signal input terminal VE is coupled, so it can be considered that the voltages of the second pole of the first transistor M1, the second pole of the fourth transistor M4, the second pole of the second transistor M2, and the second pole of the third transistor M3 are the same or similar , and the first pole of the first transistor M1, the first pole of the fourth transistor M4, the first pole of the second transistor M2 and the first pole of the third transistor M3 are all coupled with the first current source Iref 1, so it can be considered
  • the voltages of the first pole of the first transistor M1, the first pole of the fourth transistor M4, the first pole of the second transistor M2 and the first pole of the third transistor M3 are the same, so that the Vds of the first transistor M1 , the Vds of the fourth transistor M4, the Vds of the second transistor M2 and the Vds of the third transistor M3 are the same or similar, so the influence of the channel length modulation effect can be reduced.
  • the demodulator 200 further includes a filter 204 coupled between the third signal input terminal VE and the ground terminal GND.
  • the filter 204 can play the role of voltage stabilization, the filter 204 is coupled at the third signal input terminal VE, which can ensure that the voltage provided by the third signal input terminal VE is stable, which is conducive to improving the performance of the demodulator 200. performance.
  • the filter 204 may include a capacitor C and a third resistor R3; the capacitor C and the third resistor R3 are connected in series between the third signal input terminal VE and the ground terminal GND.
  • the current comparator 202A in the demodulator 200 can be implemented in the following ways for example.
  • the current comparator 202A may include: a voltage comparator (voltage comparator) 2021, a first resistor R1 and a second resistor R2; the first input terminal of the voltage comparator 2021 and the first terminal of the transconductance circuit 201 Coupling, the second input terminal of the voltage comparator 2021 is coupled with the second current source Iref2, the output terminal of the voltage comparator 2021 is coupled to the signal output terminal Dout; the first resistor R1 is coupled between the first input terminal of the voltage comparator 2021 and ground The second resistor R2 is coupled between the second input terminal of the voltage comparator 2021 and the ground terminal GND.
  • a voltage comparator voltage comparator
  • the first input terminal of the voltage comparator 2021 is used as the first input terminal of the current comparator 202A
  • the second input terminal of the voltage comparator 2021 is used as the second input terminal of the current comparator 202A
  • the voltage The output terminal of the comparator 2021 is used as the output terminal of the current comparator 202A.
  • first input terminal of the voltage comparator 2021 and the first terminal of the transconductance circuit 201 may be directly coupled, or may be coupled together through other circuit structures such as the first current mirror 203A.
  • first input terminal of the voltage comparator 2021 is coupled to the first terminal of the transconductance circuit 201 through the first current mirror 203A
  • the first input terminal of the voltage comparator 2021 is coupled to the output terminal of the first current mirror 203A.
  • the voltage comparator 2021 is used to compare the voltage at the first input terminal of the voltage comparator 2021 with the voltage at the second input terminal of the voltage comparator 2021, so as to output the first digital signal "" at the output terminal of the voltage comparator 2021 1", or the second digital signal "0", when the voltage at the first input terminal of the voltage comparator 2021 is greater than the voltage at the second input terminal of the voltage comparator 2021, the first digital signal "1" is output; when the voltage comparator 2021 When the voltage at the first input terminal of the voltage comparator 2021 is lower than the voltage at the second input terminal of the voltage comparator 2021, a second digital signal “0” is output.
  • the voltage at the first input terminal of the voltage comparator 2021 is equal to the current at the first input terminal of the voltage comparator 2021 multiplied by the first resistor R1
  • the voltage at the second input terminal of the voltage comparator 2021 is equal to the second input terminal of the voltage comparator 2021 The current at the terminal is multiplied by the second resistor R2.
  • the size of the first resistor R1 and the size of the second resistor R2 may be equal or not.
  • the voltage of the first input terminal of the voltage comparator 2021 as an example, when the current of the first input terminal of the voltage comparator 2021 is constant, if the resistance value of the first resistor R1 is increased, the first voltage of the voltage comparator 2021 can be increased.
  • the resistance value of the first resistor R1 needs to be larger, which will result in a larger area occupied by the first resistor R1. Based on this, in some examples, as shown in FIG.
  • the current comparator 202A further includes: a fifth transistor M5 and a sixth transistor M6; the fifth transistor M5 and the first resistor R1 are connected in series at the first Between the input terminal and the ground terminal GND, the gate and the first pole of the fifth transistor M5 are coupled to the first input terminal of the voltage comparator 2021, and the second pole of the fifth transistor M5 is coupled to the ground terminal GND; the fifth transistor One of the first pole and the second pole of M5 is a source, and the other is a drain; the sixth transistor M6 and the second resistor R2 are connected in series between the second input terminal of the voltage comparator 2021 and the ground terminal GND, and the sixth transistor Both the gate and the first pole of M6 are coupled to the second input terminal of the voltage comparator 2021, and the second pole of the sixth transistor M6 is coupled to the ground terminal GND; one of the first pole and the second pole of the sixth transistor M6 is source and one drain.
  • the gate and the first pole of the fifth transistor M5 may be coupled to the first input terminal of the voltage comparator 2021 through the first resistor R1, and the second pole of the fifth transistor M5 is directly coupled to the ground terminal GND;
  • the gate and first pole of the fifth transistor M5 are directly coupled to the first input terminal of the voltage comparator 2021, and the second pole of the fifth transistor M5 is coupled to the ground terminal GND through the first resistor R1.
  • the gate and first pole of the sixth transistor M6 may be coupled to the second input terminal of the voltage comparator 2021 through the second resistor R2, and the second pole of the sixth transistor M6 may be directly coupled to the ground terminal GND;
  • the gate and first pole of the sixth transistor M6 are directly coupled to the second input terminal of the voltage comparator 2021 , and the second pole of the sixth transistor M6 is directly coupled to the ground terminal GND through the second resistor R2 .
  • the fifth transistor M5 and the sixth transistor M6 may be, for example, MOS transistors.
  • the fifth transistor M5 and the sixth transistor M6 are N-type transistors.
  • the current comparator 202A includes a fifth transistor M5, the fifth transistor M5 can act as a resistor, thereby increasing the voltage of the first input terminal of the voltage comparator 2021, and in the case of the same resistance value, the occupied area of the fifth transistor M5 Compared with pure resistance, the area is small.
  • the current comparator 202A includes a sixth transistor M6, the sixth transistor M6 can act as a resistor, thereby increasing the voltage of the second input terminal of the voltage comparator 2021, and under the same resistance value, the sixth transistor M6 Compared with pure resistance, the occupied area is smaller.
  • the above-mentioned current comparator 202A includes: a second current mirror 2022
  • the input terminal of the second current mirror 2022 is coupled with the second current source Iref2, and the output terminal and the signal output terminal Dout of the second current mirror 2022 are all coupled with the first pole of the eighth transistor M8; the second current mirror 2022 is used to The current mirror of the second current source Iref2 is amplified, and the amplified current is output to the output terminal of the second current mirror 2022 .
  • the current comparator 202A includes the second current mirror 2022
  • the first pole of the eighth transistor M8 is equivalent to the first input terminal a of the current comparator 202A2
  • the first input terminal a of the current comparator 202A2 a is coupled with the signal output terminal Dout.
  • one input terminal of the second current mirror 2022 is coupled to the second current source Iref2, and the other input terminal may be coupled to the ground terminal GND.
  • magnification of the second current mirror 2022 is not limited, and the magnification of the second current mirror 2022 can be adjusted by adjusting the structure and parameters of the second current mirror 2022 .
  • the second current mirror 2022 includes: a ninth transistor M9 and a tenth transistor M10; the gate and the first electrode of the ninth transistor M9 are both coupled to the second current source Iref2, and the ninth transistor M9
  • the second pole of the transistor M9 is coupled to the ground terminal GND; one of the first pole and the second pole of the ninth transistor M9 is a source, and the other is a drain; the gate of the tenth transistor M10 is coupled to the second current source Iref2,
  • the first pole of the tenth transistor M10 and the signal output terminal Dout are both coupled to the first pole of the eighth transistor M8, and the second pole of the tenth transistor M10 is coupled to the ground terminal GND; the first pole of the tenth transistor M10 and the second One of the poles is the source and the other is the drain.
  • the ninth transistor M9 and the tenth transistor M10 may be, for example, MOS transistors.
  • the ninth transistor M9 and the tenth transistor M10 are N-type transistors.
  • the mirror magnification of the second current mirror 2022 can be adjusted by adjusting the aspect ratio of the ninth transistor M9 and the tenth transistor M10.
  • the current comparator 202A includes a second current mirror 2022
  • the current output by the second current source Iref2 is amplified by the second current mirror 2022 and then compared with the current output by the first pole of the eighth transistor M8 to generate a corresponding
  • the signal output terminal Dout outputs the first digital signal "1"
  • the signal output terminal Dout outputs the second digital signal "0"
  • the circuit structure of the current comparator 202A is simpler, the area is smaller, and the cost is lower.
  • the implementation of the current comparator 202A in the demodulator 200 includes but is not limited to the above two methods, and may also include other methods, so that the current of the first input terminal a of the current comparator 202A and the current After the current of the second input terminal b of the comparator 202A is compared, the first digital signal "1" or the second digital signal "0" shall prevail.
  • the load module 203 includes an impedance
  • the signal source Ref is a reference voltage source Vref
  • the comparator 202 is a voltage comparator 2021
  • the second input terminal of the voltage comparator 2021 b is coupled to the reference voltage source Vref
  • the voltage comparator 2021 is used to compare the voltage of the first input terminal a with the voltage of the second input terminal b, and output the comparison result.
  • the voltage comparator 2021 is used to compare the voltage at the first input terminal a with the voltage at the second input terminal b, and when the voltage at the first input terminal a is greater than the voltage at the second input terminal b, output the first A digital signal "1"; when the voltage at the first input terminal a is lower than the voltage at the second input terminal b, a second digital signal "0" is output.
  • the first terminal of the transconductance circuit 201 is directly coupled to the first input terminal a of the voltage comparator 2021 .
  • the impedance may include a twelfth transistor M12 as shown in FIG.
  • the first terminal of the circuit 201 is coupled, and the second pole of the twelfth transistor M12 is coupled to the third signal input terminal VE, wherein, one of the first pole and the second pole of the twelfth transistor M12 is a source, and the other is a drain
  • the impedance may also include a resistor RL as shown in FIG.
  • the second embodiment only introduces the parts that are different from the first embodiment, and the same parts as the first embodiment can refer to the first embodiment above, which will not be repeated here.
  • the working principle of the demodulator 200 , the specific structure of the transconductance circuit 201 , the eleventh transistor M11 , and the filter 204 can refer to the first embodiment above.
  • the embodiment of the present application also provides a control method for the above-mentioned near field communication system 10A, as shown in FIG. 13 , the Control methods include:
  • the first signal input terminal VC and the second signal input terminal VD of the demodulator 200 receive radio frequency signals, and the third signal input terminal VE of the demodulator 200 receives a DC signal; wherein, the first signal input terminal VC and the second signal input terminal VC
  • the radio frequency signal received by the signal input terminal VD is a pair of differential signals.
  • the demodulator 200 selects whether to use the current signal provided by the third signal input terminal VE according to the comparison result of the voltage at the first signal input terminal VC or the voltage at the second signal input terminal VD and the voltage at the third signal input terminal VE.
  • the first current source Iref1 flows through the first end of the transconductance circuit 201 or the second end of the transconductance circuit 201 .
  • the demodulator 200 determines the voltage at the first signal input terminal VC or When the voltage of the second signal input terminal VD is greater than the voltage of the third signal input terminal VE, the current signal provided by the third signal input terminal VE flows to the first current source Iref1 through the first terminal of the transconductance circuit 201, and passes through the first The current source Iref1 flows to the ground terminal GND.
  • the demodulator 200 calculates the voltage at the first signal input terminal VC and When the voltage of the second signal input terminal VD is lower than the voltage of the third signal input terminal VE, the current signal provided by the third signal input terminal VE flows to the first current source Iref1 through the second terminal of the transconductance circuit 201, and passes through the second terminal of the transconductance circuit 201. A current source Iref1 flows to the ground terminal GND.
  • the comparator 202 compares the signal at the first input terminal a with the signal at the second input terminal b, and outputs a comparison result.
  • the comparator 202 compares the signal at the first input terminal a with the signal at the second input terminal b, and outputs a first digital signal when the signal at the first input terminal a is greater than the signal at the second input terminal b "1"; when the signal at the first input terminal a is smaller than the signal at the second input terminal b, output a second digital signal "0".
  • the current comparator 202 compares the current at the first input terminal a with the current at the second input terminal b, and the current at the first input terminal a is greater than the current at the second input terminal b When the current is higher, the first digital signal "1" is output; when the current at the first input terminal a is smaller than the current at the second input terminal b, the second digital signal "0" is output.
  • the voltage comparator 2021 compares the voltage at the first input terminal a with the voltage at the second input terminal b, and the voltage at the first input terminal a is greater than that at the second input terminal
  • the first digital signal "1" is output; when the voltage of the first input terminal a is lower than the voltage of the second input terminal b, the second digital signal "0" is output.
  • control method of the near-field communication system 10A provided in the embodiment of the present application has the same technical effect as the above-mentioned near-field communication system 10A, and reference can be made to the above-mentioned description about the technical effect of the near-field communication system 10A. Let me repeat.
  • the antenna 800 in the near field communication system 10A provides a pair of differential signals to the demodulator 200, that is, the demodulator 200 includes a first signal input terminal VC and the second signal input terminal VD.
  • the antenna 800 in the near field communication system 10A provides a single-ended signal to the demodulator 200, that is, the demodulator 200 includes a first signal input terminal VC and does not include a second signal input terminal VD.
  • the demodulator 200 in the near field communication system 10A includes: a transconductance circuit 201, a first current source Iref1, a signal source Ref, a comparator 202, a load module 203, a first The signal input terminal VC, the third signal input terminal VE and the signal output terminal Dout; wherein, the first signal input terminal VC is used for receiving radio frequency signals, and the signal output terminal of the rectifier 100 is also connected with the third signal input terminal VE of the demodulator 200 Coupling for providing a DC signal to the third signal input terminal VE.
  • the bias terminal of the transconductance circuit 201 is coupled to the first current source Iref1, the first terminal of the transconductance circuit 201 is coupled to the first input terminal a of the comparator 202, and the second terminal of the transconductance circuit 201 is coupled to the third signal input
  • the control terminal of the transconductance circuit 201 is coupled to both the first signal input terminal VC and the third signal input terminal VE.
  • the transconductance circuit 201 is used to select whether to pass the current signal provided by the third signal input terminal VE through the first terminal of the transconductance circuit 2001 according to the comparison result of the voltage at the first signal input terminal VC and the voltage at the third signal input terminal VE Or the second end of the transconductance circuit 201 flows to the first current source Iref1.
  • the transconductance circuit 201 is used to pass the current signal provided by the third signal input terminal VE through the first signal of the transconductance circuit 201 when the voltage of the first signal input terminal VC is greater than the voltage of the third signal input terminal VE. Terminal flows to the first current source Iref1, and flows to the ground terminal GND through the first current source Iref1. In some examples, the transconductance circuit 201 is used to pass the current signal provided by the third signal input terminal VE through the second terminal of the transconductance circuit 201 when the voltage of the first signal input terminal VC is lower than the voltage of the third signal input terminal VE. Terminal flows to the first current source Iref1, and flows to the ground terminal GND through the first current source Iref1.
  • the first input terminal a of the comparator 202 is also coupled to the third signal input terminal VE through the load module 203, the second input terminal b of the comparator 202 is coupled to the signal source Ref, and the output terminal of the comparator 202 is coupled to the signal output terminal Dout , the comparator 202 is used to compare the signal at the first input terminal a with the signal at the second input terminal b, and output the comparison result.
  • the comparator 202 is used to compare the signal at the first input terminal a with the signal at the second input terminal b, and output the first input terminal b when the signal at the first input terminal a is greater than the signal at the second input terminal b.
  • a digital signal such as "1"; when the signal at the first input terminal a is smaller than the signal at the second input terminal b, a second digital signal such as "0" is output.
  • the load module 203 includes a first current mirror 203A, the signal source Ref is a second current source Iref2, the comparator 202 is a current comparator 202A, the second input terminal b of the current comparator 202A is coupled to the second current source Iref2, and the current comparison The device 202A is used to compare the current of the first input terminal a with the current of the second input terminal b, and output the comparison result.
  • the current comparator 202A is used to compare the current of the first input terminal a with the current of the second input terminal b, and when the current of the first input terminal a is greater than the current of the second input terminal b, output the second A digital signal "1"; when the current at the first input terminal a is smaller than the current at the second input terminal b, a second digital signal "0" is output.
  • the working process of the demodulator 200 can refer to the above, and will not be repeated here.
  • the transconductance circuit 201 only includes the first transistor M1 and the second transistor M2. In some other examples, the transconductance circuit 201 includes a first transistor M1 , a second transistor M2 and a fourth transistor M4 . The connections and functions of the first transistor M1 , the second transistor M2 and the fourth transistor M4 can be referred to above, and will not be repeated here.
  • the demodulator 200 may further include a first current mirror 203A, an eleventh transistor M11, a filter 204, etc., the second
  • the structures, connection relationships, and functions of the first current mirror 203A, the eleventh transistor M11 , and the filter 204 can be referred to above, and will not be repeated here.
  • the implementation manner of the current comparator 202A in the demodulator 200, the control method of the near field communication system 10A, etc. can also refer to the above, and will not be repeated here.
  • the load module 203 includes a first current mirror 203A, the signal source Ref is a second current source Iref2 , and the comparator 202 is a current comparator 202A as an example for illustration.
  • the load module 203 includes an impedance, the signal source Ref is a reference voltage source Vref, the comparator 202 is a voltage comparator 2021, and the second input terminal b of the voltage comparator 2021 is coupled to the reference voltage source Vref, specifically Reference may be made to Embodiment 2, which will not be repeated here.

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Abstract

本申请实施例提供一种近场通信系统及其控制方法、电子设备，可以改善解调器灵敏度低的问题。近场通信系统包括整流器、解调器和电源管理单元；解调器包括跨导电路、第一电流源、信号源、负载模块、第一信号输入端、第二信号输入端、第三信号输入端以及信号输出端；跨导电路的偏置端与第一电流源耦合，跨导电路的第二端与第三信号输入端耦合，跨导电路的控制端与第一信号输入端、第二信号输入端和第三信号输入端均耦合；跨导电路用于根据第一信号输入端的电压或第二信号输入端的电压与第三信号输入端的电压的比较结果，选择是否将第三信号输入端提供的电流信号通过跨导电路的第一端或跨导电路的第二端流向第一电流源。

Description

近场通信系统及其控制方法、电子设备 技术领域
本申请涉及近场通信技术领域，尤其涉及一种近场通信系统及其控制方法、电子设备。
背景技术
近场通信(near filed communication，NFC)，也可以称为近距离近场通信，是一种能够让两个设备或更多的设备之间进行信息交换的近场通信技术，用于设备之间非接触的数据传输和交换。
目前，用于实现近场通信的近场通信系统主要包括整流器(rectifier)、解调器(demodulator)、电源管理单元(power management unit，PMU)等部分。其中，整流器用于将天线接收到的射频信号转换为直流信号，以供近场通信系统内部的其它模块例如解调器使用。解调器用于将接收到的调制信号解调为数字信号。然而，由于现有的解调器的灵敏度较低，因而不能解调低调制深度的信号，例如不能解调VHBR(very-high-bit-rates，超高速比特率)协议中的6.8Mbps信号。
发明内容
本申请的实施例提供一种近场通信系统及其控制方法、电子设备，可以改善解调器的灵敏度低的问题。
第一方面，提供一种近场通信系统，该近场通信系统包括：整流器、解调器和电源管理单元；解调器包括：跨导电路、第一电流源、信号源、负载模块、第一信号输入端、第二信号输入端、第三信号输入端以及信号输出端；其中，第一信号输入端和第二信号输入端用于接收射频信号，且第一信号输入端和第二信号输入端接收的射频信号为一对差分信号，整流器的信号输出端与电源管理单元耦合，电源管理单元与解调器的电源输入端耦合，用于为解调器供电；整流器的信号输出端还与解调器的第三信号输入端耦合，用于为第三信号输入端提供直流信号；跨导电路的偏置端与第一电流源耦合，跨导电路的第二端与第三信号输入端耦合，跨导电路的控制端与第一信号输入端、第二信号输入端和第三信号输入端均耦合；跨导电路用于根据第一信号输入端的电压或第二信号输入端的电压与第三信号输入端的电压的比较结果，选择是否将第三信号输入端提供的电流信号通过跨导电路的第一端或跨导电路的第二端流向第一电流源。
在近场通信系统中，解调器的第一信号输入端和第二信号输入端通常接收的是天线传输的射频信号，而解调器的第三信号输入端通常与整流器的输出端耦合，用于接收整流器将从天线接收到的射频信号转换成的直流信号，因此第一信号输入端接收到的射频信号的峰值、第二信号输入端接收到的射频信号的峰值与第三信号输入端接收到的直流信号的值比较接近。在此基础上，本申请提供的解调器在解调时，由于是以第三信号输入端的电压为参考，和第一信号输入端的电压、以及第二信号输入端的电压进行对比，而第一信号输入端接收到的射频信号的峰值、第二信号输入端接收到的射频信号的峰值与第三信号输入端接收到的直流信号的值比较接近，因而本申请提供 的解调器在解调时只对有用的信号进行量化，从而可以实现解调器有较高的灵敏度。
在一种可能的实施方式中，跨导电路用于在第一信号输入端的电压或第二信号输入端的电压大于第三信号输入端的电压时，将第三信号输入端提供的电流信号通过跨导电路的第一端流向第一电流源。此处提供了跨导电路可以实现的一个作用。
在一种可能的实施方式中，跨导电路用于在第一信号输入端的电压和第二信号输入端的电压均小于第三信号输入端的电压时，将第三信号输入端提供的电流信号通过跨导电路的第二端流向第一电流源。此处提供了跨导电路可以实现的一个作用。
在一种可能的实施方式中，解调器还包括比较器；比较器的第一输入端与跨导电路的第一端耦合，比较器的第一输入端还通过负载模块与第三信号输入端耦合，比较器的第二输入端与信号源耦合，比较器的输出端耦合至信号输出端，比较器用于将第一输入端的信号和第二输入端的信号进行比较，并输出比较结果。例如，比较器在第一输入端的信号大于第二输入端的信号时，输出第一数字信号；在第一输入端的信号小于第二输入端的信号时，输出第二数字信号。
在一种可能的实施方式中，信号源为第二电流源，比较器为电流比较器；负载模块包括：第一电流镜，第一电流镜的第一输入端与跨导电路的第一端耦合，第一电流镜的第二输入端与第三信号输入端耦合，第一电流镜的输出端与电流比较器的第一输入端耦合；第一电流镜用于将跨导电路的第一端的电流镜像放大，并将放大后的电流输出至第一电流镜的输出端。在解调器包括第一电流镜的情况下，由于第一电流镜可以将跨导电路的第一端的电流镜像放大后输出给电流比较器的第一输入端，因而将电流比较器的第一输入端和第二输入端的电流进行比较时，这样可以降低对电流比较器的灵敏度的要求。
在一种可能的实施方式中，跨导电路包括第一晶体管、第二晶体管和第三晶体管；第一晶体管的栅极和第二极均与第三信号输入端耦合，第一极与第一电流源耦合；第一晶体管的第一极和第二极中一个为源极，一个为漏极；第二晶体管的栅极与第一信号输入端耦合，第一极与第一电流源耦合，第二极与比较器的第一输入端耦合；第二晶体管的第一极和第二极中一个为源极，一个为漏极；第三晶体管的栅极与第二信号输入端耦合，第一极与第一电流源耦合，第二极与比较器的第一输入端耦合；第三晶体管的第一极和第二极中一个为源极，一个为漏极。以第一信号输入端为例，在第一信号输入端的电压大于第三信号输入端的电压时，第三晶体管断开，第一晶体管断开，第二晶体管导通，第三信号输入端提供的电流信号通过第二晶体管(即跨导电路的第一端)流向第一电流源，并通过第一电流源流向接地端；在第一信号输入端的电压小于第三信号输入端的电压时，第三晶体管断开，第二晶体管断开，第一晶体管导通，第三信号输入端提供的电流信号通过第一晶体管(即跨导电路的第二端)流向第一电流源，并通过第一电流源流向接地端。
在一种可能的实施方式中，跨导电路还包括第四晶体管；第四晶体管的栅极与第三信号输入端耦合，第一极与第一电流源耦合，第二极与比较器的第一输入端耦合；第四晶体管的第一极和第二极中一个为源极，一个为漏极。以第一信号输入端为例，在第一信号输入端的电压小于第三信号输入端的电压时，第三信号输入端提供的电流信号通过第一晶体管(即跨导电路的第二端)流向第一电流源，并通过第一电流源流 向接地端；第三信号输入端提供的电流信号还通过第四晶体管(即跨导电路的第一端)流向第一电流源，并通过第一电流源流向接地端，基于此，可以看出第四晶体管的加入能够保持跨导电路的第一端上持续有电流，加快运放响应速度。
在一种可能的实施方式中，电流比较器包括：电压比较器、第一电阻和第二电阻；电压比较器的第一输入端与跨导电路的第一端耦合，电压比较器的第二输入端与第二电流源耦合，电压比较器的输出端耦合至信号输出端；第一电阻耦合在电压比较器的第一输入端和接地端之间，第二电阻耦合在电压比较器的第二输入端和接地端之间。电压比较器用于将电压比较器的第一输入端的电压与电压比较器的第二输入端的电压进行比较，从而在电压比较器的输出端输出第一数字信号，或者第二数字信号，当电压比较器的第一输入端的电压大于电压比较器的第二输入端的电压时，输出第一数字信号；当电压比较器的第一输入端的电压小于电压比较器的第二输入端的电压时，输出第二数字信号。此外，电压比较器的第一输入端的电压等于电压比较器的第一输入端的电流乘以第一电阻，电压比较器的第二输入端的电压等于电压比较器的第二输入端的电流乘以第二电阻。
在一种可能的实施方式中，电流比较器还包括：第五晶体管和第六晶体管；第五晶体管和第一电阻串联在电压比较器的第一输入端和接地端之间，第五晶体管的栅极和第一极均与电压比较器的第一输入端耦合，第五晶体管的第二极与接地端耦合；第五晶体管的第一极和第二极中一个为源极，一个为漏极；第六晶体管和第二电阻串联在电压比较器的第二输入端和接地端之间，第六晶体管的栅极和第一极均与电压比较器的第二输入端耦合，第六晶体管的第二极与接地端耦合；第六晶体管的第一极和第二极中一个为源极，一个为漏极。由于电流比较器包括第五晶体管，第五晶体管可以充当电阻，因而可以提高电压比较器的第一输入端的电压，且在相同阻值的情况下，第五晶体管的所占面积相对于纯电阻而言，面积较小。同样的，由于电流比较器包括第六晶体管，第六晶体管可以充当电阻，因而可以提高电压比较器的第二输入端的电压，且在相同阻值的情况下，第六晶体管所占的面积相对于纯电阻而言，面积较小。
在一种可能的实施方式中，第一电流镜包括第七晶体管和第八晶体管；第七晶体管的栅极和第一极与跨导电路的第一端耦合，第七晶体管的第二极与第三信号输入端耦合；第七晶体管的第一极和第二极中一个为源极，一个为漏极；第八晶体管的栅极与第七晶体管的栅极耦合，第八晶体管的第一极与电流比较器的第一输入端耦合，第八晶体管的第二极与第三信号输入端VE耦合；第八晶体管的第一极和第二极中一个为源极，一个为漏极。可以通过调整第七晶体管和第八晶体管的长宽比，来调整第一电流镜的镜像放大倍数。
在一种可能的实施方式中，电流比较器包括：第二电流镜；第二电流镜的输入端与第二电流源耦合，第二电流镜的输出端和信号输出端均与第八晶体管的第一极耦合；第二电流镜用于将第二电流源的电流镜像放大，并将放大后的电流输出至第二电流镜的输出端。在电流比较器包括第二电流镜的情况下，电流比较器的电路结构更为简单，面积更小，成本更低。
在一种可能的实施方式中，第二电流镜包括：第九晶体管和第十晶体管；第九晶体管的栅极和第一极均与第二电流源耦合，第九晶体管的第二极与接地端耦合；第九 晶体管的第一极和第二极中一个为源极，一个为漏极；第十晶体管的栅极与第二电流源耦合，第十晶体管的第一极和信号输出端均与第八晶体管的第一极耦合；第十晶体管的第二极与接地端耦合；第十晶体管的第一极和第二极中一个为源极，一个为漏极。在电流比较器包括第二电流镜的情况下，第二电流源输出的电流经过第二电流镜放大后和第八晶体管的第一极输出的电流作比较，就能产生对应的数字信号，当第八晶体管的第一极输出的电流大于第二电流源输出的电流经过第二电流镜放大后的电流时，信号输出端输出第一数字信号；当第八晶体管的第一极输出的电流小于第二电流源输出的电流经过第二电流镜放大后的电流时，信号输出端输出第二数字信号。
在一种可能的实施方式中，解调器还包括：第十一晶体管，第十一晶体管的栅极和第一极与跨导电路的第二端耦合，第十一晶体管的第二极与第三信号输入端耦合；第十一晶体管的第一极和第二极中一个为源极，一个为漏极。在解调器中设置第十一晶体管时，对于跨导电路中的第一晶体管、第四晶体管、第二晶体管和第三晶体管而言，由于第一晶体管的第二极通过第十一晶体管与第三信号输入端耦合，第四晶体管的第二极、第二晶体管的第二极和第三晶体管的第二极通过第七晶体管与第三信号输入端耦合，因此可以认为第一晶体管的第二极、第四晶体管的第二极、第二晶体管的第二极和第三晶体管的第二极的电压相同或相近，而第一晶体管的第一极、第四晶体管的第一极、第二晶体管的第一极和第三晶体管的第一极均与第一电流源耦合，因而可以认为第一晶体管的第一极、第四晶体管的第一极、第二晶体管的第一极和第三晶体管的第一极的电压是相同，这样一来，第一晶体管的Vds、第四晶体管的Vds、第二晶体管的Vds和第三晶体管的Vds是相同或相近的，因此可以降低沟道长度调制效应的影响。
在一种可能的实施方式中，解调器还包括滤波器，滤波器串联在第三信号输入端和接地端之间。由于滤波器可以起到稳压的作用，因而在第三信号输入端耦合滤波器，这样可以确保第三信号输入端提供的电压是稳定的，进而有利于提高解调器的性能。
在一种可能的实施方式中，滤波器包括电容和第三电阻；电容和第三电阻耦合在第三信号输入端和接地端之间。电容和第三电阻可以构成滤波器。
在一种可能的实施方式中，负载模块包括阻抗，信号源为参考电压源，比较器为电压比较器，电压比较器的第二输入端与参考电压源耦合。
在一种可能的实施方式中，阻抗包括第十二晶体管，第十二晶体管的栅极和第一极与跨导电路的第一端耦合，第十二晶体管的第二极与第三信号输入端耦合，其中，第十二晶体管的第一极和第二极中一个为源极，一个为漏极；或者，阻抗包括电阻，电阻的一端与第三信号输入端耦合，另一端与跨导电路的第一端耦合。
在一种可能的实施方式中，近场通信系统还包括天线，解调器的第一信号输入端和第二信号输入端均与天线耦合，天线将接收到的射频信号传输给第一信号输入端和第二信号输入端。天线可以向第一信号输入端和第二信号输入端提供射频信号。
第二方面，提供一种近场通信系统的控制方法，近场通信系统包括：整流器、解调器和电源管理单元；解调器包括：跨导电路、第一电流源、信号源、负载模块、第一信号输入端、第二信号输入端、第三信号输入端以及信号输出端；整流器的信号输出端与电源管理单元耦合，电源管理单元与解调器的电源输入端耦合，整流器的信号 输出端还与解调器的第三信号输入端耦合；跨导电路的偏置端与第一电流源耦合，跨导电路的第二端与第三信号输入端耦合，跨导电路的控制端与第一信号输入端、第二信号输入端和第三信号输入端均耦合；上述控制方法包括：首先，解调器的第一信号输入端和第二信号输入端接收射频信号，解调器的第三信号输入端接收直流信号；其中，第一信号输入端和第二信号输入端接收到的射频信号为一对差分信号；接下来，解调器根据第一信号输入端的电压或第二信号输入端的电压与第三信号输入端的电压的比较结果，选择是否将第三信号输入端提供的电流信号通过跨导电路的第一端或跨导电路的第二端流向第一电流源。该近场通信系统的控制方法具有与上述第一方面提供的近场通信系统相同的技术效果，可以参考上述第一方面的描述，此处不再赘述。
在一种可能的实施方式中，解调器还包括比较器；比较器的第一输入端与跨导电路的第一端耦合，比较器的第一输入端还通过负载模块与第三信号输入端耦合，比较器的第二输入端与信号源耦合，比较器的输出端耦合至信号输出端；上述控制方法还包括：比较器将第一输入端的信号和第二输入端的信号进行比较，并输出比较结果。例如在第一输入端的信号大于第二输入端的信号时，输出第一数字信号；在第一输入端的信号小于第二输入端的信号时，输出第二数字信号。可以参考上述第一方面的相关描述，此处不再赘述。
第三方面，提供一种近场通信系统，该近场通信系统包括：整流器、解调器和电源管理单元；解调器包括：跨导电路、第一电流源、信号源、负载模块、第一信号输入端、第三信号输入端以及信号输出端；其中，第一信号输入端用于接收射频信号，整流器的信号输出端与电源管理单元耦合，电源管理单元与解调器的电源输入端耦合，用于为解调器供电；整流器的信号输出端还与解调器的第三信号输入端耦合，用于为第三信号输入端提供直流信号；跨导电路的偏置端与第一电流源耦合，跨导电路的第二端与第三信号输入端耦合，跨导电路的控制端与第一信号输入端和第三信号输入端均耦合；跨导电路用于根据第一信号输入端的电压与第三信号输入端的电压的比较结果，选择是否将第三信号输入端提供的电流信号通过跨导电路的第一端或跨导电路的第二端流向第一电流源。可以参考上述第一方面的相关描述，此处不再赘述。
在一种可能的实施方式中，跨导电路用于在第一信号输入端的电压大于第三信号输入端的电压时，将第三信号输入端提供的电流信号通过跨导电路的第一端流向第一电流源。
在一种可能的实施方式中，跨导电路用于在第一信号输入端的电压小于第三信号输入端的电压时，将第三信号输入端提供的电流信号通过跨导电路的第二端流向第一电流源。
在一种可能的实施方式中，解调器还包括比较器；比较器的第一输入端与跨导电路的第一端耦合，比较器的第一输入端还通过负载模块与第三信号输入端耦合，比较器的第二输入端与信号源耦合，比较器的输出端耦合至信号输出端，比较器用于将第一输入端的信号和第二输入端的信号进行比较，并输出比较结果。可以参考上述第一方面的相关描述，此处不再赘述。
第四方面，提供一种近场通信系统的控制方法，该近场通信系统包括：整流器、解调器和电源管理单元；解调器包括：跨导电路、第一电流源、信号源、负载模块、 第一信号输入端、第三信号输入端以及信号输出端；整流器的信号输出端与电源管理单元耦合，电源管理单元与解调器的电源输入端耦合；整流器的信号输出端还与解调器的第三信号输入端耦合；跨导电路的偏置端与第一电流源耦合，跨导电路的第二端与第三信号输入端耦合，跨导电路的控制端与第一信号输入端和第三信号输入端均耦合；上述控制方法包括：首先，解调器的第一信号输入端接收射频信号，解调器的第三信号输入端接收直流信号；接下来，解调器根据第一信号输入端的电压与第三信号输入端的电压的比较结果，选择是否将第三信号输入端提供的电流信号通过跨导电路的第一端或跨导电路的第二端流向第一电流源。可以参考上述第一方面的相关描述，此处不再赘述。
在一种可能的实施方式中，解调器还包括比较器；比较器的第一输入端与跨导电路的第一端耦合，比较器的第一输入端还通过负载模块与第三信号输入端耦合，比较器的第二输入端与信号源耦合，比较器的输出端耦合至信号输出端；上述控制方法还包括：比较器将第一输入端的信号和第二输入端的信号进行比较，并输出比较结果。可以参考上述第一方面的相关描述，此处不再赘述。
第五方面，提供一种电子设备，该电子设备包括印刷电路板和上述第一方面或第三方面提供的近场通信系统。该电子设备具有与上述第一方面提供的近场通信系统相同的技术效果，可以参考上述第一方面的相关描述，此处不再赘述。
附图说明
图1为本申请的实施例提供的一种电子设备的结构示意图；
图2为本申请的实施例提供的一种近场通信系统的结构示意图；
图3a为相关技术提供的一种解调器的结构示意图；
图3b为另一相关技术提供的一种解调器的结构示意图；
图4为本申请的实施例提供的一种解调器的结构示意图；
图5为本申请的另一实施例提供的一种解调器的结构示意图；
图6为图5所示的解调器中各个电压端、电流端、以及信号输出端对应的曲线图；
图7a为本申请的又一实施例提供的一种解调器的结构示意图；
图7b为本申请的又一实施例提供的一种解调器的结构示意图；
图8为本申请的又一实施例提供的一种解调器的结构示意图；
图9为本申请的又一实施例提供的一种解调器的结构示意图；
图10为本申请的又一实施例提供的一种解调器的结构示意图；
图11为本申请的又一实施例提供的一种解调器的结构示意图；
图12a为本申请的又一实施例提供的一种解调器的结构示意图；
图12b为本申请的又一实施例提供的一种解调器的结构示意图；
图13为本申请的实施例提供的一种解调器的控制方法的流程示意图；
图14为本申请的又一实施例提供的一种解调器的结构示意图。
附图标记：1-电子设备；10-无线通信系统；10A-近场通信系统；11-处理器；12-电源；13-存储器；14-输入单元；15-显示装置；16-音频电路；100-整流器；141-触摸屏；142-其他输入设备；151-显示面板；161-扬声器；162-麦克风；200-解调器；201-跨导电路；202-比较器；202A-电流比较器；203-负载模块；203A-第一电流镜；204- 滤波器；300-负载调制器；400-时钟数据恢复电路；500-电源管理单元；600-数字处理电路；700-其它模块；800-天线；900-匹配网络和/或滤波器；2021-电压比较器；2022-第二电流镜。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请实施例中，除非另有明确的规定和限定，术语“耦合”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
本申请的实施例提供一种电子设备，该电子设备例如可以为手机(mobile phone)、平板电脑(pad)、个人数字助理(personal digital assistant，PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)电子设备、增强现实(augmented reality，AR)电子设备、充电家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等不同类型的用户设备或者电子设备；该电子设备还可以为基站等网络设备。本申请实施例对电子设备的具体形式不作特殊限制。
图1为本申请实施例示例性地提供的一种电子设备的结构示意图。如图1所示，该电子设备1包括无线通信系统10、处理器11、电源12、存储器13、输入单元14、显示装置15、音频电路16等部件。可以理解的是，图1示意的结构并不构成对该电子设备1的具体限定。在本申请另一些实施例中，电子设备1可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
上述处理器11是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备的各个部分，通过运行或执行存储在存储器13内的软件程序和/或模块，以及调用存储在存储器13内的数据，执行电子设备的各种功能和处理数据，从而对电子设备进行整体监控。可选的，处理器11可包括一个或多个处理单元；在一些示例中，处理器11可集成应用处理器(application processor，AP)和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理近场通信。可以理解的是，上述调制解调处理器也可以不集成到处理器11中。
上述无线通信系统10可用于收发信息或通话过程中，信号的接收和发送，特别地，将基站的下行信息接收后，给处理器11处理；另外，将上行的数据发送给基站。上述无线通信系统10包括近场通信系统和远场通信系统，通常，无线通信系统10可以通 过近场通信或远场通信与网络和其他设备通信。近场通信可以使用任一通信标准或协议，包括但不限于全球移动通讯系统(global system of mobile communication，GSM)、通用分组无线服务(general packet radio service，GPRS)、码分多址(code division multiple access，CDMA)、宽带码分多址(wideband code division multiple access，WCDMA)、长期演进(long term evolution，LTE)、电子邮件、短消息服务(short messaging service，SMS)等。
上述电源12例如可以包括电池，电源12可以给各个部件供电，可选的，电源12可以通过电源管理单元与处理器11逻辑相连，从而通过电源管理单元实现管理充电、放电、以及功耗管理等功能。
上述存储器13可以用于存储软件程序以及模块，处理器11通过运行存储在存储器13中的软件程序以及模块，从而执行电子设备的各种功能应用以及数据处理。存储器13主要包括存储程序区和存储数据区，其中，存储程序区可以存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可以存储根据手机的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储器13可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
上述输入单元14可以用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。具体地，输入单元14可以包括触摸屏141以及其他输入设备142。触摸屏141，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏141上或在触摸屏141附近的操作)，并根据预先设定的程式驱动相应的连接电子设备。其他输入设备142可以包括但不限于物理键盘、功能键(比如音量控制按键、电源开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。
上述显示装置15可以用于显示由用户输入的信息或提供给用户的信息以及电子设备的各种菜单。显示装置15可以包括显示面板151，显示面板151可以为液晶显示(liquid crystal display，LCD)面板、有机发光二极管(organic light emitting diode，OLED)显示面板、或者Micro-LED(微型发光二极管)显示面板等。此外，触摸屏141可覆盖显示面板151，当触摸屏141检测到在触摸屏141上或附近的触摸操作后，传送给处理器11以确定触摸事件的类型，随后处理器11根据触摸事件的类型在显示面板151上提供相应的视觉输出。虽然在图1中，触摸屏141与显示面板151是作为两个独立的部件来实现装置的输入和输出功能，但是在某些实施例中，可以将触摸屏141与显示面板151集成而实现装置的输入和输出功能。
音频电路16、扬声器161和麦克风162，用于提供用户与电子设备之间的音频接口。音频电路16可将接收到的音频数据转换后的电信号，传输到扬声器161，由扬声器161转换为声音信号输出；另一方面，麦克风162将收集的声音信号转换为电信号，由音频电路16接收后转换为音频数据，再将音频数据输出至近场通信系统以发送给比如另一电子设备，或者将音频数据输出至存储器13以便进一步处理。
可选的，如图1所示的电子设备还可以包括各种传感器。例如陀螺仪传感器、湿度计传感器、红外线传感器、磁力计传感器等，在此不再赘述。可选的，如图1所示 的电子设备还可以包括无线保真(wireless fidelity，WiFi)模块、蓝牙模块等，在此不再赘述。
在此基础上，上述电子设备1还可以包括印刷电路板(printed circuit boards，PCB)，电子设备1中的一些芯片或电子器件例如处理器11、存储器13等可以设置于PCB上。
本申请的实施例还提供一种近场通信(near field communication，NFC)系统，该近场通信系统可以作为无线通信系统10的一种，应用于上述的电子设备1中。如图2所示，该近场通信系统10A可以包括整流器(rectifier)100、解调器(demodulator)200、负载调制器(load modulator)300、时钟数据恢复(clock and data recovery，CDR)电路400、电源管理单元(power management unit，PMU)500、数字(digital)处理电路600、以及其它模块700等部分，其它模块例如可以包括射频限幅(radio frequency limiter，RF limiter)模块、场监测(filed detector)模块、安全模块(secure element，SE)等。
在此基础上，如图2所示，上述近场通信系统10A还可以包括天线(antenna)800、以及匹配网络(match)和/或滤波器(filter)900等部分。天线800可以通过匹配网络和/或滤波器900与整流器100、解调器200、负载调制器300、时钟数据恢复电路400等耦合。
需要说明的是，整流器100、解调器200、负载调制器300、时钟数据恢复电路400、电源管理单元500、数字处理电路600、以及其它模块700例如射频限幅模块、场监测模块、安全模块等可以集成在同一射频芯片上，也可以集成在不同的射频芯片上。图2以整流器100、解调器200、负载调制器300、时钟数据恢复电路400、电源管理单元500、数字处理电路600、以及其它模块700例如射频限幅模块、场监测模块、安全模块等集成在同一射频芯片为例进行示意。在近场通信系统10A应用于电子设备1中的情况下，射频芯片可以设置于印刷电路板上。
可以理解的是，如图2所示，射频芯片可以包括多个输入输出端口(input output pad，IO pad)10a，天线800可以通过匹配网络和/或滤波器900与射频芯片上的输入输出端口10a耦合，射频芯片上的整流器100、解调器200、负载调制器300、时钟数据恢复电路400等可以与输入输出端口10a耦合，进而接收天线800接收到的信号，或者向天线800发射信号。此外，射频芯片还可以包括与接地端耦合的端口10b，在一些示例中，如图2所示，与接地端耦合的端口10b可以通过电容C与接地端GND耦合。
在上述近场通信系统10A中，整流器100与天线800耦合，用于将天线800接收到的射频信号转换为直流能量供射频芯片内部的其他模块或其他芯片使用。整流器100的信号输出端与电源管理单元500耦合，电源管理单元500与芯片内部的其他模块或其他芯片的电源输入端耦合，例如与解调器200、负载调制器300、时钟数据恢复电路400、数字处理电路600、射频限幅模块、场监测模块、安全模块等的电源输入端或其他芯片的电源输入端耦合，通过电源管理单元500为其它模块或其他芯片供电，例如为射频芯片中的解调器200、负载调制器300、时钟数据恢复电路400、数字处理电路600、射频限幅模块、场监测模块、安全模块等供电。
解调器200与天线800耦合，且与数字处理电路600耦合，用于将接收到的调制信号解调为数字信号，并将数字信号传输给数字处理电路600进行进一步解调。
负载调制器300与数字处理电路600、天线800耦合，负载调制器300作为发射模块，用于将数字处理电路600输出的数字信号进行负载调制后输出给天线800，再通过天线800向外发射信号。
时钟数据恢复电路400与天线800、数字处理电路600耦合，用于将天线800接收到的射频信号转换为同频率时钟信号，再将时钟信号传输给数字处理电路600，让数字处理电路600在该时钟信号下工作。
数字处理电路600用于起到解调和射频芯片控制的作用。射频限幅模块与天线800耦合，用于防止天线800信号过大，超过芯片的耐压能力击穿芯片。场监测模块用于监测天线800是否有信号。
在近场通信系统10A中，提高解调器200的灵敏度是目前解调器200研究的一个难点，这是因为在近场通信系统10A中，除了整流器100会导致信号失真外，天线有限的带宽也会对输入高速调制信号产生明显的衰减作用，例如对于VHBR协议中的6.8Mbps信号会产生明显的衰减作用，这些都导致对解调器200的灵敏度有较高的要求。6.8Mbps信号经过系统衰减之后，调制深度可能只有0.1％，在低速通信中，如848kbps以下，现在普遍利用二极管的单向导通特性，实现包络检测，也就实现了解调。然而这种解调器200的灵敏度非常低，通常只能解调调制深度8％左右的信号。
为了解决现有的解调器200的灵敏度低的问题，相关技术提供一种解调器200，如图3a所示，该解调器200包括可编程增益放大器(programmable gain amplifier，PGA)和模数转换器(analog-to-digital converter，ADC)。图3a中的VAC表示天线，可编程增益放大器PGA与天线VAC耦合，通过天线VAC向可编程增益放大器PGA提供射频信号，可编程增益放大器PGA和模数转换器ADC耦合，模数转换器ADC用于输出数字信号。理论上图3a提供的解调器200可以实现无穷小的灵敏度，但是由于可编程增益放大器PGA和模数转换器ADC都需要较大的面积，因而会显著地增加芯片成本，对于一个调制深度0.1％的信号，至少需要有效位数10bit的模数转换器ADC，可编程增益放大器PGA也要能够实现10bit模数转换器ADC的性能或者更高，这样一来，会导致成本较大。
另一相关技术提供一种解调器200，如图3b所示，该解调器200包括包络检测器(envelope detector)、源跟随器(source follower)、微分器(differentiators)、比较器(comparators)以及控制逻辑电路(ctrl logic)、第一信号输入端VC、第二信号输入端VD以及信号输出端Dout；其中，第一信号输入端VC和第二信号输入端VD用于接收天线接收到的射频信号，且第一信号输入端VC接收到的射频信号和第二信号输入端VD接收到的射频信号为一对差分信号，第一信号输入端VC和第二信号输入端VD与包络检测器耦合，包络检测器与源跟随器耦合，源跟随器与微分器耦合，微分器与比较器耦合，比较器与控制逻辑电路耦合，控制逻辑电路与信号输出端Dout耦合，第一信号输入端VC和第二信号输入端VD将接收到的射频信号传输给包络检测器，接下来经过包络检测器处理后传输给源跟随器，接下来经过源跟随器处理后传输为微分器，接下来经过微分器处理后传输给比较器，接下来经过比较器处理后传输给控制逻辑电路，接下来通过控制逻辑电路向信号输出端Dout输出数字信号“1”或数字信号“0”。由于图3b提供的解调器200是由包络检测器、源跟随器、微分器、比较 器以及控制逻辑电路等构成的，而包络检测器、源跟随器、微分器、比较器都可以由简单的电路构成，因此相对于图3a提供的解调器200而言，图3b提供的解调器200所占的面积较小，成本较低。然而，虽然相关技术图3b提供的解调器200的灵敏度有所提高，但是该解调器200仍然不能解调低调制深度的信号，例如不能解调VHBR协议中的6.8Mbps信号，也就是说解调器200的灵敏度还是不够高。
为了解决上述相关技术提供的解调器200所占面积大、成本高、以及灵敏度不够的问题，本申请实施例提供一种近场通信系统10A，近场通信系统10A包括解调器200，如图4所示，近场通信系统10A中的解调器200包括：跨导电路201、第一电流源Iref1、信号源Ref、比较器202、负载模块203、第一信号输入端VC、第二信号输入端VD、第三信号输入端VE以及信号输出端Dout；其中，第一信号输入端VC和第二信号输入端VD用于接收射频信号，且第一信号输入端VC和第二信号输入端VD接收的射频信号为一对差分信号。整流器100的信号输出端还与解调器200的第三信号输入端VE耦合，用于为第三信号输入端VE提供直流信号。
在本申请实施例中，第一信号输入端VC和第二信号输入端VD接收的射频信号包含有通信信息，第一信号输入端VC接收到的射频信号的峰值、第二信号输入端VD接收到的射频信号的峰值均大于第三信号输入端VE接收到的直流信号的值，且第一信号输入端VC接收到的射频信号的峰值、第二信号输入端VD接收到的射频信号的峰值与第三信号输入端VE接收到的直流信号的值比较接近。
可以理解的是，在近场通信系统10A包括天线800的情况下，解调器200的第一信号输入端VC和第二信号输入端VD均与天线800耦合，天线800可以将接收到的射频信号传输给第一信号输入端VC和第二信号输入端VD。
在近场通信系统10A中，整流器100的作用是将射频信号(例如将从天线800接收到的射频信号)转换为直流信号，解调器200的第三信号输入端VE与整流器100的信号输出端耦合，用于接收整流器100的信号输出端输出的直流信号。
需要说明的是，由于解调器200的第一信号输入端VC和第二信号输入端VD接收的是天线800传输的射频信号，而整流器100将从天线800接收到的射频信号转换为直流信号，再提供给解调器200的第三信号输入端VE，因此第一信号输入端VC接收到的射频信号的峰值、第二信号输入端VD接收到的射频信号的峰值与第三信号输入端VE接收到的直流信号的值比较接近。
请继续参考图4，上述跨导电路201的偏置端与第一电流源Iref1耦合，跨导电路201的第一端与比较器202的第一输入端a耦合，跨导电路201的第二端与第三信号输入端VE耦合，跨导电路201的控制端与第一信号输入端VC、第二信号输入端VD和第三信号输入端VE均耦合。
此处，第一电流源Iref1的一端与跨导电路201的偏置端耦合，另一端可以与接地端GND耦合。
应当理解到，可以是跨导电路201的第一端与比较器202的第一输入端a直接耦合；也可以是跨导电路201的第一端与比较器202的第一输入端a间接耦合，即跨导电路201的第一端与比较器202的第一输入端a通过其它电路结构耦合在一起。
跨导电路201用于根据第一信号输入端VC的电压或第二信号输入端VD的电压 与第三信号输入端VE的电压的比较结果，选择是否将第三信号输入端VE提供的电流信号通过跨导电路201的第一端或跨导电路201的第二端流向第一电流源Iref1。
在一些示例中，跨导电路201用于在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压时，将第三信号输入端VE提供的电流信号通过跨导电路201的第一端流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。在一些示例中，跨导电路201用于在第一信号输入端VC的电压和第二信号输入端VD的电压均小于第三信号输入端VE的电压时，将第三信号输入端VE提供的电流信号通过跨导电路201的第二端流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。
需要说明的是，在第一信号输入端VC的电压和第二信号输入端VD的电压均小于第三信号输入端VE的电压时，在一些示例中，第三信号输入端VE提供的电流信号还可以通过跨导电路201的第一端流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。
在此基础上，比较器202的第一输入端a还通过负载模块203与第三信号输入端VE耦合，比较器202的第二输入端b与信号源Ref耦合，比较器202的输出端耦合至信号输出端Dout，比较器202用于将第一输入端a的信号和第二输入端b的信号进行比较，并输出比较结果。
在一些示例中，比较器202用于将第一输入端a的信号和第二输入端b的信号进行比较，在第一输入端a的信号大于第二输入端b的信号时，输出第一数字信号例如“1”；在第一输入端a的信号小于第二输入端b的信号时，输出第二数字信号例如“0”。下文中为了便于说明，以第一数字信号为“1”，第二数字信号为“0”为例。
以下通过几个实施例对解调器200进行示例性说明。
实施例一
在本实施例一中，如图5所示，上述负载模块203包括第一电流镜203A，信号源Ref为第二电流源Iref2，比较器202为电流比较器202A，电流比较器202A的第二输入端b与第二电流源Iref2耦合，电流比较器202A用于将第一输入端a的电流和第二输入端b的电流进行比较，并输出比较结果。在一些示例中，电流比较器202A用于将第一输入端a的电流和第二输入端b的电流进行比较，在第一输入端a的电流大于第二输入端b的电流时，输出第一数字信号“1”；在第一输入端a的电流小于第二输入端b的电流时，输出第二数字信号“0”。
在信号源Ref为第二电流源Iref2的情况下，如图5所示，第二电流源Iref2的一端与电流比较器202A的第二输入端b耦合，另一端可以与第三信号输入端VE耦合。
请继续参考图5，上述第一电流镜203A的第一输入端c与跨导电路201的第一端耦合，第一电流镜203A的第二输入端d与第三信号输入端VE耦合，第一电流镜203A的输出端e与电流比较器202A的第一输入端a耦合；第一电流镜203A用于将跨导电路201的第一端的电流镜像放大，并将放大后的电流输出至第一电流镜203A的输出端e，即将放大后的电流输出至电流比较器202A的第一输入端a。
在本实施例一中，跨导电路201的第一端通过第一电流镜203A与电流比较器202A的第一输入端a耦合。
此处，电流比较器202A的第一输入端a的电流为跨导电路201的第一端的电流的倍数。对于第一电流镜203A将跨导电路201的第一端的电流镜像放大的倍数不进行限定，可以通过调整第一电流镜203A的结构、参数等，调整第一电流镜203A的镜像放大倍数。
在负载模块203包括第一电流镜203A的情况下，由于第一电流镜203A可以将跨导电路201的第一端的电流镜像放大后输出给电流比较器202A的第一输入端a，因而将电流比较器202A的第一输入端a和第二输入端b的电流进行比较时，这样可以降低对电流比较器202A的灵敏度的要求。
在一些示例中，如图5所示，上述第一电流镜203A包括第七晶体管M7和第八晶体管M8；第七晶体管M7的栅极和第一极与跨导电路201的第一端耦合，第七晶体管M7的第二极与第三信号输入端VE耦合；第七晶体管M7的第一极和第二极中一个为源极，一个为漏极；第八晶体管M8的栅极与第七晶体管M7的栅极耦合，第八晶体管M8的第一极与电流比较器202A的第一输入端a耦合，第八晶体管M8的第二极与第三信号输入端VE耦合；第八晶体管M8的第一极和第二极中一个为源极，一个为漏极。
第七晶体管M7的栅极和第一极、以及第八晶体管M8的栅极耦合在一起，用于作为第一电流镜203A的第一输入端c，第七晶体管M7的第二极、以及第八晶体管M8的第二极耦合在一起，用于作为第一电流镜203A的第二输入端d，第八晶体管M8的第一极用于作为第一电流镜203A的输出端e。
此处，可以通过调整第七晶体管M7和第八晶体管M8的长宽比，来调整第一电流镜203A的镜像放大倍数。
此外，第七晶体管M7和第八晶体管M8例如可以为MOS管。
在此基础上，在本申请实施例中，第七晶体管M7和第八晶体管M8为P型管。以第七晶体管M7为例，对于P型管，当向七晶体管M7的栅极提供低电平信号时，第七晶体管M7导通。
在第一信号输入端VC的电压大于第三信号输入端VE的电压时，跨导电路201的第一端的电流I＝Gm×(VC-VE)；在第二信号输入端VD的电压大于第三信号输入端VE的电压时，跨导电路201的第一端的电流I＝Gm×(VD-VE)，其中，Gm为跨导系数，Gm可以根据需要进行设置。
可以理解的是，由于跨导电路201的第一端与电流比较器202A的第一输入端a耦合，因而电流比较器202A的第一输入端a的电流大小与跨导电路201的第一端的电流大小有关。由于电流比较器202A的第二输入端b与第二电流源Iref2耦合，因而电流比较器202A的第二输入端b的电流大小与第二电流源Iref2的电流大小有关。
基于上述，在解调器200的工作过程中，在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压，且第一信号输入端VC的电压或第二信号输入端VD的电压与第三信号输入端VE的电压的差值大于或等于阈值电压时，电流比较器202A的第一输入端a的电流大于电流比较器202A的第二输入端b的电流。在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压，且第一信号输入端VC的电压或第二信号输入端VD的电压与第三信号 输入端VE的电压的差值小于阈值电压，或者，第一信号输入端VC的电压、以及第二信号输入端VD的电压均小于第三信号输入端VE的电压时，电流比较器202A的第一输入端a的电流小于电流比较器202A的第二输入端b的电流。其中，阈值电压可以根据需要进行设置。
应当理解到，在第一信号输入端VC的电压、以及第二信号输入端VD的电压均小于第三信号输入端VE的电压时，由于第三信号输入端VE提供的电流信号主要通过跨导电路201的第二端流向第一电流源Iref1，或者，第三信号输入端VE提供的电流信号部分通过跨导电路201的第二端流向第一电流源Iref1，部分通过跨导电路201的第一端流向第一电流源Iref1，因此跨导电路201的第一端的电流较小，而跨导电路201的第一端与电流比较器202A的第一输入端a耦合，因而电流比较器202A的第一输入端a的电流小于电流比较器202A的第二输入端b的电流，此时电流比较器202A的输出端Dout输出第二数字信号“0”。
在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压的情况下，以第一信号输入端VC的电压大于第三信号输入端VE的电压为例，分为两种情况，第一种：第一信号输入端VC的电压与第三信号输入端VE的电压的差值大于或等于阈值电压，第三信号输入端VE提供的电流信号主要通过跨导电路201的第一端流向第一电流源Iref1，此时跨导电路201的第一端的电流I＝Gm×(VC-VE)，跨导电路201的第一端的电流较大，因而电流比较器202A的第一输入端a的电流大于电流比较器202A的第二输入端b的电流，此时电流比较器202A的输出端Dout输出第一数字信号“1”。第二种：第一信号输入端VC的电压与第三信号输入端VE的电压的差值小于阈值电压，第三信号输入端VE提供的电流信号主要通过跨导电路201的第一端流向第一电流源Iref1，此时跨导电路201的第一端的电流I＝Gm×(VC-VE)，但是跨导电路201的第一端的电流较小，因而电流比较器202A的第一输入端a的电流小于电流比较器202A的第二输入端b的电流，此时电流比较器202A的输出端Dout输出第二数字信号“0”。
参考图6，图6包括三幅关系曲线图，分别是上图、中间图和下图；其中，上图表示第一信号输入端VC的电压、第二信号输入端VD的电压、以及第三信号输入端VE的电压的关系图，中间图表示电流比较器202A的第一输入端a的电流Iout、以及电流比较器202A的第二输入端b的电流即第二电流源Iref2的电流；下图表示电流比较器202A的输入端Dout输出的结果，此处输出的结果以数字信号表示。从图6可以看出，在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压，且第一信号输入端VC的电压或第二信号输入端VD的电压与第三信号输入端VE的电压的差值大于或等于阈值电压时，电流比较器202A的第一输入端a的电流Iout大于电流比较器202A的第二输入端b的电流Iref2，电流比较器202A的输出端Dout输出第一数字信号“1”。在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压，且第一信号输入端VC的电压或第二信号输入端VD的电压与第三信号输入端VE的电压的差值小于阈值电压，或者，第一信号输入端VC的电压、以及第二信号输入端VD的电压均小于第三信号输入端VE的电压时，电流比较器202A的第一输入端a的电流Iout小于电流比较器202A的第二输入 端b的电流Iref2，电流比较器202A的输出端Dout输出第二数字信号“0”。
在本申请实施例提供的解调器200应用于近场通信系统10A中的情况下，解调器200的第一信号输入端VC和第二信号输入端VD接收的是天线800传输的射频信号，而解调器200的第三信号输入端VE与整流器100的输出端耦合，用于接收整流器100将从天线800接收到的射频信号转换成的直流信号，因此参考图6可以看出，第一信号输入端VC接收到的射频信号的峰值、第二信号输入端VD接收到的射频信号的峰值与第三信号输入端VE接收到的直流信号的值比较接近。在此基础上，本申请实施例提供的解调器200在解调时，由于是以第三信号输入端VE的电压为参考，和第一信号输入端VC的电压、以及第二信号输入端VD的电压进行对比，而第一信号输入端VC接收到的射频信号的峰值、第二信号输入端VD接收到的射频信号的峰值与第三信号输入端VE接收到的直流信号的值比较接近，因而本申请实施例提供的解调器200在解调时只对有用的信号进行量化，从而可以实现解调器200具有较高的灵敏度，这样一来，解调器200可以对低调制深度的信号进行解调，例如可以解调VHBR协议中的6.8Mbps信号，相对于图3b提供的解调器200而言，本申请实施例提供的解调器200灵敏度更高。此外，由于本申请实施例提供的解调器200主要由跨导电路201和电流比较器202A等构成，因此本申请实施例提供的解调器200所占的面积较小，成本较低。相对于图3a提供的解调器200和图3b提供的解调器200而言，本申请实施例提供的解调器200所占的面积更小，成本更低。
在本申请实施例中，上述跨导电路201示例性地可以包括以下几种实现方式：
第一种方式，如图7a所示，上述跨导电路201包括第一晶体管M1、第二晶体管M2和第三晶体管M3；第一晶体管M1的栅极和第二极均与第三信号输入端VE耦合，第一晶体管M1的第一极与第一电流源Iref1耦合；第一晶体管M1的第一极和第二极中一个为源极，一个为漏极；第二晶体管M2的栅极与第一信号输入端VC耦合，第二晶体管M2的第一极与第一电流源Iref1耦合，第二晶体管M2的第二极与比较器202的第一输入端a耦合；第二晶体管M2的第一极和第二极中一个为源极，一个为漏极；第三晶体管M3的栅极与第二信号输入端VD耦合，第三晶体管M3的第一极与第一电流源Iref1耦合，第三晶体管M3的第二极与比较器202的第一输入端a；第三晶体管M3的第一极和第二极中一个为源极，一个为漏极。
第二种方式，如图7b所示，上述跨导电路201包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4；第一晶体管M1的栅极和第二极均与第三信号输入端VE耦合，第一晶体管M1的第一极与第一电流源Iref1耦合；第一晶体管M1的第一极和第二极中一个为源极，一个为漏极；第二晶体管M2的栅极与第一信号输入端VC耦合，第二晶体管M2的第一极与第一电流源Iref1耦合，第二晶体管M2的第二极与比较器202的第一输入端a耦合；第二晶体管M2的第一极和第二极中一个为源极，一个为漏极；第三晶体管M3的栅极与第二信号输入端VD耦合，第三晶体管M3的第一极与第一电流源Iref1耦合，第三晶体管M3的第二极与比较器202的第一输入端a耦合；第三晶体管M3的第一极和第二极中一个为源极，一个为漏极；第四晶体管M4的栅极与第三信号输入端VE耦合，第四晶体管M4的第一极与第一电流源Iref1耦合，第四晶体管M4的第二极与比较器202的第一输入端a；第四晶体管 M4的第一极和第二极中一个为源极，一个为漏极。
对于跨导电路201，上述第一种方式和第二种方式的区别在于，第二种方式相对于第一种方式多了第四晶体管M4，以下以跨导电路201为第二种方式，即跨导电路201包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4为例对跨导电路201进行介绍，当跨导电路201为第一种方式时，可以参考跨导电路201为第二种方式时的介绍。
需要说明的是，第二晶体管M2的第二极、第三晶体管M3的第二极以及第四晶体管M4的第二极耦合在一起，用于作为跨导电路201的第一端；第一晶体管M1的第一极、第二晶体管M2的第一极、第三晶体管M3的第一极以及第四晶体管M4的第一极耦合在一起，用于作为跨导电路201的偏置端；第一晶体管M1的第二极用于作为跨导电路201的第二端。
此处，第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4例如可以为金属-氧化物-半导体场效应晶体管，简称金氧半场效晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)，也可以称为MOS管。
此外，在本申请实施例中，第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4为N型管。以第一晶体管M1为例，对于N型管，当向第一晶体管M1的栅极提供高电平信号时，第一晶体管M1导通。
可以理解的是，跨导电路201包括但不限于上述第一种方式和第二种方式，还可以包括与第一晶体管M1、第四晶体管M4、第二晶体管M2和第三晶体管M3串联或并联的其它一个或多个晶体管。
以跨导电路201包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4为例，以下对跨导电路201的工作过程进行说明：在第一信号输入端VC的电压大于第三信号输入端VE的电压时，第三晶体管M3断开，第一晶体管M1和第四晶体管M4断开，第二晶体管M2导通，第三信号输入端VE提供的电流信号通过第二晶体管M2(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND；在第一信号输入端VC的电压小于第三信号输入端VE的电压时，第三晶体管M3断开，第二晶体管M2断开，第一晶体管M1和第四晶体管M4导通，第三信号输入端VE提供的电流信号通过第一晶体管M1(即跨导电路201的第二端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND，第三信号输入端VE提供的电流信号还通过第四晶体管M4(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。
基于上述，在第三信号输入端VE提供的电流信号通过第二晶体管M2(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND时，根据第一信号输入端VC和第三信号输入端VE的电压的差值的不同，在第一信号输入端VC的电压与第三信号输入端VE的电压的差值大于或等于阈值电压时，电流比较器202A的第一输入端a的电流大于电流比较器202A的第二输入端b的电流；在第一信号输入端VC的电压与第三信号输入端VE的电压的差值小于阈值电压时，电流比较器202A的第一输入端a的电流小于电流比较器202A的第二输入端b的电流。
在第三信号输入端VE提供的电流信号通过第一晶体管M1(即跨导电路201的第 二端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND；第三信号输入端VE提供的电流信号还通过第四晶体管M4(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND时，电流比较器202A的第一输入端a的电流小于电流比较器202A的第二输入端b的电流。
同样的，在第二信号输入端VD的电压大于第三信号输入端VE的电压时，第二晶体管M2断开，第一晶体管M1和第四晶体管M4断开，第三晶体管M3导通，第三信号输入端VE提供的电流信号通过第三晶体管M3(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND；在第二信号输入端VD的电压小于第三信号输入端VE的电压时，第二晶体管M2断开，第三晶体管M3断开，第一晶体管M1和第四晶体管M4导通，第三信号输入端VE提供的电流信号通过第一晶体管M1(即跨导电路201的第二端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND；第三信号输入端VE提供的电流信号还通过第四晶体管M4(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。
以第一信号输入端VC为例，由于在跨导电路201包括第一晶体管M1、第二晶体管M2和第三晶体管M3，不包括第四晶体管M4的情况下，在第一信号输入端VC的电压小于第三信号输入端VE的电压时，第三信号输入端VE提供的电流信号通过第一晶体管M1(即跨导电路201的第二端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND；在跨导电路201包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4的情况下，在第一信号输入端VC的电压小于第三信号输入端VE的电压时，第三信号输入端VE提供的电流信号通过第一晶体管M1(即跨导电路201的第二端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND；第三信号输入端VE提供的电流信号还通过第四晶体管M4(即跨导电路201的第一端)流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND，基于此，可以看出第四晶体管M4的加入能够保持跨导电路201的第一端上持续有电流，加快运放响应速度。
在跨导电路201包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4，且第一电流镜203A包括第七晶体管M7和第八晶体管M8的情况下，第一晶体管M1的栅极和第四晶体管M4的栅极与第三信号输入端VE耦合，第二晶体管M2的栅极与第一信号输入端VC耦合，第三晶体管M3的栅极与第二信号输入端VD耦合，基于上述可知，第一信号输入端VC、第二信号输入端VD和第三信号输入端VE的电压相近，即可以粗略认为第一晶体管M1、第四晶体管M4、第二晶体管M2和第三晶体管M3的栅极电压相同。此外，由于第一晶体管M1的第一极、第四晶体管M4的第一极、第二晶体管M2的第一极和第三晶体管M3的第一极均与第一电流源Iref1耦合，因而可以认为第一晶体管M1的第一极、第四晶体管M4的第一极、第二晶体管M2的第一极和第三晶体管M3的第一极的电压是相同。另外，由于第四晶体管M4的第二极、第二晶体管M2的第二极和第三晶体管M3的第二极通过第七晶体管M7与第三信号输入端VE耦合，因而可以认为第四晶体管M4的第二极、第二晶体管M2的第二极和第三晶体管M3的第二极的电压是相同的，考虑到若第一晶体管M1的第二极直接与第三信号输入端VE耦合，则第一晶体管M1的第二极的电压会与第四 晶体管M4的第二极、第二晶体管M2的第二极和第三晶体管M3的第二极的电压不相同，也就是说第一晶体管M1的Vds与第四晶体管M4的Vds、第二晶体管M2的Vds和第三晶体管M3的Vds会不相同，这样会导致沟道长度调制效应。基于此，为了降低沟道长度调制效应的影响，在一些示例中，如图8所示，上述解调器200还包括第十一晶体管M11，第十一晶体管M11的栅极和第一极与跨导电路201的第二端耦合，在跨导电路201包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4的情况下，即第十一晶体管M11的栅极和第一极与第一晶体管M1的第二极耦合，第十一晶体管M11的第二极与第三信号输入端VE耦合；其中，第十一晶体管M11的第一极和第二极中一个为源极，一个为漏极。
此处，第十一晶体管M11例如可以为MOS管。
另外，在本申请实施例中，第十一晶体管M11为P型管。
在解调器200中设置第十一晶体管M11时，对于跨导电路201中的第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4而言，由于第一晶体管M1的第二极通过第十一晶体管M11与第三信号输入端VE耦合，第四晶体管M4的第二极、第二晶体管M2的第二极和第三晶体管M3的第二极通过第七晶体管M7与第三信号输入端VE耦合，因此可以认为第一晶体管M1的第二极、第四晶体管M4的第二极、第二晶体管M2的第二极和第三晶体管M3的第二极的电压相同或相近，而第一晶体管M1的第一极、第四晶体管M4的第一极、第二晶体管M2的第一极和第三晶体管M3的第一极均与第一电流源Iref 1耦合，因而可以认为第一晶体管M1的第一极、第四晶体管M4的第一极、第二晶体管M2的第一极和第三晶体管M3的第一极的电压是相同，这样一来，第一晶体管M1的Vds、第四晶体管M4的Vds、第二晶体管M2的Vds和第三晶体管M3的Vds是相同或相近的，因此可以降低沟道长度调制效应的影响。
考虑到解调器200的第三信号输入端VE通常与整流器100的输出端耦合，而整流器100的输出端会发生抖动，从而导致整流器100的输出端输出的电压不稳定，这样一来，解调器200的第三信号输入端VE的电压会不稳定。基于此，参考图8，在一些示例中，上述解调器200还包括滤波器204，滤波器204耦合在第三信号输入端VE和接地端GND之间。
由于滤波器204可以起到稳压的作用，因而在第三信号输入端VE耦合滤波器204，这样可以确保第三信号输入端VE提供的电压是稳定的，进而有利于提高解调器200的性能。
在一些示例中，如图8所示，上述滤波器204可以包括电容C和第三电阻R3；电容C和第三电阻R3串联在第三信号输入端VE和接地端GND之间。
基于上述，对于解调器200中的电流比较器202A，示例性地可以采用以下几种方式实现。
方式一
如图9所示，电流比较器202A可以包括：电压比较器(voltage comparator)2021、第一电阻R1和第二电阻R2；电压比较器2021的第一输入端与跨导电路201的第一端耦合，电压比较器2021的第二输入端与第二电流源Iref2耦合，电压比较器2021的输 出端耦合至信号输出端Dout；第一电阻R1耦合在电压比较器2021的第一输入端和接地端GND之间，第二电阻R2耦合在电压比较器2021的第二输入端和接地端GND之间。
需要说明的是，电压比较器2021的第一输入端用于作为电流比较器202A的第一输入端，电压比较器2021的第二输入端用于作为电流比较器202A的第二输入端，电压比较器2021的输出端用于作为电流比较器202A的输出端。
可以理解的是，电压比较器2021的第一输入端与跨导电路201的第一端可以直接耦合，也可以通过其他电路结构例如第一电流镜203A耦合在一起。在电压比较器2021的第一输入端通过第一电流镜203A与跨导电路201的第一端耦合的情况下，电压比较器2021的第一输入端与第一电流镜203A的输出端耦合。
应当理解到，电压比较器2021用于将电压比较器2021的第一输入端的电压与电压比较器2021的第二输入端的电压进行比较，从而在电压比较器2021的输出端输出第一数字信号“1”，或者第二数字信号“0”，当电压比较器2021的第一输入端的电压大于电压比较器2021的第二输入端的电压时，输出第一数字信号“1”；当电压比较器2021的第一输入端的电压小于电压比较器2021的第二输入端的电压时，输出第二数字信号“0”。此处，电压比较器2021的第一输入端的电压等于电压比较器2021的第一输入端的电流乘以第一电阻R1，电压比较器2021的第二输入端的电压等于电压比较器2021的第二输入端的电流乘以第二电阻R2。
此处，第一电阻R1的大小和第二电阻R2的大小可以相等，也可以不相等。
对于电压比较器2021而言，电压比较器2021的第一输入端的电压和电压比较器2021的第二输入端的电压越大，电压比较器2021的输出端输出的结果越准确。以电压比较器2021的第一输入端的电压为例，在电压比较器2021的第一输入端的电流一定的情况下，若通过提高第一电阻R1的阻值，来提高电压比较器2021的第一输入端的电压，则需要第一电阻R1的阻值较大，这样会导致第一电阻R1所占的面积较大。基于此，在一些示例中，如图10所示，上述电流比较器202A还包括：第五晶体管M5和第六晶体管M6；第五晶体管M5和第一电阻R1串联在电压比较器2021的第一输入端和接地端GND之间，第五晶体管M5的栅极和第一极均与电压比较器2021的第一输入端耦合，第五晶体管M5的第二极与接地端GND耦合；第五晶体管M5的第一极和第二极中一个为源极，一个为漏极；第六晶体管M6和第二电阻R2串联在电压比较器2021的第二输入端和接地端GND之间，第六晶体管M6的栅极和第一极均与电压比较器2021的第二输入端耦合，第六晶体管M6的第二极与接地端GND耦合；第六晶体管M6的第一极和第二极中一个为源极，一个为漏极。
此处，可以是第五晶体管M5的栅极和第一极通过第一电阻R1与电压比较器2021的第一输入端耦合，第五晶体管M5的第二极与接地端GND直接耦合；也可以是第五晶体管M5的栅极和第一极直接与电压比较器2021的第一输入端耦合，第五晶体管M5的第二极通过第一电阻R1与接地端GND耦合。同样的，可以是第六晶体管M6的栅极和第一极通过第二电阻R2与电压比较器2021的第二输入端耦合，第六晶体管M6的第二极与接地端GND直接耦合；也可以是第六晶体管M6的栅极和第一极直接与电压比较器2021的第二输入端耦合，第六晶体管M6的第二极通过第二电阻R2与 接地端GND直接耦合。
此外，第五晶体管M5和第六晶体管M6例如可以为MOS管。
在此基础上，在本申请实施例中，第五晶体管M5和第六晶体管M6为N型管。
由于电流比较器202A包括第五晶体管M5，第五晶体管M5可以充当电阻，因而可以提高电压比较器2021的第一输入端的电压，且在相同阻值的情况下，第五晶体管M5的所占面积相对于纯电阻而言，面积较小。同样的，由于电流比较器202A包括第六晶体管M6，第六晶体管M6可以充当电阻，因而可以提高电压比较器2021的第二输入端的电压，且在相同阻值的情况下，第六晶体管M6所占的面积相对于纯电阻而言，面积较小。
方式二
在解调器200包括第一电流镜203A，且第一电流镜203A包括第七晶体管M7和第八晶体管M8的情况下，如图11所示，上述电流比较器202A包括：第二电流镜2022；第二电流镜2022的输入端与第二电流源Iref2耦合，第二电流镜2022的输出端和信号输出端Dout均与第八晶体管M8的第一极耦合；第二电流镜2022用于将第二电流源Iref2的电流镜像放大，并将放大后的电流输出至第二电流镜2022的输出端。
可以理解的是，在电流比较器202A包括第二电流镜2022的情况下，第八晶体管M8的第一极相当于电流比较器202A2的第一输入端a，电流比较器202A2的第一输入端a与信号输出端Dout耦合在一起。
需要说明的是，第二电流镜2022的一个输入端与第二电流源Iref2耦合，另一个输入端可以与接地端GND耦合。
此处，对于第二电流镜2022的放大倍数不进行限定，可以通过调整第二电流镜2022的结构、参数等，调整第二电流镜2022的放大倍数。
在一些示例中，如图11所示，第二电流镜2022包括：第九晶体管M9和第十晶体管M10；第九晶体管M9的栅极和第一极均与第二电流源Iref2耦合，第九晶体管M9的第二极与接地端GND耦合；第九晶体管M9的第一极和第二极中一个为源极，一个为漏极；第十晶体管M10的栅极与第二电流源Iref2耦合，第十晶体管M10的第一极和信号输出端Dout均与第八晶体管M8的第一极耦合，第十晶体管M10的第二极与接地端GND耦合；第十晶体管M10的第一极和第二极中一个为源极，一个为漏极。
此处，第九晶体管M9和第十晶体管M10例如可以为MOS管。
此外，在本申请实施例中，第九晶体管M9和第十晶体管M10为N型管。
另外，可以通过调整第九晶体管M9和第十晶体管M10的长宽比，来调整第二电流镜2022的镜像放大倍数。
在电流比较器202A包括第二电流镜2022的情况下，第二电流源Iref2输出的电流经过第二电流镜2022放大后和第八晶体管M8的第一极输出的电流作比较，就能产生对应的数字信号，当第八晶体管M8的第一极输出的电流大于第二电流源Iref2输出的电流经过第二电流镜2022放大后的电流时，信号输出端Dout输出第一数字信号“1”；当第八晶体管M8的第一极输出的电流小于第二电流源Iref2输出的电流经过第二电流镜2022放大后的电流时，信号输出端Dout输出第二数字信号“0”。在电流比较器202A 包括第二电流镜2022的情况下，电流比较器202A的电路结构更为简单，面积更小，成本更低。
可以理解的是，解调器200中的电流比较器202A的实现方式包括但不限于上述两种方式，还可以包括其它方式，以能将电流比较器202A的第一输入端a的电流和电流比较器202A的第二输入端b的电流比较后，输出第一数字信号“1”或第二数字信号“0”为准。
实施例二
在本实施例二中，如图12a和图12b所示，上述负载模块203包括阻抗，信号源Ref为参考电压源Vref，比较器202为电压比较器2021，电压比较器2021的第二输入端b与参考电压源Vref耦合，电压比较器2021用于将第一输入端a的电压和第二输入端b的电压进行比较，并输出比较结果。在一些示例中，电压比较器2021用于将第一输入端a的电压和第二输入端b的电压进行比较，在第一输入端a的电压大于第二输入端b的电压时，输出第一数字信号“1”；在第一输入端a的电压小于第二输入端b的电压时，输出第二数字信号“0”。
在本实施例二中，跨导电路201的第一端与电压比较器2021的第一输入端a直接耦合。
需要说明的是，在负载模块203包括阻抗的情况下，示例性地，该阻抗可以包括如图12a所示的第十二晶体管M12，第十二晶体管M12的栅极和第一极与跨导电路201的第一端耦合，第十二晶体管M12的第二极与第三信号输入端VE耦合，其中，第十二晶体管M12的第一极和第二极中一个为源极，一个为漏极；该阻抗也可以包括如图12b所示的电阻RL，电阻RL的一端与第三信号输入端VE耦合，另一端与跨导电路201的第一端耦合。
本实施例二仅对与实施例一不相同的部分进行介绍，与实施例一相同的部分可以参考上述实施例一，此处不再赘述。例如，解调器200的工作原理、跨导电路201的具体结构、第十一晶体管M11、以及滤波器204等均可以参考上述实施例一。
在解调器200为上述实施例一或实施例二提供的解调器200的情况下，本申请的实施例还提供一种上述近场通信系统10A的控制方法，如图13所示，该控制方法包括：
S10、解调器200的第一信号输入端VC和第二信号输入端VD接收射频信号，解调器200的第三信号输入端VE接收直流信号；其中，第一信号输入端VC和第二信号输入端VD接收到的射频信号为一对差分信号。
S11、解调器200根据第一信号输入端VC的电压或第二信号输入端VD的电压与第三信号输入端VE的电压的比较结果，选择是否将第三信号输入端VE提供的电流信号通过跨导电路201的第一端或跨导电路201的第二端流向第一电流源Iref1。
在一些示例中，解调器200根据第一信号输入端VC的电压、第二信号输入端VD的电压与第三信号输入端VE的电压的比较结果，在第一信号输入端VC的电压或第二信号输入端VD的电压大于第三信号输入端VE的电压时，将第三信号输入端VE提供的电流信号通过跨导电路201的第一端流向第一电流源Iref1，并通过第一电流源 Iref1流向接地端GND。在一些示例中，解调器200根据第一信号输入端VC的电压、第二信号输入端VD的电压与第三信号输入端VE的电压的比较结果，在第一信号输入端VC的电压和第二信号输入端VD的电压均小于第三信号输入端VE的电压时，将第三信号输入端VE提供的电流信号通过跨导电路201的第二端流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。
S12、比较器202将第一输入端a的信号和第二输入端b的信号进行比较，并输出比较结果。
在一些示例中，比较器202将第一输入端a的信号和第二输入端b的信号进行比较，在第一输入端a的信号大于第二输入端b的信号时，输出第一数字信号“1”；在第一输入端a的信号小于第二输入端b的信号时，输出第二数字信号“0”。
在比较器202为电流比较器202A的情况下，电流比较器202A将第一输入端a的电流和第二输入端b的电流进行比较，在第一输入端a的电流大于第二输入端b的电流时，输出第一数字信号“1”；在第一输入端a的电流小于第二输入端b的电流时，输出第二数字信号“0”。在比较器202为电压比较器2021的情况下，将电压比较器2021将第一输入端a的电压和第二输入端b的电压进行比较，在第一输入端a的电压大于第二输入端b的电压时，输出第一数字信号“1”；在第一输入端a的电压小于第二输入端b的电压时，输出第二数字信号“0”。
需要说明的是，本申请实施例提供的近场通信系统10A的控制方法具有与上述近场通信系统10A相同的技术效果，可以参考上述有关近场通信系统10A的技术效果的描述，此处不再赘述。
实施例三
实施例三和实施例一的区别之处在于，在实施例一中，近场通信系统10A中的天线800向解调器200提供一对差分信号，即解调器200包括第一信号输入端VC和第二信号输入端VD。在实施例三中，近场通信系统10A中的天线800向解调器200提供单端信号，即解调器200包括第一信号输入端VC，不包括第二信号输入端VD。
在实施例三中，如图14所示，近场通信系统10A中的解调器200包括：跨导电路201、第一电流源Iref1、信号源Ref、比较器202、负载模块203、第一信号输入端VC、第三信号输入端VE以及信号输出端Dout；其中，第一信号输入端VC用于接收射频信号，整流器100的信号输出端还与解调器200的第三信号输入端VE耦合，用于为第三信号输入端VE提供直流信号。
上述跨导电路201的偏置端与第一电流源Iref1耦合，跨导电路201的第一端与比较器202的第一输入端a耦合，跨导电路201的第二端与第三信号输入端VE耦合，跨导电路201的控制端与第一信号输入端VC和第三信号输入端VE均耦合。跨导电路201用于根据第一信号输入端VC的电压与第三信号输入端VE的电压的比较结果，选择是否将第三信号输入端VE提供的电流信号通过跨导电路2001的第一端或跨导电路201的第二端流向第一电流源Iref1。
在一些示例中，跨导电路201用于在第一信号输入端VC的电压大于第三信号输入端VE的电压时，将第三信号输入端VE提供的电流信号通过跨导电路201的第一 端流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。在一些示例中，跨导电路201用于在第一信号输入端VC的电压小于第三信号输入端VE的电压时，将第三信号输入端VE提供的电流信号通过跨导电路201的第二端流向第一电流源Iref1，并通过第一电流源Iref1流向接地端GND。
比较器202的第一输入端a还通过负载模块203与第三信号输入端VE耦合，比较器202的第二输入端b与信号源Ref耦合，比较器202的输出端耦合至信号输出端Dout，比较器202用于将第一输入端a的信号和第二输入端b的信号进行比较，并输出比较结果。在一些示例中，比较器202用于将第一输入端a的信号和第二输入端b的信号进行比较，在第一输入端a的信号大于第二输入端b的信号时，输出第一数字信号例如“1”；在第一输入端a的信号小于第二输入端b的信号时，输出第二数字信号例如“0”。
上述负载模块203包括第一电流镜203A，信号源Ref为第二电流源Iref2，比较器202为电流比较器202A，电流比较器202A的第二输入端b与第二电流源Iref2耦合，电流比较器202A用于将第一输入端a的电流和第二输入端b的电流进行比较，并输出比较结果。在一些示例中，电流比较器202A用于将第一输入端a的电流和第二输入端b的电流进行比较，在第一输入端a的电流大于第二输入端b的电流时，输出第一数字信号“1”；在第一输入端a的电流小于第二输入端b的电流时，输出第二数字信号“0”。
在解调器200包括第一信号输入端VC，不包括第二信号输入端VD的情况下，解调器200的工作过程可以参考上述，此处不再赘述。
在解调器200包括第一信号输入端VC，不包括第二信号输入端VD的情况下，在一些示例中，跨导电路201仅包括第一晶体管M1和第二晶体管M2。在另一些示例中，跨导电路201包括第一晶体管M1、第二晶体管M2和第四晶体管M4。其中，第一晶体管M1、第二晶体管M2和第四晶体管M4的连接关系、以及作用可以参考上述，此处不再赘述。
在解调器200包括第一信号输入端VC，不包括第二信号输入端VD的情况下，解调器200还可以包括第一电流镜203A、第十一晶体管M11、滤波器204等，第一电流镜203A、第十一晶体管M11、滤波器204等的结构、连接关系、作用等均可以参考上述，此处不再赘述。另外，解调器200中电流比较器202A的实现方式、近场通信系统10A的控制方法等也可以参考上述，此处不再赘述。
实施例三以负载模块203包括第一电流镜203A，信号源Ref为第二电流源Iref2，比较器202为电流比较器202A为例进行说明。在另一些实施例中，上述负载模块203包括阻抗，信号源Ref为参考电压源Vref，比较器202为电压比较器2021，电压比较器2021的第二输入端b与参考电压源Vref耦合，具体可以参考实施例二，此处不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种近场通信系统，其特征在于，包括：整流器、解调器和电源管理单元；
    所述解调器包括：跨导电路、第一电流源、信号源、负载模块、第一信号输入端、第二信号输入端、第三信号输入端以及信号输出端；其中，所述第一信号输入端和所述第二信号输入端用于接收射频信号，且所述第一信号输入端和所述第二信号输入端接收的射频信号为一对差分信号；
    所述整流器的信号输出端与所述电源管理单元耦合，所述电源管理单元与所述解调器的电源输入端耦合，用于为所述解调器供电；所述整流器的信号输出端还与所述解调器的第三信号输入端耦合，用于为所述第三信号输入端提供直流信号；
    所述跨导电路的偏置端与所述第一电流源耦合，所述跨导电路的第二端与所述第三信号输入端耦合，所述跨导电路的控制端与所述第一信号输入端、所述第二信号输入端和所述第三信号输入端均耦合；
    所述跨导电路用于根据所述第一信号输入端的电压或所述第二信号输入端的电压与所述第三信号输入端的电压的比较结果，选择是否将所述第三信号输入端提供的电流信号通过所述跨导电路的第一端或所述跨导电路的第二端流向所述第一电流源。
  2. 根据权利要求1所述的近场通信系统，其特征在于，所述跨导电路用于在所述第一信号输入端的电压或所述第二信号输入端的电压大于所述第三信号输入端的电压时，将所述第三信号输入端提供的电流信号通过所述跨导电路的第一端流向所述第一电流源。
  3. 根据权利要求1或2所述的近场通信系统，其特征在于，所述跨导电路用于在所述第一信号输入端的电压和所述第二信号输入端的电压均小于所述第三信号输入端的电压时，将所述第三信号输入端提供的电流信号通过所述跨导电路的第二端流向所述第一电流源。
  4. 根据权利要求1-3任一项所述的近场通信系统，其特征在于，所述解调器还包括比较器；
    所述比较器的第一输入端与所述跨导电路的第一端耦合，所述比较器的第一输入端还通过所述负载模块与所述第三信号输入端耦合，所述比较器的第二输入端与所述信号源耦合，所述比较器的输出端耦合至所述信号输出端，所述比较器用于将所述第一输入端的信号和所述第二输入端的信号进行比较，并输出比较结果。
  5. 根据权利要求4所述的近场通信系统，其特征在于，所述信号源为第二电流源，所述比较器为电流比较器；
    所述负载模块包括第一电流镜，所述第一电流镜的第一输入端与所述跨导电路的第一端耦合，所述第一电流镜的第二输入端与所述第三信号输入端耦合，所述第一电流镜的输出端与所述电流比较器的第一输入端耦合；
    所述第一电流镜用于将所述跨导电路的第一端的电流镜像放大，并将放大后的电流输出至所述第一电流镜的输出端。
  6. 根据权利要求1-5任一项所述的近场通信系统，其特征在于，所述跨导电路包括第一晶体管、第二晶体管和第三晶体管；
    所述第一晶体管的栅极和第二极均与所述第三信号输入端耦合，第一极与所述第 一电流源耦合；所述第一晶体管的第一极和第二极中一个为源极，一个为漏极；
    所述第二晶体管的栅极与所述第一信号输入端耦合，第一极与所述第一电流源耦合，第二极与所述比较器的第一输入端耦合；所述第二晶体管的第一极和第二极中一个为源极，一个为漏极；
    所述第三晶体管的栅极与所述第二信号输入端耦合，第一极与所述第一电流源耦合，第二极与所述比较器的第一输入端耦合；所述第三晶体管的第一极和第二极中一个为源极，一个为漏极。
  7. 根据权利要求6所述的近场通信系统，其特征在于，所述跨导电路还包括第四晶体管；
    所述第四晶体管的栅极与所述第三信号输入端耦合，第一极与所述第一电流源耦合，第二极与所述比较器的第一输入端耦合；所述第四晶体管的第一极和第二极中一个为源极，一个为漏极。
  8. 根据权利要求5所述的近场通信系统，其特征在于，所述电流比较器包括：电压比较器、第一电阻和第二电阻；
    所述电压比较器的第一输入端与所述跨导电路的第一端耦合，所述电压比较器的第二输入端与所述第二电流源耦合，所述电压比较器的输出端耦合至所述信号输出端；
    所述第一电阻耦合在所述电压比较器的第一输入端和所述接地端之间，所述第二电阻耦合在所述电压比较器的第二输入端和所述接地端之间。
  9. 根据权利要求8所述的近场通信系统，其特征在于，所述电流比较器还包括：第五晶体管和第六晶体管；
    所述第五晶体管和所述第一电阻串联在所述电压比较器的第一输入端和所述接地端之间，所述第五晶体管的栅极和第一极均与所述电压比较器的第一输入端耦合，所述第五晶体管的第二极与所述接地端耦合；所述第五晶体管的第一极和第二极中一个为源极，一个为漏极；
    所述第六晶体管和所述第二电阻串联在所述电压比较器的第二输入端和所述接地端之间，所述第六晶体管的栅极和第一极均与所述电压比较器的第二输入端耦合，所述第六晶体管的第二极与所述接地端耦合；所述第六晶体管的第一极和第二极中一个为源极，一个为漏极。
  10. 根据权利要求5所述的近场通信系统，其特征在于，所述第一电流镜包括第七晶体管和第八晶体管；
    所述第七晶体管的栅极和第一极与所述跨导电路的第一端耦合，所述第七晶体管的第二极与所述第三信号输入端耦合；所述第七晶体管的第一极和第二极中一个为源极，一个为漏极；
    所述第八晶体管的栅极与所述第七晶体管的栅极耦合，所述第八晶体管的第一极与所述电流比较器的第一输入端耦合，所述第八晶体管的第二极与所述第三信号输入端耦合；所述第八晶体管的第一极和第二极中一个为源极，一个为漏极。
  11. 根据权利要求10所述的近场通信系统，其特征在于，所述电流比较器包括：第二电流镜；所述第二电流镜的输入端与所述第二电流源耦合，所述第二电流镜的输出端和所述信号输出端均与所述第八晶体管的第一极耦合；
    所述第二电流镜用于将所述第二电流源的电流镜像放大，并将放大后的电流输出至所述第二电流镜的输出端。
  12. 根据权利要求11所述的近场通信系统，其特征在于，所述第二电流镜包括：第九晶体管和第十晶体管；
    所述第九晶体管的栅极和第一极均与所述第二电流源耦合，所述第九晶体管的第二极与所述接地端耦合；所述第九晶体管的第一极和第二极中一个为源极，一个为漏极；
    所述第十晶体管的栅极与所述第二电流源耦合，所述第十晶体管的第一极和所述信号输出端均与所述第八晶体管的第一极耦合；所述第十晶体管的第二极与所述接地端耦合；所述第十晶体管的第一极和第二极中一个为源极，一个为漏极。
  13. 根据权利要求10-12任一项所述的近场通信系统，其特征在于，所述解调器还包括：第十一晶体管，所述第十一晶体管的栅极和第一极与所述跨导电路的第二端耦合，所述第十一晶体管的第二极与所述第三信号输入端耦合；
    所述第十一晶体管的第一极和第二极中一个为源极，一个为漏极。
  14. 根据权利要求1-13任一项所述的近场通信系统，其特征在于，所述解调器还包括滤波器，所述滤波器串联在所述第三信号输入端和所述接地端之间。
  15. 根据权利要求14所述的近场通信系统，其特征在于，所述滤波器包括电容和第三电阻；
    所述电容和所述第三电阻耦合在所述第三信号输入端和所述接地端之间。
  16. 根据权利要求1-15任一项所述的近场通信系统，其特征在于，所述近场通信系统还包括天线，所述解调器的所述第一信号输入端和所述第二信号输入端均与所述天线耦合，所述天线将接收到的射频信号传输给所述第一信号输入端和所述第二信号输入端。
  17. 一种近场通信系统的控制方法，其特征在于，所述近场通信系统包括：整流器、解调器和电源管理单元；所述解调器包括：跨导电路、第一电流源、信号源、负载模块、第一信号输入端、第二信号输入端、第三信号输入端以及信号输出端；所述整流器的信号输出端与所述电源管理单元耦合，所述电源管理单元与所述解调器的电源输入端耦合，所述整流器的信号输出端还与所述解调器的第三信号输入端耦合；所述跨导电路的偏置端与所述第一电流源耦合，所述跨导电路的第二端与所述第三信号输入端耦合，所述跨导电路的控制端与所述第一信号输入端、所述第二信号输入端和所述第三信号输入端均耦合；
    所述控制方法包括：
    所述解调器的所述第一信号输入端和所述第二信号输入端接收射频信号，所述解调器的所述第三信号输入端接收直流信号；其中，所述第一信号输入端和所述第二信号输入端接收到的射频信号为一对差分信号；
    所述解调器根据所述第一信号输入端的电压或所述第二信号输入端的电压与所述第三信号输入端的电压的比较结果，选择是否将所述第三信号输入端提供的电流信号通过所述跨导电路的第一端或所述跨导电路的第二端流向所述第一电流源。
  18. 根据权利要求17所述的控制方法，其特征在于，所述解调器还包括比较器； 所述比较器的第一输入端与所述跨导电路的第一端耦合，所述比较器的第一输入端还通过所述负载模块与所述第三信号输入端耦合，所述比较器的第二输入端与所述信号源耦合，所述比较器的输出端耦合至所述信号输出端；
    所述控制方法还包括：
    所述比较器将所述第一输入端的信号和所述第二输入端的信号进行比较，并输出比较结果。
  19. 一种电子设备，其特征在于，包括印刷电路板和如权利要求1-16任一项所述的近场通信系统。
PCT/CN2022/076380 2022-02-15 2022-02-15 近场通信系统及其控制方法、电子设备 WO2023155050A1 (zh)

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CN101162912A (zh) * 2007-11-19 2008-04-16 上海士康射频技术有限公司 单芯片射频收发器
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CN106815625A (zh) * 2015-12-02 2017-06-09 华大半导体有限公司 一种适合超低功耗设计的新型解调电路
CN113259292A (zh) * 2021-05-28 2021-08-13 卓捷创芯科技（深圳）有限公司 一种差分输入的射频识别标签调幅波包络信号解调电路

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US20090153240A1 (en) * 2007-08-29 2009-06-18 Texas Instruments Deutschland Gmbh Comparator with sensitivity control
CN101162912A (zh) * 2007-11-19 2008-04-16 上海士康射频技术有限公司 单芯片射频收发器
CN106815625A (zh) * 2015-12-02 2017-06-09 华大半导体有限公司 一种适合超低功耗设计的新型解调电路
CN113259292A (zh) * 2021-05-28 2021-08-13 卓捷创芯科技（深圳）有限公司 一种差分输入的射频识别标签调幅波包络信号解调电路

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