WO2023151153A1 - 晶圆分析方法及晶圆分析装置 - Google Patents
晶圆分析方法及晶圆分析装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 222
- 238000012545 processing Methods 0.000 claims abstract description 172
- 238000000034 method Methods 0.000 claims abstract description 84
- 230000005856 abnormality Effects 0.000 claims abstract description 15
- 235000012431 wafers Nutrition 0.000 claims description 327
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 238000010586 diagram Methods 0.000 description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Definitions
- the present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a wafer analysis method and a wafer analysis device.
- the exposure process is one of the important process technologies in the semiconductor process.
- the exposure quality of the exposure machine has an important influence on the exposure quality of the wafer (eg, the feature size of the exposure pattern).
- the exposure intensity deviation (Dose Error) per unit area is one of the key parameters for evaluating the exposure quality of the exposure machine. If the Dose Error of the exposure machine is too high, it will lead to abnormal product feature size. If the abnormal product cannot be intercepted in time, the product will flow to the next processing station, resulting in a decrease in product yield.
- engineers do not have an effective way to obtain abnormal wafer products during the exposure process of the exposure machine. They can only go through manual inspection, which is inefficient, time-consuming and labor-intensive, and seriously affects the production capacity of the machine.
- the present disclosure provides a wafer analysis method and a wafer analysis device, which are used to solve the current problem that automatic positioning of abnormal wafer products cannot be realized, so as to improve the yield rate of wafer products and the productivity of semiconductor machines.
- the present disclosure provides a wafer analysis method, comprising the steps of:
- Analyzing the processing information finding the machine abnormal time period when the semiconductor machine has an abnormal situation, and finding the processing time period when the wafer is processed in the semiconductor machine;
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, and it is confirmed that the wafer is an abnormal wafer.
- the specific steps of finding the machine abnormal time period when the semiconductor machine has an abnormal situation include:
- the specific steps of finding the processing time period for the wafer to perform the semiconductor process in the semiconductor tool include:
- the processing time period is the time period from entering the semiconductor machine to exiting the semiconductor machine for each batch of wafers,
- Each batch of wafers includes a plurality of wafers.
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, and it is confirmed that the wafer is an abnormal wafer. Steps include:
- the following steps are further included:
- the specific steps of finding the processing time period for the wafer to perform the semiconductor process in the semiconductor tool include:
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, and it is confirmed that the wafer is an abnormal wafer. Steps include:
- the following steps are further included:
- the abnormal wafers are automatically marked.
- the present disclosure also provides a wafer analysis device, comprising:
- the acquisition circuit is used to acquire the processing information of the semiconductor process of the wafer in the semiconductor machine
- An analysis circuit configured to analyze the processing information, find out the machine abnormal time period when the semiconductor machine has an abnormal situation, and find out the processing time period when the wafer is in the semiconductor machine for semiconductor process;
- the processor is configured to confirm that the wafer is an abnormal wafer when the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine.
- the analysis circuit is used to find a time period when the processing parameter of the semiconductor machine exceeds a threshold range, as an abnormal time period of the semiconductor machine.
- the analysis circuit is also used to search for a plurality of processing time periods corresponding to a plurality of batches of wafers one-to-one, and the processing time period is for each batch of wafers from entering the semiconductor
- Each batch of wafers includes a plurality of wafers during the time period from the machine to exiting the semiconductor machine.
- the setting circuit is also used to set a preset time period for a single batch of wafers to be processed in the semiconductor machine for the semiconductor process;
- the processor is further configured to acquire a wafer abnormal time range of abnormal wafers produced by the semiconductor tool according to the machine abnormal time period and the preset duration, and obtain at least a part of the abnormal wafer time range corresponding to the wafer abnormal time range.
- the overlapping processing time period is used as a target processing time period, and it is confirmed that the batch of wafers corresponding to the target processing time period is an abnormal batch of wafers.
- the processor is further configured to automatically intercept the abnormal batch of wafers after confirming that the batch of wafers corresponding to the target processing time period is an abnormal batch of wafers.
- the analysis circuit is used to find the start time point when each wafer starts to process the semiconductor process, and the end time point when the semiconductor process process ends, and use the start The time period between the time point and the end time point is used as the processing time period.
- the processor is configured to use the machine abnormal time period as the wafer abnormal time range of the abnormal wafer generated by the semiconductor tool, and obtain the processing time including the wafer abnormal time range segment as the target processing time segment, and confirming that the wafer corresponding to the target processing time segment is an abnormal wafer.
- the processor is further configured to automatically mark the abnormal wafers.
- the wafer analysis method and the wafer analysis device collect and analyze the processing information of the semiconductor process on the wafer in the semiconductor machine, according to the abnormal time period of the machine in the processing information and the described Whether there is overlap in the processing time of the semiconductor process in the semiconductor machine, to automatically judge whether the wafer is an abnormal wafer, so as to realize the automatic positioning of the abnormal wafer, so as to intercept the abnormal wafer products in time, etc. Measures to prevent abnormal wafer products from flowing into the next processing station, thereby achieving the effect of improving the yield rate of wafer products. At the same time, since the abnormal wafer can be automatically located, the tedious operation of manual search is avoided, thereby improving the production capacity of the semiconductor machine.
- Fig. 5 is a structural block diagram of a wafer analysis device in a specific embodiment of the present disclosure.
- FIG. 1 is a flow chart of the wafer analysis method in this specific embodiment. As shown in Figure 1, the wafer analysis method provided in this specific embodiment includes the following steps:
- Step S11 acquiring processing information of the semiconductor manufacturing process of the wafer in the semiconductor machine.
- the semiconductor equipment described in this specific embodiment may be, but not limited to, an exposure equipment.
- the processing information includes the basic information of the semiconductor machine (such as model information, etc.), the time information when the semiconductor machine performs the semiconductor process, and the semiconductor process of the wafer in the semiconductor machine. One or two or more of the processing time period of the semiconductor tool and the processing parameter information when the semiconductor tool is performing the semiconductor manufacturing process.
- the processing parameter information of the semiconductor machine when performing the semiconductor process can be obtained through detection by a sensor disposed inside the semiconductor machine.
- the processing parameter may include an exposure intensity value (Dose value) per unit area.
- Step S12 analyzing the processing information, searching for the machine abnormality time period when the semiconductor machine has an abnormal situation, and finding the processing time period for the wafer to be processed in the semiconductor machine.
- the specific steps of finding the machine abnormal time period when the semiconductor machine has an abnormal situation include:
- the processing information may be, but not limited to, a semiconductor machine log stored inside or outside the semiconductor machine.
- Pre-set the threshold range of the processing parameter of the semiconductor machine and then search for the time period when the value of the processing parameter exceeds the threshold range in the analyzed processing information, and use the time period when the value of the processing parameter exceeds the threshold range.
- the time period in the threshold range is used as the machine abnormal time period when the semiconductor machine has an abnormal situation.
- the threshold value range in this specific implementation manner includes any one of the upper limit value and the lower limit value of the processing parameter, or a combination of both.
- the semiconductor machine is an exposure machine
- the processing parameter is Dose
- the threshold range includes a range between an upper limit and a lower limit of Dose of the exposure machine.
- the time period when the Dose value in the processing information exceeds the upper limit or the lower limit is the machine abnormality time period of the exposure machine.
- the abnormal time period described in this specific embodiment includes any one of the time point when the Dose value exceeds the threshold range, the time period when the Dose value exceeds the threshold range, or a combination of both.
- the specific value of the threshold range can be set according to actual needs, for example, determined according to the specific type of the semiconductor manufacturing process.
- the specific steps of finding the processing time period for the wafer to perform the semiconductor process in the semiconductor tool include:
- the processing time period is the time period from entering the semiconductor machine to exiting the semiconductor machine for each batch of wafers,
- Each batch of wafers includes a plurality of wafers.
- the semiconductor tool sequentially processes multiple batches of wafers in the semiconductor manufacturing process, and each batch of wafers includes multiple wafers.
- the processing time period is the time period from when the first wafer of each batch enters the semiconductor tool to when the last wafer of each batch exits the semiconductor tool.
- the multiple sheets mentioned in this specific embodiment refer to more than two sheets.
- Step S13 the machine abnormality time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, and it is confirmed that the wafer is an abnormal wafer.
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, it indicates that the wafer is in the semiconductor machine. If the semiconductor process is processed during the time period when the processing parameter is abnormal, the abnormal processing parameter will cause the abnormality of the semiconductor process, and then cause the abnormality of the wafer processed by the semiconductor process.
- the overlap described in this specific embodiment may be partial overlap, or the abnormal time period of the machine is completely included in the processing time period, or the processing time period is completely included in the abnormal machine within the time period.
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, and it is confirmed that the wafer is an abnormal wafer. Steps include:
- FIG. 2 is a schematic diagram of automatic positioning of abnormal batches of wafers in a specific embodiment of the present disclosure.
- the following description will be made by taking the semiconductor machine as an exposure machine, the semiconductor process as an exposure process, and the processing parameter as Dose as an example.
- the Dose data of the exposure machine is found, and the Dose data includes a plurality of time segments and a plurality of time segments one by one Corresponding Dose value. Find the time period when the Dose value in the processing information exceeds the preset threshold range, and use it as the machine abnormal time period Dose OOS time.
- the preset duration of the exposure process for a single batch of wafers in the exposure machine is set to be (before secs, after secs).
- the preset time length can also be calculated according to the exposure processing time of a single wafer in the exposure machine and the number of wafers in each batch of wafers.
- the wafer abnormality time range of the abnormal wafer produced by the exposure machine is [Dose OOS time-before secs, Dose OOS time+after secs].
- the batch of wafers corresponding to the segment is an abnormal batch of wafers. That is, during the period of time when the Dose value of the exposure machine is abnormal, the batches of wafers that are subjected to the exposure process inside the exposure machine are abnormal batches of wafers.
- the following steps are further included:
- the identification of the abnormal batch of wafers (such as the identification number of the abnormal batch of wafers) can be obtained by searching the MES (Manufacturing Execution System, production execution management system), so as to identify all abnormal batches of wafers. Wafers of the above-mentioned abnormal batches are marked. Judging whether the abnormal batch of wafers processed by the semiconductor manufacturing process is still located inside the semiconductor machine, if so, directly and automatically intercepting the abnormal batch of wafers to avoid the abnormal batch of wafers The wafer flows into the next process. If the abnormal batch of wafers has completely left the semiconductor tool, an alarm is issued to notify users.
- MES Manufacturing Execution System, production execution management system
- the semiconductor process as an exposure process determines whether the abnormal batch of wafers is still in the exposure machine, and if so, directly, Automatically intercept the abnormal batch of wafers; if not, send an alarm.
- the specific steps of finding the processing time period for the wafer to perform the semiconductor process in the semiconductor tool include:
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, and it is confirmed that the wafer is an abnormal wafer. Steps include:
- the following steps are further included:
- the abnormal wafers are automatically marked.
- FIG. 3 is a schematic diagram of automatic positioning of abnormal wafers in a specific embodiment of the present disclosure.
- the semiconductor machine is an exposure machine
- the semiconductor process is an exposure process
- the processing parameter is Dose as an example for illustration.
- the Dose data of the exposure machine is searched, and the Dose data includes a plurality of time segments and a plurality of time segments one by one Corresponding Dose value.
- the wafer anomaly time frame for the wafer By searching the Report (report) file in the processing information of the exposure machine, obtain the start time point begin time when each wafer starts to process the exposure process, and when the exposure process process ends. The end time point end time, and the time period between the start time point begin time and the end time point end time is used as the processing time period.
- the processing time period at least partially overlapping with the wafer abnormal time range as the target processing time period selecting the processing time period at least partially overlapping with the wafer abnormal time range as the target processing time period, and confirming that the wafer corresponding to the target processing time period is an abnormal wafer. That is, during the time period when the Dose value of the exposure machine is abnormal, the wafers undergoing exposure process inside the exposure machine are abnormal wafers.
- the number of abnormal wafers can be counted, and the abnormal wafers can be automatically marked, so that the user can quickly and directly know the abnormal wafers.
- This specific embodiment can automatically locate the abnormal single wafer, thereby avoiding rework (such as re-exposure) of the entire batch of wafers, that is, reducing the number of reworked wafers and improving the yield of wafer products. At the same time, the production capacity of the semiconductor machine can be further improved.
- FIG. 4 is a schematic diagram of monitoring the performance of a semiconductor machine in a specific embodiment of the present disclosure.
- the performance of the semiconductor machine can also be monitored by parsing and searching the processing information of the semiconductor machine.
- the semiconductor machine is an exposure machine
- the semiconductor process is an exposure process
- the processing parameter is Dose as an example for illustration.
- the Dose data of the exposure machine is searched, and the Dose data includes a plurality of time periods and a plurality of the Dose values corresponding to each time period. Calculate and count the Dose index of the exposure machine, and obtain the threshold range of the Dose.
- the abscissa of the Dose performance trend graph is the time period, and the ordinate is the Dose value.
- the Dose performance trend graph Through the Dose performance trend graph, the Dose performance stability of one exposure machine can be known or the Dose performance between multiple exposure machines can be compared, so that early warning can be given in time to avoid damage to the wafer. Cause damage, but also help to further increase the production capacity of the exposure machine.
- abnormal wafers can be located directly. In another embodiment, after the abnormal batch of wafers is determined, a single abnormal wafer can be located from the abnormal batch of wafers.
- FIG. 5 is a structural block diagram of a wafer analysis device in a specific embodiment of the present disclosure.
- the wafer analysis device provided in this specific embodiment can analyze the wafer by using the wafer analysis method shown in FIGS. 1-4 .
- the wafer analysis device includes:
- the acquisition circuit 50 is used to acquire the processing information of the semiconductor process of the wafer in the semiconductor machine
- the analysis circuit 51 is used to analyze the processing information, find out the machine abnormal time period when the semiconductor machine has an abnormal situation, and find the processing time period when the wafer is processed in the semiconductor machine;
- the processor 52 is configured to confirm that the wafer is an abnormal wafer when the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine. .
- the semiconductor equipment described in this specific embodiment may be, but not limited to, an exposure equipment.
- the processing information includes the basic information of the semiconductor machine (such as model information, etc.), the time information when the semiconductor machine performs the semiconductor process, and the semiconductor process of the wafer in the semiconductor machine. One or two or more of the processing time period of the semiconductor tool and the processing parameter information when the semiconductor tool is performing the semiconductor manufacturing process.
- the processing parameter information of the semiconductor machine when performing the semiconductor process can be obtained through detection by a sensor disposed inside the semiconductor machine.
- the processing parameter may include an exposure intensity value (Dose value) per unit area.
- the machine abnormal time period when the semiconductor machine has an abnormal situation overlaps with the processing time period when the wafer is processed in the semiconductor machine, it indicates that the wafer is in the semiconductor machine. If the semiconductor process is processed during the time period when the processing parameter is abnormal, the abnormal processing parameter will cause the abnormality of the semiconductor process, and then cause the abnormality of the wafer processed by the semiconductor process.
- the overlap described in this specific embodiment may be partial overlap, or the abnormal time period of the machine is completely included in the processing time period, or the processing time period is completely included in the abnormal machine within the time period.
- the wafer analysis device also includes:
- the analysis circuit 51 is used to search for a time period when the processing parameter of the semiconductor machine exceeds a threshold range, as an abnormal time period of the semiconductor machine.
- the processing information may be, but not limited to, a semiconductor machine log stored inside or outside the semiconductor machine.
- Pre-set the threshold range of the processing parameter of the semiconductor machine and then search for the time period when the value of the processing parameter exceeds the threshold range in the analyzed processing information, and use the time period when the value of the processing parameter exceeds the threshold range.
- the time period in the threshold range is used as the machine abnormal time period when the semiconductor machine has an abnormal situation.
- the threshold value range in this specific implementation manner includes any one of the upper limit value and the lower limit value of the processing parameter, or a combination of both.
- the analysis circuit 51 is also used to find a plurality of processing time periods corresponding to a plurality of batches of wafers one-to-one, and the processing time period is for each batch of wafers from entering the The time period from the semiconductor machine to exiting the semiconductor machine, each batch of wafers includes a plurality of wafers.
- the wafer analysis device also includes:
- the setting circuit 53 is also used to set the preset duration for the wafers of a single batch to be processed in the semiconductor machine for the semiconductor process;
- the processor 52 is further configured to obtain the wafer abnormal time range of the abnormal wafer produced by the semiconductor machine according to the machine abnormal time period and the preset duration, and obtain at least the time range corresponding to the wafer abnormal time.
- the partially overlapping processing time period is used as a target processing time period, and it is confirmed that the batch of wafers corresponding to the target processing time period is an abnormal batch of wafers.
- the processor 52 is further configured to automatically intercept the abnormal batch of wafers after confirming that the batch of wafers corresponding to the target processing time period is an abnormal batch of wafers.
- the processor 52 can obtain the identification of the abnormal batch of wafers (such as the identification number of the abnormal batch of wafers) by searching MES (Manufacturing Execution System, production execution management system) ), and mark the abnormal batch of wafers. Judging whether the abnormal batch of wafers processed by the semiconductor manufacturing process is still located inside the semiconductor machine, if so, directly and automatically intercepting the abnormal batch of wafers to avoid the abnormal batch of wafers The wafer flows into the next process. If the abnormal batch of wafers has completely left the semiconductor tool, an alarm is issued to notify users.
- MES Manufacturing Execution System, production execution management system
- the analysis circuit 51 is used to find the start time point when each wafer starts to process the semiconductor process and the end time point when the semiconductor process process ends, and use the The time period between the start time point and the end time point is used as the processing time period.
- the processor 52 is configured to use the tool abnormal time period as the wafer abnormal time range of the abnormal wafer generated by the semiconductor tool, and obtain the wafer abnormal time range including the wafer abnormal time range.
- the processing time period is used as a target processing time period, and it is confirmed that the wafer corresponding to the target processing time period is an abnormal wafer.
- the processor 52 is further configured to automatically mark the abnormal wafers.
- the number of abnormal wafers can be counted, and the abnormal wafers can be automatically marked, so that the user can quickly and directly know the abnormal wafers.
- This specific embodiment can automatically locate the abnormal single wafer, thereby avoiding rework (such as re-exposure) of the entire batch of wafers, that is, reducing the number of reworked wafers and improving the yield of wafer products.
- the production capacity of the semiconductor machine can be further improved.
- the wafer analysis method and wafer analysis device collect and analyze the processing information of the semiconductor process on the wafer in the semiconductor machine, according to the abnormal time period of the machine in the processing information and the wafer Whether there is overlap in the processing time of the semiconductor process in the semiconductor machine, to automatically determine whether the wafer is an abnormal wafer, so as to realize the automatic positioning of the abnormal wafer, so as to take measures such as interception of abnormal wafer products in time , to prevent abnormal wafer products from flowing into the next processing station, thereby achieving the effect of improving the yield rate of wafer products.
- the abnormal wafer can be automatically located, the tedious operation of manual search is avoided, thereby improving the production capacity of the semiconductor machine.
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Abstract
本公开一些实施例中的晶圆分析方法包括如下步骤：获取晶圆在半导体机台内进行半导体制程的处理信息；解析所述处理信息，查找所述半导体机台出现异常状况的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段；所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆。本公开能够自动化定位异常晶圆，从而提高了半导体机台的产能和晶圆产品的良率。
Description
相关申请引用说明
本申请要求于2022年02月14日递交的中国专利申请号202210132233.1、申请名为“晶圆分析方法及晶圆分析装置”的优先权，其全部内容以引用的形式附录于此。
本公开涉及半导体制造技术领域，尤其涉及一种晶圆分析方法及晶圆分析装置。
目前，半导体集成电路(IC)产业已经经历了指数式增长。IC材料和设计中的技术进步已经产生了数代IC，其中，每代IC都比前一代IC具有更小和更复杂的电路。在IC发展的过程中，功能密度(即每一芯片面积上互连器件的数量)已普遍增加，而几何尺寸(即使用制造工艺可以产生的最小部件)却已减小。除了IC部件变得更小和更复杂之外，在其上制造IC的晶圆变得越来越大，这就对晶圆的质量要求越来越高。
曝光制程是半导体工艺中的重要制程技术之一。曝光机的曝光品质对晶圆的曝光质量(例如曝光图案的特征尺寸)有重要影响。单位面积上的曝光强度偏差(Dose Error)是评估曝光机的曝光品质的关键参数之一。曝光机的Dose Error过高会导致产品特征尺寸的异常，若不能及时的对异常产品进行拦截，会导致产品流到下一处理站，从而造成产品良率的降低。当前工程师并没有有效的方法获取在曝光机曝光过程中出现异常的晶圆产品，只能通过人工排查，效率低下，耗时耗力，严重影响机台产能。
因此，如何实现异常晶圆产品的自动化定位，从而提高晶圆产品的良率与半导体机台的产能，是当前亟待解决的技术问题。
发明内容
本公开提供一种晶圆分析方法及晶圆分析装置，用于解决当前无法实现异常晶圆产品自动化定位的问题，以提高晶圆产品的良率和半导体机台的产能。
根据一些实施例，本公开提供了一种晶圆分析方法，包括如下步骤：
获取晶圆在半导体机台内进行半导体制程的处理信息；
解析所述处理信息，查找所述半导体机台出现异常状况的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段；
所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆。
在一些实施例中，查找所述半导体机台出现异常状况的机台异常时刻段的具体步骤包括：
查找所述半导体机台的处理参数超出阈值范围的时刻段，作为所述半导体机台的机台异常时刻段。
在一些实施例中，查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段的具体步骤包括：
查找与多个批次的晶圆一一对应的多个处理时间段，所述处理时间段为每一批次的晶圆从进入所述半导体机台至退出所述半导体机台的时间段，每一批次的所述晶圆包括多片所述晶圆。
在一些实施例中，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆的具体步骤包括：
设置单一批次的所述晶圆在所述半导体机台内进行所述半导体制程处理的预设时长；
根据所述机台异常时刻段和所述预设时长获取所述半导体机台产生异常晶圆的晶圆异常时间范围；
获取至少与所述晶圆异常时间范围部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。
在一些实施例中，确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆之后，还包括如下步骤：
自动拦截所述异常批次晶圆。
在一些实施例中，查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段的具体步骤包括：
查找每片所述晶圆开始进行所述半导体制程处理时的开始时间点、以及结 束所述半导体制程处理时的结束时间点，并以所述开始时间点与所述结束时间点之间的时间段作为所述处理时间段。
在一些实施例中，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆的具体步骤包括：
以所述机台异常时刻段作为所述半导体机台生成异常晶圆的晶圆异常时间范围；
获取包含所述晶圆异常时间范围的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。
在一些实施例中，确认与所述目标处理时间段对应的所述晶圆为异常晶圆之后，还包括如下步骤：
自动标记所述异常晶圆。
根据另一些实施例，本公开还提供了一种晶圆分析装置，包括：
获取电路，用于获取晶圆在半导体机台内进行半导体制程的处理信息；
解析电路，用于解析所述处理信息，查找所述半导体机台出现异常状况的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段；
处理器，用于在所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠时，确认所述晶圆为异常晶圆。
在一些实施例中，还包括：
所述解析电路用于查找所述半导体机台的处理参数超出阈值范围的时刻段，作为所述半导体机台的机台异常时刻段。
在一些实施例中，所述解析电路还用于查找与多个批次的晶圆一一对应的多个处理时间段，所述处理时间段为每一批次的晶圆从进入所述半导体机台至退出所述半导体机台的时间段，每一批次的所述晶圆包括多片所述晶圆。
在一些实施例中，还包括：
设置电路，所述设置电路还用于设置单一批次的所述晶圆在所述半导体机台内进行所述半导体制程处理的预设时长；
所述处理器还用于根据所述机台异常时刻段和所述预设时长获取所述半导体机台产生异常晶圆的晶圆异常时间范围，并获取至少与所述晶圆异常时间范围部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。
在一些实施例中，所述处理器还用于在确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆之后，自动拦截所述异常批次晶圆。
在一些实施例中，所述解析电路用于查找每片所述晶圆开始进行所述半导体制程处理时的开始时间点、以及结束所述半导体制程处理时的结束时间点，并以所述开始时间点与所述结束时间点之间的时间段作为所述处理时间段。
在一些实施例中，所述处理器用于以所述机台异常时刻段作为所述半导体机台生成异常晶圆的晶圆异常时间范围，获取包含所述晶圆异常时间范围的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。
在一些实施例中，所述处理器还用于自动标记所述异常晶圆。
本公开一些实施例提供的晶圆分析方法及晶圆分析装置，通过收集并解析晶圆在半导体机台内进行半导体制程的处理信息，根据所述处理信息中的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段是否有重叠，来自动化判断晶圆是否为异常晶圆，从而实现了对异常晶圆的自动化定位，以便及时对异常晶圆产品采取拦截等措施，避免异常晶圆产品流入下一处理站，进而达到提高晶圆产品良率的效果。同时，由于能够自动化定位异常晶圆，避免了人工查找的繁琐操作，进而提高了半导体机台的产能。
附图1是本公开具体实施方式中晶圆分析方法的流程图；
附图2是本公开具体实施方式中自动化定位异常批次晶圆的示意图；
附图3是本公开具体实施方式中自动化定位异常晶圆的示意图；
附图4是本公开具体实施方式中对半导体机台的性能进行监测的示意图；
附图5是本公开具体实施方式中晶圆分析装置的结构框图。
下面结合附图对本公开提供的晶圆分析方法及晶圆分析装置的具体实施 方式做详细说明。
本具体实施方式提供了一种晶圆分析方法，附图1是本公开具体实施方式中晶圆分析方法的流程图。如图1所示，本具体实施方式提供的晶圆分析方法，包括如下步骤：
步骤S11，获取晶圆在半导体机台内进行半导体制程的处理信息。
本具体实施方式中所述的半导体机台可以是但不限于曝光机台。所述处理信息包括所述半导体机台的基本信息(例如型号信息等)、所述半导体机台进行所述半导体制程的时间信息、所述晶圆在所述半导体机台内进行所述半导体制程的处理时间段、所述半导体机台在进行所述半导体制程时的处理参数信息中的一种或者两种以上。所述半导体机台在进行所述半导体制程时的处理参数信息可以通过设置于所述半导体机台内部的传感器检测得到。举例来说，当所述半导体机台为曝光机台时，所述处理参数可以包括单位面积上的曝光强度值(Dose数值)。
步骤S12，解析所述处理信息，查找所述半导体机台出现异常状况的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段。
在一些实施例中，查找所述半导体机台出现异常状况的机台异常时刻段的具体步骤包括：
查找所述半导体机台的处理参数超出阈值范围的时刻段，作为所述半导体机台的机台异常时刻段。
具体来说，所述处理信息可以是但不限于存储于所述半导体机台内部或者所述半导体机台外部的半导体机台日志。预先设置所述半导体机台的所述处理参数的阈值范围，然后在解析的所述处理信息中查找所述处理参数的数值超出所述阈值范围的时刻段，并以所述处理参数的数值超出所述阈值范围的时刻段作为所述半导体机台出现异常状况的机台异常时刻段。本具体实施方式中的所述阈值范围包括所述处理参数的上限值、下限值中的任一者或者两者的组合。
举例来说，所述半导体机台为曝光机台，所述处理参数为Dose，所述阈值范围包括所述曝光机台的Dose上限值与下限值之间的范围。所述处理信息中Dose数值超出所述上限值或所述下限值的时刻段即为所述曝光机台的所述 机台异常时刻段。本具体实施方式中所述的异常时刻段包括所述Dose数值超出所述阈值范围的时刻点、所述Dose数值超出阈值范围的时间段中的任一者或者两者的组合。所述阈值范围的具体数值可以根据实际需要进行设置，例如根据所述半导体制程的具体类型确定。
在一些实施例中，查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段的具体步骤包括：
查找与多个批次的晶圆一一对应的多个处理时间段，所述处理时间段为每一批次的晶圆从进入所述半导体机台至退出所述半导体机台的时间段，每一批次的所述晶圆包括多片所述晶圆。
具体来说，所述半导体机台在所述半导体制程中依次对多个批次的晶圆进行处理，每一批次的所述晶圆包括多片所述晶圆。所述处理时间段为每一批次的第一片晶圆开始进入所述半导体机台至每一批次的最后一片晶圆退出所述半导体机台的时间段。本具体实施方式中所述的多片是指两片以上。
步骤S13，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆。
具体来说，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，则表明所述晶圆是在所述半导体机台的所述处理参数出现异常的时刻段进行所述半导体制程处理的，异常的所述处理参数会导致所述半导体制程的异常，进而导致被所述半导体制程处理的所述晶圆的异常。本具体实施方式中所述的重叠可以是部分重叠，也可以是所述机台异常时刻段完全包含于所述处理时间段内，还可以是所述处理时间段完全包含于所述机台异常时刻段内。
在一些实施例中，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆的具体步骤包括：
设置单一批次的所述晶圆在所述半导体机台内进行所述半导体制程处理的预设时长；
根据所述机台异常时刻段和所述预设时长获取所述半导体机台产生异常晶圆的晶圆异常时间范围；
获取至少与所述晶圆异常时间范围部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。
附图2是本公开具体实施方式中自动化定位异常批次晶圆的示意图。以下以所述半导体机台为曝光机台、所述半导体制程为曝光制程、所述处理参数为Dose为例进行说明。如图2所示，通过解析所述曝光机台的所述处理信息，查找得到所述曝光机台的Dose数据，所述Dose数据包括多个时刻段、以及与多个所述时刻段一一对应的Dose数值。查找所述处理信息中Dose数值超出预先设置的阈值范围的时刻段，作为所述机台异常时刻段Dose OOS time。设置单一批次的所述晶圆在所述曝光机台内进行曝光制程处理的预设时长为(before secs,after secs)。所述预设时长还可以根据单片晶圆在所述曝光机台内进行曝光制程处理的时间与每一批次晶圆中晶圆的数量计算得到。所述曝光机台产生异常晶圆的所述晶圆异常时间范围为[Dose OOS time－before secs,Dose OOS time+after secs]。之后，选择与所述晶圆异常时间范围为[Dose OOS time－before secs,Dose OOS time+after secs]至少部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。即在所述曝光机台的所述Dose数值出现异常的时间段内、于所述曝光机台内部进行曝光制程处理的批次晶圆为异常批次晶圆。
在一些实施例中，确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆之后，还包括如下步骤：
自动拦截所述异常批次晶圆。
具体来说，在确认异常批次晶圆之后，可以通过查找MES(Manufacturing Execution System，生产执行管理系统)获取异常批次晶圆的标识(例如异常批次晶圆的识别编号)，以对所述异常批次的晶圆进行标注。判断经过所述半导体制程处理的所述异常批次的晶圆是否还位于所述半导体机台内部，若是，则直接、自动的拦截所述异常批次的晶圆，避免所述异常批次的晶圆流入下一制程。若所述异常批次的晶圆已经完全离开所述半导体机台，则发出警报，以通知用户。
以所述半导体机台为曝光机台、所述半导体制程为曝光制程、所述处理参 数为Dose为例，判断所述异常批次的晶圆是否还在曝光机台内，若是，则直接、自动的拦截所述异常批次的晶圆；若否，则发出警报。
在一些实施例中，查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段的具体步骤包括：
查找每片所述晶圆开始进行所述半导体制程处理时的开始时间点、以及结束所述半导体制程处理时的结束时间点，并以所述开始时间点与所述结束时间点之间的时间段作为所述处理时间段。
在一些实施例中，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆的具体步骤包括：
以所述机台异常时刻段作为所述半导体机台生成异常晶圆的晶圆异常时间范围；
获取包含所述晶圆异常时间范围的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。
在一些实施例中，确认与所述目标处理时间段对应的所述晶圆为异常晶圆之后，还包括如下步骤：
自动标记所述异常晶圆。
附图3是本公开具体实施方式中自动化定位异常晶圆的示意图。以下仍以所述半导体机台为曝光机台、所述半导体制程为曝光制程、所述处理参数为Dose为例进行说明。如图3所示，通过解析所述曝光机台的所述处理信息，查找得到所述曝光机台的Dose数据，所述Dose数据包括多个时刻段、以及与多个所述时刻段一一对应的Dose数值。查找所述处理信息中Dose数值超出预先设置的阈值范围的时刻段，作为所述机台异常时刻段Dose OOS time，并以所述机台异常时刻段Dose OOS time作为所述曝光机台生成异常晶圆的晶圆异常时间范围。通过查找所述曝光机台的所述处理信息中的Report(报告)档案，获取每片所述晶圆开始进行所述曝光制程处理时的开始时间点begin time、以及结束所述曝光制程处理时的结束时间点end time，并以所述开始时间点begin time与所述结束时间点end time之间的时间段作为所述处理时间段。之后，选择与所述晶圆异常时间范围至少部分重叠的所述处理时间段作为目标处理时 间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。即在所述曝光机台的所述Dose数值出现异常的时间段内、于所述曝光机台内部进行曝光制程处理的晶圆为异常晶圆。
在确认所述异常晶圆之后，可以对异常晶圆的数量进行统计、并对异常晶圆进行自动标记，以便于用户能够快速、直接的获知所述异常晶圆。本具体实施方式可以自动定位到出现异常的单片晶圆，从而可以避免对整批次的晶圆进行返工(例如重曝光)，即减少了返工的晶圆数量，在提高晶圆产品良率的同时，还能进一步提高所述半导体机台的产能。
附图4是本公开具体实施方式中对半导体机台的性能进行监测的示意图。在一些实施例中，还可以通过对所述半导体机台的所述处理信息进行解析、查找，从而对所述半导体机台的性能进行监测。以下仍以所述半导体机台为曝光机台、所述半导体制程为曝光制程、所述处理参数为Dose为例进行说明。举例来说，如图4所示，通过解析所述曝光机台的所述处理信息，查找得到所述曝光机台的Dose数据，所述Dose数据包括多个时刻段、以及与多个所述时刻段一一对应的Dose数值。计算并统计所述曝光机台的Dose指标，获取所述Dose的阈值范围。整合一台或者多台所述曝光机台的Dose数据，获取一台或者多台所述曝光机台的Dose性能趋势图。所述Dose性能趋势图的横坐标为时刻段、纵坐标为Dose数值。通过所述Dose性能趋势图能够获知一台所述曝光机台的Dose性能稳定性或者能够对多台所述曝光机台之间的Dose性能进行比较，从而能够及时的进行预警，避免对晶圆造成损伤，也有助于进一步提高曝光机台的产能。
在一实施例中，可以在直接定位异常晶圆。在另一实施例中，也可以在确定异常批次的晶圆之后，然后从所述异常批次的晶圆中定位单片的异常晶圆。
不仅如此，本具体实施方式还提供了一种晶圆分析装置。附图5是本公开具体实施方式中晶圆分析装置的结构框图。本具体实施方式提供的晶圆分析装置可以采用如图1-图4所示的晶圆分析方法对晶圆进行分析。如图1-图5所示，所述晶圆分析装置，包括：
获取电路50，用于获取晶圆在半导体机台内进行半导体制程的处理信息；
解析电路51，用于解析所述处理信息，查找所述半导体机台出现异常状况 的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段；
处理器52，用于在所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠时，确认所述晶圆为异常晶圆。
本具体实施方式中所述的半导体机台可以是但不限于曝光机台。所述处理信息包括所述半导体机台的基本信息(例如型号信息等)、所述半导体机台进行所述半导体制程的时间信息、所述晶圆在所述半导体机台内进行所述半导体制程的处理时间段、所述半导体机台在进行所述半导体制程时的处理参数信息中的一种或者两种以上。所述半导体机台在进行所述半导体制程时的处理参数信息可以通过设置于所述半导体机台内部的传感器检测得到。举例来说，当所述半导体机台为曝光机台时，所述处理参数可以包括单位面积上的曝光强度值(Dose数值)。
具体来说，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，则表明所述晶圆是在所述半导体机台的所述处理参数出现异常的时刻段进行所述半导体制程处理的，异常的所述处理参数会导致所述半导体制程的异常，进而导致被所述半导体制程处理的所述晶圆的异常。本具体实施方式中所述的重叠可以是部分重叠，也可以是所述机台异常时刻段完全包含于所述处理时间段内，还可以是所述处理时间段完全包含于所述机台异常时刻段内。
在一些实施例中，所述晶圆分析装置还包括：
所述解析电路51用于查找所述半导体机台的处理参数超出阈值范围的时刻段，作为所述半导体机台的机台异常时刻段。
具体来说，所述处理信息可以是但不限于存储于所述半导体机台内部或者所述半导体机台外部的半导体机台日志。预先设置所述半导体机台的所述处理参数的阈值范围，然后在解析的所述处理信息中查找所述处理参数的数值超出所述阈值范围的时刻段，并以所述处理参数的数值超出所述阈值范围的时刻段作为所述半导体机台出现异常状况的机台异常时刻段。本具体实施方式中的所述阈值范围包括所述处理参数的上限值、下限值中的任一者或者两者的组合。
在一些实施例中，所述解析电路51还用于查找与多个批次的晶圆一一对应的多个处理时间段，所述处理时间段为每一批次的晶圆从进入所述半导体机台至退出所述半导体机台的时间段，每一批次的所述晶圆包括多片所述晶圆。
在一些实施例中，所述晶圆分析装置还包括：
设置电路53，所述设置电路53还用于设置单一批次的所述晶圆在所述半导体机台内进行所述半导体制程处理的预设时长；
所述处理器52还用于根据所述机台异常时刻段和所述预设时长获取所述半导体机台产生异常晶圆的晶圆异常时间范围，并获取至少与所述晶圆异常时间范围部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。
在一些实施例中，所述处理器52还用于在确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆之后，自动拦截所述异常批次晶圆。
具体来说，在确认异常批次晶圆之后，所述处理器52可以通过查找MES(Manufacturing Execution System，生产执行管理系统)获取异常批次晶圆的标识(例如异常批次晶圆的识别编号)，并对所述异常批次的晶圆进行标注。判断经过所述半导体制程处理的所述异常批次的晶圆是否还位于所述半导体机台内部，若是，则直接、自动的拦截所述异常批次的晶圆，避免所述异常批次的晶圆流入下一制程。若所述异常批次的晶圆已经完全离开所述半导体机台，则发出警报，以通知用户。
在一些实施例中，所述解析电路51用于查找每片所述晶圆开始进行所述半导体制程处理时的开始时间点、以及结束所述半导体制程处理时的结束时间点，并以所述开始时间点与所述结束时间点之间的时间段作为所述处理时间段。
在一些实施例中，所述处理器52用于以所述机台异常时刻段作为所述半导体机台生成异常晶圆的晶圆异常时间范围，获取包含所述晶圆异常时间范围的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。
在一些实施例中，所述处理器52还用于自动标记所述异常晶圆。
具体来说，在确认所述异常晶圆之后，可以对异常晶圆的数量进行统计、 并对异常晶圆进行自动标记，以便于用户能够快速、直接的获知所述异常晶圆。本具体实施方式可以自动定位到出现异常的单片晶圆，从而可以避免对整批次的晶圆进行返工(例如重曝光)，即减少了返工的晶圆数量，在提高晶圆产品良率的同时，还能进一步提高所述半导体机台的产能。
本具体实施方式提供的晶圆分析方法及晶圆分析装置，通过收集并解析晶圆在半导体机台内进行半导体制程的处理信息，根据所述处理信息中的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段是否有重叠，来自动化判断晶圆是否为异常晶圆，从而实现了对异常晶圆的自动化定位，以便及时对异常晶圆产品采取拦截等措施，避免异常晶圆产品流入下一处理站，进而达到提高晶圆产品良率的效果。同时，由于能够自动化定位异常晶圆，避免了人工查找的繁琐操作，进而提高了半导体机台的产能。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。
Claims (16)
- 一种晶圆分析方法，包括如下步骤：获取晶圆在半导体机台内进行半导体制程的处理信息；解析所述处理信息，查找所述半导体机台出现异常状况的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段；所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆。
- 根据权利要求1所述的晶圆分析方法，其中，查找所述半导体机台出现异常状况的机台异常时刻段的具体步骤包括：查找所述半导体机台的处理参数超出阈值范围的时刻段，作为所述半导体机台的机台异常时刻段。
- 根据权利要求1所述的晶圆分析方法，其中，查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段的具体步骤包括：查找与多个批次的晶圆一一对应的多个处理时间段，所述处理时间段为每一批次的晶圆从进入所述半导体机台至退出所述半导体机台的时间段，每一批次的所述晶圆包括多片所述晶圆。
- 根据权利要求3所述的晶圆分析方法，其中，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆的具体步骤包括：设置单一批次的所述晶圆在所述半导体机台内进行所述半导体制程处理的预设时长；根据所述机台异常时刻段和所述预设时长获取所述半导体机台产生异常晶圆的晶圆异常时间范围；获取至少与所述晶圆异常时间范围部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。
- 根据权利要求4所述的晶圆分析方法，其中，确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆之后，还包括如下步骤：自动拦截所述异常批次晶圆。
- 根据权利要求1所述的晶圆分析方法，其中，查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段的具体步骤包括：查找每片所述晶圆开始进行所述半导体制程处理时的开始时间点、以及结束所述半导体制程处理时的结束时间点，并以所述开始时间点与所述结束时间点之间的时间段作为所述处理时间段。
- 根据权利要求6所述的晶圆分析方法，其中，所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠，确认所述晶圆为异常晶圆的具体步骤包括：以所述机台异常时刻段作为所述半导体机台生成异常晶圆的晶圆异常时间范围；获取包含所述晶圆异常时间范围的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。
- 根据权利要求7所述的晶圆分析方法，其中，确认与所述目标处理时间段对应的所述晶圆为异常晶圆之后，还包括如下步骤：自动标记所述异常晶圆。
- 一种晶圆分析装置，包括：获取电路，用于获取晶圆在半导体机台内进行半导体制程的处理信息；解析电路，用于解析所述处理信息，查找所述半导体机台出现异常状况的机台异常时刻段，以及查找所述晶圆在所述半导体机台内进行半导体制程的处理时间段；处理器，用于在所述半导体机台出现异常状况的机台异常时刻段与所述晶圆在半导体机台内进行半导体制程的处理时间段重叠时，确认所述晶圆为异常晶圆。
- 根据权利要求9所述的晶圆分析装置，还包括：所述解析电路用于查找所述半导体机台的处理参数超出阈值范围的时刻段，作为所述半导体机台的机台异常时刻段。
- 根据权利要求10所述的晶圆分析装置，其中，所述解析电路还用于查找与 多个批次的晶圆一一对应的多个处理时间段，所述处理时间段为每一批次的晶圆从进入所述半导体机台至退出所述半导体机台的时间段，每一批次的所述晶圆包括多片所述晶圆。
- 根据权利要求11所述的晶圆分析装置，还包括：设置电路，所述设置电路还用于设置单一批次的所述晶圆在所述半导体机台内进行所述半导体制程处理的预设时长；所述处理器还用于根据所述机台异常时刻段和所述预设时长获取所述半导体机台产生异常晶圆的晶圆异常时间范围，并获取至少与所述晶圆异常时间范围部分重叠的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆。
- 根据权利要求12所述的晶圆分析装置，其中，所述处理器还用于在确认与所述目标处理时间段对应批次的所述晶圆为异常批次晶圆之后，自动拦截所述异常批次晶圆。
- 根据权利要求9所述的晶圆分析装置，其中，所述解析电路用于查找每片所述晶圆开始进行所述半导体制程处理时的开始时间点、以及结束所述半导体制程处理时的结束时间点，并以所述开始时间点与所述结束时间点之间的时间段作为所述处理时间段。
- 根据权利要求14所述的晶圆分析装置，其中，所述处理器用于以所述机台异常时刻段作为所述半导体机台生成异常晶圆的晶圆异常时间范围，获取包含所述晶圆异常时间范围的所述处理时间段作为目标处理时间段，并确认与所述目标处理时间段对应的所述晶圆为异常晶圆。
- 根据权利要求15所述的晶圆分析装置，其中，所述处理器还用于自动标记所述异常晶圆。
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| CN110620104A (zh) * | 2019-09-20 | 2019-12-27 | 武汉新芯集成电路制造有限公司 | 测试片及其制造方法和晶圆键合缺陷的检测方法 |
| CN112232012A (zh) * | 2019-06-27 | 2021-01-15 | 长鑫存储技术有限公司 | 半导体制程分析系统以及分析方法、计算机可读存储介质 |
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2022
- 2022-02-14 CN CN202210132233.1A patent/CN116631885A/zh active Pending
- 2022-03-18 WO PCT/CN2022/081668 patent/WO2023151153A1/zh unknown
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| US20030023454A1 (en) * | 2001-06-25 | 2003-01-30 | Tokyo Electron Limited | Managing system, managing method, host computer, and information collecting/transmitting unit |
| US20050010311A1 (en) * | 2003-07-10 | 2005-01-13 | Barbazette Christopher J. | Data collection and diagnostic system for a semiconductor fabrication facility |
| CN205984978U (zh) * | 2016-06-02 | 2017-02-22 | 中芯国际集成电路制造（天津）有限公司 | 一种监控晶圆 |
| CN112232012A (zh) * | 2019-06-27 | 2021-01-15 | 长鑫存储技术有限公司 | 半导体制程分析系统以及分析方法、计算机可读存储介质 |
| CN110620104A (zh) * | 2019-09-20 | 2019-12-27 | 武汉新芯集成电路制造有限公司 | 测试片及其制造方法和晶圆键合缺陷的检测方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116774990A (zh) * | 2023-08-25 | 2023-09-19 | 合肥晶合集成电路股份有限公司 | 一种半导体机台的产品程式管理系统及管理方法 |
| CN116774990B (zh) * | 2023-08-25 | 2023-11-28 | 合肥晶合集成电路股份有限公司 | 一种半导体机台的产品程式管理系统及管理方法 |
| CN117410215A (zh) * | 2023-12-15 | 2024-01-16 | 合肥晶合集成电路股份有限公司 | 机台参数的确定方法、控制方法、控制系统及其装置 |
| CN117410215B (zh) * | 2023-12-15 | 2024-04-09 | 合肥晶合集成电路股份有限公司 | 机台参数的确定方法、控制方法、控制系统及其装置 |
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| CN116631885A (zh) | 2023-08-22 |
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