WO2023133824A1 - 中央区域高发光的小尺寸垂直式发光二极管晶粒 - Google Patents

中央区域高发光的小尺寸垂直式发光二极管晶粒 Download PDF

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WO2023133824A1
WO2023133824A1 PCT/CN2022/072092 CN2022072092W WO2023133824A1 WO 2023133824 A1 WO2023133824 A1 WO 2023133824A1 CN 2022072092 W CN2022072092 W CN 2022072092W WO 2023133824 A1 WO2023133824 A1 WO 2023133824A1
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type
ohmic contact
type semiconductor
light
layer
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PCT/CN2022/072092
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English (en)
French (fr)
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陈復邦
黄国欣
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联嘉光电股份有限公司
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Priority to PCT/CN2022/072092 priority Critical patent/WO2023133824A1/zh
Publication of WO2023133824A1 publication Critical patent/WO2023133824A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

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  • the present invention relates to the grain structure of light-emitting diodes, in particular to the small-sized vertical light-emitting diode crystal grains that focus on the central region to emit light.
  • LED grains can be mainly divided into three major states: 1. Horizontal type (horizontal) 2. Vertical type (vertical) 3. Flip-chip type (flip-chip).
  • the small-sized horizontal LED die and vertical LED die have low luminous efficiency, so the current high-order small-pitch LED display mainly uses flip-chip small-sized die with better light efficiency, which is surface-mounted.
  • Components SMD: Surface Mounted components
  • the N electrode and the P electrode (P/N electrode) at the bottom of the chip are conductively bonded to the package substrate through the electrode pads. Therefore, the light-emitting surface above the crystal grain is not shielded by electrodes, and has better luminous efficiency in small-sized light-emitting.
  • the N electrode and the P electrode are arranged to be conductively adhered to the carrier board at the same time.
  • the electrode pads are too small and the spacing is too close, which is easy to short circuit.
  • the heat dissipation is also worse than that of the vertical LED on the bottom.
  • the manufacturing process of phosphide red light flip-chip LED grains is much more complicated than that of nitride blue-green light, and the cost of flip-chip LED grains grown on non-sapphire substrates will be higher.
  • Vertical LEDs are much higher. Therefore, vertical LEDs have advantages in reliability for automotive use, but their luminous efficacy is poor. If the luminous efficiency can be improved, it will be beneficial to the development of small-sized LED displays for automotive applications that require high reliability.
  • the structure of a conventional vertical light-emitting diode as shown in FIG. N-type electrode pad 6, wherein the grain conductive base structure 2 includes a structural metal layer 2A, a substitute substrate adhesive layer 2B, and a substitute substrate 2C, and the interface structure 4 is a local P-type ohmic contact metal layer, including P Type ohmic contact block 4A and non-P type ohmic contact block 4B.
  • the PN junction structure 5 includes a P-type semiconductor 5A, an active layer 5B and an N-type semiconductor 5C.
  • the straight-line side length of traditional small-sized vertical light-emitting diode grains is about 200 microns ( ⁇ m). Since light-absorbing interference substances such as cutting lines, side walls, and metal layer conduction layers need to be provided on the edge of the wafer, the necessary scale of about 40 ⁇ m is occupied.
  • N-type electrode pad 6 N electrode
  • the central light emission is blocked, and the N-type electrode pad 6 is located on the active layer 5B (Active Layer)
  • active layer 5B Active Layer
  • auxiliary lines 6A Finger located above the N-type semiconductor 5C in a forked shape. The more auxiliary lines 6A are arranged on the N-type semiconductor 5C, the better the current distribution will be, but the light-shielding area will also increase.
  • the main purpose of the present invention is to provide a small-sized vertical light-emitting diode chip that emits high light in the central area, and the light can be emitted from the top of the light-emitting surface without shielding, so as to meet the requirement of high light efficiency.
  • the present invention is a small-sized vertical light-emitting diode grain with high luminescence in the central area, which includes a P-type electrode, a grain conductive base structure, an interface structure, a PN junction structure, an insulating layer, and a span Connecting the metal layer, an N-type ohmic contact electrode and an N-type electrode pad.
  • the P-type electrode is arranged on one side of the grain conductive base structure
  • the interface structure is arranged on the side of the grain conductive base structure away from the P-type electrode, and the interface structure includes a highly conductive metal layer stacked in sequence 1.
  • the PN junction structure includes a P-type semiconductor, an active layer and an N-type semiconductor stacked in sequence, and the P-type semiconductor is disposed on the base of the light-emitting region, and the PN junction structure has four straight sides A long closed figure with a central region.
  • the local P-type ohmic contact layer is located at the base of the light-emitting region Below the outer extension platform, the local P-type ohmic contact layer includes a P-type ohmic contact block and a P-type non-ohmic contact block, the P-type ohmic contact block is located below the central area, and the P-type The ohmic contact block is in ohmic contact with the high-concentration P-type semiconductor layer, and the P-type non-ohmic contact block is in non-ohmic contact with the high-concentration P-type semiconductor layer.
  • the insulating layer is formed on the outer extension platform, and the insulating layer extends to cover the N-type semiconductor and forms a frame covering area at the length of the four straight sides, and the frame covering area surrounds the N-type semiconductor.
  • the bridging metal layer is disposed on the insulating layer, and two ends respectively extend to the frame coverage area and the outer extension platform.
  • the N-type ohmic contact electrode surrounds and ohmic-contacts the surface of the N-type semiconductor in the upper peripheral region of the active layer of the PN junction structure, and covers the frame coverage area.
  • the P-type semiconductor in the lower central area of the active layer is electrically connected to the P-type ohmic contact block, and the N-type ohmic contact electrode is extended to the frame coverage area and electrically connected to the jumper connected metal layer.
  • the N-type electrode pad is formed on the bridging connected metal layer at a position corresponding to the outer extending platform to electrically connect the bridging connected metal layer.
  • a current introduced by the N-type electrode pad will pass through the metal layer connected by the jumper, and the N-type ohmic contact electrode will converge downward and pass through the central region of the PN junction structure, and the current will gather at the active
  • the center of the layer achieves carrier recombination to emit light. Because the upper center of the active layer emits light without shielding, in addition to improving luminous efficiency, it can also increase the black ratio when used in small-pitch displays to achieve better display contrast.
  • the N-type electrode pad of this design is not located on the PN junction structure, and there is no problem of damaging the PN junction structure during the wire bonding process, which can meet the requirement of high reliability.
  • Figure 1 is a schematic cross-sectional view of a conventional small-sized vertical LED structure
  • Fig. 2 is a top view surface structure diagram of a conventional small-sized vertical LED
  • Fig. 3 is a schematic cross-sectional view of the grain structure of the first embodiment of the present invention.
  • FIG. 4A is a top view schematic diagram 1 of the grain structure of the first embodiment of the present invention.
  • FIG. 4B is a second schematic top view of the grain structure of the first embodiment of the present invention.
  • FIG. 4C is a top view schematic diagram III of the grain structure of the first embodiment of the present invention.
  • Fig. 5 is a top view of the grain structure of the second embodiment of the present invention.
  • Fig. 6 is a schematic cross-sectional view of the grain structure of the third embodiment of the present invention.
  • Fig. 7 is a schematic cross-sectional view of the grain structure of the fourth embodiment of the present invention.
  • Fig. 8 is a schematic cross-sectional view of the grain structure of the fifth embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of the grain structure of the sixth embodiment of the present invention.
  • FIG. 3 is the first embodiment of the present invention, which includes a P-type electrode 10, a grain conductive base structure 20, an interface structure 30, a PN junction structure 40, an insulating layer 50, an The metal layer 60 , an N-type ohmic contact electrode 70 and an N-type electrode pad 80 are bridged and connected.
  • the P-type electrode 10 is disposed on one side of the grain conductive base structure 20
  • the interface structure 30 is disposed on a side of the grain conductive base structure 20 away from the P-type electrode 10 .
  • the grain conductive base structure 20 includes a structural metal layer 21 , a substitute substrate adhesive layer 22 , and a substitute substrate 23 .
  • the interface structure 30 includes a highly conductive metal layer 31, a local P-type ohmic contact layer 32 and a light-transmitting high-concentration P-type semiconductor layer 33 stacked in sequence, and the interface structure 30 has a The light-emitting area base 301 and an outer extension platform 302 are adjacent to the light-emitting area base 301 .
  • the PN junction structure 40 is any one selected from a single PN junction light emitting diode structure or a two PN junction tunnel junction light emitting diode structure (tunnel junction light emitter diode).
  • the PN junction structure 40 includes a P-type semiconductor 41, an active layer 42 and an N-type semiconductor 43 stacked sequentially from bottom to top, and the P-type semiconductor 41 is disposed on the base of the light emitting region Above 301 , the thickness of the highest thickness region of the N-type semiconductor 43 is greater than 2.5 micrometers ( ⁇ m), and a large thickness is beneficial for inward conduction of edge currents. As shown in FIG.
  • the PN junction structure 40 has a closed geometry and has a central region 401, and the light emitting surface area of the PN junction structure 40 is less than 0.06 square millimeters (mm 2 ) (small area
  • the ohmic contact frame is connected to the central region 401 of the PN junction structure 40 via the N-type semiconductor 43 ).
  • the local P-type ohmic contact layer 32 is located under the base 301 of the light-emitting region and the outer extension platform 302, and the local P-type ohmic contact layer 32 includes a P-type ohmic contact area 321 and a P-type non-ohmic contact area. 322 , the P-type ohmic contact region 321 is located below the central region 401 .
  • the P-type ohmic contact block 321 is in ohmic contact with the high-concentration P-type semiconductor layer 33
  • the P-type non-ohmic contact block 322 is in non-ohmic contact with the high-concentration P-type semiconductor layer 33 .
  • the high-concentration P-type semiconductor layer is any one of P-type gallium nitride (p-GaN) or P-type indium gallium nitride (p-Ga (x) In (1-x) N), and the high concentration If the doping is magnesium (Mg), the material of the P-type ohmic contact block can be silver (Ag), nickel (Ni), or indium tin oxide (ITO).
  • the high-concentration P-type semiconductor layer is P-type gallium phosphide (p-GaP), P-type indium gallium phosphide (p-Ga (x) In (1-x) P), P-type gallium arsenide (p -GaAs) or p-type indium gallium arsenide (p-Ga (x) In (1-x) As), and the high concentration doping is any one selected from carbon (C) or magnesium (Mg) type, the material of the P-type ohmic contact block can be beryllium gold alloy (BeAu Alloy).
  • the p-type ohmic contact block 321 is a plurality of discontinuous regions, such as a plurality of columnar structures (for example: the material of the phosphide LED crystal grain that can be in ohmic contact with p-GaP is a BeAu columnar structure) , and in order to increase the conductivity, the P-type ohmic contact area 321 can extend vertically up and down (not shown) to the high-conductivity metal layer 31 and the high-concentration P-type semiconductor layer 33 respectively.
  • the highly conductive metal layer 31 uses chemically stable and highly conductive metal to achieve high lateral current conduction, and the material can be Ag/Au/Al/Ti/TiW or Pt.
  • FIGS. 4A to 4C are schematic diagrams of the insulating layer 50, the bridge connection metal layer 60, the N-type ohmic contact electrode 70 and the N-type electrode pad 80, and for clarity.
  • the hierarchical relationship of each layer structure, each layer structure is drawn in an opaque manner.
  • the insulating layer 50 is formed on the outer extension platform 302, and the insulating layer 50 is extended to cover the N-type semiconductor 43 and on the four straight sides 403
  • a frame coverage area 402 is formed around the N-type semiconductor 43 .
  • the insulating layer 50 is usually made of SiO 2 insulating material larger than 500 nanometers (nm) by PECVD, which can have better adhesion to the sidewall of the PN junction structure 40 .
  • the bridging connected metal layer 60 is disposed on the insulating layer 50 and both ends respectively extend to the frame coverage area 402 on the outer extension platform 302 .
  • the N-type electrode pad 80 is formed on the bridging metal layer 60 at a position corresponding to the outer extension platform 302 to electrically connect the bridging metal layer 60 .
  • the N electrode pad on the outer extension platform 302 is circular, and gold (Au) is deposited on it with about 3 ⁇ m to facilitate subsequent packaging and bonding.
  • the N-type ohmic contact electrode 70 surrounds and ohmicly contacts the surface of the N-type semiconductor 43 in the upper peripheral region of the PN junction structure 40, and covers the Frame coverage area 402, and the P-type semiconductor 41 in the lower central area of the PN junction structure 40 is electrically connected to the P-type ohmic contact block 321 (as shown in FIG. 3 ), and the N-type ohmic contact electrode 70 In order to extend to the frame coverage area 402 and electrically connect the jumper metal layer 60, and in FIG. The relative position relationship with the P-type ohmic contact block 321 .
  • the N-type ohmic contact electrode 70 is a dispersed structure, which has at least one bare opening 71, and the at least one The bare drop opening 71 extends to the boundary of the PN junction structure 40 . In this way, the shading area can be reduced and the area of the ohmic contact area can be controlled more easily.
  • the N-type ohmic contact electrode 70 may also have at least one extended electrode 72 protruding into the central region 401, and the area of the extended electrode 72 does not exceed 25% of the area of the central region 401, which may The amount of the current I passing through the central region 401 of the PN junction structure 40 is increased.
  • the grain structure of the PN junction structure 40 of this embodiment is a rectangular shape
  • the PN junction structure 40 is a closed figure with four straight-line side lengths 403, and the longest side and the shortest side of the four straight-line side lengths 403
  • the ratio of the sides is less than 3 (towards a square with symmetrical current gathering inwards), and the rectangle is beneficial for the arrangement of the multi-die structure 40 in a single package.
  • FIG. 6 is a schematic cross-sectional view of the grain structure of the third embodiment of the present invention, wherein the P-type ohmic contact block 321A is selected from a continuous integral single area, and the P-type non-ohmic contact block 322A can be transparent through Light-transmitting dielectric materials such as silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), silicon nitride (SiN), magnesium difluoride (MgF 2 ), indium tin oxide ITO, etc., or with this high-concentration P-type
  • the semiconductor 33 is made of non-ohmic contact highly reflective metal material, such as any one of aluminum (Al), silver (Ag), and gold (Au).
  • FIG. 7 is a schematic cross-sectional view of the grain structure of the fourth embodiment of the present invention, wherein the high-concentration P-type semiconductor layer 33 provided on the outer extension platform 302 is a thick-type P-type semiconductor (P-type limited layer plus a high-concentration P-type semiconductor layer) epitaxial structure, such as a phosphide LED epitaxial structure with a thick GaP high-concentration P-type semiconductor epitaxial layer, the high-concentration P-type semiconductor layer 33 can be doped with magnesium (Mg) or carbon (C) P-type indium gallium phosphide (p-Ga (x) In (1-x) P) or P-type gallium phosphide (p-GaP), and the high-concentration P-type semiconductor
  • Mg magnesium
  • C carbon
  • FIG. 8 is a schematic cross-sectional view of the grain structure of the fifth embodiment of the present invention, wherein the extended platform 302 is arranged on the local P-type ohmic contact layer 32.
  • the insulation can be strengthened.
  • FIG. 9 is a schematic cross-sectional view of the grain structure of the sixth embodiment of the present invention, wherein if the high-concentration P-type semiconductor layer 33 is P-type gallium nitride (p-GaN) doped with magnesium (Mg) or Any of P-type indium gallium nitride (p-Ga (x) In (1-x) N), and the thickness of the high-concentration P-type semiconductor layer 33 is less than 0.5 microns ( ⁇ m), and the outer extension platform 302 is disposed on the high conductive metal layer 31 .
  • p-GaN P-type gallium nitride
  • Mg magnesium
  • p-Ga (x) In (1-x) N any of P-type indium gallium nitride
  • the thickness of the high-concentration P-type semiconductor layer 33 is less than 0.5 microns ( ⁇ m)
  • the outer extension platform 302 is disposed on the high conductive metal layer 31 .
  • the features of the present invention include at least:
  • a current introduced by the N-type electrode pad will pass through the jumper to connect the metal layer. Since the N-type ohmic contact electrode is cohesively down to the central P-type ohmic contact block, the current will pass through the PN junction The central area of the light-emitting layer in the structure, and the N-type ohmic contact electrode covers the frame coverage area and is located at the periphery of the PN junction structure, and will not cover the central area. Since the PN junction structure has better epitaxial quality in the central region and can emit light without shielding, it can meet the requirement of high light efficiency.

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Abstract

一种中央区域高发光的小尺寸垂直式发光二极管晶粒，为让一PN接面结构设置于一界面结构的一发光区基座(The Base of Light Emitting Region)上，且该界面结构于该发光区基座设置一P型欧姆接触区块，并该PN接面结构的一中心区域正对该P型欧姆接触区块，一绝缘层形成于相邻该发光区基座的一外延伸平台(The extend terrace in chip structure)上，并延伸至覆盖该PN接面结构的一N型半导体上并形成一环绕该N型半导体的边框覆盖区，一N型欧姆接触电极围绕且欧姆接触该N型半导体并覆盖该边框覆盖区，一N型电极垫设置于该绝缘层上且通过一跨接连通金属层电性连接该N型欧姆接触电极，据此电流会内聚向下的通过该包含活性层的PN接面结构的中心区域以更有效率的进行载子复合发光，且因上方出光表面无遮蔽，进而更提升出光效率。

Description

中央区域高发光的小尺寸垂直式发光二极管晶粒 技术领域
本发明有关于发光二极管的晶粒结构，尤其有关于集中于中央区域发光的小尺寸垂直式发光二极管晶粒。
背景技术
LED晶粒依据外观、电极排列、半导体层电流方向，主要可分为：1.水平型(horizontal)2.垂直型(vertical)3.覆晶型(flip-chip)三大型态。其中小尺寸的水平型LED晶粒与垂直型LED晶粒发光效率较低，所以目前高阶小间距LED显示屏以使用较佳光效的覆晶型小尺寸晶粒为主，其为表面粘着元件(SMD:Surface Mounted components)，不需于发光面上方以打线方式连接电极垫，晶粒下方底部的N电极与P电极(P/N electrode)通过电极垫与封装载板导电粘结，所以晶粒上方发光表面无电极遮蔽，于小尺寸发光具有较佳的发光效率。
但在小尺寸晶粒底部同时安排N电极与P电极与载板导电粘着，有电极垫太小与间距太接近容易短路的缺点，其散热也较底部整面的垂直型LED差，于汽车使用的条件下，信赖度会有疑虑；另外磷化物红光覆晶型LED晶粒相较氮化物蓝绿光的制程复杂很多，以非蓝宝石基板长晶的覆晶型LED晶粒的成本会较垂直型LED高出许多。所以垂直型LED于车用的信赖度有优势，但其光效较差，若能改改善发光效率，有利于高信赖度需求的车用小尺寸LED显示器的发展。
习知垂直式发光二极管的结构，如图1所示，其包含一P型电极1、一晶粒导电基座结构2、一反射层3、一界面结构4、一PN接面结构5与一N型电极垫6，其中该晶粒导电基座结构2包含一结构金属层2A、一替代基板粘合层2B、一替代基板2C，该界面结构4为局部P型欧姆接触金属层，包含P型欧姆接触区块4A与非P型欧姆接触区块4B。该PN接面结构5包含一P型半导体5A、一活性层5B与一N型半导体5C。垂直式发光二极管虽具有高轴向光与良好散热性，有益于显色性与高温条件操作。但传统小尺寸垂直式发光二极管晶粒的直线边长大约为200微米(μm)，由于晶片边缘需要设置切割 道、侧壁、金属层导通层等吸光干扰物质，而占用约40μm的必要尺度，且如图2所示，因N型半导体5C(发光表面)上中央区域有N型电极垫6(N electrode)，中心发光被遮蔽，且N型电极垫6位于活性层5B(Active Layer)与N型半导体5C的上方，因其晶粒与电极垫的面积都极小，于打线时易造成活性层5B微裂痕与缺陷。又通常具有辅助线6A(Finger)以指叉状位于N型半导体5C上方，越多辅助线6A设置于N型半导体5C上，虽然电流分散越佳，但也会增加遮光面积。所以传统小尺寸垂直型LED的光效与信赖性皆劣于小尺寸覆晶型LED，但传统小尺寸垂直型LED的高轴向光与高散热特性，更有利于高对比的车用小间距显示器使用。
发明内容
爰此，本发明的主要目的在于一种会于中央区域高发光的小尺寸垂直式发光二极管晶粒，而发光面上方可无遮蔽出光，达成高光效的需求。
本发明为一种中央区域高发光的小尺寸垂直式发光二极管晶粒，其包含一P型电极、一晶粒导电基座结构、一界面结构、一PN接面结构、一绝缘层、一跨接连通金属层、一N型欧姆接触电极与一N型电极垫。其中该晶粒导电基座结构的一侧设置该P型电极，该晶粒导电基座结构远离该P型电极的一侧设置该界面结构，该界面结构包含依序堆叠的一高导电金属层、一局部P型欧姆接触层与一透光的高浓度P型半导体层，并该界面结构具有一发光区基座与一外延伸平台，该外延伸平台相邻该发光区基座。该PN接面结构包含依序堆叠的一P型半导体、一活性层与一N型半导体，且该P型半导体设置于该发光区基座之上，并该PN接面结构为具有四直线边长的封闭图形，且具有一中心区域。该四直线边长的最长边与最短边的比为小于3，并该PN接面结构的发光表面积为小于0.06平方毫米(mm 2)，该局部P型欧姆接触层位于该发光区基座与该外延伸平台的下方，该局部P型欧姆接触层包含一P型欧姆接触区块与一P型非欧姆接触区块，该P型欧姆接触区块位于该中心区域的下方，该P型欧姆接触区块与该高浓度P型半导体层达欧姆接触，而该P型非欧姆接触区块与该高浓度P型半导体层为非欧姆接触。
该绝缘层形成于该外延伸平台上，并该绝缘层延伸至覆盖该N型半导体上并于该四直线边长处形成一边框覆盖区，该边框覆盖区环绕该N型半导体。 该跨接连通金属层设置于该绝缘层上且两端分别延伸至该边框覆盖区上与该外延伸平台上。
该N型欧姆接触电极围绕且欧姆接触该PN接面结构的活性层的上方外围区域的N型半导体的表面，并覆盖该边框覆盖区。而该活性层的下方中央区域的P型半导体与该P型欧姆接触区块达到电性连接，又该N型欧姆接触电极为延伸至该边框覆盖区上并电性连接该跨接连通金属层，该N型电极垫为于对应于该外延伸平台之处形成于该跨接连通金属层上以电性连接该跨接连通金属层。
据此，由该N型电极垫导入的一电流会经该跨接连通金属层，由该N型欧姆接触电极内聚向下的通过该PN接面结构的该中心区域，电流聚集于该活性层的中央达到载子复合发光。因该活性层的中央上方发光无遮蔽，因而除了可提升发光效率外，其使用于小间距显示器也可提高黑占比，达到更佳显示器对比度。另外，此一设计的该N型电极垫非位于该PN接面结构上，没有打线制程破坏该PN接面结构的问题，可达高信赖度需求。
附图说明
图1，为习知小尺寸垂直型LED结构断面示意图；
图2，为习知小尺寸垂直型LED俯视表面结构图；
图3，为本发明第一实施例的晶粒结构断面示意图；
图4A，为本发明第一实施例的晶粒结构俯视示意图一；
图4B，为本发明第一实施例的晶粒结构俯视示意图二；
图4C，为本发明第一实施例的晶粒结构俯视示意图三；
图5，为本发明第二实施例的晶粒结构俯视图；
图6，为本发明第三实施例的晶粒结构断面示意图；
图7，为本发明第四实施例的晶粒结构断面示意图；
图8，为本发明第五实施例的晶粒结构断面示意图；
图9，为本发明第六实施例的晶粒结构断面示意图。
具体实施方式
为对本发明的特征、目的及功效，有着更加深入的了解与认同，兹列举一 较佳实施例并配合附图说明如后：
请参阅图3所示，为本发明第一实施例，其包含一P型电极10、一晶粒导电基座结构20、一界面结构30、一PN接面结构40、一绝缘层50、一跨接连通金属层60、一N型欧姆接触电极70与一N型电极垫80。其中该晶粒导电基座结构20的一侧设置该P型电极10，该晶粒导电基座结构20远离该P型电极10的一侧设置该界面结构30。该晶粒导电基座结构20包含一结构金属层21、一替代基板粘合层22、一替代基板23。在一实施例中，该界面结构30包含依序堆叠的一高导电金属层31、一局部P型欧姆接触层32与一透光的高浓度P型半导体层33，并该界面结构30具有一发光区基座301与一外延伸平台302，该外延伸平台302相邻该发光区基座301。
该PN接面结构40为选自单一PN接面的发光二极管结构或两个PN接面的穿隧接面发光二极管结构(tunnel junction light emitter diode)的任一种。一实施例中，该PN接面结构40包含由下而上依序堆叠的一P型半导体41、一活性层42与一N型半导体43，且该P型半导体41设置于该发光区基座301之上，该N型半导体43的最高厚度区域的厚度为大于2.5微米(μm)，厚度大有益于边缘电流向内导通。如图4A所示，一实施例中，该PN接面结构40为具有封闭几何图形且具有一中心区域401，该PN接面结构40的发光表面积为小于0.06平方毫米(mm 2)(小面积益于由欧姆接触边框经由N型半导体43导通至PN接面结构40的中心区域401)。
该局部P型欧姆接触层32位于该发光区基座301与该外延伸平台302的下方，该局部P型欧姆接触层32包含一P型欧姆接触区块321与一P型非欧姆接触区块322，该P型欧姆接触区321位于该中心区域401的下方。该P型欧姆接触区块321与该高浓度P型半导体层33达欧姆接触，而该P型非欧姆接触区块322与该高浓度P型半导体层33为非欧姆接触。其中若该高浓度P型半导体层为P型氮化镓(p-GaN)或P型氮化铟镓(p-Ga (x)In (1-x)N)的任一种，且高浓度掺杂为镁(Mg)，则该P型欧姆接触区块的材料可为银(Ag)、镍(Ni)、氧化铟锡(ITO)。而若该高浓度P型半导体层为P型磷化镓(p-GaP)、P型磷化铟镓(p-Ga (x)In (1-x)P)、P型砷化镓(p-GaAs)或P型砷化铟镓(p-Ga (x)In (1-x)As)的任一种，且高浓度掺杂为选自碳(C)或镁(Mg)的任一种，则该P型欧姆接触区块的材料可为铍金合金(BeAu Alloy)。
一实施例中，该P型欧姆接触区块321为非连续多个区域，如可以是多个柱状(例如:磷化物LED晶粒其可与p-GaP欧姆接触的材料为BeAu柱状结构)结构，且为了增加导电率，该P型欧姆接触区块321更可以垂直上下分别延伸(图未示)至该高导电金属层31与该高浓度P型半导体层33。而高导电金属层31以化性稳定的高导电的金属达到高横向电流传导，材料可为Ag/Au/Al/Ti/TiW或Pt。
请再一并参阅图4A～图4C所示，为该绝缘层50、该跨接连通金属层60、该N型欧姆接触电极70与该N型电极垫80的施作示意图，且为了清楚表示各层结构的层次关系，各层结构为以不透明的方式绘制。首先如图4A所示，为铺上该绝缘层50，该绝缘层50形成于该外延伸平台302上，并该绝缘层50延伸至覆盖该N型半导体43上并于该四直线边长403处形成一边框覆盖区402，该边框覆盖区402环绕该N型半导体43。该绝缘层50通常以均向沉积的PECVD施作大于500纳米(nm)的SiO 2绝缘材料，可以对该PN接面结构40的侧壁有较佳附着力。
接着如图4B所示，为铺上该跨接连通金属层60与该N型电极垫80，该跨接连通金属层60设置于该绝缘层50上且两端分别延伸至该边框覆盖区402上与该外延伸平台302上。该N型电极垫80为于对应于该外延伸平台302之处形成于该跨接连通金属层60上以电性连接该跨接连通金属层60。该外延伸平台302上的N电极垫为圆形，且上方沉积金(Au)约3μm以利后续封装打线。
接着如图4C所示，为铺上该N型欧姆接触电极70，该N型欧姆接触电极70围绕且欧姆接触该PN接面结构40的上方外围区域的N型半导体43的表面，并覆盖该边框覆盖区402，而该PN接面结构40的下方中央区域的P型半导体41与该P型欧姆接触区块321达到电性连接(如图3所示)，又该N型欧姆接触电极70为延伸至该边框覆盖区402上并电性连接该跨接连通金属层60，且于图4C中，更绘制该P型欧姆接触区块321的位置，以清楚显示该N型欧姆接触电极70与该P型欧姆接触区块321的相对位置关系。据此，由该N型电极垫80导入的一电流I会经该跨接连通金属层60(如图3所示)，由该N型欧姆接触电极70内聚向下的通过该PN接面结构40的该中心区域401。
请参阅图5所示，为第二实施例的晶粒结构俯视图，为了调整N型欧姆 接触电流扩散，该N型欧姆接触电极70为分散结构，其具有至少一裸落开口71，该至少一裸落开口71延伸至该PN接面结构40的边界。如此，即可以减少遮光面积与更易控制欧姆接触区面积。另在一实施例中，该N型欧姆接触电极70亦可以具有至少一伸入该中心区域401的延伸电极72，且该延伸电极72的面积不超过该中心区域401的面积的25％，可以增加该电流I通过该PN接面结构40的该中心区域401的量。另，此实施例的该PN接面结构40的晶粒结构为长方形状，该PN接面结构40为具有四直线边长403的封闭图形，并该四直线边长403的最长边与最短边的比为小于3(趋向正方形有对称的电流向内聚集)，长方形有益于多颗晶粒结构40于单一封装体内的排列。
请参阅图6所示，为本发明第三实施例的晶粒结构断面示意图，其中P型欧姆接触区块321A为选自连续整体单一区域，该P型非欧姆接触区块322A可以为透明穿透光介电材料如二氧化硅(SiO 2)、二氧化钛(TiO 2)、氮化硅(SiN)、二氟化镁(MgF 2)、氧化铟锡ITO等等，或与该高浓度P型半导体33非欧姆接触的高反射金属材料，如铝(Al)、银(Ag)、金(Au)的任一种制成。
请参阅图7所示，为本发明第四实施例的晶粒结构断面示意图，其中该外延伸平台302设置的该高浓度P型半导体层33上，为具有厚型P型半导体(P型局限层加上高浓度P型半导体层)的磊晶结构，如磷化物LED磊晶结构具有厚GaP高浓度P型半导体磊晶层，该高浓度P型半导体层33可以为参杂镁(Mg)或碳(C)的P型磷化铟镓(p-Ga (x)In (1-x)P)或P型磷化镓(p-GaP)的任一种，且该高浓度P型半导体层33的厚度为大于2微米(μm)，而在此实施例中，该P型欧姆接触区块321B为以铍金合金(BeAu Alloy)为欧姆接材料，该P型非欧姆接触区块322B可以为高反射金属材料如铝(Al)、银(Ag)、金(Au)等等。
请参阅图8所示，为本发明第五实施例的晶粒结构断面示意图，其中该外延伸平台302为设置于该局部P型欧姆接触层32上，在此实施例中，可以强化该绝缘层50的绝缘效果，但蚀刻的深度需要精准控制。
请参阅图9所示，为本发明第六实施例的晶粒结构断面示意图，其中若该高浓度P型半导体层33为参杂镁(Mg)的P型氮化镓(p-GaN)或P型氮化铟镓(p-Ga (x)In (1-x)N)的任一种，且该高浓度P型半导体层33的厚度低于0.5微米(μm)，并该外延伸平台302为设置于该高导电金属层31上。
如上所述，本发明的特点至少包含：
1.由该N型电极垫导入的一电流会经该跨接连通金属层，由于该N型欧姆接触电极内聚向下至中央的该P型欧姆接触区块，电流会通过该PN接面结构中的发光层中心区域，且该N型欧姆接触电极覆盖该边框覆盖区而位于该PN接面结构的外围，不会遮蔽该中心区域。由于该PN接面结构于该中心区域具有较好的磊晶品质且可无遮蔽出光，因而可以达成高光效的需求。
2.该N型电极垫下方无该PN接面结构，不会因封装制程的打线应力，而造成该PN接面结构缺陷。另外，N型电极垫因接触电阻产生的热量，不会如习知结构的向下传导至活性层，影响载子复合效率。

Claims (13)

  1. 一种中央区域高发光的小尺寸垂直式发光二极管晶粒，其特征在于，包含：
    一P型电极；
    一晶粒导电基座结构，该晶粒导电基座结构的一侧设置该P型电极；
    一界面结构，该晶粒导电基座结构远离该P型电极的一侧设置该界面结构，该界面结构包含依序堆叠的一高导电金属层、一局部P型欧姆接触层与一透光的高浓度P型半导体层，并该界面结构具有一发光区基座与一相邻该发光区基座的外延伸平台；
    一PN接面结构，该PN接面结构包含依序堆叠的一P型半导体、一活性层与一N型半导体，且该P型半导体设置于该发光区基座之上，并该PN接面结构为具有四直线边长的封闭图形且具有一中心区域，该四直线边长的最长边与最短边的比为小于3，并该PN接面结构的发光表面积为小于0.06平方毫米，该局部P型欧姆接触层位于该发光区基座与该外延伸平台的下方，该局部P型欧姆接触层包含一位于该中心区域的下方的P型欧姆接触区块与一P型非欧姆接触区块，该P型欧姆接触区块与该高浓度P型半导体层达欧姆接触，而该P型非欧姆接触区块与该高浓度P型半导体层为非欧姆接触；
    一绝缘层，该绝缘层形成于该外延伸平台上，并该绝缘层延伸至覆盖该N型半导体上并于该四直线边长处形成一环绕该N型半导体的边框覆盖区；
    一跨接连通金属层，该跨接连通金属层设置于该绝缘层上且两端分别延伸至该边框覆盖区上与该外延伸平台上；
    一N型欧姆接触电极，该N型欧姆接触电极围绕且欧姆接触该PN接面结构的活性层的上方外围区域的N型半导体的表面，并覆盖该边框覆盖区，而该活性层的下方中央区域的P型半导体与该P型欧姆接触区块达到电性连接，又该N型欧姆接触电极为延伸至该边框覆盖区上并电性连接该跨接连通金属层；以及
    一N型电极垫，该N型电极垫为于对应于该外延伸平台之处形成于该跨接连通金属层上以电性连接该跨接连通金属层。
  2. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该 N型半导体的最高厚度区域的厚度为大于2.5微米。
  3. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该PN接面结构为选自单一PN接面的发光二极管结构或两个PN接面的穿隧接面发光二极管结构的任一种。
  4. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该N型欧姆接触电极具有至少一裸落开口，该至少一裸落开口延伸至该PN接面结构的边界。
  5. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该N型欧姆接触电极具有至少一伸入该中心区域的延伸电极。
  6. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该高浓度P型半导体层为P型氮化镓或P型氮化铟镓的任一种，且高浓度掺杂为镁，该P型欧姆接触区块的材料为银、镍、氧化铟锡。
  7. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该高浓度P型半导体层为P型磷化镓、P型磷化铟镓、P型砷化镓或P型砷化铟镓的任一种，且高浓度掺杂为选自碳或镁的任一种，该P型欧姆接触区块的材料为铍金合金。
  8. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该P型非欧姆接触区块为选自透明穿透光介电材料或与该高浓度P型半导体非欧姆接触的高反射金属材料的任一种制成。
  9. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该P型欧姆接触区块为选自连续整体单一区域与非连续多个区域的任一种。
  10. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于， 该P型欧姆接触区块为垂直上下分别延伸至该高导电金属层与该高浓度P型半导体层。
  11. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该外延伸平台为设置于该高导电金属层、该局部P型欧姆接触层与该高浓度P型半导体层的任一上。
  12. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该高浓度P型半导体层为参杂镁的P型氮化镓或P型氮化铟镓的任一种，且该高浓度P型半导体层的厚度低于0.5微米，并该外延伸平台为设置于该高导电金属层上。
  13. 根据权利要求1所述的小尺寸垂直式发光二极管晶粒，其特征在于，该高浓度P型半导体层为参杂镁或碳的P型磷化铟镓或P型磷化镓的任一种，且该高浓度P型半导体层的厚度为大于2微米，并该外延伸平台为设置于该高浓度P型半导体层上。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1295350A (zh) * 1999-11-05 2001-05-16 洲磊科技股份有限公司 发光半导体装置及其制作方法
US20080173885A1 (en) * 2006-02-20 2008-07-24 Yuichi Kuromizu Semiconductor light-emitting device and method of manufacturing the same
CN101989641A (zh) * 2009-07-30 2011-03-23 日立电线株式会社 发光元件
CN105845801A (zh) * 2016-06-13 2016-08-10 天津三安光电有限公司 发光二极管及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1295350A (zh) * 1999-11-05 2001-05-16 洲磊科技股份有限公司 发光半导体装置及其制作方法
US20080173885A1 (en) * 2006-02-20 2008-07-24 Yuichi Kuromizu Semiconductor light-emitting device and method of manufacturing the same
CN101989641A (zh) * 2009-07-30 2011-03-23 日立电线株式会社 发光元件
CN105845801A (zh) * 2016-06-13 2016-08-10 天津三安光电有限公司 发光二极管及其制作方法

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