WO2023123973A1 - 实现卷积运算的电路及其方法 - Google Patents

实现卷积运算的电路及其方法 Download PDF

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WO2023123973A1
WO2023123973A1 PCT/CN2022/102952 CN2022102952W WO2023123973A1 WO 2023123973 A1 WO2023123973 A1 WO 2023123973A1 CN 2022102952 W CN2022102952 W CN 2022102952W WO 2023123973 A1 WO2023123973 A1 WO 2023123973A1
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signal
output
current
column
digital
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French (fr)
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张飞翔
李琛
余学儒
段杰斌
杨何勇
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上海集成电路装备材料产业创新中心有限公司
上海集成电路研发中心有限公司
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Publication of WO2023123973A1 publication Critical patent/WO2023123973A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

Definitions

  • the invention relates to the field of digital circuits and analog circuits, in particular to a circuit and method for realizing convolution operation.
  • the upper layer of the convolutional layer of the neural network is the activation layer, and the input of the convolutional layer is a positive number.
  • the input can be quantized into a positive integer first, and then converted into a voltage through a digital-to-analog converter.
  • the weight is generally positive or negative.
  • the method of mapping to the RRAM conductivity includes: using an asymmetric quantization algorithm to quantize the weight into a positive integer and then directly map it to the RRAM conductivity. This method needs to add additional circuits to handle the shift factor. Circuit complexity: using a symmetrical quantization algorithm, the weight is quantized as an integer (positive and negative), and the positive and negative values are represented by the RRAM pair method. This method requires a large amount of memory, increasing circuit complexity and circuit cost.
  • the circuit for realizing the convolution operation of the present invention includes an encoding module, a digital-to-analog conversion module, a memory array, an adjustment module, a symbol column processing module, and a calculation module;
  • the encoding module is used to obtain a sign bit according to the range of the quantized weight signal, and encode the quantized weight signal to obtain a weight code;
  • the digital-to-analog conversion module is used to convert an externally input digital signal into a voltage signal, and transmit the voltage signal to the memory array as an input of the memory array;
  • the memory array is used to map the weight code, and after receiving the voltage signal, each column of the memory array outputs a first current signal;
  • the adjustment module is used to obtain a first output signal according to the first current signal
  • the sign column processing module is used to obtain a sign column according to the sign bit, the sign column is the column where the sign bit is located in the memory array, and output the sign column according to the sign column and the first output signal value;
  • the calculation module is used to obtain a convolution output value according to the symbol column output value and the first output signal.
  • the memory array can not only map positive integer weights, but also map negative integer weights, so that there is no need to use the method of resistive variable memory pairs to represent the positive and negative values of weights, which saves the number of memories and solves the problem of realizing convolutional neural networks.
  • the calculation circuit needs more resistive memory, which reduces the complexity of the convolution operation, improves the efficiency and accuracy of the convolution operation, and saves the area and cost of the circuit board.
  • the memory array includes several convolution kernel mapping units, each convolution kernel mapping unit maps one weight code, and each convolution kernel mapping unit includes one symbol column and several non-symbol columns column, the sign column and several non-sign columns respectively output the first current signal.
  • the sign column processing module is connected to the output terminal of the sign column, and is used to perform an inversion operation on the first output signal output by the sign column to output the sign column output value.
  • the beneficial effect is that after the symbol sequence is obtained by the symbol sequence processing module, an inversion operation is performed on the first output signal output by the symbol sequence to output the symbol sequence output value.
  • both the sign column and the non-sign column include m first storage units, where m is a positive integer;
  • All the first storage units in the same row are connected to a voltage input terminal and receive the input voltage signal;
  • All the first storage units in the same column are connected to the current output terminal.
  • the circuit for realizing the convolution operation further includes a reference array, the input end of the reference array is connected to the output end of the digital-to-analog conversion module to receive the voltage signal, and the output end thereof is connected to the output end of the adjustment module.
  • an input terminal, the output terminal of the adjustment module is connected to the symbol column processing module;
  • the adjusting module adjusts the first current signal through the reference current signal to obtain the first output signal.
  • the reference array includes m second storage units distributed in a column, where m is a positive integer, and each second storage unit is connected to the first storage unit in the same row.
  • the adjustment module includes a current subtraction circuit, a first current-to-voltage unit, and a first analog-to-digital conversion unit;
  • the input terminal of the current subtraction circuit is connected to the current output terminal of the memory array and the current output terminal of the reference array, which is used for outputting the first current signal and the reference current signal for each column of the memory array respectively performing subtraction operations to output a plurality of second current signals;
  • the input terminal of the first current-to-voltage unit is connected to the output terminal of the current subtraction circuit to convert the second current signal into a first voltage signal;
  • the input end of the first analog-to-digital conversion unit is connected to the output end of the first current-to-voltage unit, so as to perform analog-to-digital signal conversion on the first voltage signal to output the first output signal.
  • the beneficial effect is that, since the first current signal output by each column of the memory array is equal to the multiplication and addition result of the voltage and conductivity of the memory cells in the current column, the first current signal affects the first output signal, and the first output signal affects the convolution operation Therefore, the leakage current produced by the memory array will affect the final output value of the convolution operation, and the leakage current is the current generated by the high-resistance memory unit in the memory array; through the current subtraction circuit for each of the memory array
  • the first current signal output by one column and the reference current signal respectively perform subtraction operations to output a number of second current signals, reduce the leakage current in the memory array, and weaken the influence of the leakage current on the first output signal, so as to avoid the generation of leakage current in the memory array.
  • the adjustment module includes a second current-to-voltage unit, a third current-to-voltage unit, a second analog-to-digital conversion unit, a third analog-to-digital conversion unit, and a digital domain subtractor;
  • the input end of the second current-to-voltage unit is connected to the current output end of the memory array, and the output end is connected to the input end of the second analog-to-digital conversion unit for converting the first current signal into a second Two voltage signals, the second analog-to-digital conversion unit converts the second voltage signal into a first digital signal;
  • the input end of the third current-to-voltage unit is connected to the current output end of the reference array, and the output end is connected to the input end of the third analog-to-digital conversion unit for converting the reference current signal into a third a voltage signal, the third analog-to-digital conversion unit is used to convert the third voltage signal into a second digital signal;
  • the output end of the second analog-to-digital conversion unit is connected to the first input end of the digital domain subtractor, the output end of the third analog-to-digital conversion unit is connected to the second input end of the digital domain subtractor, and the The digital domain subtractor is used to perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal.
  • the beneficial effect is that the first current signal and the reference current signal are respectively converted into the second voltage signal and the third voltage signal by the second current-to-voltage unit and the third current-to-voltage unit, and the second modulus
  • the conversion unit and the third analog-to-digital conversion unit respectively convert the second voltage signal and the third voltage signal into a first digital signal and a second digital signal; performing a subtraction operation on the second digital signal to output the first output signal.
  • the present invention also provides a method for realizing convolution operation, comprising steps:
  • the positive integer weight and the negative integer weight are mapped through the memory array, saving the amount of memory, and improving the efficiency and accuracy of convolution operation.
  • the step of obtaining the first output signal according to the first current signal includes:
  • the step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:
  • the beneficial effect is that the influence of the leakage current on the result of the convolution operation is weakened, and the accuracy of the convolution operation is improved.
  • the step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:
  • a subtraction operation is performed on the first digital signal and the second digital signal to output the first output signal.
  • Fig. 1 is the structural block diagram of the circuit that realizes the convolution operation of the embodiment of the present invention
  • Fig. 2 is the circuit diagram of the circuit realizing the convolution operation of the embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a convolution operation according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an adjustment module in a first implementation manner of an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a current subtraction circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an adjustment module in a second implementation manner of an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for implementing a convolution operation according to an embodiment of the present invention.
  • FIG. 8 is a flow chart of obtaining a first output signal in the first implementation manner of the embodiment of the present invention.
  • FIG. 9 is a flow chart of acquiring a first output signal in a second implementation manner of an embodiment of the present invention.
  • FIG. 1 is a structural block diagram of a circuit for realizing a convolution operation according to an embodiment of the present invention.
  • the circuit for realizing the convolution operation of the present invention includes an encoding module 1, a digital-to-analog conversion module 5, a memory array 2, an adjustment module 4, a symbol column processing module 6 and a calculation module 7.
  • the circuit also includes a reference array 3 .
  • the encoding module 1 is configured to obtain a sign bit according to the range of the quantized weight signal, and encode the quantized weight signal to obtain a weight code;
  • the digital-to-analog conversion module 5 is used to convert an externally input digital signal into a voltage signal, and transmit the voltage signal to the memory array 2 as an input voltage signal of the memory array 2;
  • the memory array 2 is used to map the weight code, and after receiving the input voltage signal, each column of the memory array 2 outputs a first current signal;
  • the adjustment module 4 is used to obtain a first output signal according to the first current signal
  • the sign column processing module 6 is configured to obtain a sign column according to the sign bit and the first output signal, the sign column is a column corresponding to the sign bit in the memory array 2, and according to the sign column and the first output signal output_signal_out_sym_column_out_value;
  • the calculating module 7 is used for obtaining the convolution output value according to the sign column output value and the first output signal.
  • FIG. 2 is a circuit diagram of a circuit for implementing a convolution operation according to an embodiment of the present invention.
  • the encoding module 1 is configured to obtain a sign bit according to the range of the quantized weight signal, and the step of encoding the quantized weight signal to obtain a weight code includes :
  • the quantized integer weight (weight) is coded as:
  • W is the weight after quantization
  • k is the number of resistance states of RRAM
  • map W i to the corresponding resistance value represent weight through RRAM
  • n represent the result of mapping a weight
  • the number of required RRAMs, m weights are represented by RRAMs with m rows and n columns, and the m is a positive integer
  • the value of u(i) is determined according to the value of i
  • the calculation formula of u(i) is:
  • the sign bit is obtained according to the range of the quantized weight signal.
  • the number of RRAM resistance states as 2, and 8 RRAMs to map a weight as an example:
  • the specific value can be expressed as:
  • memory array 2 comprises several convolution kernel mapping units 20, and each described convolution kernel mapping unit 20 maps a described weight code, and includes a described symbol column 201 and in each convolution kernel mapping unit 20 Several non-sign columns, the sign column 201 and the several non-sign columns respectively output the first current signal, wherein the non-sign columns are columns in the convolution kernel mapping unit 20 other than the sign column 201 .
  • Both the sign column 201 and the non-sign column include m first storage units 202, where m is a positive integer;
  • All the first storage units 202 in the same row are connected to a voltage input terminal and receive the input voltage signal;
  • All the first storage units 202 in the same column are connected to the current output terminal.
  • the first storage unit 202 is an RRAM, and the resistance state of the RRAM is not limited to high resistance and low resistance, and may also be a multi-resistance RRAM.
  • binary RRAM has only two states of high resistance and low resistance, which can represent 0 and 1, and the number of resistance states of RRAM is 2 at this time.
  • multi-value RRAM In addition to the high-resistance state and low-resistance state, multi-value RRAM also has intermediate states.
  • the resistance values of a multi-value RRAM are 6000 ⁇ , 600 ⁇ , 300 ⁇ , and 200 ⁇ , which can represent 0, 1, 2, and 3 respectively.
  • the number of resistance states of RRAM is 4.
  • the conductivity of the RRAM is related to the input voltage and output current as follows:
  • R is the resistance value of RRAM
  • G is the conductivity of RRAM
  • I is the output current of RRAM
  • U is the input voltage of RRAM
  • the final output current value of each column RRAM is the first current signal
  • the final output current value of each convolution kernel mapping unit 20 is equal to that of all columns RRAM
  • an encoding rule is also set, and the encoding rule is: the range mapped by all RRAMs in the symbol column is greater than the range of the weight signal, so that an array composed of fewer RRAMs can map one weight signal, that is, one
  • the weight signal can be represented by fewer RRAMs, saving the number of RRAMs and chip area, and saving power consumption.
  • FIG. 3 is a schematic diagram of a convolution operation in an embodiment of the present invention.
  • Input is a digital signal input by convolution
  • weight is a weight signal
  • output is a digital signal output by convolution.
  • the above-mentioned weight is mapped through the memory array 2.
  • the memory array 2 includes several columns of RRAM, and the RRAM includes high-impedance RRAM and low-impedance RRAM; set low-impedance RRAM
  • the conductivity of the high-resistance RRAM is 1, and the number 1 is mapped through the low-resistance RRAM; the conductivity of the high-resistance RRAM is set to 0.1, and the number 0 is mapped through the high-resistance RRAM.
  • the convolution input digital signal Input is 1 and 2
  • the digital-to-analog conversion module 5 converts 1 into a voltage signal and outputs it to the first storage unit 202 of the first row as the first storage unit 202 of the first row 2 is converted into a voltage signal by the digital-to-analog conversion module 5 and output to the first storage unit 202 of the second row as the input voltage of the first storage unit 202 of the second row.
  • the digital-to-analog conversion module 5 of the present invention is a digital-to-analog converter (Digital to Analog Converter, DAC), which converts an externally input digital signal into a voltage signal through the DAC, as the input of the memory array 2.
  • DAC Digital to Analog Converter
  • the input end of the reference array 3 is connected to the output end of the digital-to-analog conversion module 5 to receive the voltage signal, and its output end is connected to the first input end of the adjustment module 4, and the second input end of the adjustment module 4
  • the output end of the memory array is connected, and the output end is connected to the symbol column processing module.
  • the adjustment module 4 adjusts the first current signal through the reference current signal to obtain the first output signal.
  • the reference array 3 includes m second storage units 30 distributed in a column, and the number of rows of the first storage units 202 is the same as that of the second storage units 30 , both of which are m rows.
  • the m is a positive integer, and each second storage unit 30 is connected to the first storage unit 202 in the same row.
  • the second storage unit 30 is an RRAM, specifically, the second storage unit 30 is a high-resistance RRAM with a conductivity of 0.1.
  • the reference current is generated by the high-impedance RRAM of the reference array 3, thereby reducing the leakage current output by the memory array 1 and weakening the influence of the leakage current on the convolution output result. influence, improving the accuracy of the mapped weight signal.
  • Fig. 4 is a schematic structural diagram of an adjustment module in the first implementation mode of an embodiment of the present invention
  • Fig. 5 is a schematic structural diagram of a current subtraction circuit 40 of an embodiment of the present invention
  • I in Fig. 4 and Fig. 5 is a second current signal
  • I signal is the first current signal output by the first memory cell of each column output by the memory array 2
  • I ref is the reference current signal output by the reference array 3 .
  • the adjustment module 4 includes a current subtraction circuit 40 , a first current-to-voltage unit 41 and a first analog-to-digital conversion unit 42 .
  • the input terminal of the current subtraction circuit 40 is connected to the current output terminal of the memory array 2 and the current output terminal of the reference array 3, for the first current signal output to each column of the memory array 2 and the first current signal output by the reference array 3. Subtraction operations are performed on the reference current signals to output a plurality of second current signals.
  • the input terminal of the first current-to-voltage unit 41 is connected to the output terminal of the current subtraction circuit 40 for converting the second current signal into a first voltage signal.
  • the input end of the first analog-to-digital conversion unit 42 is connected to the output end of the first current-to-voltage unit 41 for performing analog-to-digital signal conversion on the first voltage signal to output the first output signal.
  • the convolution input digital signal is transformed into a voltage signal and used as the voltage input of the memory array 2, and the first current signal output by each column of the memory array 2 is equal to the multiplication and addition result of the voltage and the conductivity of the memory cell of the current column,
  • the first current signal affects the first output signal, and the first output signal affects the final output value of the convolution operation.
  • the leakage current generated by the memory array 2 will affect the final output value of the convolution operation.
  • the leakage current is the high-resistance storage in the memory array.
  • the influence on the first output signal improves the accuracy of the convolution operation.
  • the current subtraction circuit 40 includes a current mirror, the current mirror includes an adjustment current output terminal, a first NMOS transistor 411 and a second NMOS transistor 412, and the drain of the first NMOS transistor 411 is connected to the memory array 2
  • the current output end of the first NMOS transistor 411 is connected to the current output end of the memory array 2 to receive the first current signal, and the node between the drain of the first NMOS transistor 411 and the current output end of the memory array 2 is connected to the adjustment current output end.
  • a current mirror output terminal is also provided between the drain of the memory array 2 and the current output terminal of the memory array 2 to output the second current signal, the gate of the first NMOS transistor 411 is connected to the gate of the second NMOS transistor 412, The source of the first NMOS transistor 411 is connected to the source of the second NMOS transistor 412 .
  • the drain of the second NMOS transistor 412 is connected to the current output terminal of the reference array 3 to receive the reference current signal, and the drain and gate of the second NMOS transistor 412 are short-circuited.
  • the first NMOS transistor 411 is controlled to work in a saturation region, so that the adjusted current output end outputs the second current signal.
  • the drain of the first NMOS transistor 411 receives the first current signal I singal output from each column in the memory array 2, and the drain of the second NMOS transistor 412 receives the reference output from the reference array 3.
  • the current signal I ref the calculation formula of the second current signal I output from the adjusted current output terminal is as follows:
  • I is the second current signal
  • I singal is the first current signal output by the first memory cell of each column output by the memory array 2
  • I ref is the reference current signal output by the reference array 3 .
  • I singal is the first current signal output by the first memory cell of each column output by the memory array 2
  • I ref is the reference array 3 Output reference current signal.
  • the adjustment module includes a second current-to-voltage unit 43, a third current-to-voltage unit 44, a second analog-to-digital conversion unit 45, a third analog-to-digital conversion unit 46, and a digital domain subtractor 47;
  • the input end of the second current-to-voltage unit 43 is connected to the current output end of the memory array 2, the output end of the second current-to-voltage unit 43 is connected to the input end of the second analog-to-digital conversion unit 45, and the first The output end of two analog-to-digital conversion units 45 is connected to the first input end of the digital domain subtractor 47;
  • the input terminal of the third current-to-voltage unit 44 is connected to the current output terminal of the reference array 3, the output terminal of the third current-to-voltage unit 44 is connected to the input terminal of the third analog-to-digital conversion unit 46, and the first The output terminal of the three-analog-to-digital conversion unit 46 is connected to the second input terminal of the digital domain subtractor 47 .
  • the second current-to-voltage unit 43 is used to convert the first current signal into a second voltage signal
  • the second analog-to-digital conversion unit 45 is used to convert the second voltage signal into the first Digital signal.
  • the third current-to-voltage unit 44 is used to convert the reference current signal into a third voltage signal
  • the third analog-to-digital conversion unit 46 is used to convert the third voltage signal into a second digital signal.
  • the digital domain subtractor 47 is used for performing a subtraction operation on the first digital signal and the second digital signal to output the first output signal.
  • the first current signal and the reference current signal are respectively converted into a second voltage signal and a third voltage signal by the second current-to-voltage unit 43 and the third current-to-voltage unit 44, and the second analog-to-digital conversion unit 45 and the third analog-to-digital conversion unit 46 respectively convert the second voltage signal and the third voltage signal into a first digital signal and a second digital signal;
  • the subtraction operation is performed on the second digital signal to output the first output signal, so as to remove the leakage current in the memory array 2 and improve the accuracy of the convolution operation.
  • the present invention provides two implementations of the adjustment module. In actual operation, if the circuit performance is not considered, any one of the two adjustment modules can be selected;
  • the adjustment module can be selected according to the requirements of the circuit such as energy consumption and area, so as to improve the performance of the circuit for realizing the convolution operation of the present invention.
  • the first current-to-voltage unit 41, the second current-to-voltage unit 43, and the third current-to-voltage unit 44 may use a current-to-voltage circuit, specifically, by controlling The current is used to charge and discharge the capacitor to convert the current into the voltage across the capacitor to achieve the purpose of converting the current signal into a voltage signal.
  • the conversion calculation formula is as follows:
  • I is the current to be converted
  • T is the time to charge the capacitor
  • C is the capacitance value
  • the first analog-to-digital conversion unit 42, the second analog-to-digital conversion unit 45, and the third analog-to-digital conversion unit 46 are all analog-to-digital converters (Analog to Digital Converter, ADC), used to convert the voltage signal into a digital signal.
  • ADC Analog to Digital Converter
  • the symbol column processing module 6 is connected with the output terminal of the symbol column 201, and is used to carry out the inverse number operation to the first output signal output by the symbol column 201, to output the 201 output value of the symbol column,
  • the symbol column processing module 6 is also connected to the first adder. After the symbol column 201 is obtained by the symbol column processing module 6, the first output signal output by the symbol column 201 is inversely calculated to output the output value of the symbol column 201, so that the memory array 2 can map positive integer weights , can also map negative integer weights, saving the amount of memory.
  • the step of performing an inversion operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201 includes:
  • the inversion operation of the first output signal is equivalent to multiplying the first output signal by -1;
  • the first output signal corresponding to the symbol column 201 is realized by a binary logic operation circuit
  • it is equivalent to calculating the complement of the opposite number of the first output signal corresponding to the sign column 201, that is, adding 1 to the inverse code on the basis of the complement of the first output signal corresponding to the sign column 201 That's it.
  • the symbol sequence processing module 6 includes a Verilog language generation circuit in the digital domain, which is used to perform an inversion operation on the first output signal output by the symbol sequence 201 to output the output value of the symbol sequence 201 .
  • the calculation module 7 includes several first adders 71 and second adders 72, and each of the convolution kernel mapping units 20 corresponds to one of the first adders 71;
  • An adder 71 is connected to the output end of the symbol column processing module 6, and is used to perform a weighted sum operation on the output value of the symbol column 201 corresponding to each of the convolution kernel mapping units 20 and the first output signal to Get the weighted value.
  • the second adder 72 is connected to all the first adders 71, and is used for summing the weighted values output by all the first adders 71 to obtain the convolution output value. Its advantage is that the weighted summation operation is performed on the output value of the symbol column 201 corresponding to each of the convolution kernel mapping units 20 and the first output signal through the calculation module 7 to obtain a weighted value, and for all the first output signals The weighted values output by an adder 71 are summed to obtain the convolution output value, so as to realize the complete convolution calculation of the convolution circuit.
  • calculation module 7 can also comprise a total adder (not shown in the figure), and described total adder connects the output end connection of all symbol sequence processing modules 6, is used to receive all described symbol columns 201
  • the output value and the first output signal perform a weighted sum, and a total adder to perform the weighted sum calculation may increase the pressure on the calculation module 7 and prolong the calculation time, but it can save chip area and cost.
  • One or more adders can be set according to actual needs to calculate the final convolution output value.
  • FIG. 7 is a flow chart of a method for implementing a convolution operation according to an embodiment of the present invention.
  • the present invention also provides a kind of method that realizes convolution operation, comprises steps:
  • S5 Obtain a sign column according to the sign bit, the sign column is the column where the sign bit is located in the memory array, and output a sign column output value according to the sign column and the first output signal;
  • the memory array includes t convolution kernel mapping units, and each convolution kernel mapping unit uses n resistive storage units to map a weight, and the t and the n are both is a positive integer.
  • the resistive variable memory unit includes a high-resistance RRAM and a low-resistance RRAM, the conductivity of the high-resistance RRAM is smaller than that of the low-resistance RRAM, the high-resistance RRAM is used to map a digital 0, and the low-resistance RRAM Used to map the number 1.
  • step S2 include:
  • the step of described step S3 comprises:
  • the final output current value of each row of RRAMs is equal to the multiplication and addition result of the input voltage of the current row of RRAMs and the conductivity of the current row of RRAMs, so the final output current value of each row of RRAMs is the first a current signal.
  • the step of obtaining the first output signal according to the first current signal includes: setting a reference current signal to adjust the first current signal to obtain the first output signal, referring to FIG. 8 , which is the basic
  • the flow chart of obtaining the first output signal in the first implementation manner of the embodiment of the invention specifically includes:
  • S401 Perform a subtraction operation on the first current signal output by each column of the memory array and the reference current signal to obtain a plurality of second current signals;
  • S403 Perform analog-to-digital signal conversion on the first voltage signal to output the first output signal.
  • FIG. 9 is a flow chart of obtaining the first output signal in the second implementation manner of the embodiment of the present invention, which specifically includes:
  • S411 Convert the first current signal into a second voltage signal, and convert the second voltage signal into a first digital signal
  • S412 Convert the reference current signal into a third voltage signal, and convert the third voltage signal into a second digital signal;
  • S413 Perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal.
  • the step of outputting a symbol column output value according to the symbol column and the first output signal includes:
  • the step of obtaining the convolution output value according to the sign column output value and the first output signal includes:

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Abstract

本发明提供了一种实现卷积运算的电路及其方法，所述电路包括编码模块、数模转换模块、存储器阵列、参考阵列、调整模块、符号列处理模块和计算模块；编码模块用于获取符号位和权重编码；数模转换模块用于将输入数字信号转换为电压信号；存储器阵列用于映射所述权重编码并输出第一电流信号；调整模块用于依据所述第一电流信号获取所述第一电流信号；符号列处理模块用于获取符号列，并输出符号列输出值；计算模块用于获取卷积输出值。本发明所提供的实现卷积运算的电路节省存储器的数量，降低卷积运算的繁琐度，以提高卷积运算效率和准确性。

Description

实现卷积运算的电路及其方法
交叉引用
本申请要求2021年12月31日提交的申请号为202111675251.6的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及数字电路和模拟电路领域，尤其涉及一种实现卷积运算的电路及其方法。
技术背景
通过阻变式存储器(Resistive Random Access Memory，RRAM)电路实现卷积神经网络，需要对神经网络的输入、权重(weight)进行量化处理。通常，神经网络卷积层的上一层为激活层，卷积层的输入为正数。使用RRAM电路实现卷积层的运算时，可以将输入先量化为正整数，再经过数模转换器转变为电压。weight一般有正有负，映射到RRAM电导率的方法包括：采用非对称量化算法，将weight量化为正整数后直接映射为RRAM电导率，该方法需要增加额外的电路以处理移位因子，增加电路复杂性；采用对称量化算法，将weight量化为整数(有正有负)，使用RRAM对的方法表示正负值，该方法需要较多数量的存储器，增加电路复杂度及电路成本。
因此，有必要提供一种实现卷积运算的电路及其方法，以解决上述的现有技术中存在的问题。
发明概要
为实现上述目的，本发明的所述实现卷积运算的电路，包括编码模块、 数模转换模块、存储器阵列、调整模块、符号列处理模块和计算模块；
所述编码模块用于依据量化后的权重信号的范围获取符号位，并对所述量化后的权重信号进行编码以得到权重编码；
所述数模转换模块用于将外部输入的数字信号转换为电压信号，并将所述电压信号传输至所述存储器阵列，以作为所述存储器阵列的输入；
所述存储器阵列用于映射所述权重编码，并在接收所述电压信号后，所述存储器阵列的每一列均输出第一电流信号；
所述调整模块用于依据所述第一电流信号获取第一输出信号；
所述符号列处理模块用于依据所述符号位获取符号列，所述符号列为所述存储器阵列中符号位所在的列，并依据所述符号列和所述第一输出信号输出符号列输出值；
所述计算模块用于依据所述符号列输出值和第一输出信号获取卷积输出值。
本发明的所述实现卷积运算的电路的有益效果在于：
所述存储器阵列既可以映射正整数权重，也可以映射负整数权重，从而不需使用阻变式存储器对的方法来表示权重的正负值，节省了存储器的数量，解决了实现卷积神经网络运算的电路需要较多的阻变式存储器的问题，降低了卷积运算的繁琐度，提高了卷积运算效率和准确性，节约了电路板面积和成本。
可选地，所述存储器阵列包括若干卷积核映射单元，每个所述卷积核映射单元映射一个所述权重编码，每个卷积核映射单元中包括一个所述符号列和若干非符号列，所述符号列和若干非符号列分别输出所述第一电流信号。
可选地，所述符号列处理模块与所述符号列的输出端连接，用于对所述符号列输出的第一输出信号进行取相反数运算以输出所述符号列输出值。其有益效果在于，通过符号列处理模块获取符号列后，对所述符号列输出的第一输出信号进行取相反数运算以输出所述符号列输出值。
可选地，所述符号列和所述非符号列均包括m个第一存储单元，所述m 为正整数；
同一行的所有所述第一存储单元均连接电压输入端，并接收所述输入电压信号；
同一列的所有所述第一存储单元均连接电流输出端。
可选地，所述实现卷积运算的电路还包括参考阵列，所述参考阵列的输入端连接所述数模转换模块的输出端以接收所述电压信号，其输出端连接所述调整模块的输入端，所述调整模块的输出端连接所述符号列处理模块；
所述调整模块通过所述参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号。
可选地，所述参考阵列包括呈一列分布的m个第二存储单元，所述m为正整数，每个所述第二存储单元与其同行的所述第一存储单元连接。
可选地，所述调整模块包括电流减法电路、第一电流转电压单元和第一模数转换单元；
所述电流减法电路的输入端连接所述存储器阵列的电流输出端和所述参考阵列的电流输出端，其用于对所述存储器阵列的每一列输出的第一电流信号与所述参考电流信号分别执行减运算，以输出若干第二电流信号；
所述第一电流转电压单元的输入端连接所述电流减法电路的输出端，以将所述第二电流信号转换为第一电压信号；
所述第一模数转换单元的输入端连接所述第一电流转电压单元的输出端，以对所述第一电压信号进行模数信号转换以输出所述第一输出信号。其有益效果在于，由于存储器阵列每一列输出的第一电流信号等于当前列存储单元的电压和电导率的乘加结果，第一电流信号影响第一输出信号，而第一输出信号影响卷积运算的最终输出值，因此存储器阵列产生的漏电流会影响卷积运算的最终输出值，所述漏电流为存储器阵列中高阻存储单元产生的电流；通过所述电流减法电路对所述存储器阵列的每一列输出的第一电流信号与所述参考电流信号分别执行减运算以输出若干第二电流信号，减小存储器阵列中漏电流，减弱漏电流对第一输出信号的影响，以避免存储器阵列中产 生的漏电流对卷积运算结果的影响，提高了卷积运算的准确性。
可选地，所述调整模块包括第二电流转电压单元、第三电流转电压单元、第二模数转换单元、第三模数转换单元和数字域减法器；
所述第二电流转电压单元的输入端连接所述存储器阵列的电流输出端，其输出端连接所述第二模数转换单元的输入端，以用于将所述第一电流信号转换为第二电压信号，所述第二模数转换单元于将所述第二电压信号转换为第一数字信号；
所述第三电流转电压单元的输入端连接所述参考阵列的电流输出端，其输出端连接所述第三模数转换单元的输入端，以用于将所述参考电流信号转换为第三电压信号，所述第三模数转换单元用于将所述第三电压信号转换为第二数字信号；
所述第二模数转换单元的输出端连接所述数字域减法器的第一输入端，所述第三模数转换单元的输出端连接所述数字域减法器的第二输入端，所述数字域减法器用于对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。其有益效果在于，通过所述第二电流转电压单元和第三电流转电压单元分别将所述第一电流信号和参考电流信号转换为第二电压信号和第三电压信号，通过第二模数转换单元和第三模数转换单元分别将所述第二电压信号和第三电压信号转换为第一数字信号和第二数字信号；通过所述数字域减法器对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。
本发明还提供一种实现卷积运算的方法，包括步骤：
依据量化后的权重信号的范围获取符号位，对所述量化后的权重信号进行编码以得到权重编码；
通过存储器阵列映射所述权重编码；
将输入数字信号转换为电压信号以作为所述存储器阵列的输入电压信号，使所述存储器阵列的每一列均输出第一电流信号；
依据所述第一电流信号获取第一输出信号；
依据所述符号位获取符号列，所述符号列为所述存储器阵列中符号位所在的列，并依据所述符号列和所述第一输出信号输出符号列输出值；
依据所述符号列输出值和第一输出信号获取卷积输出值。
本发明的所述的实现卷积运算的方法有益效果在于：
通过存储器阵列映射正整数权重和负整数权重，节省存储器的数量，提高卷积运算效率和准确性。
可选地，依据所述第一电流信号获取第一输出信号的步骤包括：
设置参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号。
可选地，设置参考电流信号对所述第一电流信号进行调整以获取第一输出信号的步骤包括：
对所述存储器阵列的每一列输出的第一电流信号与所述参考电流信号分别执行减运算，以得到若干第二电流信号；
将所述第二电流信号转换为第一电压信号；
对所述第一电压信号进行模数信号转换以输出所述第一输出信号。其有益效果在于，减弱了漏电流对卷积运算结果的影响，提高了卷积运算的准确性。
可选地，设置参考电流信号对所述第一电流信号进行调整以获取第一输出信号的步骤包括：
将所述第一电流信号转换为第二电压信号，将所述第二电压信号转换为第一数字信号；
将所述参考电流信号转换为第三电压信号，将所述第三电压信号转换为第二数字信号；
对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。
附图说明
图1为本发明实施例的实现卷积运算的电路的结构框图；
图2为本发明实施例的实现卷积运算的电路的电路图；
图3为本发明实施例的卷积运算示意图；
图4为本发明实施例的第一种实施方式中调整模块的结构示意图；
图5为本发明实施例的电流减法电路结构示意图；
图6为本发明实施例的第二种实施方式中调整模块的结构示意图；
图7为本发明实施例的实现卷积运算的方法的流程图；
图8为本发明实施例的第一种实施方式中获取第一输出信号的流程图；
图9为本发明实施例的第二种实施方式中获取第一输出信号的流程图。
发明内容
为使本发明实施例的目的、技术方案和优点更加清楚，下面将对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。
本发明实施例提供了一种实现卷积运算的电路，图1为本发明实施例的实现卷积运算的电路的结构框图。
参照图1，本发明的所述实现卷积运算的电路，包括编码模块1、数模转换模块5、存储器阵列2、调整模块4、符号列处理模块6和计算模块7，本实施例中，所述电路还包括参考阵列3。
编码模块1用于依据量化后的权重信号的范围获取符号位，并对所述量化后的权重信号进行编码以得到权重编码；
数模转换模块5用于将外部输入的数字信号转换为电压信号，并将所述电压信号传输至存储器阵列2，以作为存储器阵列2的输入电压信号；
存储器阵列2用于映射所述权重编码，并在接收所述输入电压信号后，存储器阵列2的每一列均输出第一电流信号；
调整模块4用于依据所述第一电流信号获取第一输出信号；
符号列处理模块6用于依据所述符号位和所述第一输出信号获取符号列，所述符号列为存储器阵列2中符号位所对应的列，并依据所述符号列和所述第一输出信号输出符号列输出值；
计算模块7用于依据所述符号列输出值和第一输出信号获取卷积输出值。
图2为本发明实施例的实现卷积运算的电路的电路图。
在一些实施例中，参照图1和图2，所述编码模块1用于依据所述对量化后的权重信号的范围获取符号位，对量化后的权重信号进行编码以得到权重编码的步骤包括：
首先，将量化后的整数权重(weight)经过编码表示为：
Figure PCTCN2022102952-appb-000001
其中：W为量化后的weight，k为RRAM的阻态个数，w i∈[0,k-1]，将W i映射为相应的电阻值，通过RRAM表示weight，n表示映射一个weight所需的RRAM的个数，m个weight通过m行n列的RRAM表示，所述m为正整数；依据i的值来确定u(i)的值，u(i)的计算公式为：
Figure PCTCN2022102952-appb-000002
else表示i的取值为除i＝j以外的整数，j为指定的符号位，根据权重信号的范围以决定符号位的位置。
然后，根据量化后的权重信号的范围获取符号位，以8bit量化、RRAM阻态个数为2、8个RRAM来映射一个weight为例：
首先，计算量化后的weight的范围和无符号8bit范围之间的偏移量，例如：W∈[-127，128]，其与[0，255]之间的偏移量为边界相减的值，即0-(-127)＝127。
然后，计算不小于该偏移量的以阻态个数为底的最小幂，其对应的指数 值为符号位，如127＝2 7-1＝2 8-129，2 7为最接近127且不小于127的数，其对应的指数值为7，故符号位j＝7。
根据上述编码方式，具体值可以表示为：
-127＝(-1) 0×1×2 0+(-1) 0×0×2 1+(-1) 0×0×2 2+(-1) 0×0×2 3+(-1) 0×0×2 4+(-1) 0×0×2 5+(-1) 0×0×2 6+(-1) 1×1×2 7；其中，-1的指数为1，对应相乘的2的指数等于符号位的值；-1的指数为0，对应相乘的2的指数等于非符号位的值。
40＝(-1) 0×0×2 0+(-1) 0×0×2 1+(-1) 0×0×2 2+(-1) 0×1×2 3+(-1) 0×0×2 4+(-1) 0×1×2 5+(-1) 0×0×2 6+(-1) 1×0×2 7；同上，其符号位j＝7。
同理，若W∈[-6，249]，可以算出符号位j＝3，40可以表示为：
40＝(-1) 0×0×2 0+(-1) 0×0×2 1+(-1) 0×0×2 2+(-1) 1×1×2 3+(-1) 0×1×2 4+(-1) 0×1×2 5+(-1) 0×0×2 6+(-1) 0×0×2 7。
参照图2，存储器阵列2包括若干卷积核映射单元20，每个所述卷积核映射单元20映射一个所述权重编码，每个卷积核映射单元20中包括一个所述符号列201和若干非符号列，所述符号列201和若干非符号列分别输出所述第一电流信号，其中，非符号列为所述卷积核映射单元20中除所述符号列201以外的列。
所述符号列201和所述非符号列均包括m个第一存储单元202，所述m为正整数；
同一行的所有所述第一存储单元202均连接电压输入端，并接收所述输入电压信号；
同一列的所有所述第一存储单元202均连接电流输出端。
在一些实施例中，所述第一存储单元202为RRAM，RRAM的阻态不局限于高阻、低阻两种阻态，还可以是多阻态的RRAM。例如，二值RRAM只有高阻和低阻两种状态，可以表示0和1，此时RRAM的阻态个数为2。
多值RRAM除了高阻状态和低阻状态，还有中间状态，例如一个多值RRAM的阻值分别为6000Ω、600Ω、300Ω、200Ω，可分别依次表示0、1、 2、3，该多值RRAM的阻态个数为4。
在一些实施例中，RRAM的电导率与输入电压和输出电流的关系如下：
Figure PCTCN2022102952-appb-000003
Figure PCTCN2022102952-appb-000004
其中，R为RRAM的电阻值，G为RRAM的电导率，I为RRAM的输出电流，U为RRAM的输入电压；
由上述公式可知，经过存储器阵列2的转换后，每一列RRAM的最终输出电流值即为所述第一电流信号，每一个所述卷积核映射单元20的最终输出电流值等于所有列RRAM的输入电压与当前列RRAM的电导率的乘加结果；RRAM的输入电压对应输入数字信号，第一电流信号经过模数转换器转化后对应卷积输出值，可以通过不同电导率的RRAM阵列来映射不同的正整数权重和负整数权重。
在本申请中，还设置编码规则，所述编码规则为：所述符号列中的所有RRAM映射的范围大于权重信号的范围，使较少的RRAM组成的阵列即可映射一个权重信号，即一个权重信号可以用较少的RRAM来表示，节省RRAM的数量和芯片面积，节省功耗。
图3为本发明实施例中卷积运算示意图，图中的Input为卷积输入的数字信号，weight为权重信号，output为卷积输出的数字信号。
在一些实施例中，参照图2和图3，卷积的weight为1和-2，j＝2，k为2，对1进行编码：1＝(-4)×0+2×0+1×1，对-2进行编码：-2＝(-4)×1+2×1+1×0；
将上述权重weight映射到RRAM阵列中，此时m为2，n为3，通过存储器阵列2映射上述权重，存储器阵列2包括若干列RRAM，RRAM包括高阻RRAM和低阻RRAM；设置低阻RRAM的电导率为1，通过低阻RRAM映射数字1；设置高阻RRAM的电导率为0.1，通过高阻RRAM映射数字0。
卷积输入数字信号Input为1和2，通过数模转换模块5，将1转换为电压信号并输出至第一行的所述第一存储单元202，以作为第一行的第一存储 单元202的输入电压；通过数模转换模块5，将2转换为电压信号并输出至第二行的第一存储单元202，以作为第二行的第一存储单元202的输入电压。
在一些实施例中，本发明的数模转换模块5为数模转换器(Digital to Analog Converter，DAC)，通过DAC将外部输入的数字信号转换为电压信号，以作为存储器阵列2的输入。
参照图1和图2，参考阵列3的输入端连接数模转换模块5的输出端以接收所述电压信号，其输出端连接调整模块4的第一输入端，调整模块4的第二输入端连接存储器阵列的输出端，其输出端连接所述符号列处理模块。
调整模块4通过所述参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号。
参考阵列3包括呈一列分布的m个第二存储单元30，所述第一存储单元202的行数与所述第二存储单元30的行数相同，均为m行。所述m为正整数，每个所述第二存储单元30与其同行的所述第一存储单元202连接。
在一些实施例中，所述第二存储单元30为RRAM，具体地，第二存储单元30为高阻RRAM，其电导率为0.1。
现有RRAM技术不能将高阻RRAM输出的电流降低为0，通过上述的参考阵列3的高阻RRAM产生参考电流，从而减小存储器阵列1输出的漏电流，减弱漏电流对卷积输出结果的影响，提高映射的权重信号的准确性。
图4为本发明实施例的第一种实施方式中调整模块的结构示意图，图5为本发明实施例的电流减法电路40结构示意图；图4和图5中的I为第二电流信号，I singal为存储器阵列2输出的每列第一存储器单元输出的第一电流信号，I ref为参考阵列3输出的参考电流信号。
参照图4，调整模块4包括电流减法电路40、第一电流转电压单元41和第一模数转换单元42。
所述电流减法电路40的输入端连接存储器阵列2的电流输出端和参考阵列3的电流输出端，以用于对存储器阵列2的每一列输出的第一电流信号与参考阵列3输出的所述参考电流信号分别执行减运算，以输出若干第二电 流信号。
所述第一电流转电压单元41的输入端连接所述电流减法电路40的输出端，以用于将所述第二电流信号转换为第一电压信号。
所述第一模数转换单元42的输入端连接所述第一电流转电压单元41的输出端，以用于对所述第一电压信号进行模数信号转换以输出所述第一输出信号。卷积输入数字信号经过转化后变成电压信号，并作为存储器阵列2的电压输入，存储器阵列2的每一列输出的第一电流信号等于当前列的存储单元的电压和电导率的乘加结果，第一电流信号影响第一输出信号，第一输出信号影响卷积运算的最终输出值，存储器阵列2产生的漏电流会影响卷积运算的最终输出值，所述漏电流为存储器阵列中高阻存储单元产生的电流；通过所述电流减法电路40，对存储器阵列2的每一列输出的第一电流信号与所述参考电流信号分别执行减运算，以输出若干第二电流信号，由此减弱漏电流对第一输出信号的影响，提高卷积运算的准确性。
参照图5，所述电流减法电路40包括电流镜，所述电流镜包括调整电流输出端、第一NMOS管411和第二NMOS管412，所述第一NMOS管411的漏极连接存储器阵列2的电流输出端以接收所述第一电流信号，所述第一NMOS管411的漏极与存储器阵列2的电流输出端之间的节点连接所述调整电流输出端，所述第一NMOS管411的漏极与存储器阵列2的电流输出端之间还设置电流镜输出端以输出所述第二电流信号，所述第一NMOS管411的栅极连接所述第二NMOS管412的栅极，所述第一NMOS管411的源极连接所述第二NMOS管412的源极。
所述第二NMOS管412的漏极连接参考阵列3的电流输出端以接收所述参考电流信号，所述第二NMOS管412的漏极与栅极短接。
控制所述第一NMOS管411工作在饱和区，以使所述调整电流输出端输出所述第二电流信号。
在一些实施例中，参照图5，第一NMOS管411的漏极接收存储器阵列2中的每一列输出的第一电流信号I singal，第二NMOS管412的漏极接收参考 阵列3输出的参考电流信号I ref，所述调整电流输出端输出的第二电流信号I的计算公式如下：
I＝I singal-I ref
其中，I为第二电流信号，I singal为存储器阵列2输出的每列第一存储器单元输出的第一电流信号，I ref为参考阵列3输出的参考电流信号。
图6为本发明实施例的第二种实施方式中调整模块的结构示意；图中，I singal为存储器阵列2输出的每列第一存储器单元输出的第一电流信号，I ref为参考阵列3输出的参考电流信号。
参照图6，所述调整模块包括第二电流转电压单元43、第三电流转电压单元44、第二模数转换单元45、第三模数转换单元46和数字域减法器47；
所述第二电流转电压单元43的输入端连接存储器阵列2的电流输出端，所述第二电流转电压单元43的输出端连接所述第二模数转换单元45的输入端，所述第二模数转换单元45的输出端连接所述数字域减法器47的第一输入端；
所述第三电流转电压单元44的输入端连接参考阵列3的电流输出端，所述第三电流转电压单元44的输出端连接所述第三模数转换单元46的输入端，所述第三模数转换单元46的输出端连接所述数字域减法器47的第二输入端。
参照图6，所述第二电流转电压单元43用于将所述第一电流信号转换为第二电压信号，所述第二模数转换单元45于将所述第二电压信号转换为第一数字信号。
所述第三电流转电压单元44用于将所述参考电流信号转换为第三电压信号，所述第三模数转换单元46用于将所述第三电压信号转换为第二数字信号。
所述数字域减法器47用于对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。通过所述第二电流转电压单元43和第三电流转电压单元44分别将所述第一电流信号和参考电流信号转换为第二 电压信号和第三电压信号，通过第二模数转换单元45和第三模数转换单元46分别将所述第二电压信号和第三电压信号转换为第一数字信号和第二数字信号；通过所述数字域减法器47对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号，去除存储器阵列2中漏电流，提高卷积运算的准确性。
需说明的是，本发明提供了所述调整模块的两种实施方式，在实际操作中，若不考虑电路性能，可选择两种调整模块中的任意一个电路；
或，可以根据电路的能耗、面积等需求进行折中选择调整模块，以提高本发明的所述实现卷积运算的电路的性能。
在一些实施例中，参照图4和图6，所述第一电流转电压单元41、第二电流转电压单元43、第三电流转电压单元44可以采用电流转电压电路，具体地，通过控制电流以对电容进行充放电，以将电流转化为电容两端的电压，达到将电流信号转换为电压信号的目的，转换的计算公式如下：
Figure PCTCN2022102952-appb-000005
其中，I为要转换的电流，T为给电容器件充电的时间，C为电容值。
在一些实施例中，参照图4和图6，所述第一模数转换单元42、所述第二模数转换单元45和第三模数转换单元46均为模数转换器(Analog to Digital Converter，ADC)，用于将电压信号转换为数字信号。
参照图2，符号列处理模块6与所述符号列201的输出端连接，用于对所述符号列201输出的第一输出信号进行取相反数运算，以输出所述符号列201输出值，符号列处理模块6还与第一加法器相连。通过符号列处理模块6获取符号列201后，对所述符号列201输出的第一输出信号进行取相反数运算，以输出所述符号列201输出值，使得存储器阵列2既可以映射正整数权重，也可以映射负整数权重，节省存储器的数量。
在一些实施例中，对所述符号列201输出的第一输出信号进行取相反数运算以输出所述符号列201输出值的步骤包括：
计算机中常以补码的形式表示其数值，对第一输出信号进行取相反数运算相当于在对第一输出信号乘以-1；通过二进制逻辑运算电路实现对符号列201对应的第一输出信号进行取相反数运算时，相当于计算符号列201对应的第一输出信号相反数的补码，即在所述符号列201对应的第一输出信号的补码的基础上取反码再加1即可。
在一些实施例中，符号列处理模块6包括数字域的verilog语言生成电路，用以实现对所述符号列201输出的第一输出信号进行取相反数运算以输出所述符号列201输出值。
在一些实施例中，参照图2，计算模块7包括若干第一加法器71和第二加法器72，每个所述卷积核映射单元20对应一个所述第一加法器71；所述第一加法器71与符号列处理模块6的输出端连接，用于对每个所述卷积核映射单元20对应的所述符号列201输出值和所述第一输出信号执行加权求和运算以得到加权值。
所述第二加法器72连接所有所述第一加法器71，用于对所有所述第一加法器71输出的加权值进行求和运算以得到所述卷积输出值。其优点为，通过计算模块7对每个所述卷积核映射单元20对应的所述符号列201输出值和所述第一输出信号执行加权求和运算以得到加权值，对所有所述第一加法器71输出的加权值进行求和运算以得到所述卷积输出值，实现卷积运算的电路的完整的卷积计算。
参照图2，计算模块7还可以包括一个总加法器(图中未示出)，所述总加法器连接所有的符号列处理模块6的输出端连接，用于接收所有的所述符号列201输出值和所述第一输出信号执行加权求和，一个总加法器来进行加权求和计算可能会增加计算计算模块7的压力延长计算时间，但可以节约芯片面积和成本。可以根据实际的需要设置一个或多个加法器来计算最后的卷积输出值。
图7为本发明实施例的实现卷积运算的方法的流程图。
参照图7，本发明还提供一种实现卷积运算的方法，包括步骤：
S1：依据量化后的权重信号的范围获取符号位，对所述量化后的权重信号进行编码以得到权重编码；
S2：通过存储器阵列映射所述权重编码；
S3：将输入数字信号转换为电压信号以作为所述存储器阵列的输入电压信号，使所述存储器阵列的每一列均输出第一电流信号；
S4：依据所述第一电流信号获取第一输出信号；
S5：依据所述符号位获取符号列，所述符号列为所述存储器阵列中符号位所在的列，并依据所述符号列和所述第一输出信号输出符号列输出值；
S6：依据所述符号列输出值和第一输出信号获取卷积输出值。
所述步骤S2中，所述存储器阵列包括t个卷积核映射单元，所述每个卷积核映射单元均使用n个阻变式存储单元来映射一个weight，所述t和所述n均为正整数。
所述阻变式存储单元包括高阻RRAM和低阻RRAM，所述高阻RRAM的电导率小于所述低阻RRAM的电导率，所述高阻RRAM用于映射数字0，所述低阻RRAM用于映射数字1。
在一些实施例中，所述步骤S2的步骤包括：
参照图2和图3，卷积的weight为1和-2，将1表示为1＝(-4)×0+2×0+1×1，将-2表示为-2＝(-4)×1+2×1+1×0，此时符号位j＝2；
所述步骤S3的步骤包括：
经过所述存储器阵列的转换后，每一列RRAM的最终输出电流值等于当前列RRAM的输入电压与当前列RRAM的电导率的乘加结果，因此每一列RRAM的最终输出电流值即为所述第一电流信号。
所述步骤S4中，依据所述第一电流信号获取第一输出信号的步骤包括：设置参考电流信号对所述第一电流信号进行调整以获取第一输出信号，参照图8，图8为本发明实施例的第一种实施方式中获取第一输出信号的流程图， 具体包括：
S401：对所述存储器阵列的每一列输出的第一电流信号与所述参考电流信号分别执行减运算，以得到若干第二电流信号；
S402：将所述第二电流信号转换为第一电压信号；
S403：对所述第一电压信号进行模数信号转换以输出所述第一输出信号。
在一些实施例中，参照图9，图9为本发明实施例的第二种实施方式中获取第一输出信号的流程图，具体包括：
S411：将所述第一电流信号转换为第二电压信号，将所述第二电压信号转换为第一数字信号；
S412：将所述参考电流信号转换为第三电压信号，将所述第三电压信号转换为第二数字信号；
S413：对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。
作为本发明一种可选的实施方式，所述步骤S5中，依据所述符号列和所述第一输出信号输出符号列输出值的步骤包括：
对所述符号列输出的第一输出信号进行取相反数运算以输出所述符号列输出值。
所述步骤S6中，依据所述符号列输出值和第一输出信号获取卷积输出值的步骤包括：
对所述符号列输出值和所述第一输出信号执行加权求和运算以得到加权值，对所有所述加权值进行求和运算以得到所述卷积输出值。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。

Claims (12)

  1. 一种实现卷积运算的电路，其特征在于，包括编码模块、数模转换模块、存储器阵列、调整模块、符号列处理模块和计算模块；
    所述编码模块用于依据量化后的权重信号的范围获取符号位，并对所述量化后的权重信号进行编码以得到权重编码；
    所述数模转换模块用于将外部输入的数字信号转换为电压信号，并将所述电压信号传输至所述存储器阵列，以作为所述存储器阵列的输入；
    所述存储器阵列用于映射所述权重编码，并在接收所述电压信号后，所述存储器阵列的每一列均输出第一电流信号；
    所述调整模块用于依据所述第一电流信号获取第一输出信号；
    所述符号列处理模块用于依据所述符号位获取符号列，所述符号列为所述存储器阵列中符号位所在的列，并依据所述符号列和所述第一输出信号输出符号列输出值；
    所述计算模块用于依据所述符号列输出值和第一输出信号获取卷积输出值。
  2. 如权利要求1所述的实现卷积运算的电路，其特征在于，所述存储器阵列包括若干卷积核映射单元，每个所述卷积核映射单元映射一个所述权重编码，每个卷积核映射单元中包括一个所述符号列和若干非符号列，所述符号列和若干非符号列分别输出所述第一电流信号。
  3. 如权利要求2所述的实现卷积运算的电路，其特征在于，所述符号列处理模块与所述符号列的输出端连接，用于对所述符号列输出的第一输出信号进行取相反数运算以输出所述符号列输出值。
  4. 如权利要求2所述的实现卷积运算的电路，其特征在于，所述符号列 和所述非符号列均包括m个第一存储单元，所述m为正整数；
    同一行的所有所述第一存储单元均连接电压输入端，并接收所述输入电压信号；
    同一列的所有所述第一存储单元均连接电流输出端。
  5. 如权利要求4所述的实现卷积运算的电路，其特征在于，还包括参考阵列，所述参考阵列的输入端连接所述数模转换模块的输出端以接收所述电压信号，其输出端连接所述调整模块的输入端，所述调整模块的输出端连接所述符号列处理模块；
    所述调整模块通过所述参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号。
  6. 如权利要求5所述的实现卷积运算的电路，其特征在于，所述参考阵列包括呈一列分布的m个第二存储单元，所述m为正整数，每个所述第二存储单元与其同行的所述第一存储单元连接。
  7. 如权利要求4所述的实现卷积运算的电路，其特征在于，所述调整模块包括电流减法电路、第一电流转电压单元和第一模数转换单元；
    所述电流减法电路的输入端连接所述存储器阵列的电流输出端和所述参考阵列的电流输出端，其用于对所述存储器阵列的每一列输出的第一电流信号与所述参考电流信号分别执行减运算，以输出若干第二电流信号；
    所述第一电流转电压单元的输入端连接所述电流减法电路的输出端，以将所述第二电流信号转换为第一电压信号；
    所述第一模数转换单元的输入端连接所述第一电流转电压单元的输出端，以对所述第一电压信号进行模数信号转换以输出所述第一输出信号。
  8. 如权利要求4所述的实现卷积运算的电路，其特征在于，所述调整模块包括第二电流转电压单元、第三电流转电压单元、第二模数转换单元、第 三模数转换单元和数字域减法器；
    所述第二电流转电压单元的输入端连接所述存储器阵列的电流输出端，其输出端连接所述第二模数转换单元的输入端，以用于将所述第一电流信号转换为第二电压信号，所述第二模数转换单元于将所述第二电压信号转换为第一数字信号；
    所述第三电流转电压单元的输入端连接所述参考阵列的电流输出端，其输出端连接所述第三模数转换单元的输入端，以用于将所述参考电流信号转换为第三电压信号，所述第三模数转换单元用于将所述第三电压信号转换为第二数字信号；
    所述第二模数转换单元的输出端连接所述数字域减法器的第一输入端，所述第三模数转换单元的输出端连接所述数字域减法器的第二输入端，所述数字域减法器用于对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。
  9. 一种实现卷积运算的方法，其特征在于，包括步骤：
    依据量化后的权重信号的范围获取符号位，对所述量化后的权重信号进行编码以得到权重编码；
    通过存储器阵列映射所述权重编码；
    将输入数字信号转换为电压信号以作为所述存储器阵列的输入电压信号，使所述存储器阵列的每一列均输出第一电流信号；
    依据所述第一电流信号获取第一输出信号；
    依据所述符号位获取符号列，所述符号列为所述存储器阵列中符号位所在的列，并依据所述符号列和所述第一输出信号输出符号列输出值；
    依据所述符号列输出值和第一输出信号获取卷积输出值。
  10. 如权利要求9所述的实现卷积运算的方法，其特征在于，依据所述第一电流信号获取第一输出信号的步骤包括：
    设置参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号。
  11. 如权利要求10所述的实现卷积运算的方法，其特征在于，设置参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号的步骤包括：
    对所述存储器阵列的每一列输出的第一电流信号与所述参考电流信号分别执行减运算，以得到若干第二电流信号；
    将所述第二电流信号转换为第一电压信号；
    对所述第一电压信号进行模数信号转换以输出所述第一输出信号。
  12. 如权利要求10所述的实现卷积运算的方法，其特征在于，设置参考电流信号对所述第一电流信号进行调整以获取所述第一输出信号的步骤包括：
    将所述第一电流信号转换为第二电压信号，将所述第二电压信号转换为第一数字信号；
    将所述参考电流信号转换为第三电压信号，将所述第三电压信号转换为第二数字信号；
    对所述第一数字信号和所述第二数字信号执行减运算以输出所述第一输出信号。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109460817A (zh) * 2018-09-11 2019-03-12 华中科技大学 一种基于非易失存储器的卷积神经网络片上学习系统
US20200160158A1 (en) * 2017-04-14 2020-05-21 Semiconductor Energy Laboratory Co., Ltd. Neural Network Circuit
CN112686373A (zh) * 2020-12-31 2021-04-20 上海交通大学 一种基于忆阻器的在线训练强化学习方法
CN112686364A (zh) * 2019-10-18 2021-04-20 华为技术有限公司 一种神经网络计算芯片及计算方法
CN113222131A (zh) * 2021-04-30 2021-08-06 中国科学技术大学 基于1t1r的可实现带符号权重系数的突触阵列电路
CN114330694A (zh) * 2021-12-31 2022-04-12 上海集成电路装备材料产业创新中心有限公司 实现卷积运算的电路及其方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200160158A1 (en) * 2017-04-14 2020-05-21 Semiconductor Energy Laboratory Co., Ltd. Neural Network Circuit
CN109460817A (zh) * 2018-09-11 2019-03-12 华中科技大学 一种基于非易失存储器的卷积神经网络片上学习系统
CN112686364A (zh) * 2019-10-18 2021-04-20 华为技术有限公司 一种神经网络计算芯片及计算方法
CN112686373A (zh) * 2020-12-31 2021-04-20 上海交通大学 一种基于忆阻器的在线训练强化学习方法
CN113222131A (zh) * 2021-04-30 2021-08-06 中国科学技术大学 基于1t1r的可实现带符号权重系数的突触阵列电路
CN114330694A (zh) * 2021-12-31 2022-04-12 上海集成电路装备材料产业创新中心有限公司 实现卷积运算的电路及其方法

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