WO2023123829A1 - Pompe de charge - Google Patents

Pompe de charge Download PDF

Info

Publication number
WO2023123829A1
WO2023123829A1 PCT/CN2022/094190 CN2022094190W WO2023123829A1 WO 2023123829 A1 WO2023123829 A1 WO 2023123829A1 CN 2022094190 W CN2022094190 W CN 2022094190W WO 2023123829 A1 WO2023123829 A1 WO 2023123829A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
gate
module
charge pump
voltage
Prior art date
Application number
PCT/CN2022/094190
Other languages
English (en)
Chinese (zh)
Inventor
吴劲
胡建国
段志奎
王德明
丁颜玉
邓俊杰
秦军瑞
Original Assignee
广东曜芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广东曜芯科技有限公司 filed Critical 广东曜芯科技有限公司
Publication of WO2023123829A1 publication Critical patent/WO2023123829A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Definitions

  • the invention relates to the technical field of circuits, in particular to a charge pump.
  • the power supply voltage of the chip is mostly concentrated within 10 volts (V), and with the development trend of low power consumption of the chip, the power supply voltage of the chip is still decreasing; but for some special occasions, and A power signal higher than the power supply voltage is required.
  • V volts
  • a power signal higher than the power supply voltage is required.
  • a high-voltage pulse signal must be required to realize the erase operation of the storage circuit. If a high-voltage pulse signal is designed for the storage circuit alone The power supply will waste chip resources in vain.
  • the charge pump is a circuit that can provide such a high-voltage signal. It repeatedly charges and discharges the capacitor through two clock signals with opposite phases, so that the charge is continuously accumulated on the capacitor to achieve the purpose of boosting the voltage.
  • the output voltage of the charge pump will vary with the load. If the load power consumption is too large, the output voltage of the charge pump will be too low to meet the requirements for erasing and writing of the storage circuit; on the contrary, If the power consumption of the load is too low, the output voltage of the charge pump will increase uncontrollably until the switch tube is cut off due to the body effect, and then stop the boost. In this way, the excessive gate voltage will greatly reduce the switching voltage. tube life.
  • a comparator circuit is usually added at the output end of the charge pump to form a negative feedback loop to limit the rise of the output voltage of the charge pump.
  • the comparator circuit has deviations such as process angle, mismatch, or temperature, the output voltage of the charge pump will be clamped at a very low voltage, and the output voltage of the charge pump module will be too low. Module doesn't work properly.
  • the present invention provides a charge pump.
  • the present invention provides a charge pump, including a charge pump module, a clock level conversion module, a comparison module, a high voltage configuration module and a clock control module; the clock control module is connected with the clock level conversion module, the comparison module and the The charge pump module is connected, and the comparison module is also connected to the charge pump module and the high voltage configuration module;
  • the clock level conversion module is configured to convert the digital clock signal into a first level signal and send it to the clock control module; the first level signal is the clock signal required by the charge pump;
  • the high-voltage configuration module is configured to configure the target voltage of the input terminal of the comparison module
  • the comparison module is configured to compare the divided voltage of the output voltage of the charge pump module with the target voltage, and send the second level signal obtained by the comparison to the clock control module;
  • the clock control module is used to control whether to provide two reverse clock signals for the charge pump module according to the first level signal and the second level signal.
  • the first input end of the high voltage configuration module is connected to the reference voltage
  • the second input end of the high voltage configuration module is connected to the first power supply voltage
  • the third input end of the high voltage configuration module The input end is connected to the processor, the output end of the high voltage configuration module is connected to the first input end of the comparison module;
  • the reference voltage is a voltage signal output by the reference voltage circuit;
  • the processor is configured to send a first high voltage configuration signal to the high voltage configuration module when it is determined that the output voltage of the charge pump module is greater than or equal to a preset voltage;
  • the high-voltage configuration module is specifically configured to, when receiving the first high-voltage configuration signal, determine the reference voltage as the target voltage of the first input terminal of the comparison module.
  • the processor is further configured to send a second high voltage configuration signal to the high voltage configuration module when it is determined that the output voltage of the charge pump module is lower than the preset voltage;
  • the high-voltage configuration module is further specifically configured to determine the first power supply voltage as the target voltage of the first input terminal of the comparison module when receiving the second high-voltage configuration signal.
  • the clock control module includes a first switch circuit and an inverse clock generation circuit
  • the first input terminal of the first switch circuit is connected to the output terminal of the clock level conversion module, the second input terminal of the first switch circuit is connected to the output terminal of the comparison module, and the first switch circuit The output terminal of the circuit is connected with the first input terminal of the reverse clock generating circuit;
  • the second input end of the reverse clock generation circuit is connected to the processor, and the output end of the reverse clock generation circuit is connected to the charge pump module;
  • the first switch circuit is configured to send a control signal determined according to the first level signal and the second level signal to the reverse clock generation circuit;
  • the reverse clock generation circuit is configured to control two reverse clock signals of the charge pump module based on the control signal and the enable signal sent by the processor.
  • the charge pump module includes a charge pump circuit and a voltage divider circuit, the input end of the charge pump circuit is connected to the output end of the reverse clock generation circuit, and the charge pump circuit The output end of the voltage divider circuit is connected to the input end of the voltage divider circuit, and the output end of the voltage divider circuit is connected to the second input end of the comparison module;
  • the voltage divider circuit is used to divide the output voltage of the charge pump circuit and send it to the comparison module.
  • the high-voltage configuration module includes a transmission gate T1, a transmission gate T2, and an inverting gate F1;
  • the input terminal of the transmission gate T1 is connected to the reference voltage, the first control terminal of the transmission gate T1 is connected to the processor through the NOT gate F1, and the second control terminal of the transmission gate T1 is connected to the the processor connection;
  • the input terminal of the transmission gate T2 is connected to the first power supply voltage
  • the first control terminal of the transmission gate T2 is connected to the processor
  • the second control terminal of the transmission gate T2 is connected with the The processor is connected, and the output terminal of the transmission gate T2 and the output terminal of the transmission gate T1 are both connected to the first input terminal of the comparison module.
  • the first switch circuit includes an AND gate Y1;
  • the first input end of the AND gate Y1 is connected to the output end of the clock level conversion module, the second input end of the AND gate Y1 is connected to the output end of the comparison module, and the output end of the AND gate Y1 The end is connected with the first input end of the reverse clock generating circuit.
  • the reverse clock generation circuit includes a second switch circuit, a first reverse clock generation circuit and a second reverse clock generation circuit;
  • the first input end of the second switch circuit is connected to the output end of the AND gate Y1
  • the second input end of the second switch circuit is connected to the processor
  • the output ends of the second switch circuit are respectively It is connected with the input end of the first reverse clock generation circuit and the input end of the second reverse clock generation circuit
  • the output end of the first reverse clock generation circuit is connected with the second reverse clock generation circuit.
  • the output terminals of the clock generating circuit are connected with the input terminals of the charge pump module.
  • the second switch circuit includes a NAND gate YF1
  • the first reverse clock generation circuit includes a transmission gate T3, a first NOR gate HF1 and a first drive circuit, so
  • the second reverse clock generation circuit includes a NOT gate F2, a NOR gate HF2 and a second drive circuit;
  • the input terminal of the transmission gate T3 is connected to the output terminal of the NAND gate YF1, the first control terminal of the transmission gate T3 is connected to the first power supply voltage, and the second control terminal of the transmission gate T3 is grounded, so
  • the output end of the transmission gate T3 is connected with the first input end of the first NOR gate HF1, the second input end of the first NOR gate HF1 is connected with the output end of the NOR gate HF2, and the first NOR gate HF1 is connected with the output end of the NOR gate HF2.
  • the output end of the NOR gate HF1 is connected to the input end of the first driving circuit;
  • the input end of the NOT gate F2 is connected to the output end of the NAND gate YF1, the output end of the NOT gate F2 is connected to the first input end of the NOR gate HF2, and the first input end of the NOR gate HF2
  • the two input ends are connected with the output end of the first NOR gate HF1
  • the output end of the NOR gate HF2 is connected with the input end of the second drive circuit
  • the output end of the second drive circuit is connected with the output end of the second drive circuit.
  • the output ends of the first drive circuit are all connected to the charge pump circuit.
  • the charge pump circuit includes a plurality of unipolar circuits, and each of the unipolar circuits includes
  • a plurality of unipolar circuits each of which includes an NMOS transistor N1, a PMOS transistor P1, a PMOS transistor P2, and a capacitor C1;
  • the source of the NMOS transistor N1 is used as the first input terminal of the unipolar circuit, the gate of the NMOS transistor N1 is connected to the gate of the PMOS transistor P1, and the gate of the NMOS transistor N1 is used as the first input terminal of the unipolar circuit. the second input terminal of the unipolar circuit;
  • the drain of the NMOS transistor N1 is connected to the source of the PMOS transistor P1, and the drain of the PMOS transistor P1 is used as an output terminal of the unipolar circuit;
  • the gate of the PMOS transistor P2 is connected to the charge release module, the drain of the PMOS transistor P2 is connected to the first power supply voltage, the source of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1, The drain of the NMOS transistor N1 is also connected to the first terminal of the capacitor C1, the first terminal of the capacitor C1 serves as the second clock signal terminal of the unipolar circuit, and the second terminal of the capacitor C1 serves as The first clock signal terminal of the unipolar circuit.
  • the voltage divider circuit includes a capacitor C2, a capacitor C3, a capacitor C4, and a capacitor C5, one end of the capacitor C2 is connected to the output end of the charge pump circuit, and the capacitor C2 is The other end is connected to one end of the capacitor C5 through the capacitor C3 and the capacitor C4 in turn, the other end of the capacitor C5 is grounded, and the connection between the capacitor C4 and the capacitor C5 is used as the output of the voltage divider circuit The end is connected with the second input end of the comparison module.
  • the comparison module includes a comparison circuit and a shaping circuit
  • the first input end of the comparison circuit is connected to the reference voltage
  • the second input end of the comparison circuit is connected to the first power supply voltage
  • the output end of the comparison circuit is connected to the input end of the shaping circuit
  • the shaping circuit The output terminal of the circuit is connected with the second input terminal of the first switching circuit.
  • the comparison circuit includes an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, a PMOS transistor P3, a PMOS transistor P4, and a PMOS transistor P5;
  • the gate of the NMOS transistor N2 is connected to the reference voltage
  • the source of the NMOS transistor N2 is respectively connected to the source of the NMOS transistor N3 and the drain of the NMOS transistor N4, and the drain of the NMOS transistor N2
  • the poles are respectively connected to the source of the PMOS transistor P3, the gate of the PMOS transistor P3 and the gate of the PMOS transistor P4;
  • the gate of the NMOS transistor N3 is connected to the output terminal of the voltage divider circuit, and the drain of the NMOS transistor N3 is respectively connected to the source of the PMOS transistor P4 and the gate of the PMOS transistor P5;
  • the drain of the PMOS transistor P3, the drain of the PMOS transistor P4 and the drain of the PMOS transistor P5 are all connected to the first power supply voltage, and the source of the PMOS transistor P5 is connected to the drain of the NMOS transistor N5 pole connection, and the source of the PMOS transistor P5 is used as the output terminal of the comparison circuit;
  • Both the gate of the NMOS transistor N4 and the gate of the NMOS transistor N5 are connected to the output terminal of the reference voltage circuit, and the source of the NMOS transistor N4 and the source of the NMOS transistor N5 are both grounded.
  • the shaping circuit includes a PMOS transistor P6 and an NMOS transistor N6;
  • the drain of the PMOS transistor P6 is connected to the first power supply voltage, and the gate of the PMOS transistor P6 is respectively connected to the source of the PMOS transistor P5 and the gate of the NMOS transistor N6;
  • the source of the PMOS transistor P6 is connected to the drain of the NMOS transistor N6, and the source of the PMOS transistor P6 is used as the output terminal of the comparison module, and the source of the NMOS transistor N6 is grounded.
  • the clock level conversion module includes a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, an NMOS transistor N7, an NMOS transistor N8, and an NMOS transistor N9;
  • the gate of the PMOS transistor P7 is connected to the digital clock signal, and the drain of the PMOS transistor P7 is respectively connected to the source of the NMOS transistor N7 and the gate of the NMOS transistor N8; Both the drain and the drain of the NMOS transistor N8 are connected to the first power supply voltage, the gate of the NMOS transistor N7 is connected to the source of the NMOS transistor N8, and the source of the NMOS transistor N8 serves as the The output terminal of the clock level conversion module;
  • the drain of the PMOS transistor P8 is connected to the source of the NMOS transistor N8, and the gate of the PMOS transistor P8 is respectively connected to the source of the NMOS transistor N9 and the drain of the PMOS transistor P9;
  • Both the gate of the NMOS transistor N9 and the gate of the PMOS transistor P9 are connected to the gate of the PMOS transistor P7, and the drain of the NMOS transistor N9 is connected to the second power supply voltage;
  • the source of the PMOS transistor P7, the source of the PMOS transistor P8 and the source of the PMOS transistor P9 are all grounded.
  • the target voltage of the input terminal of the comparison module is configured through the high-voltage configuration module, so that the comparison module outputs the second level signal based on the divided voltage of the target voltage and the output voltage of the charge pump module, and passes the clock level
  • the conversion module converts the digital clock signal into the first level signal required by the charge pump, and finally the clock control module determines whether to provide two reverse clock signals for the charge pump module based on the first level signal and the second level signal; That is, if it is determined to provide two-way reverse clock signals for the charge pump module, the charge pump module starts charging; if it is determined not to provide two-way reverse clock signals for the charge pump module, the charge pump module stops charging, thereby realizing the charging
  • the control of the output voltage of the pump module prevents the storage module from not working properly due to the low output voltage of the charge pump module.
  • Fig. 1 is one of circuit principle block diagrams of the charge pump provided by the present invention.
  • Fig. 2 is the circuit principle block diagram two of the charge pump provided by the present invention.
  • Fig. 3 is the third of the circuit principle block diagram of the charge pump provided by the present invention.
  • Fig. 4 is the circuit principle block diagram four of the charge pump provided by the present invention.
  • Fig. 5 is a circuit diagram of a high-voltage configuration module provided by the present invention.
  • Fig. 6 is the circuit diagram of the clock control module provided by the present invention.
  • Fig. 7 is the circuit diagram of the unipolar circuit provided by the present invention.
  • Fig. 8 is a circuit diagram of a charge releasing module provided by the present invention.
  • Fig. 9 is a circuit diagram of a charge pump module provided by the present invention.
  • Fig. 10 is the circuit diagram of the voltage dividing circuit provided by the present invention.
  • Fig. 11 is the circuit diagram of the comparison module provided by the present invention.
  • Fig. 12 is a circuit diagram of a clock level conversion module provided by the present invention.
  • Fig. 13 is a circuit diagram of the charge pump provided by the present invention.
  • Fig. 1 is one of the circuit schematic diagrams of the charge pump provided by the present invention.
  • the charge pump is mainly used in some applications requiring high voltage, such as Electrically Erasable Programmable read only memory (Electrically Erasable Programmable read only) memory, EEPROM) or one-time programmable memory (Efuse) and other fields.
  • the charge pump includes a charge pump module 101, a clock level conversion module 102, a comparison module 103, a high voltage configuration module 104, and a clock control module 105;
  • the module 103 is connected to the charge pump module 101
  • the comparison module 103 is also connected to the charge pump module 101 and the high voltage configuration module 104 .
  • the clock level conversion module 102 is configured to convert the digital clock signal into a first level signal and send it to the clock control module 105; the first level signal is a clock signal required by the charge pump.
  • the high voltage configuration module 104 is configured to configure the target voltage of the input terminal of the comparison module 103;
  • the comparison module 103 is configured to compare the divided voltage of the output voltage of the charge pump module 101 with the target voltage, and send the second level signal obtained by the comparison to the clock control module 105 .
  • the clock control module 105 is configured to control whether to provide two reverse clock signals for the charge pump module 101 according to the first level signal and the second level signal.
  • the digital clock signal is a signal generated by an external clock module, and the voltage amplitude of the digital clock signal is 1.2 volts (V), and the clock level conversion module 102 is used to convert the digital clock signal into a first level signal (1.5 V) is sent to the clock control module 105; the high voltage configuration module 104 is used to configure the corresponding target voltage to the input terminal of the comparison module 103 based on the signal sent by the processor; and the comparison module 103 is used to use the output voltage of the charge pump module 101 The divided voltage is compared with the target voltage, and the second level signal obtained by the comparison is sent to the clock control module 105 .
  • V voltage amplitude of the digital clock signal
  • the clock level conversion module 102 is used to convert the digital clock signal into a first level signal (1.5 V) is sent to the clock control module 105
  • the high voltage configuration module 104 is used to configure the corresponding target voltage to the input terminal of the comparison module 103 based on the signal sent by the processor
  • the comparison module 103 is used to use the
  • the clock control module 105 determines whether to start providing two-way reverse clock signals for the charge pump module 101 based on the received first level signal and second level signal. If it is determined to provide two-way reverse clock signals for the charge pump, the charge The pump module 101 starts charging based on the two reverse clock signals; if it is determined that the two reverse clock signals are not provided for the charge pump, the charge pump module 101 stops charging, thereby realizing the control of the output voltage of the charge pump module 101 .
  • the target voltage of the input terminal of the comparison module is configured through the high-voltage configuration module, so that the comparison module outputs the second level signal based on the divided voltage of the target voltage and the output voltage of the charge pump module, and passes the clock level
  • the conversion module converts the digital clock signal into the first level signal required by the charge pump, and finally the clock control module determines whether to provide two reverse clock signals for the charge pump module based on the first level signal and the second level signal; That is, if it is determined to provide two-way reverse clock signals for the charge pump module, the charge pump module starts charging; if it is determined not to provide two-way reverse clock signals for the charge pump module, the charge pump module stops charging, thereby realizing the charging
  • the control of the output voltage of the pump module prevents the storage module from not working properly due to the low output voltage of the charge pump module.
  • FIG. 2 is the second functional block diagram of the charge pump circuit provided by the present invention.
  • the two input terminals are connected to the first power supply voltage
  • the third input terminal of the high voltage configuration module 104 is connected to the processor
  • the output terminal of the high voltage configuration module 104 is connected to the first input terminal of the comparison module 103
  • the reference voltage is a voltage signal output by the reference voltage circuit.
  • the processor is configured to send a first high voltage configuration signal to the high voltage configuration module 104 when it is determined that the output voltage of the charge pump module 101 is greater than or equal to a preset voltage.
  • the high voltage configuration module 104 is specifically configured to determine the reference voltage as the target voltage of the first input terminal of the comparison module 103 when receiving the first high voltage configuration signal.
  • the processor is further configured to send a second high voltage configuration signal to the high voltage configuration module 104 when it is determined that the output voltage of the charge pump module 101 is lower than the preset voltage.
  • the high voltage configuration module 104 is further specifically configured to determine the first power supply voltage as the target voltage of the first input terminal of the comparison module 103 when receiving the second high voltage configuration signal.
  • the processor monitors the output voltage of the charge pump module 101 in real time, and compares the output voltage of the charge pump module 101 with a preset voltage, and when it is determined that the output voltage of the charge pump module 101 is greater than or equal to the preset voltage, it indicates The output voltage of the charge pump module 101 is too high.
  • the processor sends the first high-voltage configuration signal (low-level signal) to the high-voltage configuration module 104.
  • the high-voltage configuration module 104 receives the low-level signal, it outputs a reference voltage.
  • the reference voltage is used as the target voltage, so that the output voltage of the charge pump module 101 is clamped and pulled down by the comparison module 103 .
  • the processor sends a second high voltage configuration signal (high level signal) to the high voltage configuration module 104, and the high voltage
  • the configuration module 104 receives the high-level signal, it outputs the first power supply voltage, that is, the first power supply voltage is used as the target voltage, so that the output voltage of the charge pump module 101 rises to a certain value (19V) without being clamped by the comparison module 103 .
  • the target voltage is configured for the input terminal of the comparison module through the high-voltage configuration module, so as to prevent the output voltage of the charge pump from being clamped by the comparison module when the memory module is in the erase operation. If it is too low, it cannot be erased.
  • FIG. 3 is the third functional block diagram of the charge pump circuit provided by the present invention.
  • the clock control module 105 includes a first switch circuit and an inverse clock generation circuit.
  • the first input terminal of the first switch circuit is connected to the output terminal of the clock level conversion module 102, the second input terminal of the first switch circuit is connected to the output terminal of the comparison module 103, and the first An output terminal of a switch circuit is connected to the first input terminal of the reverse clock generating circuit.
  • the second input terminal of the reverse clock generating circuit is connected to the processor, and the output terminal of the reverse clock generating circuit is connected to the charge pump module 101 .
  • the first switch circuit is configured to send a control signal determined according to the first level signal and the second level signal to the reverse clock generation circuit.
  • the reverse clock generation circuit is configured to control the two reverse clock signals of the charge pump module 101 based on the control signal and the enable signal sent by the processor.
  • the first switch circuit may be an AND gate for receiving a first-level signal and a second-level signal, based on The high and low levels of the first level signal and the second level signal output the corresponding control signal, and the control signal is used to control whether the reverse clock generation circuit is allowed to generate two reverse clock signals; when the enable signal is high When the control signal is also a high-level signal, it is allowed to generate two reverse clock signals; when the control signal is a low-level signal, the two reverse clock signals are turned off to control whether the charge pump module 101 is charged. the goal of.
  • the charge pump provided by the present invention controls the output voltage of the charge pump module through the first switch circuit to control whether the reverse clock generation circuit provides two reverse clock signals for the charge pump module.
  • FIG. 4 is the fourth circuit block diagram of the charge pump provided by the present invention.
  • the charge pump module 101 includes a charge pump circuit and a voltage divider circuit, and the input terminal of the charge pump circuit is connected The output end of the reverse clock generation circuit is connected, the output end of the charge pump circuit is connected to the input end of the voltage divider circuit, the output end of the voltage divider circuit is connected to the second input end of the comparison module 103 connect.
  • the voltage divider circuit is configured to divide the output voltage of the charge pump circuit and send it to the comparison module 103 .
  • the first power supply voltage is 1.5V
  • the digital clock signal is an external clock signal, which is 1.2V
  • the clock level conversion module 102 sets the 1.2V clock frequency to 6.78MHz (megahertz), and the high voltage configuration signal
  • the first power supply voltage is sent to the first input end of the comparison module 103
  • the high-voltage configuration signal is a low-level signal
  • the reference voltage is sent to the first input end of the comparison module 103
  • the charge pump The output voltage of the circuit is sent to the second input terminal of the comparison module 103 after being divided by the voltage divider circuit; the output of the comparison module 103 can control whether the first level signal obtained after conversion is sent to Two reverse clock generation circuits to control the output voltage of the charge pump circuit; in addition, the enable signal of the reverse clock generation circuit also controls whether the two reverse clock generation signals provide two reverse voltages for the charge pump circuit. Clock signal to achieve the purpose of controlling whether the charge pump circuit works.
  • FIG. 5 is a circuit diagram of a high-voltage configuration module provided by the present invention.
  • the high-voltage configuration module 104 includes a transmission gate T1, a transmission gate T2, and a NOT gate F1.
  • the input terminal of the transmission gate T1 is connected to the reference voltage
  • the first control terminal of the transmission gate T1 is connected to the processor through the NOT gate F1
  • the second control terminal of the transmission gate T1 is connected to the connection to the processor described above.
  • the input terminal of the transmission gate T2 is connected to the first power supply voltage, the first control terminal of the transmission gate T2 is connected to the processor, and the second control terminal of the transmission gate T2 is connected with the The processor is connected, and the output terminal of the transmission gate T2 and the output terminal of the transmission gate T1 are both connected to the first input terminal of the comparison module 103 .
  • the high-voltage configuration module 104 is composed of an inverter (inverter F1) and two transmission gates (transmission gate T1 and transmission gate T2), wherein IN0 in FIG. 5 is connected to the reference voltage generated by the voltage reference circuit, and IN1 Connect the first power supply voltage, when HV_setting is configured as the first high-voltage configuration signal (low-level signal), the reference voltage will be connected to the comparison module 103 through the output terminal (OUT terminal), and at this time, the output voltage of the charge pump circuit is divided After the voltage division of the voltage circuit acts on the comparison module 103, the output voltage of the charge pump circuit is clamped at about 15.5V; when HV_setting is configured as the second high voltage configuration signal (high level signal), the first power supply voltage will pass through OUT The terminal is connected to the comparison module 103.
  • the output voltage of the charge pump circuit acts on the comparison module 103 after being divided by the voltage divider circuit. Since the first power supply voltage has 1.5V (the output voltage of the charge pump circuit is divided by the voltage divider circuit) The highest voltage after the compression will not exceed 1.5V), at this time, the output voltage of the charge pump circuit will be pumped to the highest voltage (19V) without being controlled by the comparison module 103 .
  • HV_setting, N_HV_setting, IN0, IN1 and vref in Figure 5 are all network labels.
  • HV_setting is high level
  • N_HV_setting is a low level signal used to control the transmission gate on and off
  • vref is a high voltage configuration
  • the output voltage, vref, of the module 104 may be the power supply voltage VDDA, or the reference voltage Vref.
  • FIG. 6 is a circuit diagram of a clock control module provided by the present invention.
  • the first switch circuit includes an AND gate Y1.
  • the first input end of the AND gate Y1 is connected to the output end of the clock level conversion module 102, the second input end of the AND gate Y1 is connected to the output end of the comparison module 103, and the AND gate Y1 The output terminal of is connected with the first input terminal of the reverse clock generation circuit.
  • the AND gate Y1 is used as a switch to control whether the reverse clock generation circuit provides two reverse clock signals for the charge pump circuit, that is, to control whether the charge pump circuit is charged, and to realize the charging of the charge pump circuit. control of the output voltage.
  • the reverse clock generation circuit includes a second switch circuit, a first reverse clock generation circuit, and a second reverse clock generation circuit.
  • the first input end of the second switch circuit is connected to the output end of the AND gate Y1, the second input end of the second switch circuit is connected to the processor, and the output ends of the second switch circuit are respectively It is connected with the input end of the first reverse clock generation circuit and the input end of the second reverse clock generation circuit, and the output end of the first reverse clock generation circuit is connected with the second reverse clock generation circuit.
  • the output terminals to the clock generating circuit are all connected to the input terminals of the charge pump module 101 .
  • the charge pump provided by the present invention generates two reverse clock signals through the first reverse clock generation circuit and the second reverse clock generation circuit, so as to meet the charging requirement of the charge pump circuit.
  • the second switch circuit includes a NAND gate YF1
  • the first reverse clock generation circuit includes a transmission gate T3, a first NOR gate HF1, and a first drive circuit
  • the second reverse clock generating circuit includes a NOT gate F2, a NOR gate HF2 and a second driving circuit.
  • the input terminal of the transmission gate T3 is connected to the output terminal of the NAND gate YF1, the first control terminal of the transmission gate T3 is connected to the first power supply voltage, and the second control terminal of the transmission gate T3 is grounded, so
  • the output end of the transmission gate T3 is connected with the first input end of the first NOR gate HF1, the second input end of the first NOR gate HF1 is connected with the output end of the NOR gate HF2, and the first NOR gate HF1 is connected with the output end of the NOR gate HF2.
  • the output end of the NOR gate HF1 is connected to the input end of the first driving circuit.
  • the input end of the NOT gate F2 is connected to the output end of the NAND gate YF1, the output end of the NOT gate F2 is connected to the first input end of the NOR gate HF2, and the first input end of the NOR gate HF2
  • the two input ends are connected with the output end of the first NOR gate HF1
  • the output end of the NOR gate HF2 is connected with the input end of the second drive circuit
  • the output end of the second drive circuit is connected with the output end of the second drive circuit.
  • the output ends of the first drive circuit are all connected to the charge pump circuit.
  • a first NOR gate is designed.
  • the SR flip-flop composed of the gate HF1 and the NOR gate HF2 is used to generate two reverse non-overlapping clock signals.
  • the first driving circuit includes a NOT gate F3, a NOT gate F4 and a NOT gate F5, wherein the input terminal of the NOT gate F3 is connected to the output terminal of the first NOR gate HF1, and the output of the NOT gate F3 terminal is connected to the input terminal of the NOT gate F4, the output terminal of the NOT gate F4 is connected to the input terminal of the NOT gate F5, and the output terminal of the NOT gate F5 is connected to the charge pump circuit as a reverse clock signal.
  • the second drive circuit includes a NOT gate F6, a NOT gate F7 and a NOT gate F8, wherein the input of the NOT gate F6 is connected to the output of the NOR gate HF2, and the output of the NOT gate F6 is the NAND gate
  • the input terminal of F7 is connected, the output terminal of the NOT gate F7 is connected with the input terminal of the NOT gate F8, and the output terminal of the NOT gate F8 is connected with the charge pump circuit as another reverse clock signal.
  • both the first driving circuit and the second driving circuit are used to increase the driving capability of the corresponding reverse clock signal.
  • DPXH, clk_en, HV_EN, CP_CLK, and CP_CLKN in FIG. 6 are all network labels; wherein, DPXH represents the first level signal output by the clock level conversion circuit, and clk_en represents the second level signal output by the comparison module 103.
  • Level signal, the enable signal sent by the HV_EN processor, CP_CLK and CP_CLKN represent two reverse clock signals, both of which are connected to the input terminal of the charge pump circuit.
  • FIG. 7 is a circuit diagram of a unipolar circuit provided by the present invention.
  • the charge pump circuit includes a plurality of unipolar circuits, and each of the unipolar circuits includes an N-type metal oxide semiconductor ( N-Metal-Oxide-Semiconductor (NMOS) tube N1, P-type metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS) tube P1, PMOS tube P2 and capacitor C1.
  • N-type metal oxide semiconductor N-Metal-Oxide-Semiconductor (NMOS) tube N1
  • P-type metal oxide semiconductor positive channel Metal Oxide Semiconductor, PMOS tube P1
  • capacitor C capacitor
  • the source of the NMOS transistor N1 is used as the first input terminal of the unipolar circuit, the gate of the NMOS transistor N1 is connected to the gate of the PMOS transistor P1, and the gate of the NMOS transistor N1 is used as the first input terminal of the unipolar circuit.
  • the second input end of the unipolar circuit; the drain of the NMOS transistor N1 is connected to the source of the PMOS transistor P1, and the drain of the PMOS transistor P1 is used as the output end of the unipolar circuit; the PMOS
  • the gate of the transistor P2 is connected to the charge release module, the drain of the PMOS transistor P2 is connected to the first power supply voltage, the source of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1, and the NMOS
  • the drain of the tube N1 is also connected to the first end of the capacitor C1, the first end of the capacitor C1 is used as the second clock signal end of the unipolar circuit, and the second end of the capacitor C1 is used as the unipolar circuit The first clock signal terminal of the pole circuit.
  • the charge pump circuit can be composed of 32 unipolar circuits, each of which is shown in Figure 7, where CK is the first clock signal terminal, and the reverse clock generation The output terminal of the circuit is connected, VCK is the second clock signal terminal, VOUT is the output terminal of the unipolar circuit, VIN_1 is the first input terminal of the unipolar circuit, VIN_2 is the second input terminal of the unipolar circuit, discharge is the charge release module
  • the output signal when discharge is a low-level signal, will force the charge pump to no longer send charges, and release the charge on the charge pump through the charge release module, so that the output voltage of the charge pump is equal to the first power supply voltage VDDA .
  • the ability of the charge pump circuit to carry a load is related to the first power supply voltage VDDA, the clock frequency and the size of the capacitor C1.
  • the variation range of the first power supply voltage VDDA is 1.35V ⁇ 1.65V
  • the minimum clock frequency is 6.78 MHz, so only the capacitance value of capacitor C1 can be adjusted.
  • devices can be stacked under the capacitor C1, and the present invention places three switching transistors (NMOS transistor N1, PMOS transistor P1, and PMOS transistor P2) in the unipolar circuit under the capacitor C1 to reduce the single
  • the layout area of the pole circuit can be further greatly saved in the layout area of the charge pump circuit.
  • FIG. 8 is a circuit diagram of the charge release module provided by the present invention, as shown in Figure 8, when the enable signal HV_EN is pulled to a low level, the reverse clock generation circuit of the charge pump is turned off, and the output voltage VHH of the charge pump circuit will be Charge is no longer sent, and VHH will start to drop at this time, but if there is no leakage path, VHH can only release charge through the subthreshold conductive path of the MOS tube, and it will take a long time for VHH to drop to 1.5 of VDDA_1P2V V level, in order to speed up the process of VHH releasing charge, a charge releasing module is designed here.
  • the discharge output by the charge release module will increase with the increase of the output voltage of the charge pump circuit, maintain the high voltage of VHH, and turn off the PMOS transistor connected to VDDA_1P2V (by the characteristics of the PMOS transistor, turn off the PMOS tube, the gate voltage must be greater than the source voltage of the PMOS tube), at this time the VHH signal will be disconnected from VDDA_1P2V, the charge pump will start to send charges, and VHH will start to rise.
  • Fig. 9 is a circuit diagram of the charge pump module provided by the present invention, and the connection relationship between multiple unipolar circuits is shown in Fig. 9, for example, the number of unipolar circuits is 32, and 32 unipolar circuits Divided into 16 levels, each level includes two unipolar circuits, namely the first unipolar circuit and the second unipolar circuit.
  • the first clock signal terminal of the first unipolar circuit is connected to a reverse clock signal
  • the first input terminal of the first unipolar circuit is connected to the first power supply voltage
  • the first unipolar circuit The second input end is connected to the second clock signal end of the second unipolar circuit
  • the second clock signal end of the first unipolar circuit is connected to the second input end of the second unipolar circuit
  • the output end of the first unipolar circuit It is connected with the first input terminal of the corresponding unipolar circuit in the second group of adjacent unipolar circuits
  • the first clock signal terminal of the second unipolar circuit is connected with another reverse clock signal
  • the first input terminal of the second unipolar circuit An input end is connected to the first power supply voltage
  • the output end of the second unipolar circuit is connected to the first input end of the corresponding unipolar circuit in the second group of adjacent unipolar circuits.
  • the charge pump provided by the present invention reduces the layout area of the charge pump circuit, reserves the layout area for the high-voltage configuration module and the clock level conversion module of the present invention, and does not change the layout area of the entire charge pump as much as possible.
  • FIG. 10 is a circuit diagram of a voltage dividing circuit provided by the present invention.
  • the voltage dividing circuit includes a capacitor C2, a capacitor C3, a capacitor C4, and a capacitor C5, and one end of the capacitor C2 is connected to the The output end of the charge pump circuit is connected, the other end of the capacitor C2 is connected to one end of the capacitor C5 through the capacitor C3 and the capacitor C4 in turn, the other end of the capacitor C5 is grounded, and the capacitor C4 is connected to the capacitor C4.
  • the connection between C5 is connected to the second input end of the comparison module 103 as the output end of the voltage divider circuit.
  • the voltage divider circuit is composed of capacitor C2, capacitor C3, capacitor C4 and capacitor C5, and the connection between capacitor C4 and capacitor C5 is used as the output terminal of the voltage divider circuit, and the voltage divider is the sampling of the output voltage of the charge pump circuit Voltage, the sampling voltage is input to the comparison module 103, so that the comparison module 103 determines whether to clamp the output voltage of the charge pump circuit based on the sampling voltage and the target voltage.
  • VHH in FIG. 10 represents the output voltage of the charge pump circuit
  • c0 represents the divided voltage of the output voltage
  • GDNA represents ground.
  • FIG. 11 is a circuit diagram of a comparison module provided by the present invention.
  • the comparison module 103 includes a comparison circuit and a shaping circuit.
  • the first input end of the comparison circuit is connected to the reference voltage
  • the second input end of the comparison circuit is connected to the first power supply voltage
  • the output end of the comparison circuit is connected to the input end of the shaping circuit
  • the shaping circuit The output terminal of the circuit is connected with the second input terminal of the first switching circuit.
  • the comparison circuit includes an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, a PMOS transistor P3, a PMOS transistor P4, and a PMOS transistor P5.
  • the gate of the NMOS transistor N2 is connected to the reference voltage, the source of the NMOS transistor N2 is respectively connected to the source of the NMOS transistor N3 and the drain of the NMOS transistor N4, and the drain of the NMOS transistor N2 poles are respectively connected to the source of the PMOS transistor P3, the gate of the PMOS transistor P3 and the gate of the PMOS transistor P4; the gate of the NMOS transistor N3 is connected to the output terminal of the voltage divider circuit,
  • the drain of the NMOS transistor N3 is respectively connected to the source of the PMOS transistor P4 and the gate of the PMOS transistor P5; the drain of the PMOS transistor P3, the drain of the PMOS transistor P4 and the PMOS transistor P4
  • the drains of the transistors P5 are connected to the first power supply voltage, the source of the PMOS transistor P5 is connected to the drain of the NMOS transistor N5, and the source of the PMOS transistor P5 is used as the output terminal of the comparison circuit; Both the gate of the NMOS transistor
  • the shaping circuit includes a PMOS transistor P6 and an NMOS transistor N6.
  • the drain of the PMOS transistor P6 is connected to the first power supply voltage, and the gate of the PMOS transistor P6 is respectively connected to the source of the PMOS transistor P5 and the gate of the NMOS transistor N6;
  • the source is connected to the drain of the NMOS transistor N6, and the source of the PMOS transistor P6 is used as the output terminal of the comparison module 103, and the source of the NMOS transistor N6 is grounded.
  • the comparison module 103 is for stabilizing the output voltage of the charge pump circuit. As shown in FIG. It can be given by the reference voltage circuit of the analog part.
  • the output voltage (that is, the high-voltage signal) generated by the charge pump circuit is divided by multiple capacitors. The divided voltage is c0; When a flat high-voltage configuration signal is used, compare c0 with vref. When c0 is greater than vref, the output terminal clk_en of the comparison module 103 outputs a low level, which acts on the reverse clock generation circuit. At this time, the reverse clock generation circuit is turned off.
  • the output voltage generated by the charge pump circuit is regulated at 15.5V.
  • vref is controlled by the high-voltage configuration module 104, and the value of vref is determined by configuring the HV_Setting signal (when HV_Setting is high, vref is the first power supply voltage; when HV_Setting is low, vref is the reference voltage ), to avoid the situation that the output voltage of the charge pump circuit is clamped too low by the comparison module 103 .
  • a comparison module is added at the output end of the charge pump circuit to form a negative feedback loop to limit the rise of the output voltage of the charge pump circuit; at the same time, in order to avoid the occurrence of process angle, mismatch and temperature of the comparison module, etc.
  • a high voltage configuration module is used to configure the target voltage at the input of the comparison module.
  • FIG. 12 is a circuit diagram of a clock level conversion module provided by the present invention.
  • the clock level conversion module 102 includes a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, an NMOS transistor N7, and an NMOS transistor N8 and NMOS tube N9.
  • the gate of the PMOS transistor P7 is connected to the digital clock signal, and the drain of the PMOS transistor P7 is respectively connected to the source of the NMOS transistor N7 and the gate of the NMOS transistor N8; Both the drain and the drain of the NMOS transistor N8 are connected to the first power supply voltage, the gate of the NMOS transistor N7 is connected to the source of the NMOS transistor N8, and the source of the NMOS transistor N8 serves as the The output terminal of the clock level conversion module 102; the drain of the PMOS transistor P8 is connected to the source of the NMOS transistor N8, and the gate of the PMOS transistor P8 is respectively connected to the source of the NMOS transistor N9 and the The drain of the PMOS transistor P9 is connected; the gate of the NMOS transistor N9 and the gate of the PMOS transistor P9 are connected to the gate of the PMOS transistor P7, and the drain of the NMOS transistor N9 is connected to the second power supply voltage Connection; the source of the PMOS transistor P7, the source of the PM
  • the input terminal IN of the clock level conversion module 102 receives an external 1.2V digital clock signal, and a 1.5V first level signal can be obtained after passing through the clock level conversion module 102, namely The OUT terminal outputs 1.5V, which realizes switching of the clock voltage domain, and increases the driving capability of the charge pump without changing the layout area of the charge pump.
  • FIG. 13 is a circuit diagram of a charge pump provided by the present invention. As shown in FIG. 13, the working principle of the charge pump is as follows:
  • the clock level conversion module 102 can convert the 1.2V digital clock signal to generate the 1.5V clock signal required by the charge pump circuit, and generate two reverse clock signals after passing through two reverse clock generation circuits Supply the charge pump circuit. After the enable switch HV_EN is turned on, the two reverse clock signals start to charge the charge pump circuit. When the output voltage of the charge pump circuit rises, it will divide the voltage through the capacitor, and divide the voltage c0 with the reference voltage or the first power supply. The voltages are compared, and the selection of the reference voltage and the first supply voltage is controlled by the processor.
  • the processor monitors the output voltage of the charge pump circuit in real time, and compares the output voltage of the charge pump circuit with the preset voltage. When it is determined that the output voltage of the charge pump circuit is greater than or equal to the preset voltage, the processor sends The first high-voltage configuration signal (low-level signal), when the high-voltage configuration module 104 receives the low-level signal, the reference voltage Vref is input to the inverting input terminal of the comparison module 103, and the divided voltage c0 of the output voltage of the charge pump circuit Connected to the non-inverting input terminal of the comparison module 103, when c0 is greater than Vref, the comparison module 103 outputs a low level, then the AND gate Y1 closes the reverse clock generation circuit, and does not provide two-way two-way reverse clock signals for the charge pump circuit, so that The output voltage of the charge pump circuit is clamped by the comparison module 103 and is stable at 15.5V.
  • the first high-voltage configuration signal low-level signal
  • the processor sends a second high voltage configuration signal (high) to the high voltage configuration module 104 Level signal), when the high-voltage configuration module 104 receives the high-level signal, the first power supply voltage VDDA is input to the reverse input terminal of the comparison module 103, and the divided voltage c0 of the output voltage of the charge pump circuit is connected to the comparison module 103 At the non-inverting input terminal, since VDDA is 1.5V and c0 is about 640mV, so VDDA is greater than c0, and the comparison module 103 outputs a high level, then the AND gate Y1 turns on the reverse clock generation circuit, providing two-way and two-way reverse clock generation circuits for the charge pump circuit.
  • the clock signal makes the output voltage of the charge pump circuit rise to 19V without being clamped by the comparison module 103, so that the output voltage of the
  • the comparison module 103 In order to avoid the situation that the output voltage of the charge pump circuit is clamped lower than the 15.5V voltage required by the design due to the process angle and mismatch, etc., a special configuration is made for the comparison module 103, that is, the high voltage configuration module 104, which is controlled by the HV_Setting signal Control, when HV_Setting is high level, the output voltage of the charge pump circuit will rise to 19V without being clamped; when HV_Setting is low level, the comparison module 103 will be clamped by the reference voltage, so that the output voltage of the charge pump circuit is stable at 15.5V.
  • the high voltage configuration module 104 which is controlled by the HV_Setting signal Control
  • the combination of the clock level conversion module 102 and the high-voltage configuration module 104 can increase the digital clock voltage of the charge pump from 1.2V to 1.5V, and improve the drive of the charge pump without changing the area of the charge pump. capability; at the same time, the high-voltage configuration module 104 avoids the risk of tape-out failure when the output voltage of the charge pump circuit is clamped too low by the comparison module 103 .
  • each implementation can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware.
  • the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

Pompe de charge, comprenant un module de pompe de charge (101), un module de conversion de niveau d'horloge (102), un module de comparaison (103), un module de configuration haute-tension (104) et un module de commande d'horloge (105). Le module de conversion de niveau d'horloge (102) est utilisé pour convertir un signal d'horloge numérique en un signal de premier niveau puis envoyer le signal de premier niveau au module de commande d'horloge (105), le signal de premier niveau étant un signal d'horloge requis par la pompe de charge. Le module de configuration haute-tension (104) est utilisé pour configurer une tension cible pour une extrémité d'entrée du module de comparaison (103). Le module de comparaison (103) est utilisé pour comparer une tension partielle d'une tension de sortie du module de pompe de charge (101) à la tension cible, et envoyer un signal de second niveau obtenu par comparaison au module de commande d'horloge (105). Le module de commande d'horloge (105) est utilisé pour commander, en fonction du signal de premier niveau et du signal de second niveau, s'il faut fournir deux trajets de signaux d'horloge inverse pour le module de pompe de charge (101). La pompe de charge met en œuvre la commande de la tension de sortie du module de pompe de charge (101), et évite la situation dans laquelle un module de stockage ne peut pas fonctionner normalement en raison du fait que la tension de sortie du module de pompe de charge (101) est trop faible.
PCT/CN2022/094190 2021-12-28 2022-05-20 Pompe de charge WO2023123829A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111616180.2 2021-12-28
CN202111616180.2A CN113992001B (zh) 2021-12-28 2021-12-28 可配置电荷泵

Publications (1)

Publication Number Publication Date
WO2023123829A1 true WO2023123829A1 (fr) 2023-07-06

Family

ID=79734617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/094190 WO2023123829A1 (fr) 2021-12-28 2022-05-20 Pompe de charge

Country Status (2)

Country Link
CN (1) CN113992001B (fr)
WO (1) WO2023123829A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113992001B (zh) * 2021-12-28 2022-03-29 广东曜芯科技有限公司 可配置电荷泵
CN117394682B (zh) * 2023-12-12 2024-03-29 杰创智能科技股份有限公司 基于多级电荷泵的反馈电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101364118A (zh) * 2007-08-08 2009-02-11 海力士半导体有限公司 稳压器和高压发生器
US20160142046A1 (en) * 2014-11-18 2016-05-19 Silicon Laboratories Inc. Self clocking comparator for a charge pump
CN207490762U (zh) * 2017-11-10 2018-06-12 苏州大学 一种快速升压电荷泵电路
CN109039059A (zh) * 2018-08-23 2018-12-18 合肥工业大学 一种高效的多模式电荷泵
CN113992001A (zh) * 2021-12-28 2022-01-28 广东曜芯科技有限公司 可配置电荷泵

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007202316A (ja) * 2006-01-27 2007-08-09 Rohm Co Ltd チャージポンプ回路及びこれを備えた電気機器
TWI439837B (zh) * 2011-08-26 2014-06-01 Richtek Technology Corp 穩壓電路控制器
CN103441670B (zh) * 2013-08-28 2016-06-22 中国兵器工业集团第二一四研究所苏州研发中心 一种输出电压可控的电荷泵电路
CN113315369A (zh) * 2021-07-09 2021-08-27 北京紫光青藤微系统有限公司 一种电荷泵电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101364118A (zh) * 2007-08-08 2009-02-11 海力士半导体有限公司 稳压器和高压发生器
US20160142046A1 (en) * 2014-11-18 2016-05-19 Silicon Laboratories Inc. Self clocking comparator for a charge pump
CN207490762U (zh) * 2017-11-10 2018-06-12 苏州大学 一种快速升压电荷泵电路
CN109039059A (zh) * 2018-08-23 2018-12-18 合肥工业大学 一种高效的多模式电荷泵
CN113992001A (zh) * 2021-12-28 2022-01-28 广东曜芯科技有限公司 可配置电荷泵

Also Published As

Publication number Publication date
CN113992001A (zh) 2022-01-28
CN113992001B (zh) 2022-03-29

Similar Documents

Publication Publication Date Title
WO2023123829A1 (fr) Pompe de charge
US7579902B2 (en) Charge pump for generation of multiple output-voltage levels
US6927986B2 (en) Power supply and PWM circuits
US8547168B2 (en) High current drive switched capacitor charge pump
US6188590B1 (en) Regulator system for charge pump circuits
US7940118B1 (en) Dying gasp charge controller
US20090086511A1 (en) Converter circuit with pulse width frequency modulation and method thereof
US6373324B2 (en) Voltage blocking method and apparatus for a charge pump with diode connected pull-up and pull-down on boot nodes
US7652522B2 (en) High efficiency low cost bi-directional charge pump circuit for very low voltage applications
US7948300B2 (en) Negative supply voltage generating circuit and semiconductor integrated circuit having the same
US7439792B2 (en) High voltage generation circuit and semiconductor device having the same
US10250133B2 (en) Single-stage CMOS-based voltage quadrupler circuit
US5412257A (en) High efficiency N-channel charge pump having a primary pump and a non-cascaded secondary pump
US20190280593A1 (en) High performance switch devices and methods for operating the same
US20220247311A1 (en) Synchronization of an electronic device
US9030891B2 (en) Charge pump circuit and memory
US10116211B2 (en) Power converter with adaptive zero-crossing current detection
US6801078B2 (en) Power efficient integrated charge pump using clock gating
CN107453599B (zh) 多电压输出的正压电荷泵
US8248153B2 (en) Method and apparatus for full clock cycle charge pump operation
CN110932704A (zh) 一种上电电路及电荷泵电路
CN107017874B (zh) 半导体装置以及选择电路
CN110601528A (zh) 电荷泵及存储设备
CN101783590A (zh) 一种升压时钟电路和带该升压时钟电路的电荷泵
US8076968B1 (en) Low-input-voltage charge pump

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22913124

Country of ref document: EP

Kind code of ref document: A1