WO2023116305A1 - Module d'encapsulation et son procédé de préparation, station de base et dispositif électronique - Google Patents

Module d'encapsulation et son procédé de préparation, station de base et dispositif électronique Download PDF

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Publication number
WO2023116305A1
WO2023116305A1 PCT/CN2022/133169 CN2022133169W WO2023116305A1 WO 2023116305 A1 WO2023116305 A1 WO 2023116305A1 CN 2022133169 W CN2022133169 W CN 2022133169W WO 2023116305 A1 WO2023116305 A1 WO 2023116305A1
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layer
chip
wiring layer
plastic
electrically connected
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PCT/CN2022/133169
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English (en)
Chinese (zh)
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郭小亚
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08—Access point devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the technical field of semiconductor packaging, in particular to a packaging module, its preparation method, base station and electronic equipment.
  • the power amplifier (Power Amplifier, PA) is an important part of the wireless communication base station.
  • the power amplifier outputs signals from the top surface, and then interconnects the signals with the power amplifier board.
  • a common method at present is to package the PA chip by using a flip-chip (Flip-Chip) technology.
  • a common packaging structure 1 is shown in Figure 1.
  • the PA chip 11 is plastic-sealed on the substrate 10 through the molding compound 12.
  • the wiring layer 13 is located on the molding compound 12 and is electrically connected to the PA chip 11.
  • the signal of the PA chip 11 is arranged on the wiring layer.
  • the welding pad (Pad) 14 output on 13. Then the package structure 1 is electrically connected to the power amplifier board 2, so as to realize the board-level structure of the power amplifier board.
  • the current board-level architecture of the power amplifier board has the following problems: (1) the cavity height of the resonant cavity formed between the PA chip 11 and the power amplifier board 2 is low, which will cause the self-excitation problem of the power amplifier; (2) the PA chip 11 There is a problem of signal crosstalk between the RF signal on the power amplifier board 2 and the signal on the power amplifier board 2; (3) In order to reduce the signal reflection angle, it is necessary to set a grounding pad on the wiring layer of the package structure 1, which will increase the occupied area of the package structure 1.
  • the present application provides a packaging module, its preparation method, base station and electronic equipment, which can not only improve the self-excitation problem of the power amplifier and the signal crosstalk problem, but also reduce the signal reflection angle without increasing the occupied area.
  • the present application provides a packaging module, which may include: a substrate, a chip, a first plastic packaging layer, a wiring layer, a plurality of interconnect electrodes, a second plastic packaging layer and a conductive layer.
  • the chip is located on the substrate
  • the first plastic packaging layer is used for plastic packaging the chip
  • the wiring layer is located on the side of the first plastic packaging layer away from the substrate
  • the wiring layer is electrically connected to the chip.
  • a plurality of interconnection electrodes are located on the side of the wiring layer away from the first plastic encapsulation layer and are electrically connected to the wiring layer, so that they can be electrically connected to the chip through the wiring layer; Interconnect electrodes; the conductive layer is located on the side of the second plastic encapsulation layer away from the wiring layer, wherein the conductive layer includes ground pads and signal transmission pads electrically connected to the plurality of interconnect electrodes, and the signal transmission pads are used to realize chip input/output transmission of signals.
  • the interconnection electrode when the packaging module is interconnected with the power amplifier board, since the interconnection electrode and the conductive layer are also provided on the wiring layer, the interconnection electrode can increase the distance between the chip and the power amplifier board. The distance, so the cavity height can be increased, so that the self-excitation problem of the power amplifier can be avoided. Moreover, since the grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by using the grounding pad, so that the signal interference problem between the chip and the power amplifier board can be improved.
  • the conductive layer only needs to be provided with signal transmission pads for providing input/output signals to the chip, unlike the wiring layer that needs to be provided with traces, there can be enough area for setting ground pads without additional The area of the conductive layer is enlarged, so that the grounding pad can be provided in the conductive layer without increasing the occupied area of the packaging module, so that the reflection angle can be reduced.
  • the chip may be a power amplifier chip, a radio frequency microwave millimeter wave chip, a processor chip, or an intellectual property (Intellectual Property, IP) core (cores), etc.
  • IP Intellectual Property
  • the chip in this application may be a die or a system-on-chip (System on Chip, SOC).
  • SOC System on Chip
  • the bare chip is the crystal grain before the chip is packaged, and each bare chip is an unpackaged chip with independent functions, which can be composed of one or more circuits.
  • a system-on-a-chip is generally a product, a purpose-built integrated circuit that contains a complete system and has the full content of embedded software.
  • interconnection electrodes and conductive layers are also provided on the wiring layer electrically connected to the chip, the interconnection electrodes can be used to increase the distance between the chip and the subsequently connected circuit board.
  • the ground pad is provided in the conductive layer, signal shielding can be realized by using the ground pad.
  • the ground pad is provided in the conductive layer, there is no need to increase the area of the wiring layer.
  • the chip may include at least one active device and/or at least one passive device.
  • the chip may include at least one active device, or the chip may include at least one passive device, or the chip may include at least one active device and at least one passive device.
  • active devices refer to electronic components that require power to realize their specific functions.
  • electron tubes, transistors, integrated circuits, etc. are generally used for signal amplification, conversion, etc., and are not limited here.
  • Passive components refer to electronic components that can realize their characteristics without external power supply, such as resistors, capacitors, inductors, converters, gradienters, matching networks, resonators, filters, mixers and switches etc. are not limited here.
  • the wiring layer is generally provided with chip pads electrically connected to the input/output pins of the chip and traces electrically connected to the chip, and the traces are generally used to connect devices inside the chip.
  • the chip pads are electrically connected to the signal transmission pads through the interconnection electrodes.
  • the orthographic projection of the ground pad on the substrate covers at least part of the wiring, that is, for the wiring layer, the power amplifier can be shielded by the ground pad Signals on the big board.
  • the signal on the trace can be shielded by using the ground pad. Therefore, in specific implementation, the larger the coverage area of the ground pad, the better the shielding effect.
  • multiple chip bonding pads in the wiring layer may be arranged around the wiring, that is, the wiring is arranged in the central area, and multiple chip bonding pads are arranged in the edge area.
  • a plurality of signal transmission pads are also arranged around the ground pads.
  • the embodiment of the present application does not specifically limit other features such as the number, shape, and material of the signal transmission pads.
  • the number of signal transmission pads can be designed according to the chip pads in the wiring layer, the signal transmission pads can be round, square, or other shapes, and the material of the conductive layer can be tin, copper or other materials with conductive properties. Metal.
  • the wiring layer may include one conductive layer or multiple (at least two) conductive layers.
  • an insulating dielectric layer is also provided between adjacent conductive layers, and a dielectric through hole is provided in the insulating dielectric layer, and the adjacent conductive layers can pass through the dielectric in the insulating dielectric layer.
  • the conductive layer may include wires, and the chip pads are generally arranged in the conductive layer closest to the interconnection electrodes in the wiring layer.
  • the conductive layer may be formed using materials such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., which is not limited herein.
  • the application does not limit the material of the insulating dielectric layer, for example, it may be at least one of silicon oxide, silicon nitride, silicon oxynitride, resin material, and the like.
  • the material of the insulating medium layer may be the same as that of the first plastic sealing layer or the second plastic sealing layer, which is not limited herein.
  • the materials of the first plastic sealing layer and the second plastic sealing layer may be the same, of course, may also be different, which is not limited here.
  • the materials of the insulating medium layer, the first plastic sealing layer and the second plastic sealing layer are the same.
  • the wiring layer may be electrically connected to the chip through a plurality of metal balls stacked.
  • the application does not limit the material of the metal balls, for example, the metal balls may be made of gold, silver, aluminum, zinc, copper, chromium, nickel, palladium and other materials.
  • the wiring layer may be electrically connected to the chip through a first via hole penetrating through the first plastic encapsulation layer.
  • the conductive material in the first via hole may be formed of materials such as gold, silver, copper, etc., which is not limited herein.
  • the substrate may be formed by using a copper clad laminate.
  • any structure of lines provided on a redistribution layer or a silicon interposer may also be used instead of the substrate, which is not limited herein.
  • the wiring layer when the wiring layer needs to be electrically connected to the substrate, the wiring layer can be electrically connected to the substrate through the second via hole penetrating through the first plastic encapsulation layer.
  • the conductive material in the second via hole may be formed of materials such as gold, silver, copper, etc., which is not limited herein.
  • the present application does not limit the specific form of the interconnection electrodes.
  • the interconnection electrodes may be formed by metal pillars or metal wires.
  • the application does not limit the material of the interconnection column, for example, it may be Cu, Ni, Mo, W, tungsten alloy, Cu-Mo alloy, nickel alloy and so on.
  • a shielding layer may also be provided on the side of the packaging module.
  • the embodiment of the present application also provides a base station, including a power amplifier board (including a single board including a transceiver (TRX, Transceiver), intermediate frequency, power supply, etc.), a radiator, and a power amplifier as described in the first aspect or the first aspect
  • the power amplifier board and the heat sink are respectively located on both sides of the packaging module.
  • the power amplifier board is located on the conductive layer side of the packaging module, and the power amplifier board is electrically connected to the signal transmission pad in the conductive layer; the radiator is located on the substrate side of the packaging module.
  • AIOB power amplifier board
  • the power amplifier board is used to realize the transmission of all signals
  • the heat sink is dedicated to heat dissipation to achieve the best performance and heat dissipation effect.
  • the interconnection electrodes can increase the distance between the chip and the power amplifier board, so the cavity height can be adjusted to avoid self-excitation of the power amplifier. question.
  • the grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, so that the signal interference problem between the chip and the power amplifier board can be improved.
  • the conductive layer only needs to be provided with signal transmission pads for providing input/output signals to the chip, unlike the wiring layer that needs to be provided with traces, there can be enough area for setting ground pads without additional The area of the conductive layer is enlarged, so that the grounding pad can be provided in the conductive layer without increasing the occupied area of the packaging module, so that the reflection angle can be reduced.
  • the side of the power amplifier board facing the packaging module has a ground pad, and the ground pad in the conductive layer is welded to the ground pad in the power amplifier board.
  • the power amplifier board and the packaging module can be welded by means of Land Grid Array (LGA) or Ball Grid Array (BGA), which is not limited here.
  • LGA Land Grid Array
  • BGA Ball Grid Array
  • the present application also provides an electronic device, the electronic device includes a circuit board, a heat sink, and the packaging module as described in the first aspect or various implementations of the first aspect, the circuit board and the heat sink are respectively Located on both sides of the package module.
  • the circuit board is located on the conductive layer side of the packaging module, and the circuit board is electrically connected to the signal transmission pad in the conductive layer; the radiator is located on the substrate side of the packaging module. In this way, the circuit board can be used for all signal transmission, and the heat sink is dedicated to heat dissipation to achieve the best performance and cooling effect.
  • the interconnect electrodes and the conductive layer are arranged between the circuit board and the wiring layer, the interconnect electrodes can increase the distance between the chip and the circuit board.
  • the grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, so that the signal interference problem between the chip and the circuit board can be improved.
  • the conductive layer only needs to be provided with signal transmission pads for providing input/output signals to the chip, unlike the wiring layer that needs to be provided with traces, there can be enough area for setting ground pads without additional Expand the area of the conductive layer.
  • the electronic equipment includes but is not limited to terminal equipment such as smartphones, smart TVs, smart TV set-top boxes, PCs, wearable devices, and smart broadband; telecommunications equipment such as wireless networks, fixed networks, servers, and chip modules, memory and other electronic devices.
  • terminal equipment such as smartphones, smart TVs, smart TV set-top boxes, PCs, wearable devices, and smart broadband
  • telecommunications equipment such as wireless networks, fixed networks, servers, and chip modules, memory and other electronic devices.
  • the side of the circuit board facing the packaging module has a grounding pad, and the grounding pad in the conductive layer is welded to the grounding pad in the circuit board.
  • the embodiment of the present application also provides a method for preparing a packaging module.
  • the preparation method may include: firstly, sequentially forming a chip on a substrate, a first plastic sealing layer for plastic sealing the chip, and a The wiring layer on the side away from the substrate, and the wiring layer is electrically connected to the chip; then an interconnection electrode electrically connected to the wiring layer is formed on the side of the wiring layer away from the first plastic encapsulation layer; The second plastic sealing layer of the interconnection electrodes; finally, a conductive layer is formed on the side of the second plastic packaging layer away from the wiring layer; wherein, the conductive layer includes a grounding pad and a signal transmission pad electrically connected to the interconnection electrodes.
  • a shielding layer may also be formed on the side of the formed packaging module.
  • sequentially forming the chip, the first plastic sealing layer for plastic sealing the chip, and the wiring layer on the side of the first plastic sealing layer away from the substrate on the substrate may include: bonding the chip on the substrate; Form the first plastic packaging layer of the plastic packaging chip; etch the first plastic packaging layer to form a via hole in the area corresponding to the chip; electroplate the metal material in the via hole; form an electrical connection with the metal material in the via hole on the first plastic packaging layer the wiring layer.
  • sequentially forming the chip, the first plastic encapsulation layer for plastic encapsulating the chip, and the wiring layer on the side of the first plastic encapsulation layer away from the substrate on the substrate may include: forming in the following manner: Bond the chip on the substrate; form a plurality of metal balls stacked on the chip; form the first plastic packaging layer for plastic packaging the chip and the multiple metal balls; form a wiring layer electrically connected to the multiple metal balls on the first plastic packaging layer .
  • the wiring layer can be formed in the following manner: a first conductive layer is formed on the first plastic encapsulation layer by electroplating, and then the first layer The conductive layer is patterned to form circuit wiring in the first conductive layer. Next, an insulating dielectric layer covering the first conductive layer is formed, a dielectric through hole is etched in the insulating dielectric layer, and a metal material is plated in the dielectric through hole. Finally, a second conductive layer is formed on the insulating medium layer, and then the second conductive layer is patterned, and circuit wiring is formed in the second conductive layer, thereby forming a wiring layer with two conductive layers.
  • FIG. 1 is a schematic diagram of a board-level structure of a medium-power amplifier board in the related art
  • FIG. 2 is a schematic structural diagram of an application scenario provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a packaging module provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another packaging module provided in the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another packaging module provided in the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another packaging module provided in the embodiment of the present application.
  • FIG. 7 is a flow chart of a method for preparing a packaging module provided in an embodiment of the present application.
  • FIGS. 8a to 8h are schematic structural diagrams of the preparation process of a packaging module provided in the embodiment of the present application.
  • 9a to 9i are structural schematic diagrams of the preparation process of another packaging module provided in the embodiment of the present application.
  • 10a to 10d are structural schematic diagrams of the preparation process of the wiring layer in a packaging module provided by the embodiment of the present application;
  • FIG. 11a to 11d are structural schematic diagrams of the preparation process of the wiring layer in another packaging module provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a base station provided in an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another base station provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another base station provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of another base station provided in an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of another electronic device provided by the embodiment of the present application.
  • FIG. 18 is a schematic diagram of a 3D stack package structure provided by an embodiment of the basic application.
  • connection and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral Ground connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary, and it can be the internal communication of two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral Ground connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary, and it can be the internal communication of two components.
  • the solutions described in the embodiments of the present application can be used in various communication systems, such as the fifth generation communication system and more possible communication systems with subsequent evolution.
  • the encapsulation module provided in the embodiment of the present application can be integrated in any network element equipment that needs to amplify wireless signal power, such as a base station. Exemplarily, taking the base station as an example, as shown in FIG.
  • the power amplifier board 300 and the heat sink 200 are respectively located on both sides of the package module 100, and the power amplifier board 300 is electrically connected to the package module 100, thereby realizing the power amplifier board (All in One Board, AIOB) structure, utilizing The power amplifier board 300 realizes the transmission of all signals, and the heat sink 200 is dedicated to heat dissipation to achieve the best performance and heat dissipation effect.
  • AIOB All in One Board
  • Fig. 3 exemplarily shows a schematic structural diagram of a package module provided by an embodiment of the present application
  • Fig. 4 exemplarily shows the structure of another package module provided by an embodiment of the present application schematic diagram.
  • the packaging module 100 may include: a substrate 111 , a chip 112 , a first plastic packaging layer 113 , a wiring layer 114 , a plurality of interconnect electrodes 120 , a second plastic packaging layer 130 and a conductive layer 140 .
  • the chip 112 is located on the substrate 111 , the first plastic encapsulation layer 113 is used to encapsulate the chip 112 , the wiring layer 114 is located on the side of the first plastic encapsulation layer 113 away from the substrate 111 , and the wiring layer 114 is electrically connected to the chip 112 .
  • a plurality of interconnection electrodes 120 are located on the side of the wiring layer 114 away from the first plastic encapsulation layer 113 and are electrically connected to the wiring layer 114, so as to be electrically connected to the chip 112 through the wiring layer 114;
  • the conductive layer 140 is located on the side of the second plastic encapsulation layer 130 away from the wiring layer 114, wherein the conductive layer 140 includes a ground pad 141 and a signal electrically connected to the plurality of interconnection electrodes 120
  • the transmission pad 142, the signal transmission pad 142 is used to realize the transmission of the input/output signal of the chip.
  • the interconnection electrode when the packaging module is interconnected with the power amplifier board, since the interconnection electrode and the conductive layer are also provided on the wiring layer, the interconnection electrode can increase the distance between the chip and the power amplifier board. The distance, so the cavity height can be increased, so that the self-excitation problem of the power amplifier can be avoided. Moreover, since the grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by using the grounding pad, so that the signal interference problem between the chip and the power amplifier board can be improved.
  • the conductive layer only needs to be provided with signal transmission pads for providing input/output signals to the chip, unlike the wiring layer that needs to be provided with traces, there can be enough area for setting ground pads without additional The area of the conductive layer is enlarged, so that the grounding pad can be provided in the conductive layer without increasing the occupied area of the packaging module, so that the reflection angle can be reduced.
  • the chip may be a power amplifier chip, a radio frequency microwave millimeter wave chip, a processor chip, or an intellectual property core.
  • the chip in this application may be a bare chip or a system-on-chip.
  • the bare chip is the crystal grain before the chip is packaged, and each bare chip is an unpackaged chip with independent functions, which can be composed of one or more circuits.
  • a system-on-a-chip is generally a product, a purpose-built integrated circuit that contains a complete system and has the full content of embedded software.
  • interconnection electrodes and conductive layers are also provided on the wiring layer electrically connected to the chip, the interconnection electrodes can be used to increase the distance between the chip and the subsequently connected circuit board.
  • the ground pad is provided in the conductive layer, signal shielding can be realized by using the ground pad.
  • the ground pad is provided in the conductive layer, there is no need to increase the area of the wiring layer.
  • the chip 112 may include at least one active device 1121 and/or at least one passive device 1122 .
  • the chip 112 may include at least one active device 1121 , or the chip 112 may include at least one passive device 1122 , or the chip 112 may include at least one active device 1121 and at least one passive device 1122 .
  • active devices refer to electronic components that require power to realize their specific functions. For example, electron tubes, transistors, integrated circuits, etc., are generally used for signal amplification, conversion, etc., and are not limited here.
  • Passive components refer to electronic components that can realize their characteristics without external power supply, such as resistors, capacitors, inductors, converters, gradienters, matching networks, resonators, filters, mixers and switches etc. are not limited here.
  • FIG. 4 is only illustrated by taking the chip 112 including one active device 1121 and one passive device 1122 as an example.
  • the wiring layer is generally provided with chip pads electrically connected to the input/output pins of the chip and traces electrically connected to the chip, and the traces are generally used to connect devices inside the chip.
  • the chip pads are electrically connected to the signal transmission pads through the interconnection electrodes.
  • the orthographic projection of the ground pad on the substrate covers at least part of the wiring, that is, for the wiring layer, the power amplifier can be shielded by the ground pad Signals on the big board.
  • the signal on the trace can be shielded by using the ground pad. Therefore, in specific implementation, the larger the coverage area of the ground pad, the better the shielding effect.
  • multiple chip bonding pads in the wiring layer may be arranged around the wiring, that is, the wiring is arranged in the central area, and multiple chip bonding pads are arranged in the edge area.
  • a plurality of signal transmission pads are also arranged around the ground pads.
  • the embodiment of the present application does not specifically limit other features such as the number, shape, and material of the signal transmission pads.
  • the number of signal transmission pads can be designed according to the chip pads in the wiring layer, the signal transmission pads can be round, square, or other shapes, and the material of the conductive layer can be tin, copper or other materials with conductive properties. Metal.
  • the wiring layer may include one conductive layer or multiple (at least two) conductive layers.
  • the wiring layer 114 when the wiring layer 114 includes multiple conductive layers 1141, an insulating dielectric layer 1142 is also provided between adjacent conductive layers 1141, and dielectric through holes are provided in the insulating dielectric layer 1142 1143 , adjacent conductive layers 1141 may be electrically connected through dielectric through holes 1143 in the insulating dielectric layer 1142 .
  • the conductive layer 1141 may include wires, and the chip bonding pad is generally arranged in the conductive layer closest to the interconnection electrodes in the wiring layer.
  • the conductive layer may be formed using materials such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., which is not limited herein.
  • the application does not limit the material of the insulating dielectric layer, for example, it may be at least one of silicon oxide, silicon nitride, silicon oxynitride, resin material, and the like.
  • the material of the insulating medium layer may be the same as that of the first plastic sealing layer or the second plastic sealing layer, which is not limited herein.
  • the materials of the first plastic sealing layer and the second plastic sealing layer may be the same, of course, may also be different, which is not limited here.
  • the materials of the insulating medium layer, the first plastic sealing layer and the second plastic sealing layer are the same.
  • the present application does not limit the manner of electrical connection between the wiring layer and the chip, and may be any manner that can realize the electrical connection between the two.
  • the wiring layer 114 may be electrically connected to the chip 112 through a plurality of metal balls 115 stacked.
  • the metal balls may be made of gold, silver, aluminum, zinc, copper, chromium, nickel, palladium and other materials.
  • the wiring layer 114 may also be electrically connected to the chip 112 through the first via hole 116 penetrating through the first plastic encapsulation layer 113 .
  • the conductive material in the first via hole 116 may be formed of materials such as gold, silver, copper, etc., which is not limited here.
  • the substrate may be formed by using a copper clad laminate.
  • any structure of lines provided on a redistribution layer or a silicon interposer may also be used instead of the substrate, which is not limited herein.
  • the wiring layer when the wiring layer needs to be electrically connected to the substrate, the wiring layer can be electrically connected to the substrate 111 through the second via hole 117 penetrating through the first plastic encapsulation layer 113 .
  • the conductive material in the second via hole 117 may be formed of materials such as gold, silver, copper, etc., which is not limited here.
  • the present application does not limit the specific form of the interconnection electrodes.
  • the interconnection electrodes may be formed by metal pillars or metal wires.
  • the application does not limit the material of the interconnection column, for example, it may be Cu, Ni, Mo, W, tungsten alloy, Cu-Mo alloy, nickel alloy and so on.
  • a shielding layer 150 may also be provided on the side of the packaging module.
  • FIG. 7 schematically shows a method for preparing a packaging module provided by the present application, and the method may include the following steps:
  • Step S101 sequentially forming a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer on a side of the first plastic encapsulation layer away from the substrate on the substrate, and the wiring layer is electrically connected to the chip.
  • the present application does not limit the package structure of the chip, for example, a panel level package (Panel Level Package, PLP), chip embedded package, etc. may be used.
  • a panel level package Panel Level Package, PLP
  • chip embedded package etc.
  • the chip can be packaged in the following way:
  • a chip 112 is bonded on a substrate 111 .
  • the chip can be bonded on the substrate through a chip bonding process.
  • the first plastic encapsulation layer 113 of the plastic chip 112 is formed.
  • the first plastic encapsulation layer 113 is etched to form a first via hole 116 in a region corresponding to the chip 112 .
  • the second via hole 117 may also be formed when the first via hole 116 is formed.
  • a conductive material is formed in the first via hole 116 as shown in FIG. 8d.
  • the conductive material when the first plastic encapsulation layer 113 has the second via hole 117 , when the conductive material is formed in the first via hole 116 , the conductive material also needs to be formed in the second via hole 117 .
  • the conductive material may be a metal material, and the metal material may be plated in the via hole by electroplating.
  • a wiring layer 114 electrically connected to the conductive material in the via hole is formed on the first plastic encapsulation layer 113 .
  • the chip can be packaged in the following way as an example:
  • a chip 112 is bonded on a substrate 111 .
  • the chip can be bonded on the substrate through a chip bonding process.
  • a plurality of metal balls 115 stacked on the chip 112 are formed.
  • a first plastic packaging layer 113 for plastic packaging the chip 112 and a plurality of metal balls 115 is formed.
  • a plastic sealing compound can be used to plastic seal the plurality of metal balls, and then the plastic sealing compound is ground until the upper surfaces of the multiple metal balls are exposed, thereby forming the first plastic sealing layer.
  • the substrate when it is necessary to electrically connect the substrate to the subsequently formed wiring layer, as shown in FIG. 9 d , it is also necessary to etch the first plastic encapsulation layer 113 to form the second via hole 117 . As shown in FIG. 9e , a conductive material is formed in the second via hole 117 .
  • the conductive material may be a metal material, and the metal material may be plated in the via hole by electroplating.
  • a wiring layer 114 electrically connected to a plurality of metal balls 115 is formed on the first plastic encapsulation layer 113 .
  • the wiring layer 114 can be formed in the following manner:
  • a first conductive layer 1141 is formed on the first plastic encapsulation layer 113 by electroplating, and then the first conductive layer 1141 is patterned to form circuit wiring in the first conductive layer 1141 .
  • the circuit wiring is generally provided with traces.
  • an insulating dielectric layer 1142 covering the first conductive layer 1141 is formed.
  • the insulating medium layer 1142 may be formed using the same material as the first plastic encapsulation layer, which is not limited herein.
  • a dielectric through hole 1143 is etched in the insulating dielectric layer 1142 .
  • Metal material is plated in the dielectric via 1143 as shown in FIGS. 10d and 11d .
  • the metal material in the dielectric through hole may be the same as that of the conductive layer, which is not limited here.
  • a second conductive layer 1141 is formed on the insulating dielectric layer 1142, and then the second conductive layer 1141 is patterned, and circuit wiring is formed in the second conductive layer 1141, thereby forming a The wiring layer 114 of the conductive layer 1141 .
  • the circuit wiring of the second conductive layer 1141 is generally provided with traces and chip pads.
  • the chip pads can be electrically connected to the input/output pins of the chip 112 through the first conductive layer 1141 .
  • the embodiment of the present application takes two conductive layers 1141 in the wiring layer 114 as an example for schematic illustration. Of course, in actual implementation, there may be one conductive layer 1141, three conductive layers 1141 or more conductive layers in the wiring layer. 1141, which is not limited here.
  • Step S102 as shown in FIG. 8f and FIG. 9g , a plurality of interconnection electrodes 120 electrically connected to the wiring layer 114 are formed on the side of the wiring layer 114 away from the first plastic encapsulation layer 113 .
  • the interconnection electrodes may be formed by metal pillars or metal wires, which is not limited here.
  • an implantation process may be used to implant metal posts or wires on the chip bonding pads.
  • Step S103 forming a second plastic encapsulation layer 130 for encapsulating the plurality of interconnect electrodes 120 on the side of the wiring layer 114 facing the interconnect electrodes 120 .
  • a molding compound may be used to plastic-encapsulate a plurality of interconnected electrodes, and then the molding compound may be ground until tops of the plurality of interconnected electrodes are exposed, thereby forming a second plastic-encapsulation layer.
  • Step S104 as shown in FIG. 8h and FIG. 9i, a conductive layer 140 is formed on the side of the second plastic encapsulation layer 130 away from the wiring layer 114; wherein, the conductive layer 140 includes a ground pad 141 and a signal transmission pad electrically connected to the interconnection electrode 142.
  • step S105 may also be included, forming a shielding layer 150 on the side of the formed packaging module.
  • the shielding layer 130 may be formed by sputtering or electroplating, which is not limited herein.
  • the packaging module provided by the embodiment of the present application can fan out the signal from the side of the conductive layer to realize signal interconnection with the circuit board, and the ground pad of the chip can fan out from the side of the substrate to connect with the heat sink to realize efficient heat dissipation. Therefore, the packaging module can be applied to the fields of radio frequency chips, miniaturized digital chips, or high-power chips that require heat dissipation.
  • the embodiment of the present application provides a base station.
  • the power amplifier board 300 and the heat sink 200 are respectively located on both sides of the package module 100 .
  • the power amplifier board 300 is located on the conductive layer side of the packaging module 100 , and the power amplifier board 300 is electrically connected to the signal transmission pad 142 in the conductive layer 140 ; the heat sink 200 is located on the substrate 111 side of the packaging module 100 .
  • the power amplifier board-one-board structure is realized, and the power amplifier board 300 is used to realize the transmission of all signals, and the heat sink 200 is dedicated to heat dissipation, so as to achieve the best performance and heat dissipation effect.
  • the interconnection electrodes can increase the distance between the chip and the power amplifier board, so the cavity height can be adjusted to avoid self-excitation of the power amplifier. question.
  • the grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, so that the signal interference problem between the chip and the power amplifier board can be improved.
  • the conductive layer only needs to be provided with signal transmission pads for providing input/output signals to the chip, unlike the wiring layer that needs to be provided with traces, there can be enough area for setting ground pads without additional The area of the conductive layer is enlarged, so that the grounding pad can be provided in the conductive layer without increasing the occupied area of the packaging module, so that the reflection angle can be reduced.
  • the power amplifier board 300 has a ground pad 301 on the side facing the package module 100 , and the ground pad 141 in the conductive layer 140 is connected to the ground pad 141 in the power amplifier board 300 .
  • the ground pad 301 is soldered.
  • the power amplifier board 300 and the packaging module 100 are welded through a grid array packaging method or a ball grid array packaging method, which is not limited herein.
  • the present application also provides an electronic device 2000, which includes: a circuit board 400, a heat sink 200, and any package module 100 provided in the embodiment of the present application, the circuit The board 400 and the heat sink 200 are respectively located on two sides of the packaging module 100 .
  • the circuit board 400 is located on the conductive layer 140 side of the packaging module 100 , and the circuit board 400 is electrically connected to the signal transmission pad 142 in the conductive layer 140 ; the heat sink 200 is located on the substrate 111 side of the packaging module 100 . Therefore, the circuit board 400 is used to realize the transmission of all signals, and the heat sink 200 is dedicated to heat dissipation, so as to achieve the best performance and heat dissipation effect.
  • the interconnect electrodes and the conductive layer are arranged between the circuit board and the wiring layer, the interconnect electrodes can increase the distance between the chip and the circuit board.
  • the grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, so that the signal interference problem between the chip and the circuit board can be improved.
  • the conductive layer only needs to be provided with signal transmission pads for providing input/output signals to the chip, unlike the wiring layer that needs to be provided with traces, there can be enough area for setting ground pads without additional Expand the area of the conductive layer.
  • the electronic equipment includes but is not limited to terminal equipment such as smartphones, smart TVs, smart TV set-top boxes, PCs, wearable devices, and smart broadband; telecommunications equipment such as wireless networks, fixed networks, servers, and chip modules, memory and other electronic devices.
  • terminal equipment such as smartphones, smart TVs, smart TV set-top boxes, PCs, wearable devices, and smart broadband
  • telecommunications equipment such as wireless networks, fixed networks, servers, and chip modules, memory and other electronic devices.
  • the side of the circuit board 400 facing the package module 100 has a ground pad 401 , and the ground pad 141 in the conductive layer 140 is welded to the ground pad 401 in the circuit board 400 .
  • the reliability of double-sided welding can be improved, and its reliability and safety in application can be guaranteed.
  • the above-mentioned packaging module provided by the embodiment of the present application can also be applied to a 3D stacked packaging structure, and the packaging module provided by the embodiment of the present application can be stacked with chips of other packaging structures.
  • At least two packaging modules provided by the embodiment of the present application can be stacked, for example, as shown in FIG.
  • the side 111 is opposite, of course, the side of the substrate 111 may be opposite to the side of the conductive layer 140 , which is not limited here and may be designed according to actual products.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne un module d'encapsulation et son procédé de préparation, une station de base et un dispositif électronique. Le module d'encapsulation comprend un substrat, une puce située sur le substrat, une première couche d'encapsulation en plastique, une couche de câblage située sur la couche d'encapsulation en plastique, et une pluralité d'électrodes d'interconnexion, une seconde couche d'encapsulation en plastique et une couche conductrice qui sont situées sur la couche de câblage. Les électrodes d'interconnexion sont électriquement connectées à la couche de câblage, et la couche conductrice est située sur la seconde couche d'encapsulation en plastique et comprend un plot de soudage de mise à la terre et un plot de soudage de transmission de signal connecté électriquement à la pluralité d'électrodes d'interconnexion. Dans le module d'encapsulation, les électrodes d'interconnexion peuvent augmenter la hauteur d'une cavité, de telle sorte que le problème d'auto-excitation d'un amplificateur de puissance peut être évité. De plus, le plot de soudage de mise à la terre dans la couche conductrice peut protéger des signaux radiofréquence sur la couche de câblage, ce qui permet d'améliorer le problème d'interférence de signal entre la puce et une carte d'amplificateur de puissance. De plus, étant donné que la couche conductrice doit seulement être pourvue du plot de soudage de transmission de signal utilisé pour fournir des signaux d'entrée/sortie à la puce, et n'a pas besoin d'être pourvue de fils, une zone suffisante peut être fournie pour agencer le plot de soudage de mise à la terre, et la zone occupée par le module d'encapsulation n'est pas augmentée.
PCT/CN2022/133169 2021-12-23 2022-11-21 Module d'encapsulation et son procédé de préparation, station de base et dispositif électronique WO2023116305A1 (fr)

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CN202111587194.6 2021-12-23
CN202111587194.6A CN114566479A (zh) 2021-12-23 2021-12-23 一种封装模组、其制备方法、基站及电子设备

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CN114566479A (zh) * 2021-12-23 2022-05-31 华为技术有限公司 一种封装模组、其制备方法、基站及电子设备
CN118073333A (zh) * 2022-11-24 2024-05-24 华为技术有限公司 一种集成装置、封装结构及电子设备

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CN108615721A (zh) * 2016-12-13 2018-10-02 台湾积体电路制造股份有限公司 芯片封装
CN110137157A (zh) * 2019-06-03 2019-08-16 中芯长电半导体（江阴）有限公司 半导体封装结构及其制备方法
CN113808956A (zh) * 2021-09-17 2021-12-17 成都奕斯伟系统集成电路有限公司 芯片封装方法、芯片封装结构及电子设备
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CN105789154A (zh) * 2016-04-20 2016-07-20 广东工业大学 一种倒装芯片模组
CN108615721A (zh) * 2016-12-13 2018-10-02 台湾积体电路制造股份有限公司 芯片封装
CN110137157A (zh) * 2019-06-03 2019-08-16 中芯长电半导体（江阴）有限公司 半导体封装结构及其制备方法
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