WO2023112249A1 - 位相調整回路 - Google Patents

位相調整回路 Download PDF

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Publication number
WO2023112249A1
WO2023112249A1 PCT/JP2021/046503 JP2021046503W WO2023112249A1 WO 2023112249 A1 WO2023112249 A1 WO 2023112249A1 JP 2021046503 W JP2021046503 W JP 2021046503W WO 2023112249 A1 WO2023112249 A1 WO 2023112249A1
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WO
WIPO (PCT)
Prior art keywords
transistor
signal
end connected
resistor
differential
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/046503
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English (en)
French (fr)
Japanese (ja)
Inventor
勉 竹谷
宗彦 長谷
照男 徐
斉 脇田
宏行 高橋
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NTT Inc
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Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to PCT/JP2021/046503 priority Critical patent/WO2023112249A1/ja
Priority to JP2023567428A priority patent/JPWO2023112249A1/ja
Priority to US18/717,811 priority patent/US12537517B2/en
Publication of WO2023112249A1 publication Critical patent/WO2023112249A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/16—Networks for phase shifting
    • H03H11/20—Two-port phase shifters providing an adjustable phase shift
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

Definitions

  • the present invention relates to a sine wave phase adjustment circuit.
  • sine waves play an important role.
  • sine waves are sometimes used to generate carriers and sine waves are used as clocks.
  • clocks are used not only as carrier waves, but also as timing references for determining data.
  • Clock data recovery is a method of making data decisions at appropriate timing.
  • a configuration using a phase comparator and a phase adjustment circuit is known as means for realizing clock data recovery. In this configuration, the phases are compared by some means, and the desired phase is generated based on the comparison result.
  • FIG. 9 shows the configuration of a conventional phase adjustment circuit.
  • a sine wave sin ⁇ t as a reference and a sine wave cos ⁇ t having a fixed phase difference of ⁇ /2 with respect to the sine wave sin ⁇ t are added to generate an arbitrary intermediate phase waveform.
  • the sine waves sin ⁇ t and cos ⁇ t are multiplied by constants A and B by multipliers 101 and 102, respectively.
  • the following formula holds from the trigonometric function synthesis formula.
  • ⁇ in formula (1) is as follows.
  • a Quadrature-VCO (Voltage Controlled Oscillator) 100 is used to generate sine waves sin ⁇ t and cos ⁇ t.
  • the Quadrature-VCO 100 has a problem that it is difficult to use it in the limit region of the device because of its low oscillation frequency due to its structure.
  • a method of creating a sine wave with a fixed phase difference of ⁇ /2 from a sine wave a method using a 90-degree hybrid is known. I had a problem not to.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a phase adjustment circuit that can be used over a wide range of frequencies.
  • a phase adjustment circuit includes a clock generator configured to generate a sinusoidal clock signal, and a sinusoidal differential clock signal whose amplitude is adjusted by inputting the clock signal output from the clock generator. at the same time, a variable amplifier configured to output an amplitude-adjusted in-phase signal; an adder configured to output the added differential signal; a differential transmission line configured to transmit the differential signal output from the adder; and a terminal for terminating the differential transmission line. and a termination circuit configured to output a signal from one of the two transmission lines constituting the differential transmission line.
  • the terminating circuit includes a first resistor having one end connected to a terminating end of a first transmission line of the two transmission lines, and a first resistor having one end connected to the A second resistor connected to the end of the second transmission line of the two transmission lines, one end connected to the connection point of the first and second resistors, and the other end connected to a fixed potential or ground and a connected third resistor.
  • the adder receives a clock signal on the opposite phase side of the differential clock signal output from the variable amplifier at its base or gate, and receives it from its collector or drain.
  • a first transistor for outputting a positive phase signal of a differential signal and a positive phase clock signal out of the differential clock signals outputted from the variable amplifier are inputted to a base or a gate, and a difference is outputted from a collector or a drain.
  • resistors a fifth resistor having one end connected to the other end of the fourth resistor and the other end connected to the collector or drain of the first transistor, and one end connected to the fourth resistor a sixth resistor having one end connected to the collector or drain of the second transistor and the other end connected to the emitter or source of the first transistor and the other end connected to the third transistor and an eighth resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the third transistor , a ninth resistor having one end connected to the power supply voltage and the other end connected to the base or gate of the third transistor; and a ninth resistor having one end connected to the base or gate of the third transistor and the other end to A tenth resistor connected to the ground, and an eleventh resistor having one end connected to the emitter or source of the third transistor and the other end connected to the ground.
  • the variable amplifier includes a Gilbert cell type first variable amplifier that adjusts the amplitude of the differential clock signal and outputs the same, and a first variable amplifier that adjusts the amplitude of the in-phase signal. and a Gilbert cell-type second variable amplifier that outputs a second variable amplifier.
  • the first variable amplifier has a base or gate to which the first gain control signal is input, and a collector or drain to which a positive phase side signal of the differential clock signal is applied.
  • a fourth transistor that outputs a second gain control signal to its base or gate, a fifth transistor that outputs a signal on the opposite phase side of the differential clock signal from its collector or drain, and a base or gate to which a sixth transistor to which the first gain control signal is input and which outputs a signal on the opposite phase side of the differential clock signal from the collector or drain; and a base or gate to which the second gain control signal is input and the collector
  • a seventh transistor for outputting a positive phase side signal of the differential clock signal from the drain, a positive phase side signal of the differential clock signal inputted from the outside is inputted to the base or gate, and the collector or the drain is the above-mentioned transistor.
  • An eighth transistor connected to the emitters or sources of the fourth and fifth transistors and a signal on the opposite phase side of the externally input differential clock signal are input to the base or gate, and the collector or drain is connected to the first transistor. 6.
  • a 12th resistor connected to the collector or drain of the seventh transistor, and a 13th resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the fifth and sixth transistors.
  • the second variable amplifier includes an eleventh transistor that receives a third gain control signal at its base or gate and outputs a common-mode signal from its collector or drain; a twelfth transistor to which a fourth gain control signal is input; a thirteenth transistor to which the third gain control signal is input to a base or gate; and a base or gate to which the fourth gain control signal is input.
  • a 15th transistor connected to the emitters or sources of the 12 transistors and a signal on the opposite phase side of the differential clock signal input from the outside are input to the base or gate, and the collectors or drains are connected to the 13th and 14th transistors.
  • a 16th transistor connected to the emitter or source of the transistor; a 17th transistor having a base or gate to which a bias voltage is applied; one end of which is connected to the power supply voltage; a 17th resistor connected to the collector or drain of the transistor of; an 18th resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the 12th and 13th transistors; a nineteenth resistor having one end connected to the emitter or source of the fifteenth transistor and the other end connected to the collector or drain of the seventeenth transistor; and one end connected to the emitter or source of the sixteenth transistor.
  • a 20th resistor having the other end connected to the collector or drain of the 17th transistor; and a 21st resistor having one end connected to the emitter or source of the 17th transistor and the other end connected to the ground. It is characterized by being composed of
  • the two transmission lines forming the differential transmission line are characterized in that their respective signal lines are arranged adjacent to each other.
  • the length L of each of the two transmission lines constituting the differential transmission line is set to v d , where v c is the propagation velocity for the common mode and ⁇ is the highest angular frequency of the sinusoidal clock signal to be phase-adjusted, L ⁇ / ⁇
  • one configuration example of the phase adjustment circuit of the present invention is configured to adjust the amplitude of the signal output from one of the two transmission lines constituting the differential transmission line. It is characterized by further comprising a level adjusting section.
  • a clock generator, a variable amplifier, an adder, a differential transmission line, and a terminating circuit are provided, and a signal is output from one of the two transmission lines forming the differential transmission line.
  • FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to the first embodiment of the invention.
  • FIG. 2 is a diagram showing simulation results of the phase adjustment circuit according to the first embodiment of the present invention.
  • FIG. 3 is a circuit diagram showing the configuration of a termination circuit according to a second embodiment of the invention.
  • FIG. 4 is a circuit diagram showing the configuration of an adder according to the third embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing the configuration of a variable amplifier according to the third embodiment of the invention.
  • FIG. 6 is a circuit diagram showing the configuration of a variable amplifier according to the third embodiment of the invention.
  • 7A to 7C are cross-sectional views showing the configuration of a differential transmission line according to a fourth embodiment of the invention.
  • FIG. 8 is a block diagram showing the configuration of a phase adjustment circuit according to the fifth embodiment of the invention.
  • FIG. 9 is a block diagram showing the configuration of a conventional phase adjustment circuit.
  • FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to the first embodiment of the present invention.
  • the phase adjustment circuit receives a clock generator 1 that generates a sinusoidal differential clock signal and the differential clock signal output from the clock generator 1, and outputs the amplitude-adjusted differential clock signal.
  • a variable amplifier 2 for outputting an adjusted in-phase signal
  • an adder 3 for outputting a differential signal obtained by adding the in-phase signal to each of the positive phase side and the negative phase side of the differential clock signal output from the variable amplifier 2.
  • a differential transmission line 4 for transmitting the differential signal output from the adder 3
  • a termination circuit 5 for terminating the differential transmission line 4 .
  • variable amplifiers 20-1 and 20-2 The amplitudes of the differential clock signal and the in-phase signal are adjusted by variable amplifiers 20-1 and 20-2 respectively prepared.
  • the input format of the variable amplifiers 20-1 and 20-2 may be in-phase or differential. That is, the output of the clock generator 1 may be a single-phase clock signal.
  • the adder 3 adds the positive phase side of the differential clock signal and the in-phase signal and outputs them, and the adder 30-1 adds the reverse phase side of the differential clock signal and the in-phase signal and outputs the result. It is composed of an adder 30-2.
  • the adders 30-1 and 30-2 may be designed according to the characteristic impedance of the differential transmission line 4. FIG.
  • the differential transmission line 4 is a transmission line in which the transmission line 40-1 on the positive phase side and the transmission line 40-2 on the negative phase side are electromagnetically coupled. Further, in the differential transmission line 4 of the present embodiment, the propagation speeds of the common-mode signal and the differential signal are different.
  • a termination circuit 5 is connected to the termination of the differential transmission line 4 .
  • an intermediate phase sine wave can be extracted from the end of the transmission line 40-1 on the positive phase side. As will be described later, a sine wave may be extracted from the end of the transmission line 40-2 on the opposite phase side.
  • the differential signal at the output end of the adder 3 is ⁇ sin ⁇ T, and the in-phase signal is ⁇ sin( ⁇ T+ ⁇ )
  • the differential signal at the end of the differential transmission line 4 is ⁇ sin( ⁇ T+( ⁇ L/v d ))
  • the differential transmission The common-mode signal at the end of line 4 is ⁇ sin( ⁇ T+( ⁇ L/v c )+ ⁇ ).
  • ⁇ indicates a phase delay or advance assuming a case where the in-phase signal and the differential signal are delayed due to manufacturing errors or some other influence.
  • the output signal OUT is taken out from either one of the transmission lines 40-1 and 40-2 forming the differential transmission line 4, the output signal OUT is expressed by the following equation.
  • Equation (5) represents a reference sine wave. From equation (5), it can be seen that a sine wave with a phase difference of ⁇ from the reference phase can be generated by adding a sine wave with a reference frequency and a sine wave with an arbitrary phase ⁇ . Details are described below. Since the amount of change in the output phase can be calculated by calculating re j ⁇ , formula (5) can be rearranged into the following formula.
  • Equation (7) the phase angle ⁇ is given by Equation (7).
  • Fig. 2 shows the result of confirmation by circuit simulation that the phase of the sine wave is changed by the phase adjustment circuit of this embodiment.
  • equations (4) to Sine waves 21 and 22 are shown in which the values of amplitudes A and B in equation (7) are changed and the phase is changed by approximately 4 ps. Note that, in the example of FIG. 2, in order to make it easier to understand the change in phase, the sine waves 20 to 22 are not adjusted to have the same amplitude.
  • the transmission lines 40-1 and 40-2 may be coplanar lines or microstrip lines.
  • phase adjustment circuit of this embodiment is designed so that the equation (8) holds true at the highest possible frequency of the sinusoidal signal to be phase-adjusted.
  • the termination circuit 5 includes a resistor R1 having one end connected to the end of the transmission line 40-1, a resistor R2 having one end connected to the end of the transmission line 40-2, and a resistor R1 having one end connected to the end of the transmission line 40-2. , R2, and the other end thereof is connected to a fixed potential VTT.
  • the differential transmission line 4 is used to transmit both the in-phase signal and the differential signal, so it is necessary to set the impedance for each signal.
  • the impedance can be set for each signal mode.
  • the resistor R3 of the termination circuit 5 may be connected to the ground, it may also be connected to a fixed potential VTT other than the ground as in the example of FIG.
  • FIG. 4 shows a specific example of the adder 3 and the variable amplifier 2 of the first embodiment.
  • the adder 3 receives at its base the signal IN3n on the negative phase side of the differential clock signal output from the variable amplifier 2, and outputs a signal OUT3p on the positive phase side of the differential signal from its collector.
  • an NPN bipolar transistor Q2 whose base receives the signal IN3p on the positive phase side of the differential clock signal output from the variable amplifier 2 and outputs the signal OUT3n on the negative phase side of the differential signal from the collector.
  • an NPN bipolar transistor Q3 whose base receives the in-phase signal IN4 output from the variable amplifier 2, a resistor R4 whose one end is connected to the power supply voltage VCC, and whose other end is connected to the other end of the resistor R4, and A resistor R5 having one end connected to the collector of the transistor Q1, a resistor R6 having one end connected to the other end of the resistor R4 and the other end connected to the collector of the transistor Q2, and one end connected to the emitter of the transistor Q1, A resistor R7 whose other end is connected to the collector of the transistor Q3, a resistor R8 whose one end is connected to the emitter of the transistor Q2 and the other end is connected to the collector of the transistor Q3, and a power supply voltage VCC is connected to the other end.
  • a resistor R9 having one end connected to the base of the transistor Q3, a resistor R10 having one end connected to the base of the transistor Q3 and the other end grounded, and a resistor R10 having one end connected to the emitter of the transistor Q3 and the other end grounded. and a resistor R11 connected to .
  • the transistor Q3 is a tail current source that supplies current to the transistors Q1 and Q2 and requires an appropriate bias voltage.
  • the bias voltage for the tail current source is generated by a resistor voltage dividing circuit consisting of resistors R9 and R10.
  • the variable amplifier 20-1 has an NPN bipolar transistor Q4 which receives a gain control signal IN1n at its base, outputs a signal OUT2p on the positive phase side of the differential clock signal from its collector, and a gain control signal at its base.
  • An NPN bipolar transistor Q5 which receives the signal IN1p and outputs a signal OUT2n on the opposite phase side of the differential clock signal from the collector, and a gain control signal IN1n on the base and receives a signal on the opposite phase side of the differential clock signal from the collector.
  • An NPN bipolar transistor Q6 that outputs OUT2n, an NPN bipolar transistor Q7 that receives a gain control signal IN1p at its base and outputs a signal OUT2p on the positive phase side of the differential clock signal from its collector, and An NPN bipolar transistor Q8 whose base receives the signal IN2p on the positive phase side of the differential clock signal and whose collectors are connected to the emitters of the transistors Q4 and Q5; An NPN bipolar transistor Q9 whose base receives the signal IN2n on the side and whose collectors are connected to the emitters of the transistors Q6 and Q7; a resistor R12 whose other end is connected to the collectors of the transistors Q4 and Q7; a resistor R13 whose one end is connected to the power supply voltage VCC and whose other end is connected to the collectors of the transistors Q5 and Q6; A resistor R14 connected to the emitter and having the other end connected to the collector of the transistor Q10, a resistor R15 having one end
  • variable amplifier 20-2 includes an NPN bipolar transistor Q11 whose base receives the gain control signal IN5n and whose collector outputs the in-phase signal OUT4, and an NPN bipolar transistor Q11 whose base receives the gain control signal IN5p.
  • a bipolar transistor Q12 an NPN bipolar transistor Q13 whose base receives a gain control signal IN5n; an NPN bipolar transistor Q14 whose base receives a gain control signal IN5p and outputs a common-mode signal OUT4 from its collector;
  • An NPN bipolar transistor Q15 whose base receives the signal IN2p on the positive phase side of the differential clock signal output from and whose collector is connected to the emitters of the transistors Q11 and Q12, and the differential clock output from the clock generator 1
  • An NPN bipolar transistor Q16 whose base receives the signal IN2n of the opposite phase of the signal and whose collectors are connected to the emitters of the transistors Q13 and Q14; a resistor R17 connected to the voltage VCC and having the other end connected to the collectors of the transistors Q11 and Q14; a resistor R18 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q12 and Q13; is connected to the emitter of the transistor Q
  • the gain of the variable amplifier 20-1 can be controlled by the voltage difference between the gain control signals IN5p and IN5n.
  • the single-phase output variable amplifier 20-2 instead of the signal OUT2p on the positive phase side of the differential clock signal in FIG.
  • the output terminal of the signal OUT2n may be left open, or a dummy load may be connected.
  • FIGS. 4 to 6 show examples using bipolar transistors as the transistors Q1 to Q17, MOS transistors may be used.
  • MOS transistors may be used.
  • the base should be replaced with the gate, the collector with the drain, and the emitter with the source.
  • a resistor or capacitor for gain adjustment or frequency response adjustment may be inserted into the emitter or source of the transistor, or both a resistor and a capacitor may be inserted. Further, for level adjustment, etc., it is possible to provide an arbitrary amplifier circuit such as an emitter follower as required.
  • a fourth embodiment of the present invention will now be described.
  • This embodiment shows a specific example of the differential transmission line 4 of the first embodiment.
  • the differential transmission line 4 must have a structure in which a difference in propagation speed occurs between the differential mode and the common mode. In order to generate a propagation velocity difference between the differential mode and the common mode, it is more efficient to have electromagnetic field coupling between the differential ports.
  • the differential transmission line 4 used in the present invention does not include a ground plane between the transmission lines 40-1 and 40-2, and the transmission lines 40-1 and 40-2 are adjacent to each other so as to be electromagnetically coupled. It is good to have a form that allows
  • FIGS. 7A to 7C Cross-sectional views of the differential transmission line 4 are shown in FIGS. 7A to 7C.
  • the example of FIG. 7A shows an example of a microstrip line.
  • the transmission line 40 - 1 is composed of a dielectric 400 , a signal line 401 made of a conductor formed on the surface of the dielectric 400 , and a ground plane 403 made of a conductor formed on the back of the dielectric 400 .
  • the transmission line 40 - 2 is composed of a dielectric 400 , a signal line 402 made of a conductor formed on the surface of the dielectric 400 , and a ground plane 403 .
  • the example in FIG. 7B shows an example of a coplanar line.
  • the transmission line 40-1 is composed of a dielectric 400, a signal line 401, and a ground plane 404 made of a conductor formed on the surface of the dielectric 400 opposite to the signal line 402 with the signal line 401 interposed therebetween. be done.
  • the transmission line 40-2 is composed of a dielectric 400, a signal line 402, and a ground plane 405 made of a conductor formed on the surface of the dielectric 400 opposite to the signal line 401 with the signal line 402 interposed therebetween. be done.
  • FIG. 7C shows an example of a coplanar line with backside ground that combines the structure of FIG. 7A and the structure of FIG. 7B.
  • the transmission line 40-1 is composed of a dielectric 400, a signal line 401, and ground planes 403,404.
  • the transmission line 40-2 is composed of a dielectric 400, a signal line 402, and ground planes 403,405.
  • the signal lines 401 and 402 are laid out horizontally, but they may be stacked vertically to strengthen the coupling between the signal lines 401 and 402.
  • FIG. also, the ground planes 403-405 in FIGS. 7A-7C may be omitted.
  • providing at least one ground plane beside or above and below the signal lines 401 and 402 facilitates impedance design.
  • FIG. 8 is a block diagram showing the configuration of a phase adjustment circuit according to the fifth embodiment of the present invention.
  • the phase adjustment circuit of this embodiment is obtained by adding a level adjustment section 6 to the output terminal of the phase adjustment circuit of the first embodiment.
  • the output amplitude of the phase adjustment circuit of the present invention changes according to the adjusted phase. Therefore, the level adjusting section 6 may be provided so as to correspond to the varying output amplitude.
  • the level adjustment unit 6 there is a VGA (Variable Gain Amplifier) capable of adjusting the output amplitude, or an AGC (Automatic Gain Control) circuit that automatically adjusts the output amplitude.
  • VGA Very Gain Amplifier
  • AGC Automatic Gain Control
  • the present invention can be applied to techniques for adjusting the phase of a sine wave.
  • Reference Signs List 1 Clock generator 2, 20-1, 20-2 Variable amplifier 3 Adder 4 Differential transmission line 5 Termination circuit 6 Level adjuster 30-1, 30-2 Adder 40-1, 40-2 Transmission line 400 Dielectric 401, 402 Signal line 403 to 405 Ground plane Q1 to Q17 Transistor R1 to R21 Resistor.

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PCT/JP2021/046503 2021-12-16 2021-12-16 位相調整回路 Ceased WO2023112249A1 (ja)

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US18/717,811 US12537517B2 (en) 2021-12-16 2021-12-16 Phase adjustment circuit

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US12469947B2 (en) * 2023-10-31 2025-11-11 Texas Instruments Incorporated Differential wideband quadrature signal generation using over-coupled directional coupler

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JP2018078391A (ja) * 2016-11-07 2018-05-17 富士通株式会社 可変減衰装置、位相切り替え機能付き可変減衰装置及びフェーズシフタ
WO2019159246A1 (ja) * 2018-02-14 2019-08-22 三菱電機株式会社 ミクサ

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