WO2023110101A1 - Transistor de puissance au nitrure de gallium et procédé de production d'un transistor de puissance gan - Google Patents

Transistor de puissance au nitrure de gallium et procédé de production d'un transistor de puissance gan Download PDF

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Publication number
WO2023110101A1
WO2023110101A1 PCT/EP2021/086154 EP2021086154W WO2023110101A1 WO 2023110101 A1 WO2023110101 A1 WO 2023110101A1 EP 2021086154 W EP2021086154 W EP 2021086154W WO 2023110101 A1 WO2023110101 A1 WO 2023110101A1
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Prior art keywords
gallium nitride
layer
type doped
region
power transistor
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PCT/EP2021/086154
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English (en)
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Gilberto Curatola
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Huawei Digital Power Technologies Co., Ltd.
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Priority to PCT/EP2021/086154 priority Critical patent/WO2023110101A1/fr
Priority to CN202180099908.0A priority patent/CN117561607A/zh
Publication of WO2023110101A1 publication Critical patent/WO2023110101A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H01L29/7392—Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present disclosure relates to the field of Gallium Nitride (GaN) technology for power device applications.
  • GaN Gallium Nitride
  • the present disclosure relates to a GaN power transistor and a method for producing such GaN power transistor, in particular a GaN power field effect transistor (FET) with Conductive Modulation Enhancement Effect.
  • FET GaN power field effect transistor
  • a single AIGaN barrier with a certain thickness and Aluminum (Al) content is used to define the electrical characteristics of the two-dimensional electron gas (2DEG).
  • 2DEG two-dimensional electron gas
  • VTH threshold voltage
  • the approach is very sensitive to surface effects, i.e., dynamic effects; 3)
  • the approach is very sensitive to gate module details, i.e., Schottky versus Ohmic; 4)
  • the approach shows reduced current capabilities, that means performance must be traded-off because of reliability issues; 5) Very low VTH are generally obtained, e.g., between about 1 and 1.5V; 6) Possible issues may arise with spurious turn-on; and 7)
  • the approach is very sensitive to parasitics and voltage and current overshoots.
  • This new device concept for GaN based power transistor is based on a GaN Field effect power transistor with conductivity modulation enhancement effect.
  • the structure of this novel GaN power transistor causing this conductivity modulation enhancement effect is described in the following.
  • a basic idea of this disclosure is to implement a new device concept for a GaN-based power transistor.
  • This device is the first disclosed IGBT-like power device that is presented for GaN technology. It allows to operate under conductivity modulation thanks to the minority carrier injection from the p-GaN collector and hence a strong reduction in on-state resistance can be achieved. It employs a pGaN gate concept that allows a fast depletion of the minority carriers accumulated during the on-state conduction state. Thus, it allows to have fast switch-off transitions when compared to conventional Silicon IGBT. A suppression of tail current can be achieved with this concept and hence a better trade-off between VCEON and EOFF can be achieved. It is a lateral device concept. Therefore, the lateral breakdown can be easily increased by increasing the length of the lateral drift region.
  • Insulated Gate Bipolar Transistors IGBTs
  • GaN IGBT-based like transistors IGBT approaches are industry standard only for Silicon Technology.
  • IGBT a Bipolar-MOS BiMOS controlled switch referred to as the Insulated Gate Bipolar Transistor IGBT is the device of choice for the majority of power electronics converters with power ratings ranging from few kWs to beyond the 1GW mark.
  • IGBT is characterized by its ability to simultaneously handle large currents and large voltages.
  • the IGBT combines the simple gate-drive characteristics of power MOSFETs with the high-current and low-saturation-voltage capability of bipolar transistors.
  • the IGBT combines an isolated-gate FET for the control input and a bipolar power transistor as a switch in a single device.
  • the main features of IGBT silicon transistors can be summarized as follows: Combine high-efficiency and fast switching; High input impedance thanks to the insulated gate structure; Conductivity modulation in on-state due to minority carrier injection from p-type collector; VCEON versus EOFF trade-off; Slow switching compared to MOSFETs due to minority carrier recombination time and tail currents.
  • An IGBT features a significantly lower forward voltage drop compared to a conventional MOSFET in higher blocking voltage rated devices, although MOSFETS exhibit much lower forward voltage at lower current densities due to the absence of a diode Vf in the IGBT's output BJT.
  • the GaN-based power transistor as presented in this disclosure combines the advantages of the IGBT device with the advantages of the GaN technology.
  • a reverse-biased Schottky diode is inserted in series with the pn-pGaN/AIGaN diode. This allows a massive DC gate current reduction.
  • pGaN node is separated from the gate terminal by a reverse biased Schottky diode.
  • the disclosure relates to a Gallium Nitride power transistor, comprising: a Gallium Nitride buffer layer comprising a top surface and a bottom surface opposing the top surface, the Gallium Nitride buffer layer comprising a first region, a second region and a third region at the top surface; an Aluminum Gallium Nitride barrier layer deposited at the top surface of the Gallium Nitride buffer layer; an emitter contact formed at an interface of the Aluminum Gallium Nitride barrier layer with the Gallium Nitride buffer layer above the first region of the Gallium Nitride buffer layer; a first p-type doped Gallium Nitride layer deposited at the Aluminum Gallium Nitride barrier layer above the second region of the Gallium Nitride buffer layer, the first p-type doped Gallium Nitride layer forming a gate contact of the Gallium Nitride power transistor; and a second p-type doped Gallium Nitride layer deposited above the third region of the Gallium Nitride buffer layer, the second p-type
  • Such a GaN power transistor provides the technical advantage that tail currents can be almost completely eliminated thanks to the particular gate structure of the transistor.
  • the pGaN gate region i.e. , the second region as defined above, allows for a fast depletion of the holes that have been injected into the drift region during the on-state conduction period.
  • the switching speed of the device can be controlled.
  • GaN power transistor allows to operate under conductivity modulation thanks to the minority carrier injection from the p-GaN collector. Hence, strong reduction in on-state resistance can be achieved.
  • the GaN power transistor can achieve suppression of tail current. Hence, a better trade-off between VCEON and EOFF can be achieved.
  • the GaN power transistor follows a lateral device concept. Therefore, the lateral breakdown can be easily increased by increasing the length of the lateral drift region.
  • the emitter contact is formed with a 2-dimensional electron gas arising at the interface of the Aluminum Gallium Nitride barrier layer with the Gallium Nitride buffer layer.
  • the collector contact is formed at an interface of the second p-type doped Gallium Nitride layer with the Gallium Nitride buffer layer.
  • a p-n diode can be formed by the pGaN layer (collector) and the 2DEG formed at the AIGaN-GaN interface.
  • the p-n diode is used to implement an IGBT structure that provides the advantages described above for the first aspect.
  • the second p-type doped Gallium Nitride layer is deposited at the Aluminum Gallium Nitride barrier layer within a recess of the Aluminum Gallium Nitride barrier layer, the recess partially recessing the Aluminum Gallium Nitride barrier layer.
  • the GaN power transistor can have a flexible design with respect to an etching of the Aluminum Gallium Nitride barrier layer.
  • the second p-type doped Gallium Nitride layer is deposited at the Gallium Nitride buffer layer within a recess of the Aluminum Gallium Nitride barrier layer, the recess extending down to the Gallium Nitride buffer layer.
  • the GaN power transistor can have a flexible design with respect to an etching of the Aluminum Gallium Nitride barrier layer.
  • the second p-type doped Gallium Nitride layer is deposited at the Gallium Nitride buffer layer within a recess of the Aluminum Gallium Nitride barrier layer, the recess extending into the Gallium Nitride buffer layer and recessing the Gallium Nitride buffer layer.
  • the GaN power transistor can have a flexible design with respect to an etching of the Aluminum Gallium Nitride barrier layer and the Gallium Nitride buffer layer.
  • the GaN power transistor comprises a metal layer deposited at the first p-type doped Gallium Nitride layer, wherein an interface between the metal layer and the first p-type doped Gallium Nitride layer forms a Schottky interface or an Ohmic interface.
  • the Ohmic interface approach provides the following advantages: (i) pGaN node is tidily connected to the gate metal terminal, thus the device is less prone to VTH instability; (ii) Good reliability: Gate breakage is due to thermal runaway when large DC current flows through the gate; (iii) Large amount of hole injected from gate improves dynamic effects.
  • the Schottky interface approach provides the following advantages: (i) pGaN node is separated from the gate terminal by a reverse biased Schottky diode; (ii) Low DC gate current is obtained at the expense of VTH instabilities; (iii) Low DC current implies a more difficult dynamic effect optimization due to lower amount of holes injected into the buffer; (iv) Gate module is breaking via a TDDB mechanism (like oxide in Si-MOS devices); (v) Difficult interplay among: dynamic effects, gate reliability and VTH stability.
  • the GaN power transistor comprises a series circuit of a lateral power pGallium Nitride High Electron Mobility Transistor with a p-n diode, wherein an anode of the p-n diode forms the collector contact.
  • the Gallium Nitride power transistor particularly forms a Non-lnsulated Gate Bipolar Transistor, NIGBT.
  • the p-n diode is formed by the second p-type doped Gallium Nitride layer and the interface of the Aluminum Gallium Nitride barrier layer with the Gallium Nitride buffer layer; or the p-n diode is formed by the second p-type doped Gallium Nitride layer and the Gallium Nitride buffer layer.
  • the p-n diode is formed between the second p-type doped Gallium Nitride layer and a partially or fully recessed Aluminum Gallium Nitride barrier layer.
  • the second p-type doped Gallium Nitride layer is in direct contact with a Gallium Nitride channel formed at the top surface of the Gallium Nitride buffer layer.
  • a semiconductor doping of the second p-type doped Gallium Nitride layer is different from a semiconductor doping of the first p-type doped Gallium Nitride layer.
  • This provides the technical advantage that the first p-type doped Gallium Nitride layer and the second p-type doped Gallium Nitride layer can be formed in different process steps, hence improving design flexibility.
  • the Gallium Nitride power transistor comprises: a first metal layer deposited at the first p-type doped Gallium Nitride layer; and a second metal layer deposited at the second p-type doped Gallium Nitride layer, wherein a metal of the first metal layer is different from a metal of the second metal layer.
  • the metal of gate contact can be different from the metal of the Collector contact.
  • the gate contact and the Collector contact can be produced in different process steps which improves design flexibility.
  • a thickness of the second p-type doped Gallium Nitride layer is different from a thickness of the first p-type doped Gallium Nitride layer.
  • the pGaN layer for the gate contact and the pGaN layer for the Collector contact can be different.
  • the gate contact and the Collector contact can be formed in different process steps, thereby improving design flexibility.
  • a depletion of minority carriers from the first p-type doped Gallium Nitride layer is faster for a negative gate voltage applied to the gate contact of the Gallium Nitride power transistor during an off-state of the Gallium Nitride power transistor than for a zero gate voltage applied to the gate contact during the off-state.
  • the switching speed of the device can be increased. That means, the speed of the device can be controlled by varying the gate voltage applied to the gate electrode during off-state of the device.
  • the Aluminum Gallium Nitride barrier layer and the Gallium Nitride buffer layer comprise an additional p-type implantation at a region below the emitter contact and the gate contact.
  • the disclosure relates to a method for producing a Gallium Nitride power transistor, the method comprising: forming a Gallium Nitride buffer layer comprising a top surface and a bottom surface opposing the top surface, the Gallium Nitride buffer layer comprising a first region, a second region and a third region at the top surface; depositing an Aluminum Gallium Nitride barrier layer at the top surface of the Gallium Nitride buffer layer; depositing a first p-type doped Gallium Nitride layer at the Aluminum Gallium Nitride barrier layer above the second region of the Gallium Nitride buffer layer, the first p-type doped Gallium Nitride layer forming a gate contact of the Gallium Nitride power transistor; depositing a second p-type doped Gallium Nitride layer above the third region of the Gallium Nitride buffer layer, the second p-type doped Gallium Nitride layer forming a collector contact of the Gallium Nitride power transistor; and forming an emitter contact at an
  • Such a method provides the same advantages as the corresponding device of the first aspect.
  • the method provides the advantage that a novel GaN power transistor can be produced for which tail currents can be almost completely eliminated thanks to the particular gate structure of the transistor.
  • the pGaN gate region i.e. , the second region as defined above, allows for a fast depletion of the holes that have been injected into the drift region during the on-state conduction period.
  • the switching speed of the device can be controlled.
  • the method comprises: depositing and structuring a first hard-mask layer at the Aluminum Gallium Nitride barrier layer to define the third region of the Gallium Nitride buffer layer; trench etching the Aluminum Gallium Nitride barrier layer at the third region of the Gallium Nitride buffer layer; removing the first hard-mask layer; depositing a p-type doped Gallium Nitride layer at the Aluminum Gallium Nitride barrier layer and the Gallium Nitride buffer layer exposed by the trench etching of the Aluminum Gallium Nitride barrier layer; depositing and structuring a second hard-mask layer at the p-type doped Gallium Nitride layer to define the second region and the third region of the Gallium Nitride buffer layer; etching the p-type doped Gallium Nitride layer outside the second region and the third region of the Gallium Nitride buffer layer to form the first p-type doped Gallium Nitride layer and the second p-type doped Gallium Nitride layer; removing the
  • Such a method provides the advantage of high design flexibility.
  • the steps can also be performed in a different sequence than described above.
  • the first metal layer (Emitter) can be formed in a process step prior to the forming of the second and third metal layers (Gate and Collector).
  • the first metal layer (Emitter) can be formed in a process step after the forming of the second and third metal layers (Gate and Collector).
  • a metal of the second metal layer is different from a metal of the third metal layer.
  • the metal of the second metal layer can be different from the metal of the third metal layer, e.g., when forming both metal layers in different process steps.
  • the metal of the second metal layer can be the same as the metal of the third metal layer, e.g., when forming both metal layers in a single process step.
  • the method comprises: depositing and structuring a first hard-mask layer at the Aluminum Gallium Nitride barrier layer to define the third region of the Gallium Nitride buffer layer; trench etching the Aluminum Gallium Nitride barrier layer at the third region of the Gallium Nitride buffer layer; removing the first hard-mask layer; depositing a p-type doped Gallium Nitride layer at the Aluminum Gallium Nitride barrier layer and the Gallium Nitride buffer layer exposed by the trench etching of the Aluminum Gallium Nitride barrier layer; forming a metal layer at the p-type doped Gallium Nitride layer; depositing and structuring a second hard-mask layer at the metal layer to define the second region and the third region of the Gallium Nitride buffer layer; etching the metal layer and the p-type doped Gallium Nitride layer outside the second region and the third region of the Gallium Nitride buffer layer to form the first p-type doped Gallium Nitride layer with the second metal
  • Such a method provides the advantage of high design flexibility.
  • the steps can also be performed in a different sequence than described above.
  • the method comprises: depositing a p-type doped Gallium Nitride layer at the Aluminum Gallium Nitride barrier layer; depositing and structuring a first hard-mask layer at the p-type doped Gallium Nitride layer to define the second region of the Gallium Nitride buffer layer; etching the p-type doped Gallium Nitride layer outside the second region of the Gallium Nitride buffer layer to form the first p-type doped Gallium Nitride layer; depositing and structuring a second hard-mask layer at the first p-type doped Gallium Nitride layer and the Aluminum Gallium Nitride barrier layer exposed by the etching of the p-type doped Gallium Nitride layer to define the third region of the Gallium Nitride buffer layer; trench etching the Aluminum Gallium Nitride barrier layer at the third region of the Gallium Nitride buffer layer; depositing the second p-type doped Gallium Nitride layer at the Gallium Nitride buffer layer exposed by
  • Such a method provides the advantage of high design flexibility.
  • the steps can also be performed in a different sequence than described above.
  • the first metal layer (Emitter) can be formed in a process step prior to the forming of the second and third metal layers (Gate and Collector).
  • the first metal layer (Emitter) can be formed in a process step after the forming of the second and third metal layers (Gate and Collector).
  • a metal of the second metal layer is different from a metal of the third metal layer.
  • the metal of the second metal layer can be different from the metal of the third metal layer, e.g., when forming both metal layers in different process steps.
  • the metal of the second metal layer can be the same as the metal of the third metal layer, e.g., when forming both metal layers in a single process step.
  • the metal can be deposited prior to the pGaN etching and the etching step can be done at the same time for the metal and the pGaN layer, i.e. similar as for the methods described above.
  • the second pGaN can be deposited, then a window can be opened in the passivation that covers the first pGaN layer and then a common metal layer can be deposited for both pGaN1 and pGaN2.
  • the metal etching can be performed.
  • Fig. 1 shows a schematic cross section of the novel GaN power transistor 100 according to a first embodiment
  • Fig. 2 shows a schematic cross section of the novel GaN power transistor 200 according to a second embodiment
  • Fig. 3 shows a schematic cross section of the novel GaN power transistor 300 according to a third embodiment
  • Fig. 4 shows a schematic cross section of the novel GaN power transistor 400 according to a fourth embodiment
  • Fig. 5 shows a performance diagram illustrating an example output characteristic 500 of the novel GaN power transistor versus a conventional pGaN Schottky HEMT with comparable dimensions;
  • Fig. 6 shows current-voltage diagram of an exemplary simulation of on-to-off transitions for the novel GaN power transistor as a function of the voltage applied to the gate electrode;
  • Fig. 7 shows an example process flow 700 for producing the novel GaN power transistor according to a first embodiment
  • Fig. 8 shows an example process flow 800 for producing the novel GaN power transistor according to a second embodiment
  • Fig. 9 shows an example process flow 900 for producing the novel GaN power transistor according to a third embodiment.
  • the power transistors described herein may be used to produce integrated circuits and/or power semiconductors and may be manufactured according to various technologies.
  • the semiconductor devices may be utilized in logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, optical circuits, memory circuits and/or integrated passives.
  • Fig. 1 shows a schematic cross section of the novel GaN power transistor 100 according to a first embodiment.
  • the GaN power transistor 100 is a novel GaN Field effect power transistor with conductivity modulation enhancement effect.
  • the structure of this novel GaN power transistor 100 causing this conductivity modulation enhancement effect is described in the following.
  • This first embodiment represents a device concept implementing a total AIGaN removal without etching the GaN channel as described below.
  • the GaN power transistor 100 comprises a Gallium Nitride buffer layer 110 comprising a top surface 110a and a bottom surface 110b opposing the top surface 110a.
  • the Gallium Nitride buffer layer 110 comprises a first region 101 , a second region 102 and a third region 103 at the top surface 110a.
  • An Aluminum Gallium Nitride (AIGaN) barrier layer 112 is deposited at the top surface 110a of the GaN buffer layer 110.
  • An emitter contact E is formed at an interface of the Aluminum Gallium Nitride barrier layer 112 with the Gallium Nitride buffer layer 110 above the first region 101 of the Gallium Nitride buffer layer 110.
  • the GaN power transistor 100 comprises a first p-type doped Gallium Nitride layer 113 deposited at the Aluminum Gallium Nitride barrier layer 112 above the second region 102 of the Gallium Nitride buffer layer 110.
  • the first p-type doped Gallium Nitride layer 113 forms a gate contact G of the Gallium Nitride power transistor 100.
  • the GaN power transistor 100 comprises a second p-type doped Gallium Nitride layer 114 deposited above the third region 103 of the Gallium Nitride buffer layer 110.
  • the second p- type doped Gallium Nitride layer 114 forms a collector contact C of the Gallium Nitride power transistor 100.
  • the Aluminum Gallium Nitride barrier layer 112 may be a thin AIGaN barrier grown onto the GaN buffer layer 110 in order to create a strong two-dimensional electron gas (2DEG) at the AIGaN/GaN interface.
  • 2DEG two-dimensional electron gas
  • the first p-type doped GaN layer 113 may be composed by Magnesium as the p-type dopant, for example, which may be defined below the gate metal contact G only in the gate region, i.e., the second region 102.
  • the first p-type doped GaN layer 113 depletes the 2DEG in the gate region 102 and allows the fabrication of an enhancement-mode (normally-off) GaN power transistor 100.
  • the emitter contact E is formed with a 2-dimensional electron gas arising at the interface of the Aluminum Gallium Nitride barrier layer 112 with the Gallium Nitride buffer layer 110.
  • the collector contact C is formed at an interface of the second p-type doped Gallium Nitride layer 114 with the Gallium Nitride buffer layer 110.
  • a length of the first p-type doped GaN layer 113 is denoted as LGATE.
  • a length of the drift layer i.e., the distance between the first p-type doped GaN layer 113 and the second p-type doped GaN layer 114, is denoted as LDRIFT.
  • the GaN buffer layer 110 may be implemented as a GaN C-doped (Carbon-doped) buffer layer.
  • a GaN channel UID (unintentionally doped) may be formed on top of the GaN buffer layer 110.
  • the GaN channel UID 111 represents the channel of the GaN power transistor 100.
  • the second p-type doped Gallium Nitride layer 114 is deposited at the Gallium Nitride buffer layer 110 within a recess 119 of the Aluminum Gallium Nitride barrier layer 112.
  • the recess 119 extends down to the Gallium Nitride buffer layer 110.
  • the Gallium Nitride power transistor 100 comprises a metal layer 117 deposited at the first p- type doped Gallium Nitride layer 113. An interface between the metal layer 117 and the first p- type doped Gallium Nitride layer 113 may form a Schottky interface or an Ohmic interface.
  • the Gallium Nitride power transistor 100 may comprise a series circuit of a lateral power pGallium Nitride High Electron Mobility Transistor with a p-n diode, wherein an anode of the p- n diode forms the collector contact C.
  • the p-n diode may be formed by the second p-type doped Gallium Nitride layer 114 and the interface of the Aluminum Gallium Nitride barrier layer 112 with the Gallium Nitride buffer layer 110.
  • the p-n diode may be formed by the second p-type doped Gallium Nitride layer 114 and the Gallium Nitride buffer layer 110.
  • the p-n diode may be formed between the second p-type doped Gallium Nitride layer 114 and a partially or fully recessed Aluminum Gallium Nitride barrier layer 112.
  • the second p-type doped Gallium Nitride layer 114 is in direct contact with a Gallium Nitride channel 111 formed at the top surface 110a of the Gallium Nitride buffer layer 110.
  • a semiconductor doping of the second p-type doped Gallium Nitride layer 114 may be different from a semiconductor doping of the first p-type doped Gallium Nitride layer 113.
  • the Gallium Nitride power transistor 100 shown in Figure 1 comprises a first metal layer 117 deposited at the first p-type doped Gallium Nitride layer 113; and a second metal layer 116 deposited at the second p-type doped Gallium Nitride layer 114.
  • a metal of the first metal layer 117 may be different from a metal of the second metal layer 116.
  • the Gallium Nitride power transistor 100 shown in Figure 1 comprises a third metal layer 115 deposited at the emitter contact E.
  • a thickness of the second p-type doped Gallium Nitride layer 114 may be different from a thickness of the first p-type doped Gallium Nitride layer 113.
  • a depletion of minority carriers from the first p-type doped Gallium Nitride layer 113 is faster for a negative gate voltage applied to the gate contact of the Gallium Nitride power transistor during an off-state of the Gallium Nitride power transistor than for a zero gate voltage applied to the gate contact during the off- state. This behavior is shown in Figure 6.
  • the switching speed of the device can be increased. That means, the speed of the device can be controlled by varying the gate voltage applied to the gate electrode during off-state of the device. In this way minority carriers are directly depleted from the gate electrode, instead of the normal generation-recombination processes that are significantly slower.
  • Gate length LG defined as the lateral extension of the pGaN gate regions, i.e., second regions 102 (only one such second region 102 is shown in Figure 1);
  • P-type doping in the pGaN gate region i.e., first p-type doped GaN layer 113;
  • P-type doping in the pGaN collector region i.e., second p-type doped GaN layer 114
  • AIGaN barrier layer 112 thickness and Al content [%];
  • Passivation 118 thickness and passivation material composition (dielectric constant); Amount of recess 119 of the AIGaN barrier layer 112: partial, total, with GaN overetch; Lateral extension of the access regions: L acC ess
  • the collector contact C and the emitter contact E the following metals or a combination thereof can be used: Ti, Al, TiN, W, Au, Ni, W, for example.
  • the length of the first p-type doped GaN layer 113, LGATE can extend from 0.3um up to 5um (microns), for example.
  • the length of the drift layer, LDRIFT i.e., the distance between the first p-type doped GaN layer 113 and the second p-type doped GaN layer 114, can extend from 1 um up to 30um (microns), for example.
  • the thickness of the AIGaN barrier layer 112 can extend from 10nm up to 30nm, for example.
  • the Al content in the AIGaN barrier layer 112 can amount from 15% to 25%, for example.
  • the pGaN thickness in the second region 102 can extend from 50nm up to 200nm, for example.
  • the pGaN thickness in the third region 103 can extend from 50nm up to 500nm, for example.
  • a pGaN doping in the second region 102 can be based on Mg with a doping concentration from 1e18cm-3 up to 5e19cm-3, for example.
  • a pGaN doping in the third region 103 can be based on Mg with a doping concentration from 1e18cm-3 up to 5e19cm-3, for example.
  • Fig. 2 shows a schematic cross section of the novel GaN power transistor 200 according to a second embodiment.
  • the GaN power transistor 200 is a novel GaN Field effect power transistor with conductivity modulation enhancement effect.
  • the structure of this novel GaN power transistor 200 causing this conductivity modulation enhancement effect is described in the following.
  • This second embodiment represents a device concept implementing a total AIGaN removal and partial GaN channel over-etching as described below.
  • the structure of this second embodiment of the GaN power transistor 200 is similar to the structure of the GaN power transistor 100 according to the first embodiment described above with respect to Figure 1.
  • the GaN power transistor 200 comprises a Gallium Nitride buffer layer 110 comprising a top surface 110a and a bottom surface 110b opposing the top surface 110a.
  • the Gallium Nitride buffer layer 110 comprises a first region 101 , a second region 102 and a third region 103 at the top surface 110a.
  • An Aluminum Gallium Nitride (AIGaN) barrier layer 112 is deposited at the top surface 110a of the GaN buffer layer 110.
  • An emitter contact E is formed at an interface of the Aluminum Gallium Nitride barrier layer 112 with the Gallium Nitride buffer layer 110 above the first region 101 of the Gallium Nitride buffer layer 110.
  • the GaN power transistor 100 comprises a first p-type doped Gallium Nitride layer 113 deposited at the Aluminum Gallium Nitride barrier layer 112 above the second region 102 of the Gallium Nitride buffer layer 110.
  • the first p-type doped Gallium Nitride layer 113 forms a gate contact G of the Gallium Nitride power transistor 100.
  • the GaN power transistor 100 comprises a second p-type doped Gallium Nitride layer 114 deposited above the third region 103 of the Gallium Nitride buffer layer 110.
  • the second p- type doped Gallium Nitride layer 114 forms a collector contact C of the Gallium Nitride power transistor 100.
  • the second p-type doped Gallium Nitride layer 114 is deposited at the Gallium Nitride buffer layer 110 within a recess 119 of the Aluminum Gallium Nitride barrier layer 112.
  • the difference to the first embodiment of Figure 1 is that the recess 119 extends into the Gallium Nitride buffer layer 110 and is recessing the Gallium Nitride buffer layer 110.
  • the AIGaN barrier layer 112 is totally removed and the GaN channel 111 which is part of the upper section of the GaN buffer layer 110 is partially over-etched as can be seen from Figure 2. In one example, the over-etching may even extend down to the GaN buffer layer 110.
  • Fig. 3 shows a schematic cross section of the novel GaN power transistor 300 according to a third embodiment.
  • the GaN power transistor 300 is a novel GaN Field effect power transistor with conductivity modulation enhancement effect.
  • the structure of this novel GaN power transistor 300 causing this conductivity modulation enhancement effect is described in the following.
  • This third embodiment represents a device concept implementing a partial AIGaN over-etching as described below.
  • the structure of this third embodiment of the GaN power transistor 300 is similar to the structure of the GaN power transistor 100 according to the first embodiment described above with respect to Figure 1 and also similar to the structure of the GaN power transistor 200 according to the second embodiment described above with respect to Figure 2.
  • the GaN power transistor 300 comprises a Gallium Nitride buffer layer 110 comprising a top surface 110a and a bottom surface 110b opposing the top surface 110a.
  • the Gallium Nitride buffer layer 110 comprises a first region 101 , a second region 102 and a third region 103 at the top surface 110a.
  • An Aluminum Gallium Nitride (AIGaN) barrier layer 112 is deposited at the top surface 110a of the GaN buffer layer 110.
  • An emitter contact E is formed at an interface of the Aluminum Gallium Nitride barrier layer 112 with the Gallium Nitride buffer layer 110 above the first region 101 of the Gallium Nitride buffer layer 110.
  • the GaN power transistor 100 comprises a first p-type doped Gallium Nitride layer 113 deposited at the Aluminum Gallium Nitride barrier layer 112 above the second region 102 of the Gallium Nitride buffer layer 110.
  • the first p-type doped Gallium Nitride layer 113 forms a gate contact G of the Gallium Nitride power transistor 100.
  • the GaN power transistor 100 comprises a second p-type doped Gallium Nitride layer 114 deposited above the third region 103 of the Gallium Nitride buffer layer 110.
  • the second p- type doped Gallium Nitride layer 114 forms a collector contact C of the Gallium Nitride power transistor 100.
  • the second p-type doped Gallium Nitride layer 114 is deposited at the Aluminum Gallium Nitride barrier layer 112 within a recess 119 of the Aluminum Gallium Nitride barrier layer 112.
  • the difference to the first embodiment of Figure 1 is that the recess 119 is partially recessing the Aluminum Gallium Nitride barrier layer 112 without a total removement of the AIGaN barrier layer 112.
  • Fig. 4 shows a schematic cross section of the novel GaN power transistor 400 according to a fourth embodiment.
  • the GaN power transistor 400 is a novel GaN Field effect power transistor with conductivity modulation enhancement effect.
  • the structure of this novel GaN power transistor 400 causing this conductivity modulation enhancement effect is described in the following.
  • This fourth embodiment represents a device concept implementing an additional p-type implanting to increase electrical characteristics and suppress possible latch-up effects as described below.
  • this third embodiment of the GaN power transistor 300 is similar to any of the GaN power transistors 100, 200, 300 according to the first, second and third embodiments described above with respect to Figures 1 to 3.
  • the Aluminum Gallium Nitride barrier layer 112 and the Gallium Nitride buffer layer 110 comprise an additional p-type implantation at a region below the emitter contact and the gate contact. This additional p-type implant increases BV and suppresses possible latch-up effects.
  • Fig. 5 shows a performance diagram illustrating an example output characteristic 500 of the novel GaN power transistor versus a conventional pGaN Schottky HEMT with comparable dimensions.
  • GaN IGBT 501 shows lower on-state current at low collector-to-emitter voltages, when compared to the conventional GaN HEMT 502.
  • large improvement in the on-state conduction can be observed at higher collector-emitter voltages, thanks to the conductivity modulation of the channel.
  • Fig. 6 shows current-voltage diagram of an exemplary simulation of on-to-off transitions for the novel GaN power transistor as a function of the voltage applied to the gate electrode.
  • a first graph 601 shows the current in Amperes over the Collector-Emitter voltage in Volts for a gate voltage of zero volt applied to the gate electrode.
  • a second graph 602 shows the current in Amperes over the Collector-Emitter voltage in Volts for a gate voltage of minus five Volt applied to the gate electrode.
  • the Figure 6 shows one of the big advantages of the disclosed device concept. While, in conventional Silicon-based IGBT, the tail currents due to the slow recombination effects of the minority carriers in the drift regions strongly impact the switching speed of the device and its performance, in the newly presented device concept, the tail current can be almost completely eliminated thanks to the particular gate structure that is implemented.
  • the pGaN gate region allows for a fast depletion of the holes that have been injected into the drift region during the on-state conduction period.
  • the switching speed of the device can also be controlled.
  • Figure 6 shows, in particular, that when a negative gate voltage (in this example of -5V) is applied to the gate electrode, during the off-state period, holes can be faster depleted from the drift region and therefore the on-to-off transition period for the device becomes faster. In this way, the speed of the device can be electrically controlled just by varying the voltage applied to the gate electrode during off-state.
  • a negative gate voltage in this example of -5V
  • Fig. 7 shows an example process flow 700 for producing the novel GaN power transistor according to a first embodiment.
  • the main process steps can be summarized as follows: a) Starting epitaxial stack comprising a GaN buffer 110, an AIGaN barrier 112 and a GaN layer p-type doped 701 ; b) Sacrificial passivation deposition and structuring. This passivation layer is being used as masking layer 710 for subsequent trench etching process step. Following step is AIGaN barrier 112 trench etch (total, partial or even with overetching as described above with respect to Figures 1 to 3).
  • Hard-mask 710 is, afterwards, removed; c) pGaN 701 regrowth on blanket wafer; d) Hard-mask 711 deposition and structuring for gate and collector regions definition; e) pGaN 701 etching with stopping on AIGaN barrier 112 followed by hard-mask 711 removal; f) Contact formation (Gate G, Emitter E and Collector C) and final device passivation 118.
  • Fig. 8 shows an example process flow 800 for producing the novel GaN power transistor according to a second embodiment.
  • the process flow 800 depicted in Fig. 8 represents a small variation from the process flow 700 described above with respect to Figure 7.
  • the metal 810 for Gate, G and Collector, C contacts is deposited right after the pGaN 701 regrowth and prior to the pGaN 701 etching. Then, after hard-mask deposition and structuring, for the definition of the gate and collector regions, the metal layer 810 and the pGaN layer 701 are recessed contemporarily.
  • Fig. 9 shows an example process flow 900 for producing the novel GaN power transistor according to a third embodiment.
  • Figure 9 represents another alternative schematic process flow 900 to the process flows 700, 800 shown in Figures 7 and 8.
  • the main difference with respect to the process flows 700, 800 shown in Fig. 7 or in Fig. 8 is represented by the fact that the pGaN regions 113, 114 for the Gate, G and for the Collector, C are formed at two different steps of the process. This allows to tune independently the geometry and the doping of the two regions and give a higher degree of freedom for the final device optimization and electrical characteristics tailoring.
  • the process flows 700, 800, 900 can be described by a method for producing a Gallium Nitride power transistor 100, 200, 300, 400.
  • This method comprises the following steps: forming a Gallium Nitride buffer layer 110 comprising a top surface 110a and a bottom surface 110b opposing the top surface 110a, the Gallium Nitride buffer layer 110 comprising a first region 101 , a second region 102 and a third region 103 at the top surface 110a, e.g., as described above with respect to Figures 1 to 3; depositing an Aluminum Gallium Nitride barrier layer 112 at the top surface 110a of the Gallium Nitride buffer layer 110; depositing a first p-type doped Gallium Nitride layer 113 at the Aluminum Gallium Nitride barrier layer 112 above the second region 102 of the Gallium Nitride buffer layer 110, the first p-type doped Gallium Nitride layer 113 forming a gate contact of the Gallium Nitride power transistor 100; depositing a second p-
  • the above-described method may comprise the following method steps: depositing and structuring a first hard-mask layer 710 (see process step b) at the Aluminum Gallium Nitride barrier layer 112 to define the third region 103 of the Gallium Nitride buffer layer 110, e.g., as described above with respect to Figures 1 to 3; trench etching the Aluminum Gallium Nitride barrier layer 112 (see process step c) at the third region 103 of the Gallium Nitride buffer layer 110, e.g., as described above with respect to Figures 1 to 3; removing the first hard-mask layer 710; depositing a p-type doped Gallium Nitride layer 701 (see process step c) at the Aluminum Gallium Nitride barrier layer 112 and the Gallium Nitride buffer layer 110 exposed by the trench etching of the Aluminum Gallium Nitride barrier layer 112; depositing and structuring a second hard-mask layer 711 (see process step d) at the p-
  • a metal of the second metal layer 117 can be different from a metal of the third metal layer 116, e.g., when forming both metal layers 117, 116 in different process steps.
  • the metal of the second metal layer 117 can be the same as the metal of the third metal layer 116, e.g., when forming both metal layers 117, 116 in a single process step.
  • the first metal layer 115 (Emitter) can be formed in a process step prior to the forming of the second and third metal layers 117, 116 (Gate and Collector).
  • the first metal layer 115 (Emitter) can be formed in a process step after the forming of the second and third metal layers 117, 116 (Gate and Collector)
  • the above-described method may comprise the following method steps: depositing and structuring a first hard-mask layer 710 (see process step b) at the Aluminum Gallium Nitride barrier layer 112 to define the third region 103 of the Gallium Nitride buffer layer 110; trench etching the Aluminum Gallium Nitride barrier layer 112 (see process step b) at the third region 103 of the Gallium Nitride buffer layer 110; removing the first hard-mask layer 710 (see process step c); depositing a p-type doped Gallium Nitride layer 701 (see process step c) at the Aluminum Gallium Nitride barrier layer 112 and the Gallium Nitride buffer layer 110 exposed by the trench etching of the Aluminum Gallium Nitride barrier layer 112; forming a metal layer 810 (see process step e) at the p-type doped Gallium Nitride layer 701 ; depositing and structuring a second hard-mask layer 711 (see process step d) at the following method steps: depositing and structuri
  • the above-described method may comprise the following method steps: depositing a p-type doped Gallium Nitride layer 701 at the Aluminum Gallium Nitride barrier layer 112 (see process step a); depositing and structuring a first hard-mask layer 910 (see process step a) at the p-type doped Gallium Nitride layer 701 to define the second region 102 of the Gallium Nitride buffer layer 110; etching the p-type doped Gallium Nitride layer 701 (see process step b) outside the second region 102 of the Gallium Nitride buffer layer 110 to form the first p-type doped Gallium Nitride layer 113; depositing and structuring a second hard-mask layer 911 (see process step c) at the first p- type doped Gallium Nitride layer 102 and the Aluminum Gallium Nitride barrier layer 112 exposed by the etching of the p-type doped Gallium Nitride layer 701 to define the third region 103
  • a metal of the second metal layer 117 can be different from a metal of the third metal layer 116, e.g., when forming both metal layers 117, 116 in different process steps.
  • the metal of the second metal layer 117 can be the same as the metal of the third metal layer 116, e.g., when forming both metal layers 117, 116 in a single process step.
  • the first metal layer 115 (Emitter) can be formed in a process step prior to the forming of the second and third metal layers 117, 116 (Gate and Collector).
  • the first metal layer 115 (Emitter) can be formed in a process step after the forming of the second and third metal layers 117, 116 (Gate and Collector).
  • the metal can be deposited prior to the pGaN etching and the etching step can be done at the same time for the metal and the pGaN layer, i.e. similar as for the methods of claim 18 and 20.
  • the second pGaN can be deposited, then a window can be opened in the passivation that covers the first pGaN layer and then a common metal layer can be deposited for both pGaN1 and pGaN 2.
  • the metal etching can be performed.

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Abstract

La présente divulgation se rapporte à un transistor de puissance au nitrure de gallium (GaN) (100) comprenant : une couche tampon de nitrure de gallium (110) comprenant une surface supérieure et une surface inférieure, la couche tampon de nitrure de gallium comprenant une première région (101), une deuxième région (102) et une troisième région (103) au niveau de la surface supérieure ; une couche barrière en nitrure d'aluminium-gallium (112) déposée au niveau de la surface supérieure de la couche tampon de nitrure de gallium ; un contact d'émetteur formé au niveau d'une interface de la couche barrière de nitrure d'aluminium-gallium avec la couche tampon de nitrure de gallium au-dessus de la première région de la couche tampon de nitrure de gallium ; une première couche de nitrure de gallium dopée de type p (113) déposée au niveau de la couche barrière de nitrure d'aluminium-gallium au-dessus de la seconde région de la couche tampon de nitrure de gallium, la première couche de nitrure de gallium dopée de type p formant un contact de base du transistor de puissance au nitrure de gallium ; et une deuxième couche de nitrure de gallium dopée de type p (114) déposée au-dessus de la troisième région de la couche tampon de nitrure de gallium, la deuxième couche de nitrure de gallium dopée de type p formant un contact de collecteur du transistor de puissance au nitrure de gallium.
PCT/EP2021/086154 2021-12-16 2021-12-16 Transistor de puissance au nitrure de gallium et procédé de production d'un transistor de puissance gan WO2023110101A1 (fr)

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CN202180099908.0A CN117561607A (zh) 2021-12-16 2021-12-16 一种氮化镓功率晶体管和用于制造氮化镓功率晶体管的方法

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Citations (2)

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WO2018095931A2 (fr) * 2016-11-24 2018-05-31 Cambridge Enterprise Limited Transistor au nitrure de gallium
US20190280100A1 (en) * 2018-03-06 2019-09-12 Infineon Technologies Austria Ag High Electron Mobility Transistor with Dual Thickness Barrier Layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018095931A2 (fr) * 2016-11-24 2018-05-31 Cambridge Enterprise Limited Transistor au nitrure de gallium
US20190280100A1 (en) * 2018-03-06 2019-09-12 Infineon Technologies Austria Ag High Electron Mobility Transistor with Dual Thickness Barrier Layer

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OKITA HIDEYUKI ET AL: "Through Recess and Regrowth Gate Technology for Realizing Process Stability of GaN-Based Gate Injection Transistors", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE, USA, vol. 64, no. 3, 1 March 2017 (2017-03-01), pages 1026 - 1031, XP011641741, ISSN: 0018-9383, [retrieved on 20170223], DOI: 10.1109/TED.2017.2653847 *
WANG HAIYONG ET AL: "High-performance reverse blocking p-GaN HEMTs with recessed Schottky and p-GaN isolation blocks drain", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS, 2 HUNTINGTON QUADRANGLE, MELVILLE, NY 11747, vol. 119, no. 2, 15 July 2021 (2021-07-15), XP012258195, ISSN: 0003-6951, [retrieved on 20210715], DOI: 10.1063/5.0054370 *

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