WO2023110048A1 - Circuit de charge destiné à être utilisé dans un circuit amplificateur, circuit amplificateur et émetteur électro-optique - Google Patents

Circuit de charge destiné à être utilisé dans un circuit amplificateur, circuit amplificateur et émetteur électro-optique Download PDF

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Publication number
WO2023110048A1
WO2023110048A1 PCT/EP2021/085342 EP2021085342W WO2023110048A1 WO 2023110048 A1 WO2023110048 A1 WO 2023110048A1 EP 2021085342 W EP2021085342 W EP 2021085342W WO 2023110048 A1 WO2023110048 A1 WO 2023110048A1
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WO
WIPO (PCT)
Prior art keywords
circuit
terminal
transistor
load
branch
Prior art date
Application number
PCT/EP2021/085342
Other languages
English (en)
Inventor
Filippo SCHEMBARI
Claudio ASERO
Longfei ZHU
Original Assignee
Huawei Technologies Co., Ltd.
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Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/EP2021/085342 priority Critical patent/WO2023110048A1/fr
Publication of WO2023110048A1 publication Critical patent/WO2023110048A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45278—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using BiFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45394—Indexing scheme relating to differential amplifiers the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45691—Indexing scheme relating to differential amplifiers the LC comprising one or more transistors as active loading resistors

Definitions

  • the disclosure relates to a load circuit for use in an amplifier circuit, wherein the amplifier circuit comprises a transconductance circuit.
  • the disclosure further relates to an amplifier circuit comprising such a load circuit and a transconductance circuit.
  • the disclosure relates to an electro- optical transmitter comprising such an amplifier circuit.
  • the disclosure is in the field of amplifier circuits comprising a transconductance circuit and a load circuit.
  • Such amplifier circuits may be used in electrical devices for amplifying signals (voltages).
  • the main requirements for amplifier circuits for amplifying a signal may comprise introducing low distortion to the signal, providing a large output voltage swing, featuring a sufficiently wide bandwidth, featuring an impedance matched output so as to offer compatibility to a wide range of electrical loads.
  • an impedance matched output may mean that the output impedance of the amplifier is for example 50 Q for a single-ended topology or 100 Q for a differential topology.
  • FIG. 1 shows two examples of an amplifier circuit.
  • Each amplifier circuit 1 comprises a transconductance circuit 2 and a load circuit 3.
  • an amplifier circuit (voltage amplifier) may conceptually comprise two parts: a transconductance and a load.
  • Such amplifier circuits may be referred to as “transconductance amplifier circuits”.
  • the transconductance circuit 2 may comprise in its simplest form a single transistor.
  • the single transistor may be cascoded.
  • the load circuit 3 may be passive, e.g. comprising a resistor, or active, e.g. comprising a current source.
  • the current source may be implemented by a transistor.
  • the amplifier circuit 1 comprises an input, to which a signal to be amplified may be provided, an output for providing an amplified signal (i.e. the signal after being amplified) and a supply terminal 8 to which a supply voltage may be provided to the amplifier circuit 1.
  • the supply voltage may be referred to as the supply voltage of the amplifier circuit 1.
  • the amplifier circuit 1 on the left side of Figure 1 has a single-ended topology, i.e. it is a single-ended amplifier circuit 1.
  • the single-ended amplifier circuit 1 may comprise an input terminal IN and an output terminal OUT.
  • the amplifier circuit on the right side of Figure 1 has a differential topology, i.e. it is a differential amplifier circuit 1.
  • the differential amplifier circuit 1 may comprise two input terminals IN_a, IN_b and two output terminals OUT_a, OUT_b.
  • the amplifier circuit may be implemented as exemplarily shown in Figure 2.
  • the amplifier circuit of Figure 2 has a differential topology. This is only by way of example and, thus, the description with regard to Figure 2 is correspondingly valid for an amplifier circuit having a single-ended topology. Since the amplifier circuit 1 of Figure 2 has a differential topology it comprises two circuit branches. Thus, the transconductance circuit 2 and the load circuit 3 each have two circuit branches. As shown in Figure 2, each circuit branch of the load circuit 3 comprises a resistor RL and each circuit branch of the transconductance circuit 2 comprises two transistors T1 and T2 that are electrically connected in series.
  • a first terminal of the first transistor T1 of a respective circuit branch of the transconductance circuit 2 is electrically connected to a first terminal of the resistor RL of the respective circuit branch of the load circuit 3.
  • a second terminal of the resistor RL is electrically connected to a supply terminal of the load circuit 3 (and, thus, of the amplifier circuit 1).
  • a supply voltage VDD may be supplied to the supply terminal for electrically supplying the amplifier circuit 1.
  • the supply voltage VDD may be for example 3.3 V.
  • a second terminal of the first transistor T1 of the respective circuit branch is electrically connected to a first terminal of the second transistor T2 of the respective circuit branch.
  • a third terminal of the first transistor T1 of a first circuit branch of the two circuit branches of the transconductance circuit 2 may be electrically connected to a third terminal of the first transistor T1 of a second circuit branch of the two circuit branches of the transconductance circuit 2.
  • the third terminal of the first transistor T1 is a control terminal of the first transistor Tl.
  • a second terminal of the second transistor T2 of the respective circuit branch may be electrically connected to ground.
  • the third terminal of the second transistor T2 of the respective circuit branch may be connected to a respective input terminal of the amplifier circuit 1.
  • the third terminal of the second transistor T2 is a control terminal.
  • the node between the resistor RL and the first transistor Tl of the respective circuit branch may be electrically connected to a respective output terminal of the amplifier circuit 1.
  • the signal may be provided to the amplifier circuit 1 in the form of two input voltages VIN,P and VIN,M-
  • the amplifier circuit 1 may provide the amplified signal in the form of two output voltages VO,M and Vo,p.
  • the first transistors T1 may be implemented by bipolar junction transistor (BJTs), such as npn-type BJTs
  • the second transistors T2 may be implemented by metal-oxide- semiconductor field-effect transistors (MOSFETs), such as n-channel MOSFETs.
  • BJTs bipolar junction transistor
  • MOSFETs metal-oxide- semiconductor field-effect transistors
  • the transconductance circuit 2 may be implemented using different types of transistors.
  • the two second transistors T2 of the transconductance circuit 2 i.e. the transistors T2 of the input differential pair
  • the resistance of the resistor RL of the respective circuit branch of the load circuit 3 and, thus, of the amplifier circuit 1 may be referred to as load resistance.
  • the resistance of the resistor RL of each circuit branch of the load circuit 3 and, thus, of the amplifier circuit 1 may be set to e.g. 50 Q or close to 50 Q to ensure output impedance matching.
  • the topology of the amplifier circuit 1 of Figure 2 is not suitable for large output voltage swings. This is due to the voltage headroom taken by the two second transistors T2 (i.e. voltage headroom taken by the input differential pair of the amplifier circuit 1) and the two first transistors T1 (which may be referred to as cascode transistors).
  • FIG. 3 An improvement of the circuit topology of Figure 2 with regard to the output voltage swing is shown in Figure 3.
  • the amplifier circuit 1 of Figure 3 differs from the amplifier circuit 1 of Figure 2 with regard to the load circuit 3.
  • the above description with regard to Figure 2 is correspondingly valid for the amplifier circuit of Figure 3 and in the following mainly the difference between the amplifier circuit of Figure 2 and the amplifier circuit of Figure 3 is described.
  • the load circuit 3 of the amplifier circuit 1 of Figure 3 differs from the load circuit of Figure 2, in that the resistors RL are replaced by transistors T3.
  • the passive load circuit 3 of Figure 2 is replaced by an active load circuit 3, as shown in Figure 3.
  • the amplifier circuit 1 of Figure 3 offers a larger output voltage swing compared to the amplifier circuit 1 of Figure 2 because of replacing the passive load circuit 3 of the amplifier circuit 1 of Figure 2 with an active load circuit 3, as shown in Figure 3.
  • the active load circuit 3 of the amplifier circuit 1 of Figure 3 may be referred to as lumped current generator or lumped current source. This current generator (current source) is provided by the transistors T3 of the load circuit 3.
  • the amplifier circuit 1 of Figure 3 offers a larger output voltage swing compared to the amplifier circuit 1 of Figure 2, because, to the first order, the output DC common-mode voltage is not dictated by resistors of the load circuit 3 and the bias current IBIAS of the two circuit branches. It is also not dictated by the resistor RTERM that may be electrically connected between the second terminals of the two first transistors T1 of the transconductance circuit 2 of the amplifier circuit 1.
  • the resistor RTERM may be set to e.g. 100 Q or close to 100 Q to ensure output differential impedance matching.
  • the output DC common-mode voltage may be arbitrarily set to maximize the output voltage swing.
  • the DC commonmode voltage may be set half-way between the minimum voltage, which is possible at the collector terminal of the first transistors T1 before the first transistors T1 enter into the saturation region, and the maximum voltage, which is possible at the drain terminal of the transistors T3 of the load circuit 3 before the transistors T3 of the load circuit 3 enter into the triode region.
  • the output parasitic capacitance CPARI of the transistor T3 is rather big. Therefore, the amplifier circuit topology of Figure 3 exhibits worse bandwidth and worse output return loss compared to the amplifier circuit topology of Figure 2.
  • the present disclosure aims to provide an amplifier circuit that allows achieving a large output signal swing, a wide bandwidth, a low distortion and output impedance matching.
  • a further objective may be to provide an amplifier circuit that allows operating under the nominal voltage supply offered by the technology used for implementing the amplifier circuit.
  • a first aspect of the disclosure provides a load circuit for use in an amplifier circuit, wherein the amplifier circuit comprises a transconductance circuit.
  • the load circuit comprises a supply terminal and one circuit branch or two circuit branches.
  • Each circuit branch comprises two terminals.
  • each circuit branch comprises N inductive elements and N+l nodes, wherein N is one or more than one.
  • the N inductive elements and the N+l nodes are electrically connected in series between the two terminals, wherein any two successive nodes of the N+l nodes are electrically connected to each other via a respective inductive element of the N inductive elements.
  • each circuit branch comprises N+l transistors. Each of the N+l nodes is electrically connected to the supply terminal via a respective transistor of the N+l transistors.
  • the first aspect proposes replacing the single transistor of a respective circuit branch of the load circuit shown in Figure 3 by at least two transistors (i.e. N+l transistors).
  • the at least two transistors may be decoupled by a respective inductive element.
  • the load circuit of the first aspect allows achieving an amplifier circuit that has a large output signal swing, wide bandwidth, low distortion and output impedance matching, when the load circuit is used in the amplifier circuit.
  • the first aspect provides the advantage that the amplifier circuit may be operated under nominal voltage supply offered by the technology used for the amplifier circuit, when the load circuit of the first aspect is provided in the amplifier circuit.
  • the load circuit of the first aspect allows to improve the amplifier circuit of Figures 2 and 3 with regard to bandwidth and output return loss, when the load circuit is used in the amplifier circuit.
  • the load circuit of the first aspect replaces the load circuit of the amplifier circuit of Figure 3
  • the low bandwidth and poor output return loss of the amplifier circuit of Figure 3 may be overcome.
  • the load circuit of the first aspect is an active load circuit, as it is the case for the active load circuit of the amplifier circuit of Figure 3, the load circuit of the first aspect achieves the same advantages as the load circuit of Figure 3, described above, while improving the bandwidth and output return loss of the amplifier circuit when being used in the amplifier circuit as the load circuit.
  • the amplifier circuit may be referred to as “transconductance amplifier circuit”.
  • the amplifier circuit may be a driver amplifier. That is, the amplifier circuit may be configured to amplify a signal for driving another circuit, such as an optical modulator of an electro-optical transmitter.
  • the load circuit may be referred to as “active load circuit” or “active load”.
  • the N+l transistors of the load circuit may be referred to as “active load transistors”.
  • the N inductive elements may be referred to as “inductive decoupling elements”. Namely, a function of the N inductive elements is decoupling the N+l transistors.
  • Each transistor may act as or may be a current source.
  • the N+l transistors of the respective circuit branch may act as or may be a distributed current source of the respective circuit branch.
  • the N+l transistors of the respective circuit branch may act as or may be a distributed active load of the respective circuit branch. Since N is one or more than one, the N+l transistors may be referred to as two or more transistors. As mentioned, above N is one or more than one (N > 1). In other words, N is an integer that is greater or equal to one.
  • the number of transistors of a respective circuit branch is one more than the number of inductive elements of the respective circuit branch.
  • R1 is a ratio between channel width and channel length of the respective transistor and R2 is a ratio between channel width and channel length of a virtual single transistor that is suited for a supply voltage of the amplifier circuit.
  • a parasitic output capacitance of each transistor of the N+l transistors of the respective circuit branch may approximate to a parasitic output capacitance of the virtual single transistor divided by the number of the N+l transistors.
  • the above mentioned virtual single transistor may correspond to the single transistor (transistor T3) of a respective circuit branch of the load circuit of the amplifier circuit of Figure 3.
  • the virtual single transistor of a respective circuit branch of the load circuit may be split into N+l transistors.
  • the virtual single transistor represents a main bottleneck for an amplifier circuit, such as the amplifier circuit of Figure 3 in terms of bandwidth and output return loss.
  • each transistor of the N+l transistors may be of lower size and less weight compared to the virtual single transistor that may be heavy and of a larger size in order to be suited for the supply voltage of the amplifier circuit.
  • an output characteristic impedance of a respective circuit branch of the load circuit may be tuned to be as close as possible to a wanted impedance matching of for example 50 Q or close to 50 Q. In such way, both the bandwidth and output return loss of the amplifier circuit may be significantly improved.
  • each of the N+l transistors comprises a first terminal which is electrically connected with the supply terminal, a second terminal which is electrically connected with the respective node, and a third terminal which is a control terminal.
  • each respective transistor of the N+l transistors is one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate terminal as the third terminal; or a bipolar junction transistor (BJT) having a base terminal as the third terminal.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • BJT bipolar junction transistor
  • Each respective transistor of the N+l transistors may be a p-channel metal -oxide-semiconductor fieldeffect transistor (p-channel MOSFET), having a source terminal as the first terminal, a drain terminal as the second terminal and a gate terminal as the third terminal.
  • p-channel MOSFET metal -oxide-semiconductor fieldeffect transistor
  • each respective transistor of the N+l transistors may be a pnp-type bipolar junction transistor (pnp-type BJT), having an emitter terminal as the first terminal, a collector terminal as the second terminal, and a base terminal as the third terminal.
  • pnp-type BJT pnp-type bipolar junction transistor
  • each of the N inductive elements comprises an inductor or a transmission line.
  • the transmission line may be a micro-strip transmission line.
  • common electrical components may be used for decoupling the N+l transistors of the load circuit. This allows an easy and cheap production of the load circuit and, thus, amplifier circuit.
  • a characteristic impedance of a synthetic transmission line formed by the N inductive elements and parasitic capacitances of the N+l transistors is impedance matched to a load electrically connectable to a terminal of the two terminals.
  • the parasitic capacitances of the N+l transistors may be parasitic capacitances that are present at the N+l nodes due to the N+l transistors.
  • the parasitic capacitances may be parasitic capacitances asserting to each of the N+l nodes.
  • the parasitic capacitances of the N+l transistors may be referred to as parasitic output capacitances.
  • the transconductance circuit has a single-ended topology and the load circuit comprises the one circuit branch. Therefore, the load circuit may be used in a single- ended amplifier circuit and, thus, may improve bandwidth and output return loss of a single-ended topology.
  • the transconductance circuit has a differential topology and the load circuit comprises the two circuit branches. Therefore, the load circuit may be used in a differential amplifier circuit and, thus, may improve bandwidth and output return loss of a differential topology.
  • the load circuit may be integrated in different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • IC integrated circuit
  • BiCMOS bipolar complementary metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • SiC Silicon Carbide
  • III-V semiconductors such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • a second aspect of the disclosure provides an amplifier circuit comprising a transconductance circuit and the load circuit according to the first aspect, as described above.
  • the transconductance circuit and the load circuit are electrically connected with each other.
  • the transconductance circuit comprises one circuit branch or two circuit branches.
  • Each circuit branch of the transconductance circuit may comprise a first transistor and a second transistor electrically connected in series.
  • a first terminal of the first transistor may be electrically connected with a terminal of the two terminals of a respective circuit branch of the one or two circuit branches of the load circuit.
  • a second terminal of the first transistor may be electrically connected with a first terminal of the second transistor.
  • a control terminal of the second transistor may be electrically connected with an input terminal of the circuit branch of the transconductance circuit.
  • the first transistor of the circuit branch is one of the following: a bipolar junction transistor (BJT) having a base terminal as a third terminal, the base terminal being a control terminal; or a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate terminal as a third terminal, the gate terminal being a control terminal.
  • BJT bipolar junction transistor
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • common transistor types may be used for implementing the transconductance circuit of the amplifier circuit. That is, common technologies may be used for implementing the amplifier circuit. This allows an easy and cheap production of the amplifier circuit.
  • the first transistor of the circuit branch may be an npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal and an emitter terminal as the second terminal.
  • the first transistor of the circuit branch may be an n-channel metal-oxide-semiconductor field-effect transistor (n-channel MOSFET), having a drain terminal as the first terminal and a source terminal as the second terminal.
  • the second transistor of the circuit branch is one of the following: a bipolar junction transistor (BJT) having a base terminal as the control terminal; or a metal- oxide-semiconductor field-effect transistor (MOSFET) having a gate terminal as the control terminal.
  • BJT bipolar junction transistor
  • MOSFET metal- oxide-semiconductor field-effect transistor
  • common transistor types may be used for implementing the transconductance circuit of the amplifier circuit. That is, common technologies may be used for implementing the amplifier circuit. This allows an easy and cheap production of the amplifier circuit.
  • the second transistor of the circuit branch may be an npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal and a base terminal as the control terminal.
  • the second transistor of the circuit branch may be an n-channel metal-oxide- semiconductor field-effect transistor (n-channel MOSFET), having a drain as the first terminal and a gate terminal as the control terminal.
  • the transconductance circuit comprises the one circuit branch of the transconductance circuit and the load circuit comprises the one circuit branch of the load circuit.
  • a terminal of the two terminals of the circuit branch of the load circuit may be electrically connected with the first terminal of the first transistor of the circuit branch of the transconductance circuit, and a termination impedance may be electrically connected with the terminal of the two terminals of the circuit branch of the load circuit.
  • the transconductance circuit comprises the two circuit branches of the transconductance circuit and the load circuit comprises the two circuit branches of the load circuit.
  • a terminal of the two terminals of a first circuit branch of the two circuit branches of the load circuit may be electrically connected with the first terminal of the first transistor of a first circuit branch of the two circuit branches of the transconductance circuit.
  • a terminal of the two terminals of a second circuit branch of the two circuit branches of the load circuit may be electrically connected with the first terminal of the first transistor of a second circuit branch of the two circuit branches of the transconductance circuit.
  • a termination impedance may be electrically connected between the terminal of the two terminals of the first circuit branch of the load circuit and the terminal of the two terminals of the second circuit branch of the load circuit.
  • the amplifier circuit may be integrated in different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • IC integrated circuit
  • BiCMOS bipolar complementary metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • SiC Silicon Carbide
  • III-V semiconductors such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • the amplifier circuit of the second aspect and its implementation forms and optional features achieve the same advantages as the load circuit of the first aspect and its respective implementation forms and respective optional features.
  • a third aspect of the disclosure provides an electro-optical transmitter comprising an optical modulator, and an amplifier circuit according to the second aspect, as described above.
  • the amplifier circuit is configured to amplify a signal for driving the optical modulator.
  • the electro-optical transmitter of the third aspect and its implementation forms and optional features achieve the same advantages as the load circuit of the first aspect and its respective implementation forms and respective optional features.
  • Figure 1 shows two examples of an amplifier circuit
  • Figure 2 shows an example of an amplifier circuit
  • Figure 3 shows an example of an amplifier circuit
  • Figure 4 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit
  • Figure 5 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit
  • Figure 6 shows an amplifier circuit according to an embodiment of the present disclosure
  • Figure 7 shows an amplifier circuit according to an embodiment of the present disclosure
  • Figure 8 shows an amplifier circuit according to an embodiment of the present disclosure
  • Figure 9 shows an example of a part of a load circuit according to an embodiment of the present disclosure.
  • Figure 10 shows an example of an equivalent circuit for a load circuit according to an embodiment of the present disclosure
  • Figure 11 shows an example of total harmonic distortion versus peak-to-peak differential output voltage for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and a differential amplifier circuit according the second aspect of the present disclosure
  • Figure 12 shows an example of normalized gain versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure
  • Figure 13 shows an example of output return loss versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure
  • Figure 14 shows an example of an electro-optical transmitter according to an embodiment of the present disclosure.
  • Figure 4 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit.
  • the load circuit of Figure 4 is an example of the load circuit according to the first aspect.
  • the above description of the load circuit according to the first aspect is correspondingly valid for the load circuit of Figure 4.
  • the load circuit 3 comprises a supply terminal 8 and one circuit branch 3a.
  • a supply voltage VDD may be provided to the supply terminal 8.
  • the circuit branch 3 a comprises two terminals 5a and 5a’, N inductive elements 6, N+l nodes 7 and N+l transistors 4.
  • N is one or more than one (N > 1).
  • the N inductive elements 6 and N+l nodes 7 are electrically connected in series between the two terminals 5a and 5a’, wherein any two successive nodes of the N+l nodes are electrically connected to each other via a respective inductive element 6 of the N inductive elements 6.
  • Each node of the N+l nodes 7 is electrically connected to the supply terminal 8 via a respective transistor of the N+l transistors 4.
  • the circuit branch 3a comprises two inductive elements 6, three nodes 7 and three transistors 4. This is only by way of example and not limiting the present disclosure.
  • each inductive element of the N inductive elements 6 may be or may comprise an inductor or a transmission line.
  • each inductive element may be or may comprise a microstrip transmission line.
  • each transistor of the N+l transistors 4 comprises a first terminal 4a which is electrically connected with the supply terminal 8, a second terminal 4b which is electrically connected with the respective node 7 and a third terminal 4c which is a control terminal.
  • each transistor of the N+l transistors 4 is a p-channel metal-oxide-semiconductor fieldeffect transistor (p-channel MOSFET) having a source terminal as the first terminal 4a, a drain terminal as the second terminal 4b and a gate terminal as the third terminal (control terminal).
  • p-channel MOSFET metal-oxide-semiconductor fieldeffect transistor
  • each of the N+l transistors 4 may be a pnp-type bipolar junction transistor (pnp-type BJT), having an emitter terminal as the first terminal 4a, a collector terminal as the second terminal 4b, and a base terminal as the third terminal 4c.
  • the transistors 4 may be implemented according to different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • IC integrated circuit
  • BiCMOS bipolar complementary metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • SiC Silicon Carbide
  • III-V semiconductors such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • GaAs Gallium Arsenide
  • GaN Gallium Nitride
  • the load circuit 3 of Figure 4 is an active load circuit.
  • the circuit branch 3a of the load circuit 3 of Figure 4 differs from each circuit branch of the active load circuit 3 of Figure 3 in that the single transistor T3 of the respective circuit branch of the load circuit 3 of Figure 3 is replaced by N+l transistors 4 that are decoupled from each other by N decoupling elements 6.
  • Each of the N+l transistors 4 contributes to a parasitic capacitance CPAR-
  • the parasitic capacitance CPAR of the respective transistor 4 comprises the intrinsic drain capacitance of the respective transistor 4, the capacitance between the drain and source terminal of the respective transistor 4, the capacitance between the drain and gate terminal of the respective transistor 4, and the parasitic capacitance of the layout interconnects of the respective transistor 4.
  • the load circuit of Figure 4 may be used in an amplifier circuit having a single-ended topology.
  • An example of an amplifier circuit having a single-ended topology is shown in Figure 6.
  • FIG. 5 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit.
  • the load circuit 3 of Figure 5 differs from the load circuit 3 of Figure 4 in that the load circuit 3 of Figure 5 comprises two circuit branches 3a and 3b, whereas the load circuit 3 of Figure 4 comprises one circuit branch 3a.
  • the above description of the load circuit 3 of Figure 4 is correspondingly valid for the load circuit 3 of Figure 5.
  • the description of the circuit branch 3a of the load circuit 3 of Figure 4 is valid for each circuit branch 3a or 3b of the load circuit 3 of Figure 5.
  • a first circuit branch 3a of the two circuit branches 3a and 3b of the load circuit 3 comprises two terminals 5a and 5a’, N inductive elements 6, N+l nodes 7 and N+l transistors 4, wherein N is one or more than one.
  • the N inductive elements 6 and the N+l nodes 7 are electrically connected in series between the two terminals 5a and 5a’, as shown in Figure 5.
  • a second circuit branch 3b of the two circuit branches 3a and 3b of the load circuit 3 comprises two terminals 5b and 5b’, N inductive elements 6, N+l nodes 7 and N+l transistors 4, wherein N is one or more than one.
  • the N inductive elements 6 and the N+l nodes 7 are electrically connected in series between the two terminals 5b and 5b’, as shown in Figure 5.
  • the load circuit of Figure 5 may be used in an amplifier circuit having a differential topology. Examples of an amplifier circuit having a differential topology are shown in Figures 7 and 8.
  • Figure 6 shows an amplifier circuit according to an embodiment of the present disclosure.
  • the amplifier circuit of Figure 6 is an example of the amplifier circuit according to the second aspect.
  • the above description of the amplifier circuit according to the second aspect is correspondingly valid for the amplifier circuit of Figure 6.
  • the amplifier circuit 1 comprises a transconductance circuit 2 and a load circuit 3 that are electrically connected with each other.
  • the amplifier circuit 1 has a single-ended topology and, thus, the transconductance circuit 2 comprises one circuit branch 2a and the load circuit 3 comprises one circuit branch 3a.
  • the amplifier circuit 1 comprises one circuit branch.
  • the load circuit 3 of the amplifier circuit 1 of Figure 6 corresponds to the load circuit 3 of Figure 4 and, thus, the above description of Figure 4 is valid for the load circuit 3 of the amplifier circuit 1 of Figure 6.
  • the circuit branch 2a of the transconductance circuit 2 may comprise a first transistor 9 and a second transistor 10 electrically connected in series.
  • a first terminal 9a of the first transistor 9 is electrically connected with a terminal 5a’ of the two terminals 5a and 5a’ of the circuit branch 3a of the load circuit 3.
  • a second terminal 9b of the first transistor 9 is electrically connected with a first terminal 10a of the second transistor 10.
  • a control terminal 10c of the second transistor 10 is electrically connected with an input terminal I la of the circuit branch 2a of the transconductance circuit 2.
  • the input terminal I la represents an input terminal of the amplifier circuit 1.
  • a signal (voltage) may be applied to the input terminal I la in order to be amplified.
  • the supply terminal 8 of the load circuit 3 represents a supply terminal of the amplifier 1.
  • a supply voltage VDD may be applied to the supply terminal 8 in order to electrically supply the amplifier circuit 1 enabling the amplification function of the amplifier circuit 1.
  • a second terminal 10b of the second transistor 10 may be electrically connected to ground.
  • the terminal 5a of the two terminals 5a and 5a’ of the circuit branch 3a of the load circuit 3 may be electrically connected to or may represent an output terminal of the amplifier circuit 1.
  • the terminal 5 a is a terminal of the two terminals 5a and 5a’ of the circuit branch 3a of the load circuit 3, to which the transconductance circuit 2 is not electrically connected.
  • an amplified signal (amplified voltage) may be provided, which corresponds to the signal (voltage), applied to the input terminal of the amplifier circuit 1 , after being amplified by the amplifier circuit 1.
  • the amplification function of the amplifier circuit 1 may be controlled by applying control signals to the control terminals of the N+l transistors 4 of the load circuit 3 and a control terminal 9c of the first transistor T1 of the circuit branch 2a of the transconductance circuit 2. Such a control is known and, thus, not further described herein.
  • the control terminal 9c of the first transistor T1 may be electrically connected to a DC bias voltage VCASC-
  • the present disclosure focuses on the structure of the amplifier circuits enabling an amplifier circuit with the above described advantages.
  • the control terminal 9c of the first transistor 9 is a third terminal of the first transistor 9.
  • the control terminal 10c of the second transistor 10 is a third terminal of the second transistor 10.
  • the first transistor 9 of the circuit branch 2a of the transconductance circuit 2 is a npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal 9a, an emitter terminal as the second terminal 9b, and a base terminal as the control terminal 9c (third terminal).
  • npn-type BJT npn-type bipolar junction transistor
  • the first transistor 9 may be implemented by a different transistor type.
  • the first transistor 9 of the circuit branch 2a of the transconductance circuit 2 may be an n-channel metal- oxide-semiconductor field-effect transistor (n-channel MOSFET), having a drain terminal as the first terminal 9a, a source terminal as the second terminal 9b and a gate terminal as the control terminal 9c (third terminal).
  • n-channel MOSFET metal- oxide-semiconductor field-effect transistor
  • the second transistor 10 of the circuit branch 2a of the transconductance circuit 2 is an n-channel metal-oxide-semiconductor field-effect transistor (n-channel MOSFET), having a drain as the first terminal 10a, a source as the second terminal 10b and a gate terminal as the control terminal 10c (third terminal).
  • n-channel MOSFET metal-oxide-semiconductor field-effect transistor
  • the second transistor 10 may be implemented by a different transistor type.
  • the second transistor 10 of the circuit branch 2a of the transconductance circuit 2 may be an npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal 10a, an emitter terminal as the second terminal 10b and a base terminal as the control terminal 10c (third terminal).
  • npn-type BJT npn-type bipolar junction transistor
  • the first transistor 9 and the second transistor 10 of the circuit branch 2a of the transconductance circuit 2 may be implemented according to different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • IC integrated circuit
  • BiCMOS bipolar complementary metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • SiC Silicon Carbide
  • III-V semiconductors such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • the transistors of the amplifier circuit 1 comprising the first transistor 9 and second transistor 10 of the circuit branch 2a and the N+l transistors 4 of the load circuit 3 may be implemented according to different integrated circuit (IC) complementary technologies including (but not limited to) the aforementioned technologies.
  • a termination impedance 12 may be electrically connected with the terminal 5a’ of the two terminals 5, 5a’of the circuit branch 3a of the load circuit 3.
  • a series connection of a capacitor 13 and the termination impedance 12 may be electrically connected to the terminal 5 a’ of the circuit branch 3 a of the load circuit 3.
  • FIG. 7 shows an amplifier circuit according to an embodiment of the present disclosure.
  • the amplifier circuit 1 of Figure 7 differs from the amplifier circuit 1 of Figure 6 in that the amplifier circuit 1 of Figure 7 has a differential topology, whereas the amplifier circuit 1 of Figure 6 has a single-ended topology. Therefore, the transconductance circuit 2 of the amplifier circuit 1 of Figure 7 comprises two circuit branches 2a and 2b, whereas the transconductance circuit 2 of the amplifier circuit 1 of Figure 6 comprises one circuit branch 2a.
  • the above description of the transconductance circuit 2 of Figure 6 is correspondingly valid for the transconductance circuit 2 of Figure 7.
  • the description of the circuit branch 2a of the transconductance circuit 2 of Figure 6 is valid for each circuit branch 2a and 2b of the transconductance circuit 2 of Figure 7.
  • the load circuit 3 of Figure 7 corresponds to the load circuit 3 of Figure 5 and, thus, the above description of Figures 4 and 5 is valid for the load circuit 3 of the amplifier circuit 1 of Figure 7.
  • a first circuit branch 2a of the two circuit branches 2a and 2b of the transconductance circuit 2 comprises a first transistor 9 and a second transistor 10 electrically connected in series.
  • the first terminal of the first transistor 9 of the first circuit branch 2a is electrically connected to a terminal 5a’ of the two terminals 5a, 5a’ of a first circuit branch 3a of the two circuit branches 3a and 3b of the load circuit 3.
  • a second circuit branch 2b of the two circuit branches 2a and 2b of the transconductance circuit 2 comprises a first transistor 9 and a second transistor 10 electrically connected in series.
  • the first terminal of the first transistor 9 of the second circuit branch 2b is electrically connected to a terminal 5b’ of the two terminals 5b and 5b’ of a second circuit branch 3b of the two circuit branches 3a and 3b of the load circuit 3.
  • a control terminal of the second transistor 10 of the first circuit branch 2a is electrically connected with an input terminal 1 la of the first circuit branch 2a of the transconductance circuit 2.
  • a control terminal of the second transistor 10 of the second circuit branch 2b is electrically connected with an input terminal 11b of the second circuit branch 2b of the transconductance circuit 2.
  • the two input terminals I la and 11b represent input terminals of the amplifier circuit 1 having a differential topology.
  • a signal (voltage) may be applied to the amplifier circuit 1 for amplification by applying respective voltages to the input terminals I la and 11b.
  • the signal may be input to the amplifier circuit 1 by applying voltages VIN,P and VIN,M to the input terminals Ila and 11b, respectively.
  • the terminal 5a of the first circuit branch 3 a of the load circuit 3 may be electrically connected with or may represent a first output terminal of the amplifier circuit 1.
  • the terminal 5b of the second circuit branch 3b of the load circuit 3 may be electrically connected with or may represent a second output terminal of the amplifier circuit 1.
  • the terminals 5a and 5b of the load circuit 3 are terminals to which the transconductance circuit 2 is not electrically connected.
  • an amplified signal (amplified voltage) may be provided, which corresponds to the signal (voltage), applied to the input terminals I la and 11b of the amplifier circuit 1, after being amplified by the amplifier circuit 1.
  • the amplified signal may be provided at the output terminals of the amplifier circuit 1 by providing voltages VO,M and Vo,p at the terminals 5a and 5b of the load circuit 3, respectively.
  • a termination impedance 14 may be electrically connected between the terminal 5a’ of the first circuit branch 3a of the load circuit 3 and the terminal 5b’ of the second circuit branch 3b of the load circuit 3.
  • each of the N inductance elements 6 of each circuit branch 3a and 3b of the load circuit 3 may comprise or may be a transmission line (not shown in Figure 7).
  • each of the N inductance elements 6 may comprise or may be a micro-strip transmission line. This is only by way of example and, thus, the N inductance elements 6 of each circuit branch 3a and 3b may be differently implemented.
  • each of the N inductance elements 6 of each circuit branch 3a and 3b of the load circuit 3 may comprise or may be an inductor.
  • Figure 8 shows an amplifier circuit according to an embodiment of the present disclosure.
  • the amplifier circuit 1 of Figure 8 differs from the amplifier circuit 1 of Figure 7 in that the first transistor 9 of each circuit branch 2a and 2b of the transconductance circuit 2 is a MOSFET, whereas according to the example of Figure 7 the first transistor 9 of each circuit branch 2a and 2b of the transconductance circuit 2 is a BJT. Therefore, the above description of Figures 6 and 7 is correspondingly valid for the amplifier circuit 1 of Figure 8.
  • the circuit branch 2a of the transconductance circuit 2 of the amplifier circuit 1 of Figure 6 and each of the circuit branches 2a and 2b of the transconductance circuit 2 of the circuit amplifier circuit 1 of Figures 7 and 8 comprise cascoded transconductors in the form of the first transistor 9 and the second transistor 10.
  • an input differential pair of the amplifier circuit is formed by the second transistors 10, which are by way of example n-channel MOSFETs.
  • the control terminals (e.g. gate terminals) of these second transistors 10 are connected to the input terminals I la and 11b of the transconductance circuit 2 and, thus, of the amplifier circuit 1.
  • complementary input signals (voltages) for the amplifier circuit 1 may be applied.
  • IBIAS/2 represents the bias current of each of the two circuit branches 2a and 2b of the transconductance circuit 2.
  • This bias current IBIAS/2 may be set by providing a proper input DC commonmode voltage to the amplifier circuit 1 (i.e. to the input terminals I la and 1 lb).
  • the two first transistors 9 of the two circuit branches 2a and 2b of the transconductance circuit 2 of Figures 7 and 8 represent cascodes, whose control terminals 9c may be biased at a voltage VCASC-
  • the termination impedance 14, which is differential in the examples of Figures 7 and 8, may be set to e.g. 100 Q or close to 100 Q in order to ensure differential output impedance matching from low frequency.
  • each circuit branch 3a and 3b of the load circuit 3 comprises N+l transistors 4, each of which is N+l -times smaller than the single transistor T3 of each circuit branch of the load circuit 3 of the amplifier circuit 1 of Figure 3.
  • Each of the N+l transistors 4 of a respective circuit branch may comprise an aspect ratio of (W S /L S )/(N+1), where W s and L s denote the channel width and the channel length of the transistor T3 of the respective circuit branch of the amplifier circuit 1 of Figure 3, respectively.
  • the total bias current carried by all of the N+l respective transistors 4 within each of the two circuit branches 3a and 3b of the load circuit 3 is equal to IBIAS/2.
  • This bias current IBIAS/2 may be set by providing a proper DC voltage VGEN to the control terminals of the N+l transistors 4 of the circuit branches 3a and 3b of the load circuit 3.
  • the N+l transistors 4 of each circuit branch 3a and 3b of the load circuit 3 are separated or decoupled by inductive elements 6 (may be referred to as inductive decoupling elements), which may be for example transmission lines or inductors.
  • inductive decoupling elements may be for example transmission lines or inductors.
  • transmission line segment may be used as a synonym for the term “transmission line”.
  • Figure 9 shows an example of a part of a load circuit according to an embodiment of the present disclosure.
  • Figure 9 exemplarily shows the part of the N inductive elements and N+l nodes of a circuit branch of a load circuit according to an embodiment of the disclosure.
  • This circuit branch may correspond to the circuit branch 3a of the load circuit 3 of Figures 4 and 6 or each of the two circuit branches 3a and 3b of the load circuit 3 of Figures 5, 7 and 8.
  • N may be one or greater than one (N > 1).
  • the inductive elements 6 are transmission lines, each with length f and specific inductance L’ (i.e. inductance per unit length).
  • L specific inductance
  • the N+l transistors 4 and the transmission lines 6 form a “synthetic” transmission line with a single-ended characteristic impedance Zo equal to:
  • the single-ended characteristic impedance Zo of the respective circuit branch of the load circuit 3 may be made sufficiently high.
  • the total length of the synthetic transmission line i.e. of the distributed active load circuit formed by the N+l transistors 4, N inductive elements 6 and N+l nodes 7 of a respective circuit branch of the load circuit 3
  • NT the product of the synthetic transmission line
  • the number of inductive elements i.e. transmission lines in case of Figure 9
  • the N+l transistors are much smaller than a transmission line segment.
  • the distributed active load circuit may be referred to as distributed current source or distributed current generator.
  • the single-ended characteristic impedance Zo of the respective circuit branch of the load circuit 3 may be made as close as possible to 50 Q single-ended. This allows to significantly improve in the amplifier circuits of Figures 6, 7 and 8 both the output return loss and the bandwidth of the respective amplifier circuit topology.
  • the N+l transistors 4 of each circuit branch of the load circuit 3 are separated by inductors instead of transmission lines (i.e. the N inductive elements are inductors).
  • the N+l transistors 4 and the inductors 6 form a “synthetic” transmission line with a single-ended characteristic impedance Zo equal to: wherein Lo is the inductance of each of the N inductors 6 between adjacent transistors of the N+l transistors 4.
  • inductors, instead of transmission lines, as inductive elements 4 contributes to form a synthetic transmission line together with the N+l transistors 4.
  • Figure 10 shows an example of an equivalent circuit for a load circuit according to an embodiment of the present disclosure.
  • the load circuit 3 is part of an amplifier circuit comprising a transconductance circuit 2, such as the amplifier circuit of e.g. Figure 7.
  • an external load 19 is connected to the amplifier circuit and, thus, to the load circuit 3, wherein the external load 19 has an external load impedance ROUT- AS shown in Figure 10 (a)
  • the more the characteristic impedance Zo of the synthetic transmission line (which may be formed either by the N+l transistors 4 and N transmission lines 6 as shown in Figure 9 or N+l transistors 4 and N inductors 6) is closer to 50 Q, the lesser the impact of CPARI is on the load circuit 3.
  • the impedance seen by the transconductance circuit 2 may be the external load impedance ROUT of the external load 19.
  • the (internal) load circuit 3 would be practically almost ideal.
  • the load circuit 3 would be practically invisible for the transconductance circuit 2 (from a viewpoint towards the external load 19). That is, for the transconductance circuit 2, the load circuit 3 does not represent an additional external load in addition to the actual external load 19.
  • the output time constant may be much lower than the time constant of the load circuit 3 of Figure 3 (i.e. ROUT’CPARI) or, in other terms that the bandwidth of the amplifier circuit 1 according to Figures 6, 7 and 8 may be wider compared to the bandwidth of the amplifier circuit 1 of Figure 3.
  • the amplifier circuit’s differential output impedance Zour.diff may be equal to the internal differential termination RTERM, without any impact from CPARI, thus resulting in an ideally perfect output return loss.
  • Zo will not be perfectly matched to RTER /2 and ROUT (e.g. close to 50 Q) and, thus, the amplifier circuit’s bandwidth and output return loss will not be infinitely wide and low, respectively.
  • the bandwidth and output return loss of the amplifier circuit 1 of Figures 6, 7 and 8 significantly enhance those of the amplifier circuits of Figures 2 and 3. This is also shown in Figures 12 and 13
  • the desired impedance matching may be for example impedance matching of 50 Q or close to 50 Q. In such way, both the amplifier circuit’s bandwidth and output return loss significantly improves.
  • the load circuits and amplifier circuits according to the present disclosure allow operating under a nominal supply voltage (e.g. 3.3V in 55nm BiCMOS). Therefore, the topologies of the load circuits 3 and, thus, amplifier circuits 1 shown in Figures 4 to 8 do not introduce penalty in terms of power consumption and, moreover, they do not require the use of an additional (higher) supply voltage, which may not even be available within a system in which the load circuit or the amplifier circuit is used. In addition, the load circuits and amplifier circuits according to the present disclosure feature low design complexity.
  • a nominal supply voltage e.g. 3.3V in 55nm BiCMOS
  • the performance of the amplifier circuits of Figures 2 and 3 and the amplifier circuit of e.g. Figure 7 is compared.
  • the transistors of the transconductance circuits 2 are identical among the three topologies.
  • the three topologies (of Figure 2, 3 and 7) being compared are assumed to exhibit the same voltage gain.
  • Figure 11 shows an example of total harmonic distortion versus peak-to-peak differential output voltage for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and a differential amplifier circuit according the second aspect of the present disclosure.
  • the line LI (having squares) shows the performance of the amplifier circuit of Figure 2
  • the line L2 (having triangles) shows the performance of the amplifier circuit of Figure 3 and the amplifier circuit of Figure 7.
  • FIG 11 shows the total harmonic distortion (THD) versus the output peak-to-peak differential voltage amplitude for a differential input sinewave at e.g. 1GHz.
  • the amplifier circuit of Figure 3 and the amplifier circuit of Figure 7 perform equally, given that they exhibit the same output voltage range. They appreciably outperform the amplifier circuit of Figure 2. For example, they exhibit about 7% lower THD at 3.5VPPD output (where “VPPD” stands for “Volt peak-to-peak differential”) or, for the same THD of 3.2%, they ensure a 1.3VPPD larger output signal.
  • Figure 12 shows an example of normalized gain versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure.
  • the line LI (having squares) shows the performance of the amplifier circuit of Figure 2
  • the line L2 (having diamonds) shows the performance of the amplifier circuit of Figure 3
  • the line L3 (having triangles) shows the performance of the amplifier circuit of Figure 7.
  • Figure 12 shows the three normalized transfer functions (normalized in terms of their gain at 1GHz, set to OdB for the sake of illustration).
  • the detrimental effect of the big parasitic capacitance CPARI of the transistors T3 of the load circuit 3 of the amplifier circuit 1 of Figure 3 is visible in the form of a very narrow-band transfer function, which presents a -3dB bandwidth of nearly 17GHz (and 30GHz at -6dB).
  • the load circuit 3 of the amplifier circuit 1 of Figure 7 significantly enhances the bandwidth performance of the amplifier circuit of Figure 3, reaching a -3dB bandwidth of about 57GHz (and 98GHz at -6dB).
  • the amplifier circuit of Figure 7 also outperforms the amplifier circuit of Figure 2 with regard to bandwidth. Because of the aforementioned reason, the output return loss of the amplifier circuit of Figure 7 is also significantly better than that of the amplifier circuits of Figures 2 and 3, as shown in Figure 13.
  • Figure 13 shows an example of output return loss versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure.
  • the line LI (having squares) shows the performance of the amplifier circuit of Figure 2
  • the line L2 (having diamonds) shows the performance of the amplifier circuit of Figure 3
  • the line L3 (having triangles) shows the performance of the amplifier circuit of Figure 7.
  • the load circuit proposed by the present disclosure allows increasing the output voltage swing of an amplifier circuit, such as the amplifier circuit of Figure 2 or 3, for a given total harmonic distortion when the load circuit of the present disclosure is used in the amplifier circuit. Moreover, using the load circuit in an amplifier circuit, such as the amplifier circuit of Figure 2 or 3, has no penalties in terms of bandwidth, output impedance matching and power consumption.
  • FIG 14 shows an example of an electro-optical transmitter according to an embodiment of the present disclosure.
  • the electro-optical transmitter 15 comprises an amplifier circuit 1 and an optical modulator 18, wherein the amplifier circuit 1 is configured to amplify a signal for driving the optical modulator 18.
  • the amplifier circuit 1 is an amplifier circuit according to the second aspect of the present disclosure.
  • the amplifier circuit 1 may be implemented in line with the description of Figures 6, 7 and 8. Since the amplifier circuit 1 is used in the electro-optical transmitter 15 for amplifying a driver signal for driving the optical modulator 18, the amplifier circuit 1 is a driver amplifier. As shown in Figure 14 the amplifier circuit 1 may be part of an analog integrated circuit 17 (analog IC).
  • the analog IC 17 and, thus, the amplifier circuit 1 may be implemented using different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).
  • the optical modulator 18 may be a Mach-Zehnder modulator (MZM), such as a silicon photonics (SiPh) MZM, an electroabsorption modulated laser (EML) or any other known optical modulator.
  • MZM Mach-Zehnder modulator
  • SiPh silicon photonics
  • EML electroabsorption modulated laser
  • the electro-optical transmitter 15 may comprise an optional digital integrated circuit 16 (digital IC).
  • the digital IC 16 may provide an analog signal to the amplifier circuit 1 for being amplified so that the amplifier circuit 1 may output the amplified analog signal as a signal for driving the optical modulator 18.
  • the digital IC 16 may comprise a digital signal processor 16a (DSP) and a digital-to-analog- con verter 16b (DAC).
  • DSP digital signal processor
  • DAC digital-to-analog- con verter 16b
  • the electro-optical transmitter 15 is an example of a radio-frequency integrated circuit.
  • the amplifier circuit 1 of the present disclosure e.g. the amplifier circuit 1 of Figures 6 to 8 may be used in radio-frequency integrated circuits (RFIC).
  • the amplifier circuit 1 of the present disclosure may represent a broadband amplifier circuit for optical and wireline communications.
  • the ever increasing demand for high data-rates in wireline, wireless and optical communications requests RFICs with broader signal bandwidths.
  • the increasing complexity of data modulation schemes further demands high quality signals without penalty in terms of power consumption.
  • the driver amplifier i.e. the amplifier circuit
  • the amplifier circuit plays a critical role. Namely, the amplifier circuit may represent the interface between the digital domain (e.g.
  • the amplifier circuit of the present disclosure is suitable to be used radio-frequency integrated circuits (RFIC), e.g. in electro-optical transmitters.
  • RFIC radio-frequency integrated circuits
  • the amplifier circuit of the present disclosure may feature an impedance matched output (e.g. 50 Q or close to 50 Q in case of a single-ended topology of the amplifier circuit or e.g. 100 Q or close to 100 Q in case of a differential topology of the amplifier circuit) so as to offer compatibility to a wide range of optical modulators.
  • an impedance matched output e.g. 50 Q or close to 50 Q in case of a single-ended topology of the amplifier circuit or e.g. 100 Q or close to 100 Q in case of a differential topology of the amplifier circuit
  • the amplifier topologies proposed by the present disclosure are suitable for broadband fully-integrated optical modulators and wireline driver amplifiers requiring low distortion, large output signal swing and output impedancematching.

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  • Amplifiers (AREA)

Abstract

La présente divulgation concerne un circuit de charge (3) destiné à être utilisé dans un circuit amplificateur (1). Le circuit amplificateur (1) comprend un circuit de transconductance (2). Le circuit de charge (3) comprend une branche de circuit (3a) ou deux branches de circuit (3a, 3b). Chaque branche de circuit comprend : deux bornes (5a, 5a' ; 5b, 5b'), N éléments inductifs (6) et N+1 nœuds (7) et N+1 transistors (4), N étant un ou plus. Les N éléments inductifs (6) et les N+1 nœuds (7) sont connectés électriquement en série entre les deux bornes (5a, 5a' ; 5b, 5b'), deux nœuds successifs des N+1 nœuds (7) étant reliés électriquement l'un à l'autre par l'intermédiaire d'un élément inductif respectif des N éléments inductifs (6). Chacun des N+1 nœuds (7) est connecté électriquement à la borne d'alimentation (8) par l'intermédiaire d'un transistor respectif des N+1 transistors (4).
PCT/EP2021/085342 2021-12-13 2021-12-13 Circuit de charge destiné à être utilisé dans un circuit amplificateur, circuit amplificateur et émetteur électro-optique WO2023110048A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP2021/085342 WO2023110048A1 (fr) 2021-12-13 2021-12-13 Circuit de charge destiné à être utilisé dans un circuit amplificateur, circuit amplificateur et émetteur électro-optique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2021/085342 WO2023110048A1 (fr) 2021-12-13 2021-12-13 Circuit de charge destiné à être utilisé dans un circuit amplificateur, circuit amplificateur et émetteur électro-optique

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WO2023110048A1 true WO2023110048A1 (fr) 2023-06-22

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Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
CHEN W-S ET AL: "CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 40, no. 2, 1 February 2005 (2005-02-01), pages 548 - 552, XP011126092, ISSN: 0018-9200, DOI: 10.1109/JSSC.2004.840979 *
HEE-TAE AHN ET AL: "A 0.5-8.5-GHz Fully Differential CMOS Distributed Amplifier", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 37, no. 8, 1 August 2002 (2002-08-01), XP011065808, ISSN: 0018-9200 *
KIMIA T ANSARI ET AL: "A low-power 0.4-22GHz CMOS cascode distributed amplifier for optical communication systems", ELECTRONICS, CIRCUITS, AND SYSTEMS, 2009. ICECS 2009. 16TH IEEE INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 13 December 2009 (2009-12-13), pages 387 - 390, XP031626312, ISBN: 978-1-4244-5090-9 *
MOEZ K K ET AL: "A novel loss compensation technique for broadband CMOS distributed amplifiers", 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS 21-24 MAY 2006 ISLAND OF KOS, GREECE, IEEE - PISCATAWAY, NJ, USA, 21 May 2006 (2006-05-21), pages 4pp - 1638, XP032458038, ISBN: 978-0-7803-9389-9, DOI: 10.1109/ISCAS.2006.1692915 *

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