WO2023106241A1

WO2023106241A1 - Copper-based wire rod, and semiconductor device

Info

Publication number: WO2023106241A1
Application number: PCT/JP2022/044602
Authority: WO
Inventors: 茂樹関谷; 勝政長谷川; 秀一北河; 邦照三原; 秀雄金子; 司高澤
Original assignee: 古河電気工業株式会社
Priority date: 2021-12-07
Filing date: 2022-12-02
Publication date: 2023-06-15
Also published as: CN116568835A

Abstract

This copper-based wire rod is composed of copper or a copper alloy, and in a cross-section perpendicular to the longitudinal direction of the copper-based wire rod, the average crystal grain size is 20 μm to 150 μm, an accumulation rate of crystal orientation <111> is 40% or less, the Young's modulus is 80 GPa to 120 GPa, and 0.2% yield strength is 20 MPa to 90 MPa.

Description

Copper-based wires and semiconductor devices

The present disclosure relates to copper-based wires and semiconductor devices.

In a semiconductor device, a bonding wire is a wire-shaped member that electrically connects a semiconductor chip and an electrode. Typically, bonding wires are bonded to semiconductor chips using ultrasonic bonding.

If the bonding wire is hard, the load on the semiconductor chip increases when the bonding wire is pressed against the semiconductor chip, causing the problem of damage to the semiconductor chip. Furthermore, in recent years, next-generation power semiconductor chips (SiC, GaN, etc.) have been developed that contribute to higher output and higher current. , the requirements for durability are becoming more stringent.

For example, Patent Document 1 describes a solar cell lead wire that can suppress uneven deformation during winding onto and unwinding from a bobbin. Low. However, Patent Document 1 does not mention the Young's modulus of the solar cell lead wire, and it is unclear whether the solar cell lead wire can withstand the impact when ultrasonically bonded to the semiconductor chip by wedge bonding.

In addition, Patent Document 2 describes a palladium-coated copper bonding wire that suppresses shrinkage cavities that are formed during ball bonding and that can accommodate narrower pitches between bonding wires. However, in Patent Document 2, there is no mention of the Young's modulus and 0.2% yield strength of the palladium-coated copper bonding wire. Not sure. Furthermore, there is a problem that a sufficient current cannot be passed because the final wire diameter of the palladium-coated copper bonding wire is too thin to meet the demand for high output and high current.

JP 2013-102054 A WO2020/183748

An object of the present disclosure is to provide a soft copper-based wire that is small in load even when pressed against a semiconductor chip and has excellent impact durability, and a semiconductor device that includes the copper-based wire as a bonding wire.

[1] A copper-based wire made of copper or a copper alloy, having an average crystal grain size of 20 μm or more and 150 μm or less in a cross section perpendicular to the longitudinal direction of the copper-based wire, and a crystal orientation of <111 > is 40% or less, Young's modulus is 80 GPa or more and 120 GPa or less, and 0.2% yield strength is 20 MPa or more and 90 MPa or less.
[2] The copper-based wire according to [1] above, wherein the total integration rate of the crystal orientation <100> and the crystal orientation <110> in the cross section is 15% or more and 40% or less. .
[3] In the cross section, the ratio (L _T /L _B ) of the length L _T of the twin grain boundary to the length L _B of the grain boundary where the misorientation of adjacent crystals is 15 degrees or more is 0.0. The copper-based wire according to the above [1] or [2], which is 7 or more and 1.0 or less.
[4] The copper-based wire according to any one of [1] to [3] above, wherein the copper-based wire is a round wire or a ribbon wire.
[5] The copper-based wire according to any one of [1] to [4] above, wherein the copper-based wire is made of oxygen-free copper.
[6] The copper-based wire according to any one of [1] to [5] above, wherein the copper-based wire has a palladium coating layer covering the outer peripheral surface.
[7] A semiconductor chip and a bonding wire bonded to the semiconductor chip, wherein the bonding wire is made of copper or a copper alloy, and at a bonding portion between an electrode provided on the top of the semiconductor chip and the bonding wire, A semiconductor device having an average crystal grain size of 10 μm or more and 100 μm or less and an integration rate of crystal orientation <111> of 40% or less in a cross section of the bonding wire perpendicular to the longitudinal direction of the bonding wire.
[8] The semiconductor device according to [7], wherein the total integration rate of the crystal orientation <100> and the crystal orientation <110> in the cross section is 15% or more and 40% or less.
[9] In the cross section, the ratio (L _T /L _B ) of the length L _T of the twin grain boundary to the length L _B of the grain boundary where the misorientation of adjacent crystals is 15 degrees or more is 0.0. The semiconductor device according to the above [7] or [8], which is 7 or more and 1.0 or less.
[10] The semiconductor device according to any one of [7] to [9] above, wherein the bonding wire is made of oxygen-free copper.
[11] The semiconductor device according to any one of [7] to [10] above, wherein the bonding wire has a palladium covering layer covering an outer peripheral surface.

According to the present disclosure, it is possible to provide a soft copper-based wire that is small in load even when pressed against a semiconductor chip and has excellent impact durability, and a semiconductor device that includes the copper-based wire as a bonding wire.

FIG. 1 is a perspective view showing an example of a half tower device of an embodiment. FIG. 2 is a schematic diagram showing an example of a cross section perpendicular to the longitudinal direction of the bonding wire before wedge bonding. FIG. 3 is a schematic diagram showing an example of a cross section perpendicular to the longitudinal direction of the bonding wire during wedge bonding.

The embodiment will be described in detail below.

As a result of extensive research, the present inventors have focused on simultaneously controlling the crystal grain size and crystal orientation of a copper-based wire, and found that the crystal grain size and crystal orientation in the cross section of the copper-based wire are different from those of the copper-based wire. It was found to affect Young's modulus and 0.2% yield strength. As a result, a soft copper-based wire that is small in load even when pressed against a semiconductor chip and has excellent impact durability is achieved. I have found that it can be suppressed. The present disclosure has been completed based on such findings.

First, the copper-based wire according to the embodiment will be described.

A copper-based wire according to an embodiment is made of copper or a copper alloy, and has an average crystal grain size of 20 μm or more and 150 μm or less in a cross section perpendicular to the longitudinal direction of the copper-based wire, and has a crystal orientation of <111>. The accumulation rate is 40% or less, the Young's modulus is 80 GPa or more and 120 GPa or less, and the 0.2% yield strength is 20 MPa or more and 90 MPa or less.

A copper-based wire is composed of copper (copper wire) or copper alloy (copper alloy wire).

The copper-based wire may be a copper alloy containing a small amount of elements such as silver (Ag), chromium (Cr), and tin (Sn). , copper is preferred in view of the trend toward larger currents. Among them, the higher the copper content, the higher the conductivity, so it is preferable to use tough pitch copper, which is pure copper composed of 99.90% by mass or more of copper (Cu) and inevitable impurities, and 99.96% by mass or more. of Cu, 10 ppm or less of oxygen and unavoidable impurities.

The copper alloy constituting the copper-based wire includes 0.1% by mass to 1.0% by mass of Ag, 0.1% by mass to 1.0% by mass of Cr, and 0.1% by mass to 1.0% by mass. It is preferable to have an alloy composition containing at least one element of Sn in mass % or less, with the balance being Cu and unavoidable impurities.

When Ag, Cr, and Sn are at least the above lower limits, the tensile durability of the copper-based wire can be improved. Therefore, when the copper-based wire is used as a bonding wire and bonded to the electrode of the semiconductor chip, it can withstand a tensile load when the copper-based wire is drawn out, and the bonding speed can be improved. On the other hand, when Ag, Cr, and Sn exceed the above upper limit values, it can be a factor of lowering the electrical conductivity of the copper-based wire. Therefore, in order to use the copper-based wire as a bonding wire for power semiconductors, it is preferable to add the above elements at a low concentration. From this point of view, when the copper alloy contains Ag, the upper limit of the Ag content is more preferably 0.7% by mass or less, and still more preferably 0.4% by mass or less. When the copper alloy contains Cr, the upper limit of the Cr content is more preferably 0.7% by mass or less, and still more preferably 0.4% by mass or less. When the copper alloy contains Sn, the upper limit of the Sn content is more preferably 0.7% by mass or less, and still more preferably 0.4% by mass or less.

The remainder other than the elements mentioned above is unavoidable impurities. Unavoidable impurities mean impurities at a content level that are unavoidably mixed in during the manufacturing process. Since the content of unavoidable impurities may cause the conductivity of the copper-based wire to decrease, the content of unavoidable impurities is preferably small.

When the copper-based wire is a copper alloy, the inevitable impurities include, for example, aluminum (Al), beryllium (Be), cadmium (Cd), iron (Fe), magnesium (Mg), nickel (Ni), phosphorus (P). , lead (Pd), silicon (Si), and titanium (Ti). When the copper-based wire is copper, the inevitable impurities include, in addition to the above elements, elements intentionally contained in the copper alloy and alloyed with copper, such as Ag, Cr, and Sn. . The upper limit of the content of inevitable impurities is preferably 20 ppm or less in total of the above elements.

In addition, in the cross section perpendicular to the longitudinal direction of the copper-based wire, the average crystal grain size is 20 μm or more and 150 μm or less, and the crystal orientation <111> integration rate is 40% or less. In the cross section of the copper-based wire, the accumulation rate of the <111> crystal orientation is the ratio of the crystal orientations in the range ±15° shifted from the <111> crystal orientation to the total crystal orientation.

Here, in the past, it was difficult to simultaneously lower the Young's modulus and the 0.2% yield strength, which were in a contradictory relationship, but the crystal grain size and crystal orientation affect the Young's modulus and the 0.2% yield strength. I found Based on these findings, by controlling the average crystal grain size and the crystal orientation <111> accumulation rate in the cross section of the copper-based wire within the above ranges, as described below, the Young's modulus of the copper-based wire and the 0.0. The 2% proof stress can be easily controlled within the above range.

When the average crystal grain size of the copper-based wire is 20 μm or more in the cross section perpendicular to the longitudinal direction of the copper-based wire, an increase in the 0.2% proof stress of the copper-based wire can be suppressed. Further, when the average crystal grain size is 150 μm or less, disconnection of the copper-based wire due to non-uniform deformation that occurs when the copper-based wire is pulled can be suppressed. From the above viewpoint, the lower limit of the average crystal grain size in the cross section of the copper-based wire is 20 μm or more, preferably 30 μm or more, more preferably 40 μm or more, and the upper limit is 150 μm or less.

In addition, in the cross section perpendicular to the longitudinal direction of the copper-based wire, if the crystal orientation <111> concentration of the copper-based wire is 40% or less, an increase in Young's modulus can be suppressed and the softness is improved. From the above point of view, the integration rate of the <111> crystal orientation in the cross section of the copper-based wire is 40% or less, preferably 30% or less, more preferably 20% or less.

Here, in the field of metal materials, crystal grain size and crystal orientation are generally known material factors. However, when the heat treatment temperature is set high for the purpose of increasing the crystal grain size, the crystal orientation also changes depending on the heat treatment temperature, making it impossible to simultaneously control the crystal grain size and the crystal orientation. In the present disclosure, by controlling the crystal grain size and crystal orientation within the above ranges, the Young's modulus and 0.2% proof stress can be controlled within the above ranges, so the copper-based wire is soft and pressed against the semiconductor chip. It has a small load and excellent impact resistance.

Also, regarding the Young's modulus of the copper-based wire, the lower limit is 80 GPa or more, and the upper limit is 120 GPa or less, preferably 110 GPa or less, and more preferably 100 GPa or less.

In addition, the 0.2% yield strength of the copper-based wire has a lower limit of 20 MPa or more and an upper limit of 90 MPa or less, preferably 60 MPa or less, and more preferably 40 MPa or less.

Here, material deformation includes elastic deformation and plastic deformation. In elastic deformation, there is a relationship of σ=Eε (σ: stress, E: Young's modulus, ε: strain), and stress acts in proportion to applied strain. That is, the lower the Young's modulus, the more moderate the deformation, so the load becomes smaller. Then, when a certain strain region is exceeded, plastic deformation occurs in which the material cannot return to its original state, and the stress at which this plastic deformation begins is called proof stress. For this reason, the lower the yield strength, the easier the plastic deformation and the smaller the load. A copper-based wire is required to have a low Young's modulus and a low yield strength from the viewpoints of being soft, having a small load when pressed against a semiconductor chip, and being excellent in impact durability.

When the Young's modulus and 0.2% proof stress of the copper-based wire are within the above range, it is soft, the load is small even when pressed against a semiconductor chip, and the impact resistance is excellent. Therefore, when manufacturing a semiconductor device using a copper-based wire as a bonding wire, the load on the semiconductor chip is reduced when the copper-based wire is bonded to the semiconductor chip, so damage to the semiconductor chip can be suppressed. In particular, the lower the Young's modulus and the 0.2% yield strength within the above ranges, the easier the copper-based wire is to be deformed when bonded to a semiconductor chip, and the better the impact durability. In addition, when the Young's modulus and 0.2% yield strength are equal to or higher than the above lower limits, when the copper-based wire is fed out from the bobbin to be set in an ultrasonic bonding machine for bonding with the semiconductor chip, the copper-based wire Can suppress tensile breakage.

In addition, there is a work hardening index (also called n value) as a material property that indicates the ease of hardening during plastic deformation, and the n value is expressed by the formula: σ = C × ε ⁿ (σ: true stress, C: strength constant, ε: true strain). The n value is generally a contradictory characteristic to the 0.2% yield strength, and the lower the 0.2% yield strength, the higher the n value, and the higher the 0.2% yield strength, the lower the n value. When used as a wire, ideally, a low n value is preferable in that it can be easily deformed after plastic deformation begins. Therefore, the n value of the copper-based wire is preferably 0.45 or less, more preferably 0.35 or less. In addition, the n value is a value that changes during plastic deformation, and considering the ease of deformation as a bonding wire, it is considered that the n value should be defined by the value at the initial stage of deformation. % to 5% range. For samples in which a nominal strain of 5% or more could not be obtained, the n value was calculated in the range from the nominal strain when calculating the 0.2% proof stress by the offset method to the nominal strain at which the maximum tensile strength was obtained.

In the cross section of the copper-based wire, the total integration rate of the crystal orientation <100> and the crystal orientation <110> is preferably 15% or more, more preferably 20% or more, and still more preferably 25%. % or more. The total integration rate of the crystal orientation <100> and the crystal orientation <110> is 15% or more, that is, the crystal orientation <100> and the crystal orientation <110> are copper-based at a rate of 15% or more If it is oriented in the longitudinal direction of the wire, the Young's modulus tends to be low, and a soft copper-based wire tends to be obtained.

In addition, in the cross section of the copper-based wire, the total integration rate of the crystal orientation <100> and the crystal orientation <110> is preferably 40% or less. When the total accumulation rate is 40% or less, the copper-based wire can be more durable against a tensile load when unwinding from the bobbin.

Here, in the cross section of the copper-based wire, the total integration rate of the crystal orientation <100> and the crystal orientation <110> is ±15° shifted from the crystal orientation <100> with respect to all crystal orientations. It is the ratio of the total crystal orientation of the crystal orientations in the range of +15° and the crystal orientations in the range ±15° from the crystal orientation <110>.

In addition, since twin grain boundaries are low-energy grain boundaries with high atomic coherence, dislocations are less likely to accumulate during working than at large-angle grain boundaries, and the force applied during bending can be reduced. The larger the existence ratio of the twin grain boundaries, the better. Therefore, in the cross section of the copper-based wire, the ratio (L _T /L _B ) of the length L _T of the twin grain boundary to the length L _B of the grain boundary where the misorientation of adjacent crystals is 15 degrees or more is It is preferably 0.7 or more and 1.0 or less.

In addition, the shape of the copper-based wire can be appropriately selected according to the amount of current required for the semiconductor device, the wiring space, etc., and is preferably a round wire or a ribbon wire. A round wire is a copper-based wire having a circular cross section. Ribbon wires include rectangular wires, striated wires, and track-shaped wires. A rectangular wire has a shape in which a cross section of a copper-based wire is surrounded by four straight lines. The striated wire is a copper-based wire having a rectangular cross-sectional shape. The track-shaped wire is a shape in which the cross section of the copper-based wire is surrounded by two straight lines and two curved lines connecting the ends of the two straight lines, that is, a so-called track shape.

When the copper-based wire is a round wire, if the wire diameter of the copper-based wire (round wire) is 0.1 mm or more, a relatively high current can flow through the copper-based wire, so the copper-based wire is used as a power semiconductor. Suitable for bonding wires for Further, when the wire diameter of the copper-based wire (round wire) is 0.5 mm or less, it is possible to adequately secure wiring space for the trend toward miniaturization of semiconductor devices, and it is easy to bend.

In addition, when the copper-based wire is a ribbon wire, if the thickness of the copper-based wire (ribbon wire) is 0.1 mm or more, a relatively high current can flow through the copper-based wire. Suitable for bonding wires for power semiconductors. Further, when the thickness of the copper-based wire (ribbon wire) is 0.5 mm or less, it is possible to adequately secure wiring space for the trend toward miniaturization of semiconductor devices, and it is easy to bend.

In addition, in order to prevent oxidation of the outer peripheral surface of the copper-based wire, the copper-based wire may have a metal coating layer covering the outer peripheral surface. A preferred metal coating layer is a palladium coating layer. The palladium covering layer covering the outer peripheral surface of the copper-based wire is formed by plating, for example.

Such a copper-based wire is suitable for bonding wires for semiconductor devices because it is soft, has a small load even when pressed against a semiconductor chip, has excellent impact durability, and is soft.

Next, a method for manufacturing the copper-based wire according to the embodiment will be described.

In the method for manufacturing a copper-based wire according to the embodiment, first, a casting process is performed. In the casting process, electrolytic copper is melted in a reducing atmosphere to obtain a cylindrical ingot called a billet.

After the casting process, the extrusion process or rolling process is performed. In the extrusion process, the billet is processed into a round bar by hot extrusion. The rolling process is performed continuously with the casting process using a continuous casting and rolling mill. In this case, molten copper is poured into a ring-shaped rotating mold to form an ingot, and rolling is repeated in the vertical or horizontal direction to obtain a wire rod.

After the extrusion process or rolling process, the first wire drawing process is performed. In the first wire drawing step, the round bar or wire rod obtained in the above step is drawn to a predetermined wire diameter. In addition, the first wire drawing step includes a peeling step for removing surface defects that have occurred up to the above steps.

After the first wire drawing process, the first heat treatment process is performed. In the first heat treatment step, after the second heat treatment step, which is a subsequent step, the average crystal grain size in the cross section of the copper-based wire and the accumulation rate of the predetermined crystal orientation are simultaneously controlled within a predetermined range. heat treatment.

When the first heat treatment step is a batch type heat treatment using a batch annealing furnace, the heat treatment temperature is 400°C or higher and 900°C or lower. If the heat treatment temperature is less than 400° C., the crystal grains are difficult to grow, and the second heat treatment step simultaneously reduces the average crystal grain size in the cross section of the copper-based wire to 20 μm or more and the crystal orientation <111> accumulation rate of 40% or less. difficult to achieve. In Patent Document 1, the heat treatment is performed at 200 to 300° C., but as shown in Comparative Examples A2 and A3 described later, either the average crystal grain size or the crystal orientation <111> accumulation rate is used. or both do not meet the above given ranges of this disclosure. On the other hand, if the heat treatment temperature exceeds 900° C., the average crystal grain size in the cross section of the copper-based wire exceeds 150 μm due to the second heat treatment step, and the copper-based wire cannot withstand the tension when it is drawn out from the bobbin. , cause disconnection.

Also, when the first heat treatment step is a batch heat treatment, the heat treatment time is 10 minutes or more and 6 hours or less. If the heat treatment time is less than 10 minutes, the crystal grains will not be uniform because the time is insufficient for uniformly heat treating the entire sample when a large number of samples are heated in a batch furnace. Therefore, it is not possible to stably achieve an average crystal grain size of 20 μm or more in the cross section of the copper-based wire by the second heat treatment step. On the other hand, if the heat treatment time exceeds 6 hours, the second heat treatment step will increase the average crystal grain size in the cross section of the copper-based wire to 20 μm or more, but the industrial cost will be too high.

In the case of the heat treatment while running, in which the wire is annealed in a heating furnace having a certain length in the first heat treatment step, the heat treatment time is shortened to 6 seconds or more and 15 seconds or less compared to the batch heat treatment, so the heat treatment temperature is 700 ° C. or more. Set to 950°C or less. The reason for setting the upper limit and lower limit of the heat treatment temperature in the heat treatment while running is the same as in the batch heat treatment.

After the first heat treatment process, the second wire drawing process is performed. In the second wire drawing step, wire drawing is performed at a processing rate of 10% or more and 70% or less. If the processing rate is less than 10%, the driving force for recrystallization during the second heat treatment step is insufficient, and the second heat treatment step reduces the accumulation rate of the predetermined crystal orientation in the cross section of the copper-based wire within the desired range. cannot be controlled. On the other hand, if the working rate is more than 70%, a large amount of working strain is introduced, and strain is introduced into the entire sample. The accumulation rate cannot be controlled within the desired range, and furthermore, it is difficult to achieve an average crystal grain size of 20 μm or more in the cross section of the copper-based wire. From this point of view, it is preferable that the processing rate is 15% or more and 50% or less. The processing rate is expressed by dividing the value obtained by subtracting the sample cross-sectional area after wire drawing from the sample cross-sectional area before wire drawing by the sample cross-sectional area before wire drawing and multiplying by 100.

After the second wire drawing process, the second heat treatment process is performed. In the second heat treatment step, the heat treatment temperature is 500° C. or more and 900° C. or less, and the heat treatment time is 6 seconds or more and 15 seconds or less. Thus, a copper-based wire can be obtained.

In addition, when the copper-based wire has a metal coating layer, it is preferable to perform a plating process on the copper-based wire. In the plating step, first, the copper-based wire is immersed in an alkaline bath, and electricity is applied so that the copper-based wire becomes a cathode, thereby removing organic stains present on the surface of the copper-based wire. Subsequently, the washed copper-based wire is immersed in a sulfuric acid bath to remove the oxide film on the surface of the copper-based wire. Subsequently, the washed copper-based wire is immersed in a palladium-containing solution and electroplated with a predetermined current and time to form a palladium coating layer, which is a metal coating layer, on the surface of the copper-based wire. The electroplating current and time are appropriately set according to the thickness of the metal coating layer.

Next, the semiconductor device of the embodiment will be described.

FIG. 1 is a perspective view showing an example of a half tower device of an embodiment. As shown in FIG. 1, the semiconductor device of the embodiment includes a semiconductor chip and bonding wires bonded to the semiconductor chip, the bonding wires being made of copper or a copper alloy and provided on top of the semiconductor chip. In the cross section of the bonding wire perpendicular to the longitudinal direction of the bonding wire at the junction between the electrode and the bonding wire, the average crystal grain size is 10 μm or more and 100 μm or less, and the crystal orientation <111> integration rate. is 40% or less.

In a semiconductor device 1, a semiconductor chip 2 is provided on a die pad 3, and an electrode 2a is provided above the semiconductor chip 2. On the other hand, there are inner leads 5 as substrate electrodes. It is connected. Electrode 2a is, for example, an aluminum electrode or a copper electrode.

The bonding wire 4 is made of copper (copper wire) or copper alloy (copper alloy wire).

The bonding wire may be, for example, a copper alloy containing a small amount of elements such as Ag, Cr, and Sn. In addition, it is preferably copper. Among them, the higher the copper content, the higher the conductivity, so it is preferable to use tough pitch copper, which is pure copper containing 99.90% by mass or more of Cu and unavoidable impurities, and 99.96% by mass or more of Cu, Oxygen-free copper containing 10 ppm or less of oxygen and unavoidable impurities is more preferable.

As the copper alloy constituting the bonding wire 4, 0.1% by mass or more and 1.0% by mass or less of Ag, 0.1% by mass or more and 1.0% by mass or less of Cr, 0.1% by mass or more and 1.0% by mass or less It is preferable to have an alloy composition containing at least one element of Sn in mass % or less, with the balance being Cu and unavoidable impurities.

The tensile durability of the bonding wire 4 can be improved when Ag, Cr, and Sn are at least the above lower limits. Therefore, it is possible to withstand a tensile load when the bonding wires 4 are drawn out when bonding the bonding wires 4 to the electrodes 2a of the semiconductor chip 2, and the bonding speed can be improved. On the other hand, when Ag, Cr, and Sn exceed the above upper limits, it can be a factor of lowering the electrical conductivity of the bonding wire 4 . Therefore, it is preferable to add the above elements at a low concentration for bonding wires for power semiconductors. From this point of view, when the copper alloy contains Ag, the upper limit of the Ag content is more preferably 0.7% by mass or less, and still more preferably 0.4% by mass or less. When the copper alloy contains Cr, the upper limit of the Cr content is more preferably 0.7% by mass or less, and still more preferably 0.4% by mass or less. When the copper alloy contains Sn, the upper limit of the Sn content is more preferably 0.7% by mass or less, and still more preferably 0.4% by mass or less.

The remainder other than the elements mentioned above is unavoidable impurities. It is preferable that the content of the inevitable impurities is small because the conductivity of the bonding wire 4 may be lowered depending on the content of the inevitable impurities.

When the bonding wire 4 is made of a copper alloy, the inevitable impurities include, for example, aluminum (Al), beryllium (Be), cadmium (Cd), iron (Fe), magnesium (Mg), nickel (Ni), and phosphorus (P). , lead (Pd), silicon (Si), and titanium (Ti). When the bonding wire 4 is made of copper, the inevitable impurities include, in addition to the above elements, elements intentionally contained in the copper alloy and alloyed with copper, such as Ag, Cr, and Sn. . The upper limit of the content of inevitable impurities is preferably 20 ppm or less in total of the above elements.

In addition, in the cross section of the bonding wire 4 perpendicular to the longitudinal direction of the bonding wire 4 at the bonding portion 6 between the electrode 2a on the semiconductor chip 2 and the bonding wire 4, the average crystal grain size is 10 μm or more and 100 μm or less, and , the integration rate of the crystal orientation <111> is 40% or less. In the cross section of the bonding wire 4, the integration rate of the <111> crystal orientation is the ratio of the crystal orientations in the range ±15° shifted from the <111> crystal orientation to the total crystal orientation. The bonding portion 6 is a portion of the bonding wire 4 that is bonded to the electrode 2 a on the semiconductor chip 2 .

In the cross section of the bonding wire 4 at the bonding portion 6, if the average crystal grain size and the integration rate of the crystal orientation <111> of the bonding wire 4 are within the above ranges, the bonding between the semiconductor chip 2 and the bonding wire 4 will cause Damage to the semiconductor chip 2 is suppressed, and a good semiconductor device 1 can be obtained.

In addition, in the cross section of the bonding wire 4 at the bonding portion 6, the total integration rate of the crystal orientation <100> and the crystal orientation <110> is preferably 15% or more and 40% or less. In the cross section of the bonding wire 4 at the bonding portion 6, the total integration rate of the crystal orientation <100> and the crystal orientation <110> is ±15° from the crystal orientation <100> with respect to all crystal orientations. It is the ratio of the total crystal orientation of the crystal orientations in the deviated range and the crystal orientations in the range ±15° deviated from the crystal orientation <110>.

When the total integration rate of the bonding wires 4 is within the above range in the cross section of the bonding wires 4 in the bonding portion 6, the bonding wires 4 are soft, have excellent impact resistance, and are easy to bend during routing. As a result, space can be saved.

In addition, in the cross section of the bonding wire 4 at the bonding portion 6, the ratio of the length _LT of the twin grain boundary to the length _LB of the grain boundary where the misorientation of adjacent crystals is 15 degrees or more ( _LT /L _B ) is preferably 0.7 or more and 1.0 or less. When the ratio (L _T /L _B ) is within the above range in the cross section of the bonding wire 4 at the bonding portion 6, the bonding wire 4 is soft, has excellent impact durability, and is easy to bend during routing. As a result, space can be saved.

When the bonding wire 4 is a round wire, the wire diameter of the bonding wire 4 (round wire) is 0.1 mm or more. A relatively high current can flow through the bonding wire 4 when the thickness is 0.1 mm or more. Therefore, the bonding wire 4 is suitable as a bonding wire for power semiconductors.

Further, if the wire diameter of the bonding wire 4 (round wire) is 0.5 mm or less and the thickness of the bonding wire 4 (ribbon wire) is 0.5 mm or less, the wiring space is reduced in response to the trend toward miniaturization of semiconductor devices. In addition, the bonding wire 4 can be easily bent.

Also, in order to prevent oxidation of the outer peripheral surface of the bonding wire 4, the bonding wire 4 may have a metal film layer (not shown) covering the outer peripheral surface. A preferred metal coating layer is a palladium coating layer. The palladium covering layer covering the outer peripheral surface of the bonding wire 4 is formed by plating, for example.

From the viewpoint of suppressing breakage of the semiconductor chip 2 due to bonding between the electrode 2a of the semiconductor chip 2 and the bonding wire 4, the bonding wire 4 is preferably the copper-based wire material of the above embodiment.

Next, a method of bonding the semiconductor chip 2 and the bonding wires 4 in the semiconductor device of the embodiment will be described. Here, a method of joining the semiconductor chip 2 and the bonding wires 4 by wedge bonding will be described, but the method of joining the semiconductor chip 2 and the bonding wires 4 is not limited to wedge bonding.

FIG. 2 is a schematic diagram showing an example of a cross section perpendicular to the longitudinal direction of the bonding wire before wedge bonding, and FIG. 3 is a schematic diagram showing an example of a cross section perpendicular to the longitudinal direction of the bonding wire during wedge bonding. It is a diagram.

The bonding wires 4 are joined to the electrodes 2a on the semiconductor chip 2. In wedge bonding, the bonding wire 4 is pressed against the electrode 2a on the semiconductor chip 2 with a wedge-shaped tool 7, and ultrasonic waves are applied at a frequency of 60 kHz or more and 120 kHz or less for a time of 0.1 seconds or more and 0.8 seconds or less. Then, the bonding wires 4 are joined to the electrodes 2 a of the semiconductor chip 2 . Thus, a semiconductor device comprising the semiconductor chip 2 and the bonding wires 4 bonded to the semiconductor chip 2 can be obtained.

According to the embodiments described above, focusing on simultaneously controlling the crystal grain size and the crystal orientation of the copper-based wire, the average crystal grain size and the crystal orientation <111> integration rate in the cross section of the copper-based wire are controlled. By doing so, the Young's modulus and the 0.2% yield strength, which have conventionally been in a trade-off relationship, can be lowered at the same time. Therefore, the copper-based wire is soft, and even if it is pressed against a semiconductor chip, the load is small and it is excellent in impact resistance. Furthermore, when a copper-based wire is used as a bonding wire, the copper-based wire (bonding wire) deforms appropriately when it is bonded to a semiconductor chip mounted on a semiconductor device, reducing the load on the semiconductor chip. Therefore, damage to the semiconductor chip due to bonding between the semiconductor chip and the bonding wire can be suppressed.

Although the embodiments have been described above, the present invention is not limited to the above embodiments, and includes all aspects included in the concept and claims of the present disclosure, and can be variously modified within the scope of the present disclosure. be able to.

Next, examples and comparative examples will be described, but the present disclosure is not limited to these examples.

(Examples A1 to A4, A7 to A14 and Comparative Examples A1 to A3)
A copper-based material composed of the components shown in Table 1 was subjected to a casting process, an extrusion process, and a first wire drawing process to obtain a wire having a wire diameter of 0.56 mm. Subsequently, a first heat treatment step was performed under the conditions shown in Table 2. Subsequently, a second wire drawing process was performed to obtain wires having the shape, wire diameter, thickness, width, and working ratio shown in Table 2. In the second wire drawing step, a round hole die, a rectangular die, or a cassette roller die (CRD) that draws wire through a gap arranged between two rolls was used to finish a round wire or ribbon wire. Subsequently, a second heat treatment step was performed under the conditions shown in Table 2. Thus, a copper-based wire was obtained.

(Examples A5-A6)
A copper-based material composed of the components shown in Table 1 was subjected to a casting process, a rolling process, and a first wire drawing process to obtain a strip having a thickness of 0.56 mm. Subsequently, a first heat treatment step was performed under the conditions shown in Table 2. Subsequently, a second wire drawing process was performed to obtain wires having the shape, thickness, width, and working ratio shown in Table 2. In the second wire drawing step, the wire was rolled to a thickness shown in Table 2, slitted, cut into a desired width, and finished into a ribbon wire. Subsequently, a second heat treatment step was performed under the conditions shown in Table 2. Thus, a copper-based wire was obtained.

(Example A15)
A plating step was performed on the copper-based wire obtained in Example A1. In the plating process, first, a copper-based wire is immersed in an alkaline bath containing caustic soda, sodium carbonate, and sodium silicate, and a current of 5 A/dm ² is applied for 5 seconds so that the copper-based wire becomes the cathode. Organic stains present on the surface of the wire were removed. Subsequently, the washed copper-based wire was immersed in a 10% concentration sulfuric acid bath for 5 seconds to remove the oxide film on the surface of the copper-based wire. Subsequently, the washed copper-based wire was immersed in a palladium-containing solution, electroplating was performed at a current of 4 to 20 A/dm ² , and the current value and time were adjusted so that the thickness of the palladium coating layer was 1 μm. Then, a palladium coating layer was formed on the surface of the copper-based wire. The thickness of the palladium coating layer was obtained by observing a cross section perpendicular to the longitudinal direction of the copper-based wire with an optical microscope.

The palladium-containing solution consisted of 8 g/L of palladium metal (98 g/L of dichlorotetraamminepalladium, which is a palladium metal complex), 400 g/L of ammonium nitrate and 160 g/L of ammonium chloride, and was diluted with aqueous ammonia to a pH of 8 to 9. The pH was adjusted so that The temperature of the palladium-containing solution was 60°C.

(Examples B1 to B15 and Comparative Examples B1 to B3)
As shown in Table 4, using the copper-based wires obtained in the above Examples and Comparative Examples as bonding wires, copper-based electrodes (aluminum electrode pads) provided on a semiconductor chip having a length of 10 mm and a width of 10 mm. The wires were pressed against each other and ultrasonic bonding was applied to join the copper-based wires to the semiconductor chip. The ultrasonic waves were applied at a frequency of 60 kHz and a time of 0.3 seconds. Thus, a semiconductor device was obtained by wedge bonding.

[evaluation]
The copper-based wires and semiconductor devices obtained in the above Examples and Comparative Examples were evaluated as follows. The results are shown in Tables 3-4.

[1] Average crystal grain size, crystal orientation accumulation rate, and ratio (L _T /L _B )
The average crystal grain size, crystal orientation and ratio (L _T /L _B ) were measured using an EBSD detector (manufactured by TSL, OIM5.0 It was obtained from crystal orientation analysis data calculated using analysis software (manufactured by TSL, OIM Analysis) from crystal orientation data continuously measured using HIKARI). "EBSD" is an abbreviation for Electron Backscatter Diffraction, and is a crystal orientation analysis technique that utilizes backscattered electron Kikuchi line diffraction that occurs when a measurement sample is irradiated with an electron beam in a scanning electron microscope (SEM).

The object to be measured is the cross-section cut perpendicular to the longitudinal direction of a copper-based wire rod, which is mirror-finished by polishing, or the joint 6 between the semiconductor chip and the bonding wire as shown in FIG. A cross section cut along the cutting line P perpendicular to the longitudinal direction of the wire is mirror-finished by polishing (in FIG. 1, of the two cross sections, the surface of the bonding wire on the front right side of the paper surface) and The measurement area was the entire range of the cross section. The measurement was performed with an EBSD step size of 1 μm. In the EBSD measurement, n3 (three measurement targets) was measured and the average value was calculated.

The average crystal grain size was calculated by the area method by selecting the chart-grain size (diameter) of the analysis software for the measurement range.

For the integration rate of each crystal orientation, an orientation parallel to the longitudinal direction of the copper-based wire or bonding wire is selected on the IPFmap, and the crystal orientation <111> and the crystal orientation <100> with respect to that orientation on the chart-crystal direction. , the ratio of the area of grains oriented ±15° from the crystal orientation <110> to the area of grains of all orientations, respectively, the integration rate of crystal orientation <111>, the integration rate of crystal orientation <100>, and the crystal orientation <110> as the accumulation rate.

In addition, 15° or more and 65° or less was selected for Rotation Angle, the total length of the crystal misorientation was defined as _LB , Σ3 was selected for CSL, and the total length was defined as _LT . Then, _LB was divided by _LT to calculate the ratio (L _T /L _B ). CSL is an abbreviation for Coincidence Site Lattice and means correspondence, and the twin grain boundary is represented by the correspondence grain boundary Σ3.

[2] Component analysis At the stage of obtaining a rough drawn wire with a wire diameter of 8 mm, the rough drawn wire was pressed into a flat shape, and the average value of n3 was calculated using emission spectroscopic analysis.

[3] 0.2% Yield Strength According to JIS Z2241, a tensile test was performed using a precision universal testing machine (manufactured by Shimadzu Corporation), and the 0.2% yield strength (MPa) was determined by the offset method. In addition, the tensile test was performed for each of three samples (n3), and the average value was obtained. A 0.2% yield strength of 20 MPa or more and 90 MPa or less was considered acceptable.

[4] Young's modulus Young's modulus was measured using a Young's modulus measuring device JE-RT (manufactured by Technoplus Japan) using a resonance method. The sample was cut into an arbitrary length of 40 mm or more and 60 mm or less so that the amplitude at the resonance frequency during measurement was large, and the weight of the sample was measured to calculate the density. n3 was measured and the average value was calculated. A Young's modulus of 80 GPa or more and 120 GPa or less was considered acceptable.

[5] Work hardening index According to JIS Z2241, a tensile test is performed using a precision universal testing machine (manufactured by Shimadzu Corporation), formula: σ = C × ε ⁿ (σ: true stress, C: strength constant , ε: true strain, n: work hardening index).

[6] Breakage of semiconductor chip Damage state of the semiconductor chip when the copper-based wire is pressed against the aluminum electrode pad provided on the semiconductor chip, ultrasonic bonding is performed, and the copper-based wire is bonded to the semiconductor chip. was evaluated. For the semiconductor devices obtained in Examples and Comparative Examples, the surfaces of the aluminum electrode pads on the semiconductor chips after ultrasonic bonding were visually observed. bottom. On the other hand, those in which no cracks were observed were judged to have passed as no damage to the semiconductor chip.

As shown in Tables 1 to 3, in Examples A1 to A15, the average crystal grain size and crystal orientation <111> accumulation ratio in the cross section of the copper-based wire, the Young's modulus of the copper-based wire, and the 0.2% proof stress was controlled within a predetermined range, the copper-based wire material was soft, had a small load even when pressed against a semiconductor chip, and was excellent in impact resistance. Furthermore, as shown in Table 4, in Examples B1 to B15 using the copper-based materials obtained in Examples A1 to A15 as bonding wires, the average crystal grain size and crystal The integration rate of the <111> orientation is within a predetermined range, and the copper-based wire deforms appropriately when bonded to the semiconductor chip, so the load on the semiconductor chip is reduced. No breakage of the semiconductor chip occurred.

On the other hand, in Comparative Example A1, the accumulation rate of the crystal orientation <111> in the cross section of the copper-based wire and the Young's modulus of the copper-based wire were not controlled within a predetermined range. Furthermore, in Comparative Example B1 in which the copper-based material obtained in Comparative Example A1 was used as the bonding wire, the integration rate of the crystal orientation <111> was not within the predetermined range in the cross section of the bonding wire at the joint. Therefore, in Comparative Example B1, the semiconductor chip was damaged due to bonding between the semiconductor chip and the bonding wire.

In addition, in Comparative Example A2, the average crystal grain size and crystal orientation <111> accumulation rate in the cross section of the copper-based wire, as well as the Young's modulus and 0.2% yield strength of the copper-based wire, were not controlled within a predetermined range. rice field. Furthermore, in Comparative Example B2 using the copper-based material obtained in Comparative Example A2 as a bonding wire, the average crystal grain size and the crystal orientation <111> integration rate in the cross section of the bonding wire at the bonding portion were within a predetermined range. it wasn't Therefore, in Comparative Example B2, the semiconductor chip was damaged due to the bonding between the semiconductor chip and the bonding wire.

Also, in Comparative Example A3, the average crystal grain size in the cross section of the copper-based wire and the 0.2% yield strength were not controlled within the predetermined ranges. Furthermore, in Comparative Example B3 in which the copper-based material obtained in Comparative Example A3 was used as the bonding wire, the average crystal grain size was not within the predetermined range in the cross section of the bonding wire at the joint. Therefore, in Comparative Example B3, the semiconductor chip was damaged due to the bonding between the semiconductor chip and the bonding wire.

REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor chip 2a electrode 3 die pad 4 bonding wire 5 inner lead 6 junction 7 wedge-shaped tool

Claims

A copper-based wire made of copper or a copper alloy,
In the cross section perpendicular to the longitudinal direction of the copper-based wire, the average crystal grain size is 20 μm or more and 150 μm or less, and the crystal orientation <111> integration rate is 40% or less,
Young's modulus is 80 GPa or more and 120 GPa or less,
A copper-based wire having a 0.2% yield strength of 20 MPa or more and 90 MPa or less.
The copper-based wire according to claim 1, wherein the total integration rate of the crystal orientation <100> and the crystal orientation <110> in the cross section is 15% or more and 40% or less.
In the cross section, the ratio (L T /L B ) of the length L T of the twin grain boundary to the length L B of the grain boundary where the misorientation of adjacent crystals is 15 degrees or more is 0.7 or more and 1 The copper-based wire according to claim 1 or 2, which is .0 or less.
The copper-based wire according to any one of claims 1 to 3, wherein the copper-based wire is a round wire or a ribbon wire.
The copper-based wire according to any one of claims 1 to 4, wherein the copper-based wire is made of oxygen-free copper.
The copper-based wire according to any one of claims 1 to 5, wherein the copper-based wire has a palladium coating layer covering the outer peripheral surface.
A semiconductor chip and a bonding wire bonded to the semiconductor chip,
the bonding wire is made of copper or a copper alloy,
an average crystal grain size of 10 μm or more and 100 μm or less in a cross section of the bonding wire perpendicular to the longitudinal direction of the bonding wire at a joint portion between the electrode provided on the upper portion of the semiconductor chip and the bonding wire, and A semiconductor device having a <111> crystal orientation integration rate of 40% or less.
8. The semiconductor device according to claim 7, wherein the total integration rate of the crystal orientation <100> and the crystal orientation <110> in the cross section is 15% or more and 40% or less.
In the cross section, the ratio (L T /L B ) of the length L T of the twin grain boundary to the length L B of the grain boundary where the misorientation of adjacent crystals is 15 degrees or more is 0.7 or more and 1 9. The semiconductor device according to claim 7 or 8, which is less than or equal to 0.0.
The semiconductor device according to any one of claims 7 to 9, wherein said bonding wires are made of oxygen-free copper.
The semiconductor device according to any one of claims 7 to 10, wherein said bonding wire has a palladium covering layer covering its outer peripheral surface.