WO2023103716A1 - 一种芯片系统及通信设备 - Google Patents

一种芯片系统及通信设备 Download PDF

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Publication number
WO2023103716A1
WO2023103716A1 PCT/CN2022/131597 CN2022131597W WO2023103716A1 WO 2023103716 A1 WO2023103716 A1 WO 2023103716A1 CN 2022131597 W CN2022131597 W CN 2022131597W WO 2023103716 A1 WO2023103716 A1 WO 2023103716A1
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WO
WIPO (PCT)
Prior art keywords
shielding structure
chip
shielding
connection
circuit board
Prior art date
Application number
PCT/CN2022/131597
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English (en)
French (fr)
Inventor
杜白
姬忠礼
佘飞
李瑞琳
郭庆超
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华为技术有限公司
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Publication of WO2023103716A1 publication Critical patent/WO2023103716A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Definitions

  • the present application relates to the field of chip technology, in particular to a chip system and communication equipment.
  • a conventional method to reduce the influence of electromagnetic radiation is to set up electromagnetic shielding bodies for devices that generate electromagnetic radiation or sensitive devices that are susceptible to electromagnetic radiation.
  • FIG. 1 this figure is a schematic diagram of an electromagnetic shielding body of a conventional chip package.
  • the illustrated chip package includes a chip 11 and a packaging substrate 14 .
  • the chip 11 and the packaging substrate 14 are bonded by solder balls.
  • the electromagnetic shielding body 13 is generally a technical stamping structure, covers the top side of the chip 11 , and is fixed to the upper surface of the package substrate 14 through the connection portion 15 .
  • the upper surface of the chip 11 is in contact with the electromagnetic shield 13 through a thermal interface material (TIM) 12 to accelerate heat dissipation.
  • TIM thermal interface material
  • the packaging substrate 14 and the printed circuit board (Printed Circuit Board, PCB) 20 are connected by the solder balls 30, there is a gap between the solder balls 30, so that the solder balls 30 become a leakage source of electromagnetic radiation.
  • the frequency continues to increase, the demand for reducing electromagnetic radiation leakage continues to increase, and the electromagnetic radiation leaked from the solder balls 30 may even seriously affect the performance of the chip.
  • the present application provides a chip system and a communication device, which reduce the electromagnetic leakage of the first connection part, thereby improving the electromagnetic shielding capability of the chip and ensuring the performance of the chip.
  • the present application provides a chip system, the chip system includes a chip package and an electromagnetic shielding body, the chip package is electrically connected to the circuit board through a first connection part, in a typical implementation, the first The connection part includes solder balls.
  • the chip package includes an electrically connected packaging substrate and at least one chip, and the electromagnetic shield includes a conductive first shielding structure and a conductive second shielding structure.
  • the first shielding structure is connected to the packaging substrate, and the first shielding structure includes a first cavity, and the first cavity is used for accommodating at least one chip.
  • the first end of the second shielding structure is connected to the circuit board or the pad on the circuit board, and the second end of the second shielding structure is connected to the first shielding structure to form a second cavity, or the first end of the second shielding structure
  • the pads on the circuit board or the circuit board are connected, the second shielding structure covers the first shielding structure to form a second cavity, and the first connection part is located in the second cavity.
  • the second cavity formed surrounds the first connection part. Since the first shielding structure and the second shielding structure are both conductive, the first shielding structure and the second shielding structure The second shielding structure plays a shielding role together, which can realize the electromagnetic shielding of the first connection part, reduce the electromagnetic leakage of the first connection part, and then improve the electromagnetic shielding ability, ensure the performance of the chip, and reduce the damage of other circuit components. The influence of electromagnetic leakage.
  • the first connection part includes an insulating material and a plurality of electrical connection structures, wherein the plurality of electrical connection structures are used to connect the chip package and the circuit board, and the insulating material is filled in the chip package.
  • the electrical connection structure is a solder ball
  • the first connecting portion includes a solder ball and an insulating material
  • the solder ball is used to realize the electrical connection between the chip package and the circuit board.
  • the insulating material can play a role in assisting heat dissipation; on the other hand, the insulating material filled between the chip package and the circuit board can also play a supporting role, so that the second shielding structure can be closely attached to the insulating material.
  • the side wall is more stable and reliable.
  • the connection area between the chip package and the circuit board is increased, and the stability of the connection between the chip package and the circuit board is improved.
  • the first connection portion filled with insulating material includes two connection surfaces, one connection surface close to the circuit board is the first connection surface, and one connection surface close to the chip package is the second connection surface,
  • the width of the first connection surface is greater than the width of the second connection surface. That is, the insulating material is narrow on the upper side and wider on the lower side after being filled, so as to provide support for the second shielding structure.
  • the second shielding structure covers all the sidewalls of the insulating material, or partially covers the sidewalls of the insulating material.
  • the insulating material When the insulating material is filled in the connection area between the chip package and the circuit board, the insulating material can be filled through the capillary principle, and the second shielding structure covers all or part of the sidewall of the insulating material, that is, the metal solder balls are surrounded inside, and then Electromagnetic shielding of metal solder balls is realized.
  • the second shielding structure when the second shielding structure is in contact with the edge of the insulating material, the insulating material filled between the connection area of the chip package and the circuit board can also play a supporting role, so that the second shielding structure can be close to the side wall of the insulating material , more stable and reliable.
  • the first end of the second shielding structure is connected to a pad on the circuit board, so as to improve the stability of the connection of the second shielding structure.
  • the first end of the second shielding structure is connected to a pad on the circuit board, and the pad is grounded.
  • the electromagnetic shielding body improves the electromagnetic shielding capability of the chip and the first connecting portion.
  • the packaging substrate is located on the pad, and the first end of the second shielding structure is electrically connected to the pad.
  • the chip package is electrically connected to the circuit board by using LGA packaging technology, and the ground pin of the chip package is electrically connected to the second shielding structure. Since the pad is electrically connected to the first shielding structure through the second shielding structure, when the pad is grounded, the second shielding structure and the first shielding structure are also grounded, which improves the performance of electromagnetic shielding.
  • grounding pins on the circuit board are located outside the range covered by the outline of the chip package, they can also be electrically connected to the first shielding structure through the process of creep soldering, thereby avoiding grounding through wiring, which simplifies the ground line.
  • the first surface of each chip in the at least one chip is connected to the first shielding structure through the first material.
  • the second surface of each chip in the at least one chip is electrically connected to the first surface of the packaging substrate, and the first shielding structure is connected to the first surface of the packaging substrate through the second connection portion.
  • the first material can be thermal interface material (Thermal Interface Material, TIM) material
  • thermal interface material is mostly flexible material, for example can be gel, silicone grease material, fill between the first surface of the chip and the first shielding structure, a
  • TIM Thermal Interface Material
  • thermal interface material is mostly flexible material, for example can be gel, silicone grease material, fill between the first surface of the chip and the first shielding structure, a
  • it can assist heat dissipation, so that the heat generated when the chip is working can be quickly transferred to the first shielding structure; on the other hand, it provides support for the first shielding structure and improves the stability of the first shielding structure.
  • the first shielding structure is fixed to the first surface of the packaging substrate through the second connection part, and the first shielding structure is also fixed to the first surface of the chip through the first material, which improves the stability of the first shielding structure.
  • the packaging substrate passes through After the first connecting portion is fixed to the circuit board, the position of the first shielding structure relative to the circuit board is also fixed.
  • the second connection part is metal solder, and the first shielding structure is welded to the first surface of the packaging substrate through the second connection part. At this time, the connection between the first shielding structure and the packaging substrate is firm, and the electromagnetic The shielding body has good electromagnetic shielding performance.
  • the second connection part is conductive glue, and the first shielding structure is connected to the first surface of the packaging substrate through the second connection part. This method can make the electromagnetic shielding body have good electromagnetic shielding performance.
  • the second connection part is insulating melt, and the first shielding structure is connected to the first surface of the package substrate through the second connection part, which reduces the difficulty of manufacturing process and can make the connection between the first shielding structure and the package substrate firm .
  • the first surface of each chip in at least one chip is connected to the first shielding structure through a first material.
  • the second surface of each chip of the at least one chip is electrically connected to the first surface of the packaging substrate.
  • the first shielding structure is connected to the sidewall of the packaging substrate through the second connecting portion.
  • the first material can be a thermal interface material, and the first material is filled between the first surface of the chip and the first shielding structure.
  • it can assist heat dissipation, so that the heat generated when the chip is in operation can be quickly conducted to the first shielding structure.
  • providing support for the first shielding structure improving the stability of the connection of the first shielding structure.
  • the first shielding structure is connected to the side wall of the packaging substrate, thereby surrounding the chip package, thereby improving the effect of electromagnetic shielding.
  • the second connection part is metal solder, and the first shielding structure is welded to the side wall of the packaging substrate through the second connection part. At this time, the connection between the first shielding structure and the packaging substrate is firm, and the electromagnetic shielding The body has good electromagnetic shielding performance.
  • the second connection part is conductive glue, and the first shielding structure is connected to the side wall of the packaging substrate through the second connection part. This method can make the electromagnetic shielding body have good electromagnetic shielding performance.
  • the second connection part is insulating melt, and the first shielding structure is connected to the sidewall of the package substrate through the second connection part, which reduces the difficulty of manufacturing process and can make the connection between the first shielding structure and the package substrate firm.
  • the first shielding structure is a metal structure.
  • the metal structural part can be a metal structural part with a groove structure formed by stamping or casting, which is not specifically limited in the embodiment of the present application.
  • the groove is used to accommodate the corresponding part of the chip package, thereby realizing the chip package. electromagnetic shielding.
  • the chip package further includes a plastic encapsulant.
  • Each of the at least one chip is embedded in the molding compound.
  • the first shielding structure covers the outer surface of the molding compound and the sidewall of the packaging substrate.
  • the plastic encapsulant can assist heat dissipation, so that the heat generated by the chip can be quickly transferred to the first shielding structure; on the other hand, it provides support for the first shielding structure and improves the stability of the connection of the first shielding structure.
  • the first shielding structure covers the outer surface of the molding compound and the sidewall of the packaging substrate, and then surrounds the chip package, thereby improving the effect of electromagnetic shielding.
  • the chip package further includes a molding compound, each of the at least one chip is embedded in the molding compound, and each of the at least one chip is electrically connected to the first surface of the packaging substrate.
  • a shielding structure covers the outer surface of the molding compound and extends to the first surface of the packaging substrate.
  • the plastic encapsulant can assist in heat dissipation, so that the heat generated by the chip can be quickly transferred to the first shielding structure; on the other hand, it provides support for the first shielding structure and improves the stability of the connection of the first shielding structure.
  • the first shielding structure covers the outer surface of the molding compound and the sidewall of the packaging substrate, reducing the usage of the molding compound and reducing the material consumption of the first shielding structure.
  • the first shielding structure is any one of a conductive film, a metal material, or a conductive adhesive material.
  • the conductive film can be formed by spraying; when the first shielding structure is realized by a metal material, the metal material can be deposited by metal sputtering or electroplating; When the first shielding structure is realized by using a conductive adhesive material, the conductive adhesive material may be formed by coating.
  • the second shielding structure is any one of a conductive film, a metal material, or a conductive adhesive material.
  • the plurality of electrical connection structures included in the first connection part may be any one of metal solder balls, sintering, metal structural parts or plug terminals, and other electrical connection structures may also be used. Implementation manners, the present application will not give examples one by one here.
  • the second shielding structure completely covers the first shielding structure, so as to improve electromagnetic shielding capability.
  • the second shielding structure is a conductive film, it can also reduce the difficulty of forming the second shielding structure.
  • the second shielding structure can be connected to the first shielding structure through an adhesive material, that is, between the second shielding structure and the first shielding structure Adhesive material is added to the contact surface to improve the stability of the connection between the two.
  • the implementation manners of the second shielding structure and the first shielding structure may be the same or different, which is not specifically limited in this application.
  • the conductive film can be formed by spraying;
  • the metal material can be deposited by metal sputtering or electroplating;
  • the conductive adhesive material may be formed by coating.
  • the second shielding structure is located outside the first shielding structure, and at least a part of the second cavity is located between the packaging substrate and the circuit board.
  • the second shielding structure can be connected to the outside of the first shielding structure, which is easy to process and shape.
  • Layer shielding structure improves electromagnetic shielding performance.
  • the second cavity is located between the packaging substrate and the circuit board, and is used for accommodating the first connection part, so as to realize electromagnetic shielding for the first connection part.
  • the present application further provides a communication device, where the communication device includes the chip system provided in the above implementation manner.
  • the chip package included in the communication equipment has high requirements on electromagnetic shielding, so when the chip package is mounted on the PCB, it is necessary to perform more comprehensive and complete electromagnetic shielding on the chip package.
  • the electromagnetic shielding body included in the communication equipment provided by the present application can realize the electromagnetic shielding of the electrical connection structural parts in the first connection part, reduce the electromagnetic leakage of the electrical connection structural parts in the first connection part, and improve the safety of the chip package.
  • the electromagnetic shielding ability ensures the performance of the chip, and can also reduce the influence of electromagnetic leakage on other circuit components, thus improving the performance of communication equipment.
  • the communication device is a radio frequency transceiver.
  • the radio frequency transceiver is connected to the base band processing unit (Base band Unit, BBU) of the base station through an optical fiber.
  • BBU Base band Unit
  • the BBU is used to process data transmitted by the radio frequency transceiver, and transmit data to be transmitted to the radio frequency transceiver.
  • the technical solution of the present application improves the electromagnetic shielding ability of the chip package, and further improves the working performance of the radio frequency transceiver.
  • At least one chip includes an intermediate frequency chip.
  • the intermediate frequency chip is used in the intermediate frequency circuit of the radio frequency transceiver.
  • Fig. 1 is the schematic diagram of traditional electromagnetic shielding body
  • FIG. 2A is a schematic cross-sectional view of a chip system provided by an embodiment of the present application.
  • FIG. 2B is a side view corresponding to FIG. 2A provided by the embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • Figure 4A is an enlarged view of area A in Figure 3 provided by the embodiment of the present application.
  • FIG. 4B is a top view corresponding to FIG. 3 provided by the embodiment of the present application.
  • FIG. 4C is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • Fig. 5 is the waveform diagram of the simulation test that the embodiment of the present application provides
  • FIG. 6 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional view of another chip system provided by the embodiment of the present application.
  • FIG. 11 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • FIG. 12 is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • Fig. 13A is the first schematic cross-sectional view corresponding to Fig. 12 provided by the embodiment of the present application;
  • Fig. 13B is the second schematic cross-sectional view corresponding to Fig. 12 provided by the embodiment of the present application.
  • Figure 14 is the first side view corresponding to Figure 12 provided by the embodiment of the present application.
  • Figure 15A is the third schematic cross-sectional view corresponding to Figure 12 provided by the embodiment of the present application.
  • Fig. 15B is a schematic cross-sectional view four corresponding to Fig. 12 provided by the embodiment of the present application;
  • Figure 16A is the first side view corresponding to Figures 15A and 15B provided by the embodiment of the present application;
  • Figure 16B is the second side view corresponding to Figures 15A and 15B provided by the embodiment of the present application.
  • FIG. 17 is a schematic diagram of a radio frequency transceiver system provided by an embodiment of the present application.
  • a chip package includes a chip and a packaging substrate.
  • Chips include but are not limited to intermediate frequency (Intermediate Frequency, IF) chips, radio frequency (Radio Frequency, RF) chips, central processing unit (Central Processing Unit, CPU), graphics processing unit (Graphics Processing Unit, GPU), field programmable logic gate Array (Field Programmable Gate Array, FPGA) and neural network processor (Neural network Processing Unit, NPU), etc.
  • solder ball connection between the chip package and the PCB as an example, continue to refer to FIG. 1, there is a gap between the solder balls 30, so that the solder balls 30 become a leakage source of electromagnetic radiation, which affects the performance of the chip 11, and will also Electromagnetic interference is caused to the radio frequency circuit contained in the electronic equipment itself, as well as the processor and memory that need to use the clock signal.
  • the present application provides a chip system and a communication device.
  • the chip system includes a chip package and an electromagnetic shielding body, the chip package is electrically connected to the circuit board through the first connection part, and the chip package includes a package substrate and at least one chip. An electrical connection is made between the packaging substrate and the at least one chip.
  • the electromagnetic shielding body includes a conductive first shielding structure and a conductive second shielding structure.
  • the first shielding structure is connected to the packaging substrate, the first cavity of the first shielding structure is used to accommodate at least one chip, the first end of the second shielding structure is connected to the circuit board or a pad on the circuit board, and the first end of the second shielding structure The two ends are connected to the first shielding structure to form the second cavity, or the first end of the second shielding structure is connected to the pad on the circuit board or connected to the circuit board, and the second shielding structure covers the first shielding structure to form the second cavity. Two cavities, the first connecting part is located in the second cavity.
  • the electromagnetic shielding body provided by this application can realize electromagnetic shielding for the first connecting part, reduce the electromagnetic leakage of the first connecting part, further improve the electromagnetic shielding capability of the chip package, ensure the performance of the chip, and reduce other The effects of electromagnetic leakage on circuit components.
  • Words such as “first” and “second” in the description of the present application are used for description purposes only, and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • orientation terms such as “upper” and “lower” may include, but are not limited to, definitions relative to the schematic placement orientations of components in the drawings. It should be understood that these directional terms may be relative concepts, They are used for description and clarification relative to, which may change accordingly according to changes in the orientation in which parts of the figures are placed in the figures.
  • “communication” should be understood in a broad sense.
  • “communication” can be fixed connection, detachable connection, or integration; Can be connected indirectly through an intermediary.
  • the chip package may include one chip or multiple chips.
  • the following embodiments all take the chip package including one chip as an example for illustration.
  • FIG. 2A this figure is a schematic cross-sectional view of a chip system provided by an embodiment of the present application.
  • the illustrated chip package includes a chip 11 and a packaging substrate 14 .
  • the packaging substrate 14 may be a circuit board including multiple conductive layers, and the upper surface and the lower surface of the packaging substrate 14 are provided with exposed pad structures.
  • the chip 11 is electrically connected to the package substrate 14 .
  • the surface of the chip 11 includes metal bumps, and the chip 11 and the packaging substrate 14 are soldered.
  • the solder can be tin-containing alloy solder, and solder paste is printed on the surface of the substrate by reflow soldering. Realize the connection between the chip and the substrate.
  • the electromagnetic shielding body includes: a first shielding structure 13 and a second shielding structure 16 .
  • Both the first shielding structure 13 and the second shielding structure 16 are conductive structures.
  • the first shielding structure 13 is connected to the packaging substrate 14 , the first shielding structure 13 includes a first inner cavity, and the chip 11 is located in the first inner cavity of the first shielding structure 13 .
  • the second shielding structure 16 is located outside the first shielding structure 13, and at least a part of the second cavity is located between the packaging substrate and the circuit board. At this time, the second shielding structure can be connected to the outside of the first shielding structure, which is easy to process and shape. Layer shielding structure improves electromagnetic shielding performance.
  • the second cavity is located between the packaging substrate and the circuit board, and is used for accommodating the first connection part, so as to realize electromagnetic shielding for the first connection part.
  • the chip package is electrically connected to the PCB 20 through the first connecting portion.
  • the first connecting part includes a plurality of electrical connecting structural parts, and the electrical connecting structural parts may include metal solder balls, sintering, metal structural parts or plug terminals, etc., and may also be other electrical connecting structural parts, so as to realize the connection between the first connecting part and
  • the electrical connection between the PCBs 20 is not specifically limited in this embodiment of the present application.
  • the electrical connection structural member of the first connection part is the metal solder ball 30 as an example for illustration.
  • FIG. 2B this figure is a side view corresponding to FIG. 2A provided by the embodiment of the present application.
  • FIG. 2B is a schematic diagram of external observation.
  • the first end of the second shielding structure 16 is connected to the circuit board 20, or connected to the pad 201 on the circuit board 20, and the second end of the second shielding structure 16
  • the first shielding structure 13 is connected to form a second cavity, the second shielding structure 16 completely covers the side of the package substrate, and the first connection part is located in the second cavity formed around itself, at this time, the external observation shown in FIG. 2B
  • the first connection part is completely blocked by the second shielding structure 16 .
  • the electromagnetic shield formed by the first shielding structure 13 and the second shielding structure 16 covers the chip package and the first connection part, reduces the electromagnetic leakage of the first connection part, and then improves the electromagnetic shielding of the chip package The ability ensures the performance of the chip, and can also reduce the influence of electromagnetic leakage on other circuit components.
  • the second shielding structure 16 partially covers the side of the package substrate, thereby saving materials.
  • this figure is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • the packaging substrate 14 and the PCB 20 may be connected by a ball grid array (Ball Grid Array, BGA) package or a land grid array (Land Grid Array, LGA) package.
  • BGA Ball Grid Array
  • LGA Land Grid Array
  • a plurality of solder balls between the package substrate 14 and the PCB 20 form an array and are distributed between the package substrate and the PCB 20 so that the PCB 20 communicates with the chip package.
  • the required contacts for connecting the chip package body to the PCB 20 are located on the PCB 20 , and the underside of the package substrate covers the grid-shaped connection ends.
  • the point contact technology is used to make the PCB20 communicate with the chip package, and the PCB20 provides pins, which can replace the solder balls in the BGA package.
  • the multiple electrical connection structures of the first connection part in FIG. 3 are specifically a plurality of metal solder balls 30. Specific limits. It can be understood that, in some other embodiments, when the packaging method is replaced by LGA, the first connection part includes pins and contacts, which will not be repeated in this embodiment of the present application.
  • the first surface of the chip 11 is fixed to the first shielding structure 13 through the first material 12 .
  • the first material 12 is a thermal interface (Thermal Interface Material, TIM) material, and the thermal interface material is mostly a flexible material, such as a gel or a silicone grease material, which is filled in the first layer of the chip 11.
  • TIM Thermal Interface Material
  • the thermal interface material is mostly a flexible material, such as a gel or a silicone grease material, which is filled in the first layer of the chip 11.
  • the second surface of the chip 11 is electrically connected to the first surface of the packaging substrate 14 .
  • the surface of the chip 11 includes metal bumps
  • the upper surface of the packaging substrate 14 includes pads
  • solder paste is printed on the surface of the packaging substrate 14
  • the chip 11 and the packaging substrate 14 are soldered by reflow soldering.
  • an underfill material can be injected between the chip 11 and the packaging substrate 14 to improve the stability of the connection.
  • the underfill material is an insulating material.
  • the embodiment of the present application does not limit the specific type of the underfill material. , such as epoxy resin.
  • the first shielding structure 13 is fixed to the first surface of the packaging substrate 14 through the second connecting portion 15 .
  • the first shielding structure 13 is fixed to the first surface of the packaging substrate 14 through the second connection portion 15, and the first shielding structure 13 is also fixed to the first surface of the chip 11 through the first material 12, the first shielding structure 13 is improved. stability, when the packaging substrate is fixed to the circuit board 20 through the first connection portion, the position of the first shielding structure 13 relative to the circuit board is also fixed.
  • the first shielding structure 13 is a metal structural part, and the metal structural part may be formed by stamping or casting, which is not specifically limited in this embodiment of the present application.
  • the metal structure has a groove structure, and the groove is used to accommodate the corresponding part of the chip package, thereby realizing electromagnetic shielding of the chip package.
  • the second connecting portion 15 is metal solder, and the first shielding structure 13 is welded to the first surface of the packaging substrate 14 through the second connecting portion 15. At this time, the first shielding structure 13 and the packaging substrate 14 The connection is firm, and the electromagnetic shielding body has good electromagnetic shielding performance.
  • the second connection part 15 is conductive glue
  • the first shielding structure 13 is fixed to the first surface of the packaging substrate 14 through the second connection part 15. This method can make the electromagnetic shielding body have good performance. electromagnetic shielding performance.
  • the second connection part is insulating melt
  • the first shielding structure 13 is fixed to the first surface of the packaging substrate 14 through the second connection part 15, which reduces the difficulty of manufacturing process and can Make the connection between the first shielding structure 13 and the packaging substrate firm.
  • the lower surface of the packaging substrate 14 is electrically connected to the PCB 20 through metal solder balls 30 , specifically, the electrical connection between the substrate circuit 14 and the PCB can be realized through a reflow process.
  • the PCB 20 includes multiple layers of circuit layers, and the PCB shown in the figure is only an illustration, and does not constitute a limitation to the technical solution of the present application.
  • the pad 201 is a metal pad.
  • the pad 201 is connected to the ground circuit layer of the PCB. Examples are not specifically limited.
  • the first connection portion also includes an insulating material 17 .
  • connection area between the chip package and the circuit board 20 is filled with the insulating material 17 , that is, the connection area between the lower surface of the package substrate 14 and the PCB 20 is filled with the insulating material 17 .
  • the insulating material 17 can be an underfill material, such as epoxy resin material, etc., and the insulating material 17 can fill the gaps between the plurality of metal solder balls through the capillary principle.
  • the insulating material 17 can fill the gaps between the plurality of metal solder balls as much as possible, or only fill the insulating material 17 at the edge of the connection area between the chip package and the circuit board 20 .
  • the second shielding structure 16 shown in the figure covers the sidewall of the insulating material 17, the first end of the second shielding structure 16 is connected to the pad 201, and the pad 201 is grounded, thereby improving the electromagnetic shielding effect on the chip 11 and the first connecting portion. Electromagnetic shielding capability, the second end of the second shielding structure 16 is connected to the first shielding structure 13 .
  • the second shielding structure 16 surrounds each metal solder ball 30 inside, thereby realizing electromagnetic shielding for the metal solder ball 30 .
  • the insulating material 17 can also play a supporting role, and the second shielding structure can be closely attached to the side wall of the insulating material, which is more stable and reliable.
  • the second shielding structure 16 is any one of a conductive film, a metal material or a conductive adhesive material, which is not specifically limited in this embodiment of the present application.
  • the conductive film can be formed by spraying.
  • the metal material can be deposited by metal sputtering or electroplating, and the metal material can be copper, silver or other metal materials, which are not specifically limited in the embodiment of the present application.
  • the conductive adhesive material can be formed by coating.
  • a commonly used conductive adhesive material may be a conductive adhesive material containing metallic silver, that is, conductive silver adhesive.
  • FIG. 4A is an enlarged view of area A in FIG. 3 provided by the embodiment of the present application.
  • the side wall formed by the insulating material 17 extends outward along the direction from top to bottom.
  • the first connection portion filled with the insulating material 17 includes two connection surfaces, one connection surface close to the circuit board is the first connection surface, and the other connection surface close to the chip package is the second connection surface.
  • the width of the first connection surface is greater than the width of the second connection surface. That is, the upper side of the insulating material 17 is narrow and the lower side is wider.
  • the conductive film can be formed by spraying on the side walls of the insulating material 17 to ensure that the second shielding structure 16 surrounds the metal solder balls 30 inside. .
  • the metal material can be deposited by metal sputtering deposition or electroplating process, and can also rely on the sidewall of insulating material 17 to ensure that the second shielding structure 16 welds each metal
  • the ball 30 surrounds the inside.
  • the conductive adhesive material can be formed by coating, relying on the sidewall of the insulating material 17, so as to ensure that the second shielding structure 16 surrounds each metal solder ball 30 inside .
  • the sidewalls of the insulating material 17 can provide support for the second shielding structure 16 .
  • the insulating material 17 can also strengthen the connection between the PCB and the package substrate.
  • the insulating material 17 in the following drawings and descriptions of the present application is the filling method in FIG. 4A , which will not be repeated one by one.
  • FIG. 4B is a top view corresponding to FIG. 3 provided by the embodiment of the present application.
  • the top view shown in FIG. 4B is a cross-sectional view from a top view angle.
  • the first shielding structure 13, the second shielding structure 16 and the PCB 20 together form a cavity, and the second shielding structure 16 completely covers the side of the package substrate 14, and makes the first connecting portion Located within the cavity formed around itself.
  • the pads shown in FIG. 4B surround the chip package and are used to fully fix the first end of the second shielding structure 16, so as to improve the stability of the connection of the second shielding structure 16 and improve the electromagnetic shielding capability of the electromagnetic shielding body. .
  • the pads may not surround the chip package to save material.
  • the electromagnetic shield formed by the first shielding structure 13 and the second shielding structure 16 covers the chip package and the first connection part, reduces the electromagnetic leakage of the first connection part, and then improves the electromagnetic shielding of the chip package The ability ensures the performance of the chip, and can also reduce the influence of electromagnetic leakage on other circuit components.
  • this figure is a schematic cross-sectional view of another electromagnetic shielding body of a chip package provided by an embodiment of the present application.
  • the second shielding structure 16 of the electromagnetic shielding body is a conductive film, and the conductive film can also completely cover the second shielding structure 13.
  • the second shielding structure 16 can be connected to the first shielding structure through an adhesive material (Cohensive). 13 connection, that is, adding an adhesive material on the contact surface between the second shielding structure 16 and the first shielding structure 13, so as to improve the stability of the connection between the two.
  • this figure is a waveform diagram of a simulation test provided by an embodiment of the present application.
  • the waveform diagrams illustrating the simulation test show the shielding effectiveness in the frequency band from 2 GHz to 10 GHz when the schemes in Fig. 3 and Fig. 1 are adopted respectively.
  • Shielding effectiveness shows the degree of attenuation of electromagnetic waves by the shielding body. Since shielding can usually attenuate the intensity of electromagnetic waves to one percent to one ten thousandth of the original, it is usually expressed in decibels (dB).
  • the shielding performance can be increased by about 7dB to 8dB. That is, the electromagnetic leakage of the solder balls can be reduced, thereby improving the electromagnetic shielding capability of the chip package and ensuring the performance of the chip.
  • this figure is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • the first surface of the chip 11 is connected to the first shielding structure 13 through the first material 12 .
  • the second surface of the chip 11 is electrically connected to the first surface of the packaging substrate 14 .
  • the first shielding structure 13 is fixed to the sidewall of the packaging substrate 14 through the second connecting portion 15 .
  • the first material 12 can be a thermal interface material, and the thermal interface material is filled between the first surface of the chip 11 and the first shielding structure.
  • the heat is quickly conducted to the first shielding structure, on the other hand, it provides support for the first shielding structure and improves the stability of the first shielding structure.
  • the first shielding structure is fixed to the side wall of the package substrate, and then surrounds the side of the chip package, thereby improving the effect of electromagnetic shielding.
  • the second connecting portion 15 is metal solder, and the first shielding structure 13 is welded to the side wall of the packaging substrate 14 through the second connecting portion 15. At this time, the first shielding structure 13 and the packaging substrate 14 The connection is firm, and the electromagnetic shielding body has good electromagnetic shielding performance.
  • the second connection part 15 is conductive glue
  • the first shielding structure 13 is fixed to the side wall of the packaging substrate 14 through the second connection part 15. This method can make the electromagnetic shielding body have good performance. Electromagnetic shielding performance.
  • the second connecting portion 15 is insulating melt, and the first shielding structure 13 is fixed to the sidewall of the package substrate 14 through the second connecting portion 15, which reduces the difficulty of manufacturing process and can Make the connection between the first shielding structure and the packaging substrate firm.
  • the first end of the second shielding structure 16 is connected to the pad 201, and the grounding of the pad 201 improves the electromagnetic shielding ability of the electromagnetic shielding body to the chip and the first connection part, and the second end of the second shielding structure 16 is connected to the first shielding structure 13 .
  • this figure is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • the first connecting part further includes an insulating material 17 .
  • the insulating material 17 is filled between the chip package, the circuit board 20 and the plurality of metal solder balls 30 , that is, the insulating material 17 is filled in the gap between the lower surface of the package substrate 14 and the PCB 20 .
  • the insulating material 17 can be an underfill material, such as epoxy resin material, etc., and the insulating material 17 can fill the gaps between the plurality of metal solder balls through the capillary principle.
  • the insulating material 17 can fill the space between the chip package, the circuit board 20 and the plurality of metal solder balls as much as possible, or only fill the insulating material 17 at the edge of the connection area between the chip package and the circuit board 20 .
  • the second shielding structure 16 covers the sidewall of the insulating material 17, the first end of the second shielding structure 16 is connected to the pad 201, and the pad 201 is grounded, thereby improving the electromagnetic shielding ability of the electromagnetic shielding body to the chip and the first connection part, A second end of the second shielding structure 16 is connected to the first shielding structure 13 .
  • using the electromagnetic shielding body provided by this application can achieve electromagnetic shielding for the first connecting part, reduce the electromagnetic leakage of the first connecting part, further improve the electromagnetic shielding capability of the chip package, and ensure the performance of the chip , It can also reduce the influence of electromagnetic leakage on other circuit components.
  • FIG. 8 this figure is a schematic cross-sectional view of another chip system provided by the embodiment of the application.
  • the chip package shown in FIG. 8 also includes a molding compound 18 , and the chip 11 is embedded in the molding compound 18 .
  • the chip 11 is electrically connected to the first surface of the packaging substrate 14 , and the first shielding structure covers the outer surface of the molding compound 18 and the sidewall of the packaging substrate 14 .
  • the first shielding structure 13 may be a conductive film, a metal material or a conductive adhesive material.
  • the conductive film may be formed by spraying.
  • the metal material can be deposited by metal sputtering or electroplating, and the metal material can also be a stamped or cast metal structure.
  • the conductive adhesive material may be formed by coating.
  • the molding compound 18 can assist heat dissipation, so that the heat generated by the chip can be quickly transferred to the first shielding structure 13; Stability also enables the first shielding structure 13 to be formed by relying on the molding compound 18 .
  • the first shielding structure 13 covers the outer surface of the molding compound 18 and the sidewall of the package substrate 14 , and further surrounds the chip package, thereby improving the effect of electromagnetic shielding.
  • the second surface of the chip 11 is electrically connected to the first surface of the packaging substrate 14 .
  • the surface of the chip 11 includes metal bumps
  • the upper surface of the packaging substrate 14 includes pads
  • solder paste is printed on the surface of the packaging substrate 14
  • the chip 11 and the packaging substrate 14 are soldered by reflow soldering.
  • an underfill material can be injected between the chip 11 and the packaging substrate 14 to improve the stability of the connection.
  • the underfill material is an insulating material. The embodiment of the present application does not limit the specific type of the underfill material, for example, For epoxy resin.
  • the lower surface of the packaging substrate 14 is electrically connected to the PCB 20 through metal solder balls 30 , specifically, the electrical connection between the substrate circuit 14 and the PCB can be realized through a reflow process.
  • the pad 201 is a metal pad.
  • the pad 201 is connected to the ground circuit layer of the PCB.
  • the connection between the pad 201 and the ground circuit layer of the PCB can be a plated through-hole structure or slotting
  • the electroplating structure is not specifically limited in this embodiment of the present application.
  • the second shielding structure 16 surrounds each metal solder ball 30 inside, thereby realizing electromagnetic shielding for the metal solder ball 30 .
  • the implementation manners of the second shielding structure and the first shielding structure may be the same or different, which is not specifically limited in this application.
  • the conductive film can be formed by spraying; when the second shielding structure is realized by a metal material, the metal material can be deposited by metal sputtering or electroplating; When the second shielding structure is realized by using a conductive adhesive material, the conductive adhesive material may be formed by coating.
  • this figure is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • the first connecting part further includes an insulating material 17 .
  • the area between the package substrate of the chip package, the circuit board 20 and the plurality of metal solder balls is filled with the insulating material 17 , that is, the gap between the lower surface of the package substrate 14 and the PCB 20 is filled with the insulating material 17 .
  • the insulating material 17 can use an underfill material, such as epoxy resin material, etc., and the insulating material 17 can fill the gaps between multiple metal solder balls through the capillary principle.
  • the insulating material 17 can fill as much as possible the area between the packaging substrate of the chip package, the circuit board 20 and the plurality of metal solder balls, or only fill the insulating material 17 at the edge of the connection area between the chip package and the circuit board 20 .
  • the second shielding structure 16 covers the sidewall of the insulating material 17, the first end of the second shielding structure 16 is connected to the pad 201, and the pad 201 is grounded to improve the electromagnetic shielding ability of the electromagnetic shielding body to the chip and the first connection part.
  • the second end of the shielding structure 16 is connected to the first shielding structure 13 .
  • using the electromagnetic shielding body provided by this application can achieve electromagnetic shielding for the first connecting part, reduce the electromagnetic leakage of the first connecting part, further improve the electromagnetic shielding capability of the chip package, and ensure the performance of the chip , It can also reduce the influence of electromagnetic leakage on other circuit components.
  • FIG. 10 is a schematic cross-sectional view of another chip system provided by the embodiment of the present application.
  • the difference between the electromagnetic shielding body shown in FIG. 10 and FIG. 8 is that the first shielding structure 13 covers the outer surface of the molding compound 18 and extends to the first surface of the packaging substrate 14 .
  • the plastic encapsulant 18 can assist heat dissipation, so that the heat generated by the chip 11 can be quickly transferred to the first shielding structure 13; on the other hand, it provides support for the first shielding structure 13, improving the stability of the first shielding structure sex.
  • the first shielding structure covers the outer surface of the molding compound and the sidewall of the packaging substrate. Compared with the implementation in FIG. 8 , the usage of the molding compound 18 and the material consumption of the first shielding structure 13 are reduced.
  • the conductive film can be formed by spraying; when the first shielding structure 13 is realized by a metal material, the metal material can be deposited by metal sputtering or electroplating Generation; when the first shielding structure 13 is realized by using a conductive adhesive material, the conductive adhesive material may be formed by coating.
  • the first end of the second shielding structure 16 is connected to the pad 201 on the PCB 20, the pad 201 is grounded to improve the electromagnetic shielding ability of the electromagnetic shielding body to the chip and the metal solder ball, and the second end of the second shielding structure 16 is connected to the first shielding structure 13 , at this moment, the second shielding structure 16 also covers the side surface of the packaging substrate 14 .
  • the implementation manners of the second shielding structure 16 and the first shielding structure 13 may be the same or different, which is not specifically limited in this embodiment of the present application.
  • the conductive film can be formed by spraying; when the second shielding structure 16 is realized by a metal material, the metal material can be deposited by metal sputtering or electroplating. Formation; when the second shielding structure 16 is realized by using a conductive adhesive material, the conductive adhesive material may be formed by coating.
  • FIG. 11 this figure is a schematic cross-sectional view of another chip system provided by an embodiment of the present application.
  • the first connection part further includes an insulating material 17 .
  • the area between the packaging substrate of the chip package, the circuit board 20 and the plurality of metal solder balls 30 is filled with the insulating material 17 , that is, the gap between the lower surface of the packaging substrate 14 and the PCB 20 is filled with the insulating material 17 .
  • the insulating material 17 can use an underfill material, such as epoxy resin material, etc., and the insulating material 17 can fill the gaps between multiple metal solder balls through the capillary principle.
  • the insulating material 17 can fill as much as possible the area between the packaging substrate of the chip package, the circuit board 20 and the plurality of metal solder balls 30 , or only fill the insulating material 17 at the edge of the connection area between the chip package and the circuit board 20 .
  • the second shielding structure 16 covers the sidewall of the insulating material 17, the first end of the second shielding structure 16 is connected to the pad 201, and the pad 201 is grounded, thereby improving the electromagnetic shielding ability of the electromagnetic shielding body to the chip and the first connection part, A second end of the second shielding structure 16 is connected to the first shielding structure 13 .
  • using the electromagnetic shielding body provided by this application can achieve electromagnetic shielding for the first connecting part, reduce the electromagnetic leakage of the first connecting part, further improve the electromagnetic shielding capability of the chip package, and ensure the performance of the chip , It can also reduce the influence of electromagnetic leakage on other circuit components.
  • FIG. 12 this figure is a schematic cross-sectional view of another chip system provided by the embodiment of the present application.
  • Fig. 12 is a top view of the plane where the x and y axes are located.
  • the chip package 10 is represented by a solid line frame, and the first shielding structure is not shown in Fig. 12 and a second shielding structure.
  • the chip package 10 includes a chip and a packaging substrate, the packaging substrate is located on the pad 201 , the first end of the second shielding structure is electrically connected to the pad 201 , and the second end of the second shielding structure is electrically connected to the first shielding structure.
  • the pins on the PCB 20 include first pins 202 and ground pins 203 , and the application does not specifically limit the specific distribution and quantity of the first pins 202 and ground pins 203 .
  • the first pin 202 is a signal transmission pin
  • the ground pin 203 is used for grounding.
  • the projection of the first pin 202 on the plane where the x and y axes are located is located in the range covered by the outline of the chip package 10; the projection of the grounding pin 203 on the plane where the x and y axes are located is partially located in the area covered by the outline of the chip package 10 within the range covered by the outline of the chip package body 10 , or all located outside the range covered by the outline of the chip package body 10 , the present application will take a part within the range covered by the outline of the chip package body 10 as an example for illustration.
  • the projections of the two sides of the pad 201 on the plane where the x and y axes are located are located outside the range covered by the outline of the chip package 10, and the areas extending from both sides of the pad 201, that is, the B area and the B1 area shown in the figure, are represented by
  • the welding pad 201 is electrically connected to the first shielding structure through a creeping soldering process.
  • the embodiment of the present application does not limit the specific area of the B1 area of the B area.
  • Area C and area C1 in the figure are areas where the chip package 10 and the PCB 20 are electrically connected.
  • the required contacts when the chip package 10 is connected to the PCB 20 are located on the PCB 20 , and the underside of the package substrate covers the grid-shaped connection terminals.
  • the point contact technology is used to make the PCB20 communicate with the chip package, and the PCB20 provides pins, which can replace the solder balls in the BGA package.
  • the region can be filled with insulating material, and the insulating material can be an underfill material, such as epoxy resin material, etc., and the insulating material can fill the gap through capillary principle.
  • the insulating material can be an underfill material, such as epoxy resin material, etc., and the insulating material can fill the gap through capillary principle.
  • the region may not be filled with insulating material.
  • FIG. 13A this figure is the first schematic cross-sectional view corresponding to FIG. 12 provided by the embodiment of the present application.
  • Figure 13A is a cross-sectional view of the plane where the x and z axes are located
  • the areas extending from both sides of the pad 201 ie, the B area and the B1 area shown in the figure, are used to form the second shielding structure 16 through a creep soldering process, so that the pad 201 is electrically connected to the first shielding structure 13 .
  • one end of the second shielding structure 16 is connected to the pad 201 , and the other end is connected to the first shielding structure 13 .
  • the first surface of the chip 11 is fixed to the first shielding structure 13 through the first material 12 .
  • the first material 12 is a TIM material
  • the TIM material is mostly a flexible material, such as a gel or a silicone material, which is filled between the first surface of the chip 11 and the first shielding structure 13
  • the TIM material can assist heat dissipation, so that the heat generated by the chip 11 can be quickly transferred to the first shielding structure; on the other hand, it provides support for the first shielding structure 13, thereby improving the stability of the first shielding structure 13 .
  • the first shielding structure 13 is a metal structural part, and the metal structural part may be formed by stamping or casting, which is not specifically limited in this embodiment of the present application.
  • the metal structure has a groove structure, and the groove is used to accommodate the corresponding part of the chip package, thereby realizing electromagnetic shielding of the chip package.
  • the pad 201 Since the pad 201 is electrically connected to the first shielding structure 13 through the second shielding structure 16, when the pad 201 is grounded, the second shielding structure 16 and the first shielding structure 13 are also grounded, which improves the performance of electromagnetic shielding.
  • ground pins 203 on the PCB 20 are partly located outside the range covered by the outline of the chip package 10, they can also be electrically connected to the first shielding structure 13 through a process of creep soldering, thereby avoiding the need for wiring on the PCB 20. ground, simplifying the ground wiring.
  • FIG. 13B is the second schematic cross-sectional view corresponding to FIG. 12 provided by the embodiment of the present application.
  • 13B is a cross-sectional view of the plane where the x and z axes lie.
  • the chip package also includes a plastic encapsulant 18 , and the chip 11 is embedded in the plastic encapsulant 18 .
  • the first shielding structure 13 may be a conductive film, a metal material or a conductive adhesive material.
  • the conductive film may be formed by spraying.
  • the metal material can be deposited by metal sputtering or electroplating, and the metal material can also be a stamped or cast metal structure.
  • the conductive adhesive material may be formed by coating.
  • the molding compound 18 can assist heat dissipation, so that the heat generated by the chip can be quickly transferred to the first shielding structure 13; Stability also enables the first shielding structure 13 to be formed by relying on the molding compound 18 .
  • the first shielding structure 13 covers the outer surface of the molding compound 18 and the sidewall of the package substrate 14 , and further surrounds the chip package, thereby improving the effect of electromagnetic shielding.
  • FIG. 14 this figure is the first side view corresponding to FIG. 12 provided by the embodiment of the present application.
  • Fig. 14 is a side view of the plane where the y and z axes are located.
  • the second shielding structure 16 is formed by using the process of creep welding, so that the pad 201 is electrically connected to the first shielding structure 13, and the second shielding structure 16 only Part of the second shielding structure 16 is covered to save material.
  • the part of the ground pin 203 extending to the outside of the chip package body 10 can also form the second shielding structure 16 through a creep soldering process to realize the electrical connection with the first shielding structure 13, thereby avoiding the grounding of the PCB 20 through wiring, simplifying ground line.
  • the ground pin 203 , the bonding pad 201 , the first shielding structure 13 and the second shielding structure 16 surround the first pin 202 , which also improves the electromagnetic shielding performance of the chip system.
  • FIG. 15A this figure is the third schematic cross-sectional view corresponding to FIG. 12 provided by the embodiment of the present application.
  • FIG. 15A is a cross-sectional view of the plane where the x and z axes are located.
  • the difference between the chip system shown in FIG. 15A and FIG. 13A is that the second shielding structure 16 of the chip system shown in 15A is a conductive film, and the conductive film covers the outside of the second shielding structure 13. .
  • FIG. 15B is a schematic cross-sectional view corresponding to FIG. 12 provided in the embodiment of the present application.
  • FIG. 15B is a cross-sectional view of the plane where the x and z axes lie.
  • the difference between the chip system shown in FIG. 15B and FIG. 15A is that the chip package also includes a plastic encapsulant 18 in which the chip 11 is embedded.
  • the first shielding structure 13 may be a conductive film, a metal material or a conductive adhesive material.
  • the conductive film may be formed by spraying.
  • the metal material can be deposited by metal sputtering or electroplating, and the metal material can also be a stamped or cast metal structure.
  • the conductive adhesive material may be formed by coating.
  • the molding compound 18 can assist heat dissipation, so that the heat generated by the chip can be quickly transferred to the first shielding structure 13; Stability also enables the first shielding structure 13 to be formed by relying on the molding compound 18 .
  • the first shielding structure 13 covers the outer surface of the molding compound 18 and the sidewall of the package substrate 14 , and further surrounds the chip package, thereby improving the effect of electromagnetic shielding.
  • FIG. 16A this figure is the first side view corresponding to FIGS. 15A and 15B provided by the embodiment of the present application.
  • Fig. 16A is a side view of the plane where the y and z axes are located, and the second shielding structure includes two parts at this time.
  • the first part of the second shielding structure is a conductive film, which covers the outside of the second shielding structure 13 , and the conductive film is fixed by the areas extending from both sides of the pad 201 .
  • the ground pin 203 extends to the part outside the range of the chip package body 10, and the second part of the second shielding structure 16 is formed by a creep welding process, so as to realize the electrical connection with the first shielding structure 13, thereby avoiding grounding on the PCB 20 through wiring. , simplifying the ground wiring.
  • the ground pin 203 , the bonding pad 201 , the first shielding structure 13 and the second shielding structure 16 surround the first pin 202 , which improves the electromagnetic shielding performance of the chip system.
  • FIG. 16B this figure is the second side view corresponding to FIGS. 15A and 15B provided by the embodiment of the present application.
  • FIG. 16B is a side view of the plane where the y and z axes are located.
  • the second shielding structure 16 is a conductive film
  • the ground pin 203 extends to the part outside the range of the chip package 10. and the parts extending out of the chip package 10 on both sides of the pad 201 are used for electrical connection with the conductive film.
  • the conductive film can completely cover the first shielding structure 13 or completely cover the sidewall of the first shielding structure 13 .
  • the pad 201 , the first shielding structure 13 and the second shielding structure 16 surround the first pin 202 , which improves the electromagnetic shielding performance of the chip system.
  • the first pin 202 and the ground pin 203 are located on the upper and lower sides of the chip package 10 in the chip system as an example. As the number of ground pins 203 changes, their layout positions can be adjusted accordingly, and can be arranged on only one side, or on three sides, or on four sides, which will not be repeated here.
  • an embodiment of the present application further provides a communication device using the system-on-a-chip, which will be described in detail below.
  • the communication device includes a PCB, and chip packages corresponding to intermediate frequency (Intermediate Frequency, IF) chips and radio frequency (Radio Frequency, RF) chips on the PCB may use the chip system provided in the above embodiments.
  • IF Intermediate Frequency
  • RF Radio Frequency
  • this figure is a schematic diagram of a radio frequency transceiver system provided by an embodiment of the present application.
  • the radio frequency transceiver 01 applied to the wireless communication system supports multiple-input multiple-output (Multiple-Input Multiple-Output, MIMO) function, and can transmit signals to different user equipments (User Equipment, UE) simultaneously by using multiple transmitting antennas, And use multiple receiving antennas to simultaneously receive signals sent by multiple UE02s.
  • MIMO Multiple-Input Multiple-Output
  • the radio frequency transceiver system provided in the embodiment of the present application includes: a radio frequency transceiver 01 and a baseband processing unit (Base band Unit, BBU) 03.
  • BBU Base band Unit
  • a radio frequency transceiver system generally includes multiple radio frequency transceivers 01 and multiple BBUs 03 .
  • One BBU03 supports simultaneous access to multiple radio frequency transceivers 01, and this embodiment of the present application does not limit the specific number of radio frequency transceivers 01 that one BBU03 simultaneously accesses.
  • the number of radio frequency transceivers 01 connected to each BBU 03 may be the same or different, which is not specifically limited in this embodiment of the present application.
  • the RF transceiver 01 is connected to the BBU03 through an optical fiber.
  • the RF transceiver 01 obtains the optical signal sent by the BBU through an optical fiber, converts the optical signal into a high-speed electrical signal through an optical module, and passes through the internal baseband circuit, intermediate frequency circuit and After processing by the radio frequency power amplifier circuit, it transmits to multiple user equipments through multiple transmitting antennas; on the other hand, the radio frequency transceiver 01 can receive radio frequency signals sent by multiple user equipments through multiple receiving antennas, and transmit the signals through the internal radio frequency
  • the power amplification circuit, intermediate frequency circuit and baseband circuit are processed and converted into high-speed electrical signals, and then the high-speed electrical signals are converted into optical signals through optical modules and then transmitted to BBU03 through optical fibers.
  • the intermediate frequency chip of the intermediate frequency circuit can apply the chip system provided by the embodiment of the present application, that is, the above electromagnetic shielding body is used to arrange the chip package of the intermediate frequency chip on the PCB where the intermediate frequency circuit is located.
  • the chip system included in the communication device provided by the embodiment of the present application can realize electromagnetic shielding for the first connecting part, reduce the electromagnetic leakage of the first connecting part, improve the electromagnetic shielding capability of the chip package, and ensure It not only improves the performance of the chip, but also reduces the influence of electromagnetic leakage on other circuit components, thus improving the performance of communication equipment.

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Abstract

本申请公开了一种芯片系统及通信设备，涉及芯片封装技术领域。芯片系统包括芯片封装体和电磁屏蔽体，芯片封装体通过第一连接部与电路板电连接，芯片封装体包括电连接的封装基板和至少一个芯片，电磁屏蔽体包括导电的第一屏蔽结构和导电的第二屏蔽结构；第一屏蔽结构与封装基板连接；第一屏蔽结构包括的第一腔体用于容纳至少一个芯片；第二屏蔽结构的第一端连接电路板或电路板的焊盘或，第二屏蔽结构的第二端连接第一屏蔽结构以形成第二腔体；或，第二屏蔽结构的第一端连接电路板或电路板上的焊盘，第二屏蔽结构覆盖第一屏蔽结构以形成第二腔体；第一连接部位于第二腔体内。该方案降低了第一连接部的电磁泄漏，提升了对芯片封装的电磁屏蔽能力。

Description

一种芯片系统及通信设备
本申请要求于2021年12月06日提交中国国家知识产权局、申请号为202111479134.2、发明名称为“一种芯片系统及通信设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，尤其涉及一种芯片系统及通信设备。
背景技术
随着半导体工艺尺寸不断缩小，电子设备内的各类芯片的集成度逐渐提高，芯片的工作频率不断提高，这使得电子设备内部尺寸较小的导电元件或导电结构会成为天线，向外进行电磁辐射，进而对电子设备自身包含的易受射频干扰影响的射频电路，以及需要使用时钟信号的处理器、存储器等造成电磁干扰。减少电磁辐射影响的常规方法是对产生电磁辐射辐射器件，或对易受电磁辐射影响的敏感器件设置电磁屏蔽体。
参见图1，该图为传统芯片封装体的电磁屏蔽体的示意图。
图示的芯片封装体包括了芯片11和封装基板14。芯片11和封装基板14之间通过焊球焊接。电磁屏蔽体13一般为技术冲压结构，覆盖芯片11上方即侧面，并且与封装基板14的上表面通过连接部15进行固定。芯片11上表面通过热界面材料(Thermal interface material，TIM)12与电磁屏蔽体13接触以加快散热。利用电磁屏蔽体13可以减小芯片11的电磁辐射。
但是由于封装基板14和印制电路板(Printed Circuit Board，PCB)20通过焊球30实现连接，各焊球30之间有间隙，使得焊球30成为电磁辐射的泄漏源，随着芯片11工作频率的不断升高，对降低电磁辐射泄漏的需求不断增强，焊球30泄漏的电磁辐射甚至会严重影响芯片的性能。
发明内容
为了解决上述问题，本申请提供了一种芯片系统及通信设备，降低了第一连接部的电磁泄漏，进而提升了芯片的电磁屏蔽能力，保障了芯片性能。
第一方面，本申请提供了一种芯片系统，该芯片系统包括芯片封装体和电磁屏蔽体，芯片封装体通过第一连接部与电路板电连接，在一种典型的实现方式中，第一连接部包括焊球。芯片封装体包括电连接的封装基板和至少一个芯片，电磁屏蔽体包括导电的第一屏蔽结构和导电的第二屏蔽结构。第一屏蔽结构与封装基板连接，第一屏蔽结构包括第一腔体，第一腔体用于容纳至少一个芯片。第二屏蔽结构的第一端连接电路板或连接电路板上的焊盘，第二屏蔽结构的第二端连接第一屏蔽结构以形成第二腔体，或者，第二屏蔽结构的第一端连接电路板上的焊盘或连接电路板，第二屏蔽结构覆盖第一屏蔽结构以形成第二腔体，第一连接部位于第二腔体内。
本申请提供的芯片系统，第一屏蔽结构和第二屏蔽结构连接后，形成的第二腔体包围第一连接部，由于第一屏蔽结构和第二屏蔽结构均导电，因此第一屏蔽结构和第二屏蔽结构共同起屏蔽作用，能够实现对第一连接部的电磁屏蔽，减少了第一连接部的电磁泄漏，进而提升了电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。 在一种可能的实现方式中，第一连接部包括绝缘材料以及多个电连接结构件，其中，多个电连接结构件用于连接芯片封装体以及电路板，绝缘材料填充于芯片封装体的封装基板、电路板以及多个电连接结构件之间的区域。
在一种典型的实现方式中，电连接结构件为焊球，第一连接部包括焊球和绝缘材料，焊球用于实现芯片封装体和电路板之间的电连接。
一方面，绝缘材料可以起到辅助散热的作用；另一方面，芯片封装体和电路板的连接区域之间填充的绝缘材料还能够起到支撑作用，使得第二屏蔽结构可以紧贴绝缘材料的侧壁，更加稳定可靠，此外还增加了芯片封装体和电路板的连接面积，提升了芯片封装体和电路板之间连接的稳定性。
在一种可能的实现方式中，填充绝缘材料的第一连接部包括两个连接面，靠近电路板的一个连接面为第一连接面，靠近芯片封装体的一个连接面为第二连接面，第一连接面的宽度大于所述第二连接面的宽度。也即绝缘材料在填充后上侧窄，下侧宽，进而可以为第二屏蔽结构提供支撑。
在一种可能的实现方式中，第二屏蔽结构覆盖全部绝缘材料的侧壁，或者部分覆盖绝缘材料的侧壁。
当在芯片封装体和电路板的连接区域填充绝缘材料时，绝缘材料可以通过毛细原理实现填充，第二屏蔽结构覆盖全部或部分绝缘材料的侧壁，也即将各金属焊球包围在内部，进而实现了对金属焊球的电磁屏蔽。同时，当第二屏蔽结构与绝缘材料的边缘接触时，芯片封装体和电路板的连接区域之间填充的绝缘材料还能够起到支撑作用，使得第二屏蔽结构可以紧贴绝缘材料的侧壁，更加稳定可靠。
在一种可能的实现方式中，第二屏蔽结构的第一端连接电路板上的焊盘，以提升第二屏蔽结构连接的稳定性。
在一种可能的实现方式中，第二屏蔽结构的第一端连接电路板上的焊盘，且该焊盘接地。此时该电磁屏蔽体，提升了对芯片以及第一连接部的电磁屏蔽能力。
在一种可能的实现方式中，封装基板位于焊盘上，第二屏蔽结构的第一端与焊盘电连接。
在一种可能的实现方式中，芯片封装体采用栅格阵列LGA封装技术和电路板电连接，芯片封装体的接地引脚与第二屏蔽结构电连接。由于焊盘通过第二屏蔽结构与第一屏蔽结构实现电连接，因此当焊盘接地时，第二屏蔽结构与第一屏蔽结构也接地，提升了电磁屏蔽的性能。
进一步的，电路板上的各接地引脚部分位于芯片封装体轮廓所覆盖的范围外时，也可以通过爬焊的工艺实现与第一屏蔽结构的电连接，进而避免在通过布线接地，简化了接地线路。在一种可能的实现方式中，至少一个芯片中的每个芯片的第一表面通过第一材料与第一屏蔽结构连接。至少一个芯片中的每个芯片的第二表面与封装基板的第一表面电连接，第一屏蔽结构通过第二连接部与封装基板的第一表面连接。
第一材料可以采用热界面(Thermal Interface Material，TIM)材料，热界面材料多为柔性材料，例如可以为凝胶、硅脂类材料，填充在芯片第一表面与第一屏蔽结构之间，一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构，另一方面，提供了对第一屏 蔽结构的支撑，提升了第一屏蔽结构的稳定性。
第一屏蔽结构通过第二连接部与封装基板的第一表面固定，并且第一屏蔽结构还通过第一材料与芯片的第一表面固定，提升了第一屏蔽结构的稳定性，当封装基板通过第一连接部与电路板固定后，第一屏蔽结构相对于电路板的位置也即固定。
在一种可能的实现方式中，第二连接部为金属焊料，第一屏蔽结构通过第二连接部与封装基板的第一表面焊接，此时第一屏蔽结构和封装基板的连接牢固，并且电磁屏蔽体具有良好的电磁屏蔽性能。或，第二连接部为导电胶，第一屏蔽结构通过第二连接部与封装基板的第一表面连接，采用该方式能够使电磁屏蔽体具有良好的电磁屏蔽性能。或，第二连接部为绝缘熔胶，第一屏蔽结构通过第二连接部与封装基板的第一表面连接，该方式降低了工艺制造难度，并且能够使第一屏蔽结构和封装基板的连接牢固。
在一种可能的实现方式中，至少一个芯片中的每个芯片的第一表面通过第一材料与所述第一屏蔽结构连接。至少一个芯片中的每个芯片的第二表面与封装基板的第一表面电连接。
第一屏蔽结构通过第二连接部与封装基板的侧壁连接。
第一材料可以采用热界面材料，第一材料填充在芯片第一表面与第一屏蔽结构之间，一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构，另一方面，提供了对第一屏蔽结构的支撑，提升了第一屏蔽结构连接的稳定性。此外，第一屏蔽结构与封装基板的侧壁连接，进而将芯片封装体包围，提升了电磁屏蔽的效果。
在一种可能的实现方式中，第二连接部为金属焊料，第一屏蔽结构通过第二连接部与封装基板的侧壁焊接，此时第一屏蔽结构和封装基板的连接牢固，并且电磁屏蔽体具有良好的电磁屏蔽性能。或，第二连接部为导电胶，第一屏蔽结构通过第二连接部与封装基板的侧壁连接，采用该方式能够使电磁屏蔽体具有良好的电磁屏蔽性能。或，第二连接部为绝缘熔胶，第一屏蔽结构通过第二连接部与封装基板的侧壁连接，该方式降低了工艺制造难度，并且能够使第一屏蔽结构和封装基板的连接牢固。
在一种可能的实现方式中，第一屏蔽结构为金属结构件。
该金属结构件可以为冲压成型或者铸造成型的具备凹槽结构的金属结构件，本申请实施例对此不作具体限定，凹槽内用于容纳芯片封装体的对应部分，进而实现对芯片封装体的电磁屏蔽。
在一种可能的实现方式中，芯片封装体还包括塑封料。至少一个芯片中的每个芯片埋设于塑封料中。第一屏蔽结构覆盖塑封料的外表面以及封装基板的侧壁。
塑封料一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构，另一方面，提供了对第一屏蔽结构的支撑，提升了第一屏蔽结构连接的稳定性。此外，第一屏蔽结构覆盖塑封料的外表面以及封装基板的侧壁，进而将芯片封装体包围，提升了电磁屏蔽的效果。
在一种可能的实现方式中，芯片封装体还包括塑封料，至少一个芯片中的每个芯片埋设于塑封料中，至少一个芯片中的每个芯片与封装基板的第一表面电连接，第一屏蔽结构覆盖塑封料的外表面并延伸至封装基板的第一表面。
塑封料一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构，另一方 面，提供了对第一屏蔽结构的支撑，提升了第一屏蔽结构连接的稳定性。此外，第一屏蔽结构覆盖塑封料的外表面以及封装基板的侧壁，减少了塑封料的使用量，以及减少了第一屏蔽结构材料消耗。
在一种可能的实现方式中，第一屏蔽结构为导电薄膜、金属材料或导电胶材料中的任意一种。
当第一屏蔽结构采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成；当第一屏蔽结构采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积生成；当第一屏蔽结构采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
在一种可能的实现方式中，第二屏蔽结构为导电薄膜、金属材料或导电胶材料中的任意一种。
在一种可能的实现方式中，第一连接部包括的多个电连接结构可以为金属焊球、烧结、金属结构件或插接端子中的任意一种，电连接结构件还可以采用其它的实现方式，本申请在此不再一一举例说明。
在一种可能的实现方式中，第二屏蔽结构完全包覆第一屏蔽结构，以提升电磁屏蔽能力。当第二屏蔽结构为导电膜时，还能够降低第二屏蔽结构成型难度，此时第二屏蔽结构可以通过粘接材料与第一屏蔽结构连接，也即在第二屏蔽结构与第一屏蔽结构的接触面添加粘接材料，以提升两者连接的稳定性。
第二屏蔽结构和第一屏蔽结构的实现方式可以相同，也可以不同，本申请不作具体限定。当第二屏蔽结构采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成；当第二屏蔽结构采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积形成；当第二屏蔽结构采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
在一种可能的实现方式中，第二屏蔽结构位于第一屏蔽结构的外侧，第二腔体的至少一部分位于封装基板与所述电路板之间。
此时第二屏蔽结构可以与第一屏蔽结构的外侧进行连接，易于加工成型，当第二屏蔽结构覆盖第一屏蔽结构时，使得第一屏蔽结构与第二屏蔽结构连接的位置处包括内外两层屏蔽结构，提升了电磁屏蔽性能。第二腔体位于封装基板与所述电路板之间部分，用于容纳第一连接部，以实现对第一连接部的电磁屏蔽。
第二方面，本申请还提供了一种通信设备，该通信设备包括以上实现方式中提供的芯片系统。通信设备内包括的芯片封装体对电磁屏蔽的要求高，因此将芯片封装体安装在PCB上时，需要更加全面完备地对芯片封装体进行电磁屏蔽。
本申请提供的通信设备包括的电磁屏蔽体，能够实现对第一连接部中的电连接结构件的电磁屏蔽，减少了第一连接部的电连接结构件的电磁泄漏，提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响，因此还提升了通信设备的性能。
在一种可能的实现方式中，通信设备为射频收发信机。射频收发信机通过光纤与基站的基 带处理单元(Base band Unit，BBU)连接。BBU用于对射频收发信机传输的数据进行处理，以及向射频收发信机传输待发射的数据。本申请的技术方案提升了对芯片封装体的电磁屏蔽能力，进而也提升了射频收发信机工作性能。
在一种可能的实现方式中，至少一个芯片包括中频芯片。中频芯片应用于射频收发信机的中频电路。
附图说明
图1为传统的电磁屏蔽体的示意图；
图2A为本申请实施例提供的一种芯片系统的剖面示意图；
图2B为本申请实施例提供的图2A对应的侧示图；
图3为本申请实施例提供的另一种芯片系统的剖面示意图；
图4A为本申请实施例提供的图3中A区域的放大图；
图4B为本申请实施例提供的图3对应的俯视图；
图4C为本申请实施例提供的另一种芯片系统的剖面示意图；
图5为本申请实施例提供的仿真测试的波形图；
图6为本申请实施例提供的又一种芯片系统的剖面示意图；
图7为本申请实施例提供的再一种芯片系统的剖面示意图；
图8为本申请实施例提供的另一种芯片系统的剖面示意图；
图9为本申请实施例提供的又一种芯片系统的剖面示意图；
图10为本申请实施例提供的再一种芯片系统的剖面示意图；
图11为本申请实施例提供的另一种芯片系统的剖面示意图；
图12为本申请实施例提供的又一种芯片系统的剖面示意图；
图13A为本申请实施例提供的图12对应的剖面示意图一；
图13B为本申请实施例提供的图12对应的剖面示意图二；
图14为本申请实施例提供的图12对应的侧视图一；
图15A为本申请实施例提供的图12对应的剖面示意图三；
图15B为本申请实施例提供的图12对应的剖面示意图四；
图16A为本申请实施例提供的图15A和15B对应的侧视图一；
图16B为本申请实施例提供的图15A和15B对应的侧视图二；
图17为本申请实施例提供的一种射频收发系统的示意图。
具体实施方式
为了使本领域技术人员更好地理解本申请实施例提供的技术方案，下面先介绍本申请提供的技术方案的应用场景。
随着芯片的工作频率的不断提升，对降低电磁干扰的需求增强，因此为了提升芯片封装体的性能，需要更加全面地对芯片封装体进行电磁屏蔽，以减少电磁辐射泄漏。
芯片封装体包括芯片和封装基板。芯片包括但不限于中频(Intermediate Frequency，IF)芯片、射频(Radio Frequency，RF)芯片、中央处理器(Central Processing Unit，CPU)、 图形处理器(Graphics Processing Unit，GPU)、现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)以及神经网络处理器(Neural network Processing Unit，NPU)等
以芯片封装体与PCB之间通过焊球连接为例，继续参见图1，各焊球30之间存在间隙，使得焊球30成为电磁辐射的泄漏源，影响了芯片11的性能，并且还会对电子设备自身包含的射频电路，以及需要使用时钟信号的处理器、存储器等造成电磁干扰。
为了解决以上技术问题，本申请提供了一种芯片系统及通信设备。芯片系统包括芯片封装体和电磁屏蔽体，该芯片封装体通过第一连接部与电路板电连接，芯片封装体包括封装基板和至少一个芯片。封装基板和至少一个芯片之间电连接。电磁屏蔽体包括导电的第一屏蔽结构和导电的第二屏蔽结构。第一屏蔽结构与封装基板连接，第一屏蔽结构的第一腔体用于容纳至少一个芯片，第二屏蔽结构的第一端连接电路板或电路板上的焊盘，第二屏蔽结构的第二端连接第一屏蔽结构以形成第二腔体，或者，第二屏蔽结构的第一端连接电路板上的焊盘或连接电路板，第二屏蔽结构覆盖所述第一屏蔽结构以形成第二腔体，第一连接部位于第二腔体内。利用本申请提供的电磁屏蔽体，能够实现对第一连接部的电磁屏蔽，减少了第一连接部的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
本申请说明中的“第一”、“第二”等用词仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
此外，本申请中，“上”、“下”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连通”应做广义理解，例如，“连通”可以是固定连通，也可以是可拆卸连通，或成一体；可以是直接连通，也可以通过中间媒介间接连通。
芯片封装体中可以包括一个芯片或多个芯片，为了方便说明，以下实施例中均以芯片封装体包括一个芯片为例进行说明。
参见图2A，该图为本申请实施例提供的一种芯片系统的剖面示意图。
图示的芯片封装体包括芯片11和封装基板14。
封装基板14可为包括多层导电层的电路板，封装基板14的上表面和下表面均设置有外露的焊盘结构。
芯片11和封装基板14电连接。在一种可能的实现方式中，芯片11表面包括金属凸点，芯片11和封装基板14之间采用焊接的方式，焊料可以采用含锡合金焊料，在基板表面印刷锡膏，通过回流焊的方式实现芯片和基板之间的连接。
将芯片封装体焊接在PCB20上时，利用本申请提供的电磁屏蔽体，实现对芯片封装体的电磁屏蔽，该电磁屏蔽体包括：第一屏蔽结构13和第二屏蔽结构16。
第一屏蔽结构13和第二屏蔽结构16均为导电的结构。
其中，第一屏蔽结构13和封装基板14连接，第一屏蔽结构13包括第一内腔，芯片11位于第一屏蔽结构13的第一内腔中。
第二屏蔽结构16位于第一屏蔽结构13的外侧，第二腔体的至少一部分位于封装基板与电路板之间。此时第二屏蔽结构可以与第一屏蔽结构的外侧进行连接，易于加工成型，当第二屏蔽结构覆盖第一屏蔽结构时，使得第一屏蔽结构与第二屏蔽结构连接的位置处包括内外两层屏蔽结构，提升了电磁屏蔽性能。第二腔体位于封装基板与所述电路板之间部分，用于容纳第一连接部，以实现对第一连接部的电磁屏蔽。
芯片封装体通过第一连接部与PCB20电连接。
第一连接部包括多个电连接结构件，电连接结构件可以包括金属焊球、烧结、金属结构件或者插接端子等，还可以为其它的电连接结构件，以实现第一连接部与PCB20之间的电连接，本申请实施例对此不作具体限定，以下说明中以第一连接部的电连接结构件为金属焊球30为例进行说明。
参见图2B，该图为本申请实施例提供的图2A对应的侧示图。
图2B为外部观测的示意图，一并参见图2A和2B，第二屏蔽结构16的第一端连接电路板20，或者连接电路板20上的焊盘201，第二屏蔽结构16的第二端连接第一屏蔽结构13以形成第二腔体，第二屏蔽结构16完全覆盖封装基板的侧面，并且使第一连接部位于自身围绕形成的第二腔体内，此时图2B所示的外部观测的示意图中，第一连接部被第二屏蔽结构16完全遮挡。
此时第一屏蔽结构13和第二屏蔽结构16共同形成的电磁屏蔽体，笼罩了芯片封装体和第一连接部，减少了第一连接部的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。
在另一些可能的实现方式中，第二屏蔽结构16部分覆盖封装基板的侧面，进而可以节省材料。
下面结合具体的实现方式进行说明。
参见图3，该图为本申请实施例提供的另一种芯片系统的剖面示意图。
本申请实施例中的封装基板14与PCB20之间可以采用球栅阵列(Ball Grid Array，BGA)封装或栅格阵列(Land Grid Array，LGA)封装的方式进行连接。
其中，当采用BGA封装的方式时，封装基板14与PCB20之间的多个焊球形成阵列，分布在封装基板与PCB20之间，以使使PCB20与芯片封装体进行通信。
当采用LGA封装的方式时，芯片封装体与PCB20连接时所需的触点位于PCB20上，封装基板下侧覆盖网格状的连接端。采用点接触技术使PCB20与芯片封装体进行通信，由PCB20提供针脚，可以替代BGA封装中的焊球。
为了方便说明，下面以采用BGA封装为例，则图3中第一连接部的多个电连接结 构件具体为多个金属焊球30，本申请实施例对金属焊球的数量与排列方式不作具体限定。可以理解的是，在另一些实施例中，当替换为LGA封装方式时，第一连接部则包括针脚与触点，本申请实施例不再赘述。
芯片11的第一表面通过第一材料12与第一屏蔽结构13固定。
在一种可能的实现方式中，第一材料12为热界面(Thermal Interface Material，TIM)材料，热界面材料多为柔性材料，例如可以为凝胶、硅脂类材料，填充在芯片11第一表面与第一屏蔽结构13之间时，一方面可以辅助散热，使芯片11工作时产生的热量快速传导至第一屏蔽结构，另一方面，提供了对第一屏蔽结构13的支撑，进而提升了第一屏蔽结构13的稳定性。
芯片11的第二表面与封装基板14的第一表面电连接。
具体的，芯片11表面包含金属凸点，封装基板14上表面包括焊盘，在封装基板14表面印刷锡膏，通过回流焊的方式实现芯片11和封装基板14的焊接。
在一些实施例中，芯片11和封装基板14之间可以注入底部填充(underfill)材料，以提升连接的稳定性，底部填充材料为绝缘材料，本申请实施例对底部填充材料的具体类型不作限定，例如可以为环氧树脂。
第一屏蔽结构13通过第二连接部15与封装基板14的第一表面固定。
由于第一屏蔽结构13通过第二连接部15与封装基板14的第一表面固定，并且第一屏蔽结构13还通过第一材料12与芯片11的第一表面固定，提升了第一屏蔽结构13的稳定性，当封装基板通过第一连接部与电路板20固定后，第一屏蔽结构13相对于电路板的位置也即固定。
此时的第一屏蔽结构13为金属结构件，该金属结构件可以为冲压成型或者铸造成型，本申请实施例对此不作具体限定。金属结构件具备凹槽结构，凹槽内用于容纳芯片封装体的对应部分，进而实现对芯片封装体的电磁屏蔽。
在一种可能的实现方式中，第二连接部15为金属焊料，第一屏蔽结构13通过第二连接部15与封装基板14的第一表面焊接，此时第一屏蔽结构13和封装基板14连接牢固，并且电磁屏蔽体具有良好的电磁屏蔽性能。
在另一种可能的实现方式中，第二连接部15为导电胶，第一屏蔽结构13通过第二连接部15与封装基板14的第一表面固定，采用该方式能够使电磁屏蔽体具有良好的电磁屏蔽性能。
在又一种可能的实现方式中，第二连接部为绝缘熔胶，第一屏蔽结构13通过第二连接部15与封装基板14的第一表面固定，该方式降低了工艺制造难度，并且能够使第一屏蔽结构13和封装基板的连接牢固。
封装基板14的下表面通过金属焊球30与PCB20实现电连接，具体可以通过回流焊工艺实现基板电路14和PCB的电连接。
其中，PCB20包含多层的电路层，图示的PCB仅为一种示意，并不构成对于本申请技术方案的限定。
PCB上面有焊盘201，焊盘201为金属焊盘，焊盘201和PCB的接地电路层连接， 焊盘201和接地电路层连接方式可为电镀通孔结构，或者开槽电镀结构，本申请实施例不作具体限定。
第一连接部中除了包括电连接结构件，也即图中的金属焊球30，还包括绝缘材料17。
芯片封装体和电路板20的连接区域填充绝缘材料17，也即封装基板14的下表面和PCB20的连接区域填充绝缘材料17。
绝缘材料17可以采用底部填充(underfill)材料，例如环氧树脂类材料等，绝缘材料17可通过毛细原理填充多个金属焊球之间的空隙。
绝缘材料17可以尽量填充满多个金属焊球之间的空隙，或者只在芯片封装体和电路板20的连接区域边缘填充绝缘材料17。
图示的第二屏蔽结构16覆盖绝缘材料17的侧壁，第二屏蔽结构16的第一端连接焊盘201，焊盘201接地，进而提升了电磁屏蔽体对芯片11以及第一连接部的电磁屏蔽能力，第二屏蔽结构16的第二端连接第一屏蔽结构13。
此时第二屏蔽结构16将各金属焊球30包围在内侧，进而实现了对金属焊球30的电磁屏蔽。
绝缘材料17还能够起到支撑作用，第二屏蔽结构可以紧贴绝缘材料的侧壁，更加稳定可靠。
第二屏蔽结构16为导电薄膜、金属材料或导电胶材料中的任意一种，本申请实施例不作具体限定。
当第二屏蔽结构16为导电薄膜时，导电薄膜可以通过喷涂的方式形成。
当第二屏蔽结构16为金属材料时，金属材料可以通过金属溅射沉积生成，或者电镀工艺沉积形成，金属材料可以为铜、银或者其它金属材料，本申请实施例不作具体限定。
当第二屏蔽结构16为导电胶材料时，导电胶材料可以采用涂覆的方式形成。常用的导电胶材料可以为包含金属银的导电胶材料，也即导电银胶。
参见图4A，该图为本申请实施例提供的图3中A区域的放大图。
在填充绝缘材料17时，绝缘材料17形成的侧壁沿由上至下的方向向外侧延伸。
此时填充绝缘材料17的第一连接部包括两个连接面，靠近电路板的一个连接面为第一连接面，靠近芯片封装体的另一个连接面为第二连接面。
第一连接面的宽度大于第二连接面的宽度。也即绝缘材料17的上侧窄，下侧宽。
当第二屏蔽结构16的材质采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式，依托于绝缘材料17的侧壁形成，以确保第二屏蔽结构16将各金属焊球30包围在内侧。
当第二屏蔽结构采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积形成，也可以依托于绝缘材料17的侧壁，以确保第二屏蔽结构16将各金属焊球30包围在内侧。
当第二屏蔽结构采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式， 依托于绝缘材料17的侧壁形成，以确保第二屏蔽结构16将各金属焊球30包围在内侧。
综上，绝缘材料17的侧壁可以为第二屏蔽结构16提供支撑。此外，绝缘材料17也可以加固PCB与封装基板之间的连接。
本申请以下附图与说明中的绝缘材料17均为图4A中的填充方式，不再一一赘述。
参见图4B，该图为本申请实施例提供的图3对应的俯视图。
图4B所示的俯视图为俯视角度的剖面图，第一屏蔽结构13、第二屏蔽结构16和PCB20共同形成腔体，第二屏蔽结构16完全覆盖封装基板14的侧面，并且使第一连接部位于自身围绕形成的腔体内。
图4B所示的焊盘围绕芯片封装体，用于和第二屏蔽结构16的第一端进行全面的固定，以提升第二屏蔽结构16连接的稳定性，并且提升电磁屏蔽体的电磁屏蔽能力。
在另一些实施例中，焊盘也可以不围绕芯片封装体，以节省材料。
此时第一屏蔽结构13和第二屏蔽结构16共同形成的电磁屏蔽体，笼罩了芯片封装体和第一连接部，减少了第一连接部的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。
参见图4C，该图为本申请实施例提供的另一种芯片封装体的电磁屏蔽体的剖面示意图。
该实现方式下，电磁屏蔽体的第二屏蔽结构16为导电薄膜，导电薄膜还可以完全覆盖第二屏蔽结构13，此时第二屏蔽结构16可以通过粘接材料(Cohensive)与第一屏蔽结构13连接，也即在第二屏蔽结构16与第一屏蔽结构13的接触面添加粘接材料，以提升两者连接的稳定性。
下面结合具体的测试数据说明图3所示电磁屏蔽体的技术效果。
参见图5，该图为本申请实施例提供的仿真测试的波形图。
图示仿真测试的波形图示出了分别采用图3和图1的方案时，在2GHz至10GHz的频段内的屏蔽效能。
屏蔽效能表现了屏蔽体对电磁波的衰减程度。由于屏蔽体通常能将电磁波的强度衰减到原来的百分之一至万分之一，因此通常用分贝(dB)来表述。
图中5仿真测试的数据对应以下表1所示。
表1：屏蔽效能的比较
频率 图1方案的屏蔽效能 图3方案屏蔽效能
2GHz 53.07dB 60.83dB
4GHz 52.96dB 60.79dB
6GHz 52.93dB 60.75dB
8GHz 52.43dB 60.06dB
10GHz 51.62dB 59.02dB
可以发现，采用本申请实施例的电磁屏蔽体，相较于图1所示的现有技术而言，蔽效能可以增加约7dB至8dB。也即能够降低了焊球的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能。
下面说明电磁屏蔽体的其它实现方式。
参见图6，该图为本申请实施例提供的又一种芯片系统的剖面示意图。
芯片11的第一表面通过第一材料12与第一屏蔽结构13连接。芯片11的第二表面与封装基板14的第一表面电连接。第一屏蔽结构13通过第二连接部15与封装基板14的侧壁固定。
在一种可能的实现方式中，第一材料12可以采用热界面材料，热界面材料填充在芯片11的第一表面与第一屏蔽结构之间，一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构，另一方面，提供了对第一屏蔽结构的支撑，提升了第一屏蔽结构的稳定性。此外，第一屏蔽结构与封装基板的侧壁固定，进而将芯片封装体的侧面包围，提升了电磁屏蔽的效果。
在一种可能的实现方式中，第二连接部15为金属焊料，第一屏蔽结构13通过第二连接部15与封装基板14的侧壁焊接，此时第一屏蔽结构13和封装基板14的连接牢固，并且电磁屏蔽体具有良好的电磁屏蔽性能。
在另一种可能的实现方式中，第二连接部15为导电胶，第一屏蔽结构13通过第二连接部15与封装基板14的侧壁固定，采用该方式能够使电磁屏蔽体具有良好的电磁屏蔽性能。
在又一种可能的实现方式中，第二连接部15为绝缘熔胶，第一屏蔽结构13通过第二连接部15与封装基板14的侧壁固定，该方式降低了工艺制造难度，并且能够使第一屏蔽结构和封装基板的连接牢固。
第二屏蔽结构16的第一端连接焊盘201，焊盘201接地提升了电磁屏蔽体对芯片以及第一连接部的电磁屏蔽能力，第二屏蔽结构16的第二端连接第一屏蔽结构13。
参见图7，该图为本申请实施例提供的再一种芯片系统的剖面示意图。
图示实现方式与图6的区别在于，第一连接部还包括了绝缘材料17。
芯片封装体、电路板20和多个金属焊球30之间填充绝缘材料17，也即封装基板14的下表面和PCB20之间的空隙内填充绝缘材料17。
绝缘材料17可以采用底部填充(underfill)材料，例如环氧树脂类材料等，绝缘材料17可通过毛细原理填充多个金属焊球之间的空隙。
绝缘材料17可以尽量填充满芯片封装体、电路板20和多个金属焊球之间的空隙，或者只在芯片封装体和电路板20的连接区域边缘填充绝缘材料17。
第二屏蔽结构16覆盖绝缘材料17的侧壁，第二屏蔽结构16的第一端连接焊盘201，焊盘201接地，进而提升了电磁屏蔽体对芯片以及第一连接部的电磁屏蔽能力，第二屏蔽结构16的第二端连接第一屏蔽结构13。
综上所述，利用本申请提供的电磁屏蔽体，能够实现对第一连接部的电磁屏蔽，减少了第一连接部的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。
下面说明其它的电磁屏蔽体的实现方式。
参见图8，该图为申请实施例提供的另一种芯片系统的剖面示意图。
图8所示的芯片封装体还包括塑封料18，芯片11埋设于塑封料18中。
芯片11与封装基板14的第一表面电连接，第一屏蔽结构覆盖塑封料18的外表面以及封装基板14的侧壁。
此时，第一屏蔽结构13可以为导电薄膜、金属材料或导电胶材料。
具体的，当第一屏蔽结构13采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成。
当第一屏蔽结构13采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积生成，金属材料也可以为冲压成型或者铸造成型的金属结构件。
当第一屏蔽结构13采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
塑封料18一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构13；另一方面，塑封料18提供了对第一屏蔽结构13的支撑，提升了第一屏蔽结构的稳定性，也使得第一屏蔽结构13能够依托于塑封料18成型。
第一屏蔽结构13覆盖塑封料18的外表面以及封装基板14的侧壁，进而将芯片封装体包围，提升了电磁屏蔽的效果。
芯片11的第二表面与封装基板14的第一表面电连接。
在一种可能的实现方式中，芯片11表面包含金属凸点，封装基板14上表面包括焊盘，在封装基板14表面印刷锡膏，通过回流焊的方式实现芯片11和封装基板14的焊接。在一些实施例中，芯片11和封装基板14之间可以注入底部填充材料，以提升连接的稳定性，底部填充材料为绝缘材料，本申请实施例对底部填充材料的具体类型不作限定，例如可以为环氧树脂。
封装基板14的下表面通过金属焊球30与PCB20实现电连接，具体可以通过回流焊工艺实现基板电路14和PCB的电连接。
PCB上面有焊盘201，焊盘201为金属焊盘，焊盘201和PCB的接地电路层连接，焊盘201和PCB的接地电路层之间的连接方式可为电镀通孔结构，或者开槽电镀结构，本申请实施例不作具体限定。
第二屏蔽结构16将各金属焊球30包围在内侧，进而实现了对金属焊球30的电磁屏蔽。第二屏蔽结构和第一屏蔽结构的实现方式可以相同，也可以不同，本申请不作具体限定。
当第二屏蔽结构采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成；当第二屏蔽结构采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积形成；当第二屏蔽结构采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
参见图9，该图为本申请实施例提供的又一种芯片系统的剖面示意图。
图示实现方式与图8的区别在于，第一连接部还包括绝缘材料17。
芯片封装体的封装基板、电路板20和多个金属焊球之间的区域填充绝缘材料17，也即封装基板14的下表面和PCB20之间的空隙填充绝缘材料17。
绝缘材料17可以采用底部填充材料，例如环氧树脂类材料等，绝缘材料17可通过毛细原理填充多个金属焊球之间的空隙。
绝缘材料17可以尽量填充满芯片封装体的封装基板、电路板20和多个金属焊球之间的区域，或者只在芯片封装体和电路板20的连接区域边缘填充绝缘材料17。
第二屏蔽结构16覆盖绝缘材料17的侧壁，第二屏蔽结构16的第一端连接焊盘201，焊盘201接地提升了电磁屏蔽体对芯片以及第一连接部的电磁屏蔽能力，第二屏蔽结构16的第二端连接第一屏蔽结构13。
综上所述，利用本申请提供的电磁屏蔽体，能够实现对第一连接部的电磁屏蔽，减少了第一连接部的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。
下面说明再一种芯片封装体的电磁屏蔽体的示意图。
图10为本申请实施例提供的再一种芯片系统的剖面示意图；
图10所示的电磁屏蔽体与图8的区别在于：第一屏蔽结构13覆盖塑封料18的外表面并延伸至封装基板14的第一表面。
塑封料18一方面可以辅助散热，使芯片11工作时产生的热量快速传导至第一屏蔽结构13，另一方面，提供了对第一屏蔽结构13的支撑，提升了第一屏蔽结构固定的稳定性。此外，第一屏蔽结构覆盖塑封料的外表面以及封装基板的侧壁，相较于图8的实现方式，减少了塑封料18的使用量，以及减少了第一屏蔽结构13的材料消耗。
当第一屏蔽结构13采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成；当第一屏蔽结构13采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积生成；当第一屏蔽结构13采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
第二屏蔽结构16的第一端连接PCB20上的焊盘201，焊盘201接地以提升电磁屏蔽体对芯片以及金属焊球的电磁屏蔽能力，第二屏蔽结构16的第二端连接第一屏蔽结构13，此时第二屏蔽结构16还覆盖封装基板14的侧面。
第二屏蔽结构16和第一屏蔽结构13的实现方式可以相同，也可以不同，本申请实施例对此不作具体限定。当第二屏蔽结构16采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成；当第二屏蔽结构16采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积形成；当第二屏蔽结构16采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
参见图11，该图为本申请实施例提供的另一种芯片系统的剖面示意图。
图示实现方式与图10的区别在于，第一连接部还包括了绝缘材料17。
芯片封装体的封装基板、电路板20和多个金属焊球30之间的区域填充绝缘材料17，也即封装基板14的下表面和PCB20的之间的空隙区域填充绝缘材料17。
绝缘材料17可以采用底部填充材料，例如环氧树脂类材料等，绝缘材料17可通过毛细原理填充多个金属焊球之间的空隙。
绝缘材料17可以尽量填充满芯片封装体的封装基板、电路板20和多个金属焊球30之间的区域，或者只在芯片封装体和电路板20的连接区域边缘填充绝缘材料17。
第二屏蔽结构16覆盖绝缘材料17的侧壁，第二屏蔽结构16的第一端连接焊盘201，焊盘201接地，进而提升了电磁屏蔽体对芯片以及第一连接部的电磁屏蔽能力，第二屏蔽结构16的第二端连接第一屏蔽结构13。
综上所述，利用本申请提供的电磁屏蔽体，能够实现对第一连接部的电磁屏蔽，减少了第一连接部的电磁泄漏，进而提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响。
下面说明另一种芯片系统的实现方式。
参见图12，该图为本申请实施例提供的又一种芯片系统的剖面示意图；
图12为x、y轴所在平面的俯视图，为了能够显示出PCB20上的焊盘201和各引脚的位置，芯片封装体10用实线框来表示，图12中未示出第一屏蔽结构和第二屏蔽结构。
芯片封装体10包括芯片与封装基板，封装基板位于焊盘201上，第二屏蔽结构的第一端与焊盘201电连接，第二屏蔽结构的第二端与第一屏蔽结构电连接。
PCB20上的引脚包括第一引脚202和接地引脚203，本申请对第一引脚202和接地引脚203的具体分布和数量不作具体限定。其中，第一引脚202为信号传输引脚，接地引脚203用于接地。
第一引脚202在x、y轴所在平面的投影，位于芯片封装体10轮廓所覆盖的范围内；接地引脚203在x、y轴所在平面的投影，部分位于芯片封装体10轮廓所覆盖的范围内，或者全部位于芯片封装体10轮廓所覆盖的范围外，本申请中以部分位于芯片封装体10轮廓所覆盖的范围内为例进行说明。
焊盘201的两侧在x、y轴所在平面的投影，位于芯片封装体10轮廓所覆盖的范围外，焊盘201两侧延伸出的区域，也即图示的B区域和B1区域，用于通过爬焊的工艺，使焊盘201与第一屏蔽结构实现电连接。本申请实施例对B区域B1区域的具体面积不作限定。
图中的C区域和C1区域，为芯片封装体10和PCB20进行电信号连接的区域。在一种可能的实现方式中，当采用LGA封装的方式时，芯片封装体10与PCB20连接时所需的触点位于PCB20上，封装基板下侧覆盖网格状的连接端。采用点接触技术使PCB20与芯片封装体进行通信，由PCB20提供针脚，可以替代BGA封装中的焊球。
该区域内可以填充绝缘材料，绝缘材料可以采用底部填充材料，例如环氧树脂类材料等，绝缘材料可通过毛细原理填充空隙。
在另一些实施例中，该区域内也可以不填充绝缘材料。
参见图13A，该图为本申请实施例提供的图12对应的剖面示意图一。
图13A为x、z轴所在平面的剖面图，
焊盘201两侧延伸出的区域，也即图示的B区域和B1区域，用于通过爬焊的工艺，形成第二屏蔽结构16，使焊盘201与第一屏蔽结构13实现电连接。
也即第二屏蔽结构16的一端连接焊盘201，另一端连接第一屏蔽结构13。
芯片11的第一表面通过第一材料12与第一屏蔽结构13固定。
在一种可能的实现方式中，第一材料12为TIM材料，TIM材料多为柔性材料，例如可以为凝胶、硅脂类材料，填充在芯片11第一表面与第一屏蔽结构13之间时，一方面可以辅助散热，使芯片11工作时产生的热量快速传导至第一屏蔽结构，另一方面，提供了对第一屏蔽结构13的支撑，进而提升了第一屏蔽结构13的稳定性。
此时的第一屏蔽结构13为金属结构件，该金属结构件可以为冲压成型或者铸造成型，本申请实施例对此不作具体限定。金属结构件具备凹槽结构，凹槽内用于容纳芯片封装体的对应部分，进而实现对芯片封装体的电磁屏蔽。
由于焊盘201通过第二屏蔽结构16与第一屏蔽结构13实现电连接，因此当焊盘201接地时，第二屏蔽结构16与第一屏蔽结构13也接地，提升了电磁屏蔽的性能。
进一步的，PCB20上的各接地引脚203由于部分位于芯片封装体10轮廓所覆盖的范围外，因此也可以通过爬焊的工艺实现与第一屏蔽结构13的电连接，进而避免在PCB20通过布线接地，简化了接地线路。
参见图13B，该图为本申请实施例提供的图12对应的剖面示意图二。
图13B为x、z轴所在平面的剖面图，该实现方式与图13A所示的实现方式的区别在于：芯片封装体还包括塑封料18，芯片11埋设于塑封料18中。
此时，第一屏蔽结构13可以为导电薄膜、金属材料或导电胶材料。
具体的，当第一屏蔽结构13采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成。
当第一屏蔽结构13采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积生成，金属材料也可以为冲压成型或者铸造成型的金属结构件。
当第一屏蔽结构13采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
塑封料18一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构13；另一方面，塑封料18提供了对第一屏蔽结构13的支撑，提升了第一屏蔽结构的稳定性，也使得第一屏蔽结构13能够依托于塑封料18成型。
第一屏蔽结构13覆盖塑封料18的外表面以及封装基板14的侧壁，进而将芯片封装体包围，提升了电磁屏蔽的效果。
参见图14，该图为本申请实施例提供的图12对应的侧视图一。
图14为y、z轴所在平面的侧视图，依据图14，利用爬焊的工艺，形成第二屏蔽结构16，使焊盘201与第一屏蔽结构13实现电连接，第二屏蔽结构16仅覆盖部分第二屏蔽结构16以节省材料。
接地引脚203延伸至芯片封装体10范围外的部分，也可以通过爬焊的工艺形成第 二屏蔽结构16，以实现与第一屏蔽结构13的电连接，进而避免在PCB20通过布线接地，简化了接地线路。此外，接地引脚203、焊盘201、第一屏蔽结构13和第二屏蔽结构16将第一引脚202包围，还提升了芯片系统的电磁屏蔽性能。
参见图15A，该图为本申请实施例提供的图12对应的剖面示意图三。
图15A为x、z轴所在平面的剖面图，图15A所示芯片系统与图13A的区别在于：15A所示芯片系统的第二屏蔽结构16为导电薄膜，导电薄膜覆盖第二屏蔽结构13外部。
参见图15B，该图为本申请实施例提供的图12对应的剖面示意图四。
图15B为x、z轴所在平面的剖面图，图15B所示芯片系统与图15A的区别在于：芯片封装体还包括塑封料18，芯片11埋设于塑封料18中。
此时，第一屏蔽结构13可以为导电薄膜、金属材料或导电胶材料。
具体的，当第一屏蔽结构13采用导电薄膜的实现方式时，导电薄膜可以通过喷涂的方式形成。
当第一屏蔽结构13采用金属材料的实现方式时，金属材料可以通过金属溅射沉积生成或电镀工艺沉积生成，金属材料也可以为冲压成型或者铸造成型的金属结构件。
当第一屏蔽结构13采用导电胶材料的实现方式时，导电胶材料可以采用涂覆的方式形成。
塑封料18一方面可以辅助散热，使芯片工作时产生的热量快速传导至第一屏蔽结构13；另一方面，塑封料18提供了对第一屏蔽结构13的支撑，提升了第一屏蔽结构的稳定性，也使得第一屏蔽结构13能够依托于塑封料18成型。
第一屏蔽结构13覆盖塑封料18的外表面以及封装基板14的侧壁，进而将芯片封装体包围，提升了电磁屏蔽的效果。
参见图16A，该图为本申请实施例提供的图15A和15B对应的侧视图一。
图16A为y、z轴所在平面的侧视图，此时第二屏蔽结构包括两部分。
第二屏蔽结构的第一部分为导电薄膜，导电薄膜覆盖第二屏蔽结构13外部，导电薄膜利用焊盘201两侧延伸出的区域实现固定。
接地引脚203延伸至芯片封装体10范围外的部分，利用爬焊的工艺形成第二屏蔽结构16的第二部分，以实现与第一屏蔽结构13的电连接，进而避免在PCB20通过布线接地，简化了接地线路。此外，接地引脚203、焊盘201、第一屏蔽结构13和第二屏蔽结构16将第一引脚202包围，提升了芯片系统的电磁屏蔽性能。
参见图16B，该图为本申请实施例提供的图15A和15B对应的侧视图二。
图16B为y、z轴所在平面的侧视图，图16B所示芯片系统与图16A的区别在于：第二屏蔽结构16为导电薄膜，接地引脚203延伸至芯片封装体10范围外的部分，以及焊盘201两侧延伸出芯片封装体10范围外的部分，共同用于和导电薄膜进行电连接，导电薄膜可以完全覆盖第一屏蔽结构13，或者完全覆盖第一屏蔽结构13的侧壁。
此时焊盘201、第一屏蔽结构13和第二屏蔽结构16将第一引脚202包围，提升了芯片系统的电磁屏蔽性能。
可以理解的是，以上说明中以芯片系统中第一引脚202和接地引脚203位于芯片封装体10的上、下两侧为例进行说明，实际应用中，随着第一引脚202和接地引脚203的数量的变化，其布局位置可以相应调整，可以仅布置在一侧，或者布置在三侧，或者布置在四侧，在此不再赘述。
基于上述实施例提供的芯片系统，本申请实施例还提供了一种应用该芯片系统的通信设备，下面具体说明。
通信设备中包括PCB，PCB上的中频(Intermediate Frequency，IF)芯片、射频(Radio Frequency，RF)芯片对应的芯片封装体可以采用以上实施例提供的芯片系统。
下面以该通信设备为射频收发信机为例进行说明。
参见图17，该图为本申请实施例提供的一种射频收发系统的示意图。
应用于无线通信系统的射频收发信机01支持多入多出(Multiple-Input Multiple-Output，MIMO)功能，能够使用多个发射天线同时将信号发射至不同的用户设备(User Equipment，UE)，以及使用多个接收天线同时接受多个UE02发送的信号。
本申请实施例提供的射频收发系统包括：射频收发信机01和基带处理单元(Base band Unit，BBU)03。
实际应用中，射频收发系统一般包括多个射频收发信机01，以及多个BBU03。一个BBU03支持同时接入多个射频收发信机01，本申请实施例对一个BBU03同时接入的射频收发信机01的具体数量不做限定。
当射频收发系统包括多个BBU03时，每个BBU03上接入的射频收发信机01的数量可以相同，也可以不同，本申请实施例不做具体限定。
射频收发信机01通过光纤和BBU03进行连接，一方面，射频收发信机01通过光纤获取BBU发送的光信号，通过光模块将光信号转换为高速电信号，经由内部的基带电路、中频电路和射频功率放大电路进行处理后，通过多个发射天线向多个用户设备进行发送；另一方面，射频收发信机01能够通过多个接收天线接收多个用户设备发送的射频信号，经由内部的射频功率放大电路、中频电路和基带电路进行处理后转换为高速电信号，再通过光模块将高速电信号转换为光信号后通过光纤传输至BBU03。
中频电路的中频芯片可以应用本申请实施例提供的芯片系统，也即采用以上的电磁屏蔽体将中频芯片的芯片封装体布置于中频电路所在的PCB上。
综上所述，本申请实施例提供的通信设备包括的芯片系统，能够实现对第一连接部的电磁屏蔽，减少了第一连接部的电磁泄漏，提升了芯片封装体的电磁屏蔽能力，保障了芯片性能，也能降低其它电路元器件受到的电磁泄漏的影响，因此提升了通信设备的性能。
以上仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (22)

  1. 一种芯片系统，其特征在于，所述芯片系统包括芯片封装体和电磁屏蔽体，所述芯片封装体通过第一连接部与电路板电连接，所述芯片封装体包括封装基板和至少一个芯片，所述封装基板和所述至少一个芯片电连接，所述电磁屏蔽体包括：第一屏蔽结构和第二屏蔽结构，所述第一屏蔽结构与第二屏蔽结构均导电；
    所述第一屏蔽结构与所述封装基板连接；
    所述第一屏蔽结构包括第一腔体，所述第一腔体用于容纳所述至少一个芯片；
    所述第二屏蔽结构的第一端连接所述电路板上的焊盘或连接所述电路板，所述第二屏蔽结构的第二端连接所述第一屏蔽结构以形成第二腔体；或者，所述第二屏蔽结构的第一端连接所述电路板上的焊盘或连接所述电路板，所述第二屏蔽结构覆盖所述第一屏蔽结构以形成第二腔体；
    所述第一连接部位于所述第二腔体内。
  2. 根据权利要求1所述的芯片系统，其特征在于，所述第一连接部包括绝缘材料以及多个电连接结构件；
    所述多个电连接结构件，用于连接所述芯片封装体以及所述电路板；
    所述绝缘材料填充于所述封装基板、所述电路板以及所述多个电连接结构件之间的区域。
  3. 根据权利要求2所述的芯片系统，其特征在于，所述第一连接部包括两个连接面，靠近所述电路板的一个连接面为第一连接面，靠近所述芯片封装体的另一连接面为第二连接面，所述第一连接面的宽度大于所述第二连接面的宽度。
  4. 根据权利要求2或3所述的芯片系统，其特征在于，所述第二屏蔽结构覆盖全部所述绝缘材料的侧壁，或覆盖部分所述绝缘材料的侧壁。
  5. 根据权利要求1至4中任一项所述的芯片系统，其特征在于，所述焊盘接地。
  6. 根据权利要求5所述的芯片系统，其特征在于，所述封装基板位于所述焊盘上，所述第二屏蔽结构的第一端与所述焊盘电连接。
  7. 根据权利要求6所述的芯片系统，其特征在于，所述芯片封装体采用栅格阵列LGA封装技术和所述电路板电连接，所述芯片封装体的接地引脚与所述第二屏蔽结构电连接。
  8. 根据权利要求1-7中任一项所述的芯片系统，其特征在于，所述至少一个芯片中的每个芯片的第一表面，通过第一材料与所述第一屏蔽结构连接；
    所述至少一个芯片中的每个芯片的第二表面，与所述封装基板的第一表面电连接；
    所述第一屏蔽结构通过第二连接部与所述封装基板的第一表面连接。
  9. 根据权利要求8所述的芯片系统，其特征在于，所述第二连接部为金属焊料；或，所述第二连接部为导电胶；或，所述第二连接部为绝缘熔胶。
  10. 根据权利要求1-7中任一项所述的芯片系统，其特征在于，所述至少一个芯片中的每个芯片的第一表面，通过第一材料与所述第一屏蔽结构连接；
    所述至少一个芯片中的每个芯片的第二表面，与所述封装基板的第一表面电连接；
    所述第一屏蔽结构通过第二连接部与所述封装基板的侧壁连接。
  11. 根据权利要求9所述的芯片系统，其特征在于，所述第二连接部为金属焊料；或，所述第二连接部为导电胶；或，所述第二连接部为绝缘熔胶。
  12. 根据权利要求1-11中任一项所述的芯片系统，其特征在于，所述第一屏蔽结构为金属结构件。
  13. 根据权利要求1-7中任一项所述的芯片系统，其特征在于，所述芯片封装体还包括塑封料；
    所述至少一个芯片中的每个芯片埋设于所述塑封料中；
    所述第一屏蔽结构覆盖所述塑封料的外表面以及所述封装基板的侧壁。
  14. 根据权利要求1-7中任一项所述的芯片系统，其特征在于，所述芯片封装体还包括塑封料；
    所述至少一个芯片埋设于所述塑封料中；
    所述至少一个芯片中的每个芯片与所述封装基板的第一表面电连接；
    所述第一屏蔽结构覆盖所述塑封料的外表面，并延伸至所述封装基板的第一表面。
  15. 根据权利要求13或14所述的芯片系统，其特征在于，所述第一屏蔽结构为以下中的任意一种：
    导电薄膜、金属材料或导电胶材料。
  16. 根据权利要求1至15中任一项所述的芯片系统，其特征在于，所述第二屏蔽结构为以下中的任意一种：
    导电薄膜、金属材料或导电胶材料。
  17. 根据权利要求2所述的芯片系统，其特征在于，所述多个电连接结构件为以下中的任意一种：
    金属焊球、烧结、金属结构件或插接端子。
  18. 根据权利要求1至17中任一项所述的芯片系统，其特征在于，所述第二屏蔽结构完全包覆所述第一屏蔽结构，且所述第二屏蔽结构与所述第一屏蔽结构的接触面有粘接材料。
  19. 根据权利要求1至18中任一项所述的芯片系统，其特征在于，所述第二屏蔽结构位于所述第一屏蔽结构的外侧，所述第二腔体的至少一部分位于所述封装基板与所述电路板之间。
  20. 一种通信设备，其特征在于，所述通信设备包括权利要求1至19中任一项所述的芯片系统。
  21. 根据权利要求20所述的通信设备，其特征在于，所述通信设备为射频收发信机；
    所述射频收发信机用于通过光纤与基站的基带处理单元BBU连接。
  22. 根据权利要求20或21所述的通信设备，其特征在于，所述至少一个芯片包括中频IF芯片。
PCT/CN2022/131597 2021-12-06 2022-11-14 一种芯片系统及通信设备 WO2023103716A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412703B1 (en) * 2015-02-17 2016-08-09 Powertech Technology Inc. Chip package structure having a shielded molding compound
JP2018093015A (ja) * 2016-12-01 2018-06-14 太陽誘電株式会社 無線モジュール及び無線モジュールの製造方法
CN112242386A (zh) * 2019-07-16 2021-01-19 江苏长电科技股份有限公司 Sip封装结构
CN112466849A (zh) * 2020-11-25 2021-03-09 杭州星阖科技有限公司 晶圆级自屏蔽封装结构及其制作方法
CN112563249A (zh) * 2019-09-25 2021-03-26 江苏长电科技股份有限公司 集成封装结构
CN212991092U (zh) * 2020-09-21 2021-04-16 青岛歌尔微电子研究院有限公司 封装模组、模组载板和电子设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412703B1 (en) * 2015-02-17 2016-08-09 Powertech Technology Inc. Chip package structure having a shielded molding compound
JP2018093015A (ja) * 2016-12-01 2018-06-14 太陽誘電株式会社 無線モジュール及び無線モジュールの製造方法
CN112242386A (zh) * 2019-07-16 2021-01-19 江苏长电科技股份有限公司 Sip封装结构
CN112563249A (zh) * 2019-09-25 2021-03-26 江苏长电科技股份有限公司 集成封装结构
CN212991092U (zh) * 2020-09-21 2021-04-16 青岛歌尔微电子研究院有限公司 封装模组、模组载板和电子设备
CN112466849A (zh) * 2020-11-25 2021-03-09 杭州星阖科技有限公司 晶圆级自屏蔽封装结构及其制作方法

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