WO2023097906A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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Publication number
WO2023097906A1
WO2023097906A1 PCT/CN2022/077795 CN2022077795W WO2023097906A1 WO 2023097906 A1 WO2023097906 A1 WO 2023097906A1 CN 2022077795 W CN2022077795 W CN 2022077795W WO 2023097906 A1 WO2023097906 A1 WO 2023097906A1
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WIPO (PCT)
Prior art keywords
storage
substrate
bit line
active
transistor
Prior art date
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PCT/CN2022/077795
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English (en)
French (fr)
Inventor
王晓光
李辉辉
张强
吴敏敏
汪珊
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Changxin Memory Technologies Inc
Beijing Superstring Academy of Memory Technology
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Changxin Memory Technologies Inc
Beijing Superstring Academy of Memory Technology
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Priority to US17/853,877 priority Critical patent/US20230171971A1/en
Publication of WO2023097906A1 publication Critical patent/WO2023097906A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment

Definitions

  • the embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • MRAM Magnetic Random Access Memory
  • Magnetic Random Access Memory includes a transistor structure and a magnetoresistive tunnel junction (MTJ, Magnetic Tunnel Junction) inserted between two metal lines. By controlling the transistor in the transistor structure, the magnetoresistance tunnel junction can be changed. The resistance value, and then read and write data.
  • MRAM Magnetic Random Access Memory
  • the storage units in the magnetic random access memory and the storage units in the dynamic random access memory are integrated for use.
  • the two types of memory cells are usually stacked in a direction perpendicular to the substrate, which makes the process complicated and reduces the production efficiency.
  • the first aspect of the present application provides a semiconductor structure, including: a substrate, the substrate includes a first array region and a second array region; a plurality of first memory cells are disposed on the first array region A first storage array composed of structures; a plurality of second storage arrays composed of second storage structures are arranged on the second array area.
  • the first storage structure includes a first bit line structure, a first transistor structure, and a capacitor structure, the first bit line structure is located below the first transistor, and the capacitor structure is disposed on On the corresponding first transistor structure;
  • the second storage structure includes a source line structure, a second bit line structure and a second transistor structure, the source line structure is located below the second transistor structure, the The second bit line structure is located above the second transistor structure; the first bit line structure and the source line structure are arranged in the same layer.
  • the first bit line structure includes a plurality of first bit lines extending along a first direction and arranged at intervals in a second direction
  • the first transistor structure includes a plurality of first bit lines arranged on the first A plurality of first active pillars on the bit line, the extending direction of the first active pillars is perpendicular to the surface of the substrate, and the projection of the first active pillars on the substrate is the same as that of the first active pillars.
  • the projections of the bit lines on the substrate are at least partially overlapped, and the first direction is perpendicular to the second direction;
  • the source line structure includes a plurality of A source line
  • the second transistor structure includes a plurality of second active columns arranged on the source line, the extending direction of the second active columns is perpendicular to the substrate surface, the second
  • the projection of the active column on the substrate and the projection of the source line on the substrate are at least partially coincident; the first active column and the second active column are arranged on the same layer.
  • the first transistor structure includes a plurality of first word lines extending along the second direction and arranged at intervals in the first direction, the first word lines surrounding the first active pillar The middle sidewall is arranged;
  • the second transistor structure includes a plurality of second word lines extending along the second direction and arranged at intervals in the first direction, and the second word lines surround the middle sidewall of the second active pillar set up;
  • the first word line and the second word line are arranged in the same layer.
  • the first storage structure further includes a first contact pad disposed on the corresponding first active pillar; the second storage structure further includes a second A contact pad, the second contact pad is disposed on the corresponding second active column; the first contact pad is disposed on the same layer as the second contact pad.
  • the capacitive structure includes a lower electrode, an upper electrode, and a capacitive dielectric layer, the capacitive dielectric layer is located between the lower electrode and the upper electrode, and the upper electrode is connected to the second
  • the bit line structure is set on the same layer.
  • the second storage structure includes a contact structure and a magnetic storage structure, and the magnetic storage structure is disposed on the corresponding second contact pad; the magnetic storage structure communicates with the contact structure through the contact structure.
  • the second bit line is electrically connected.
  • the magnetic storage structure includes a reference layer, a magnetic tunneling barrier layer, and a free layer, the reference layer is disposed on the corresponding second contact pad, and the magnetic tunneling barrier layer between the reference layer and the free layer.
  • the second bit line structure includes a plurality of second bit lines extending along the second direction and arranged at intervals in the first direction.
  • the second aspect of the present application provides a method for fabricating a semiconductor structure, including:
  • a substrate is provided, and the substrate includes a first array area and a second array area; a first storage array composed of a plurality of first storage structures arranged in an array is formed on the first array area; A second storage array composed of a plurality of second storage structures arranged in an array is formed on the second array area; the first storage array and the second storage array are formed synchronously.
  • the first storage structure includes a first bit line structure, a first transistor structure, and a capacitor structure
  • the second storage structure includes a source line structure, a second bit line structure, and a second transistor structure
  • the first bit line structure and the source line structure are synchronously formed on the first array area and the second array area
  • the first bit line structure is located below the first transistor, so
  • the capacitor structure is disposed on the corresponding first transistor
  • the source line structure is located below the second transistor structure
  • the second bit line structure is located above the second transistor structure.
  • the first transistor structure includes a plurality of first active pillars
  • the second transistor structure includes a plurality of second active pillars; the first active pillars and the first active pillars are formed synchronously.
  • the projection on the bottom is at least partially coincident; the extension direction of the second active column is perpendicular to the surface of the substrate, and the projection of the second active column on the substrate is the same as that of the source line on the
  • the projections on the substrate are at least partially coincident.
  • the first transistor structure further includes a plurality of first word lines
  • the second transistor structure further includes a plurality of second word lines; between the first bit line structure and the source A first word line and a second word line are synchronously formed on the polar line structure; a plurality of the first word lines extend along the second direction and are arranged at intervals in the first direction, and the first word lines surround the first active
  • the middle sidewall of the source pillar is arranged; a plurality of the second word lines extend along the second direction and are arranged at intervals in the first direction, and the second wordlines are arranged around the middle sidewall of the second active pillar.
  • the first storage structure further includes first contact pads disposed on corresponding first active pillars
  • the second storage structure further includes first contact pads disposed on corresponding second active pillars.
  • a dielectric layer is formed on the first contact pad and the second contact pad, the dielectric layer has a plurality of capacitance holes, and the projection of the capacitance holes on the substrate is located at the The first array area, and at least partially overlaps with the projection of the first contact pad on the substrate;
  • a plurality of magnetic storage structures and contact structures are sequentially formed on the second contact pad.
  • the capacitive structure includes a lower electrode, an upper electrode, and a capacitive dielectric layer, and the capacitive dielectric layer is located between the lower electrode and the upper electrode, and the second bit line structure includes a A plurality of second bit lines above the contact structure, the plurality of second bit lines extend along the second direction and are arranged at intervals in the first direction; electrode with the second bit line.
  • Embodiments of the present application provide a semiconductor structure and a method for fabricating the semiconductor structure.
  • the substrate includes a first array area and a second array area; the first array area is provided with a first storage array composed of a plurality of first storage structures; the second array area is provided with a plurality of second storage structures constitute the second storage array.
  • the first storage structure and the second storage structure are arranged side by side on the substrate, which is beneficial to simplify the process and improve the Productivity.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 2 is a top view of a substrate provided in an embodiment of the present application.
  • FIG. 3 is a flow chart of the steps of a method for fabricating a semiconductor structure provided in an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of synchronously forming a first bit line structure and a source line structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of synchronously forming a first active column and a second active column in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of synchronously forming a first word line and a second word line in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of synchronously forming a first contact pad and a second contact pad in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of forming a dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of forming a partial capacitor structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of removing part of the dielectric layer in the method for fabricating the semiconductor structure provided by the embodiment of the present application;
  • FIG. 11 is a schematic structural diagram of a magnetic storage structure formed in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of forming a contact structure in a method for fabricating a semiconductor structure provided in an embodiment of the present application
  • FIG. 13 is a schematic structural view of synchronous formation of an upper electrode and a second bit line structure in the method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • the semiconductor structure provided by the embodiment of the present application includes a substrate.
  • the material of the substrate 10 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC) ; It can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide.
  • the substrate 10 is provided with a peripheral area 13 and an array area adjacent to the peripheral area 13. Referring to FIG.
  • the peripheral area 13 can be set on the periphery of the array area, of course, in some other examples, the relative position of the peripheral area 13 and the array area can also be set according to actual needs, the peripheral area 13 can be used for example to form Cooperating structures cooperating with peripheral circuits, the array area can be used to form cooperating structures cooperating with memory cells, for example.
  • the array region includes a first array region 11 and a second array region 12. With continued reference to FIG. Periphery of District 12.
  • the first array area 11 is provided with a first storage array composed of a plurality of first storage structures
  • the second array area 12 is provided with a second storage array composed of a plurality of second storage structures.
  • the storage principle of the first storage structure in the first storage array is different from the storage principle of the second storage structure in the second storage array.
  • the first storage structure may have storage units of dynamic random access memory
  • the second storage structure For example, there may be a storage unit of magnetic random access memory.
  • DRAM is a volatile storage device
  • MRAM is a non-volatile storage device.
  • the embodiment of the present application provides a semiconductor structure, including a substrate 10, and the substrate 10 includes a first array region 11 and a second array region 12; the first array region 11 is provided with a first memory structure composed of a plurality of first memory structures. Array; the second array area 12 is provided with a second storage array composed of a plurality of second storage structures.
  • the first storage structure and the second storage structure are arranged side by side on the substrate 10, which is beneficial to simplify the process , reduce connection complexity and improve production efficiency.
  • the first storage structure may include a first bit line structure 21, a first transistor structure and a capacitor structure, the first bit line structure 21 is located below the first transistor, and the capacitor structure is arranged on a corresponding on the first transistor structure.
  • the second storage structure may include a source line structure 22, a second bit line structure 623 and a second transistor structure, the source line structure 22 is located below the second transistor structure, and the second bit line structure 623 is located above the second transistor structure.
  • the first bit line structure 21 and the source line structure 22 can be arranged in the same layer, the height of the first bit line structure 21 and the source line structure 22 are the same in the direction perpendicular to the surface of the substrate 10, and in parallel The shapes in the cross-section of the surface of the substrate 10 are the same, so that the first bit line structure 21 and the source line structure 22 can be formed synchronously, thereby simplifying the manufacturing process of the semiconductor structure.
  • the direction parallel to the substrate 10 in the illustrated position is the first direction
  • the direction parallel to the substrate 10 and perpendicular to the first direction in the illustrated position is the second direction.
  • the first bit line structure 21 includes a plurality of first bit lines extending along the first direction and arranged at intervals in the second direction
  • the source line structure 22 includes a plurality of first bit lines extending along the first direction and arranged at intervals in the second direction. source line.
  • the material of the first bit line and the source line can be the same, so as to further improve the manufacturing efficiency of the first bit line and the source line.
  • the material of the first bit line and the source line may include conductive materials doped with one or more combinations of polysilicon, titanium, titanium nitride and tungsten.
  • first isolation structure 211 between adjacent first bit lines
  • second isolation structure 221 between adjacent source lines. Since the first bit in the first bit line structure 21
  • the source lines in the line and source line structure 22 can be formed synchronously, the first isolation structure 211 and the second isolation structure 221 can also be formed synchronously, and the first isolation structure 211 and the second isolation structure 221 can have the same material, In this way, the manufacturing process of the semiconductor structure is further simplified.
  • the material of the first isolation structure 211 and the second isolation structure 221 may include, for example, one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.
  • the first transistor structure includes a plurality of first active pillars 311 arranged on the first bit line
  • the second transistor structure includes a plurality of second active pillars 312 arranged on the source line.
  • the active column 311 and the second active column 312 have the same height in the direction perpendicular to the surface of the substrate 10, and have the same shape in a section parallel to the surface of the substrate 10.
  • the first active column 311 and the second active column 312 can be arranged in the same layer, so that the first active pillar 311 and the second active pillar 312 can be formed synchronously, thereby simplifying the manufacturing process of the semiconductor structure.
  • the extending direction of the first active column 311 is perpendicular to the surface of the substrate 10, and the projection of the first active column 311 on the substrate 10 is at least partially coincident with the projection of the first bit line on the substrate 10, So that the first transistor structure can be electrically connected to the first bit line through the first active pillar 311 .
  • the extending direction of the second active column 312 is perpendicular to the surface of the substrate 10, and the projection of the second active column 312 on the substrate 10 and the projection of the source line on the substrate 10 at least partially coincide, so that the second transistor structure can It is electrically connected to the source line through the second active pillar 312 .
  • the material of the first active column 311 and the second active column 312 can be the same, and the material of the first active column 311 and the second active column 312 can include silicon (Si), germanium (Ge), or silicon germanium (GeSi). ), silicon carbide (SiC); silicon germanium carbide (SiGeC), indium arsenide (InAs); or other materials, such as III-V group compounds such as gallium arsenide.
  • the first active pillar 311 and the second active pillar 312 have the same structure, including a source region, a drain region, and a channel region between the source region and the drain region. It is worth noting that in this embodiment, the source The bit line is connected to the source region of the second active pillar 312 , and the first bit line is connected to the source region of the first active pillar 311 .
  • the first transistor structure further includes a plurality of first word lines 321, and the second transistor structure further includes a plurality of second word lines 322, and the first word lines 321 and the second word lines 322 may be arranged in the same layer.
  • a word line 321 and a second word line 322 have the same height in a direction perpendicular to the surface of the substrate 10, and have the same shape in a section parallel to the surface of the substrate 10, so that the first word line 321 and the second word line 322 can be Synchronous formation, thereby simplifying the manufacturing process of the semiconductor structure.
  • a plurality of first word lines 321 extend along the second direction and are arranged at intervals in the first direction.
  • the first word lines 321 are arranged around the middle sidewall of the first active pillar 311.
  • the first word lines The line 321 is disposed around the channel region in the middle of the first active pillar 311 , and a first gate dielectric layer may also be disposed between the first word line 321 and the first active pillar 311 .
  • a plurality of second word lines 322 extend along the second direction and are arranged at intervals in the first direction.
  • the second word lines 322 are arranged around the middle sidewall of the second active pillar 312.
  • the second word lines 322 surround A channel region is disposed in the middle of the second active pillar 312 , and a second gate dielectric layer may also be disposed between the second word line 322 and the second active pillar 312 .
  • the structure and material of the second gate dielectric layer and the first gate dielectric layer are the same, and the second gate dielectric layer and the first gate dielectric layer can also be formed synchronously.
  • the second insulating structure 324, the structure and material of the first insulating structure 314 and the second insulating structure 324 are the same, and may include one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.
  • the first insulating structure 314 and the second insulating structure 324 may also be formed synchronously.
  • each first word line 321 is connected to a different first active column 311, and adjacent first word lines 321 are not connected.
  • each second word line 322 is connected to a different The second active pillars 312 are connected, and the adjacent second word lines 322 are not connected.
  • the width here refers to the width of the first word line 321 or the second word line 322 in the first direction
  • the first word line 321 or the second word line 322 can connect two adjacent first active pillars 311 or second active pillars 312 as many as possible and evenly.
  • first transistor structure and the second transistor structure in this embodiment are vertical gate-all-around gate transistors (Gate-All-Around, GAA).
  • GAA vertical gate-all-around gate transistors
  • This structure has the characteristics of high integration, which is beneficial to improve the unit
  • the quantity of the first storage structure and the second storage structure within the area is used to increase the arrangement density.
  • the first storage structure may further include a plurality of first contact pads 41
  • the second storage structure may further include a plurality of second contact pads 42
  • the first contact pads 41 and the second contact pads 42 may be arranged in the same layer.
  • the first contact pad 41 and the second contact pad 42 have the same height in the direction perpendicular to the surface of the substrate 10, and have the same shape in a section parallel to the surface of the substrate 10, so that the first contact pad 41 and the second contact pad 42 can be formed simultaneously, thereby simplifying the manufacturing process of the semiconductor structure.
  • first contact pads 41 are disposed on corresponding first active pillars 311
  • second contact pads 42 are disposed on corresponding second active pillars 312 .
  • the material of the first contact pad 41 and the second contact pad 42 can be the same, and the material of the first contact pad 41 and the second contact pad 42 can include tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (TiNx) or a combination of more.
  • a first insulating block 411 is also arranged between adjacent first contact pads 41
  • a second insulating block 421 is also arranged between adjacent second contact pads 42.
  • the first insulating block 411 and the second insulating block 421 The structure is the same as the material, and may include one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide.
  • the first insulating block 411 and the second insulating block 421 may also be formed synchronously.
  • a first dielectric layer 50 and a capacitor structure are disposed on the first transistor structure.
  • the first dielectric layer 50 is provided with a through capacitor hole 51, the projection of the capacitor hole 51 on the substrate 10 at least partially overlaps with the projection of the first contact pad 41 on the substrate 10, and part of the capacitor structure is arranged in the capacitor hole 51 , so as to connect with the first contact pad 41.
  • the capacitive structure may include a lower electrode 611 , an upper electrode 613 and a capacitive dielectric layer 612 , and the capacitive dielectric layer 612 is located between the lower electrode 611 and the upper electrode 613 .
  • the lower electrode 611 covers the hole wall of the capacitor hole 51
  • the capacitor medium layer 612 covers the surface of the lower electrode 611
  • the upper electrode 613 covers the capacitor medium layer 612 .
  • the capacitor structure may also include other structures in related technologies, which are not specifically limited in this embodiment of the present application.
  • the second transistor is provided with a contact structure 622, a magnetic storage structure 621 and a second bit line structure 623, and the magnetic storage structure 621 is provided on the corresponding second contact pad 42; the contact The structure 622 is disposed on the corresponding magnetic storage structure 621.
  • the projection of the contact structure 622 on the substrate 10 and the projection of the magnetic storage structure 621 on the substrate 10 at least partially overlap, so that the contact structure 622 and the magnetic storage structure Structure 621 is electrically connected.
  • the second bit line structure 623 is disposed on the contact structure 622 , and the magnetic storage structure 621 is electrically connected to the second bit line structure 623 through the contact structure 622 .
  • the second bit line structure 623 includes a plurality of second bit lines extending along the second direction and arranged at intervals along the first direction.
  • a first supporting structure 6211 is further disposed between adjacent magnetic storage structures 621
  • a second supporting structure 6222 is further disposed between adjacent contact structures 622 .
  • the upper electrode 613 and the second bit line structure 623 can be arranged on the same layer, the upper electrode 613 and the second bit line structure 623 can be arranged on the same layer, and the upper electrode 613 and the second bit line structure 623 can be arranged vertically to the substrate
  • the surface of the substrate 10 has the same height in the direction and the same shape in the cross-section parallel to the surface of the substrate 10, so that the upper electrode 613 and the second bit line structure 623 can be formed synchronously, thereby simplifying the manufacturing process of the semiconductor structure.
  • the magnetic storage structure 621 of this embodiment is a magnetic tunnel junction (Magnetic Tunneling Junction, MTJ), including a reference layer, a magnetic tunneling barrier layer and a free layer, and the reference layer is arranged on the corresponding second contact pad 42, the magnetic tunneling barrier layer is located between the reference layer and the free layer, that is, in this embodiment, the magnetic storage structure 621 is the reference layer, the magnetic storage structure 621 from the direction close to the substrate 10 to the direction away from the substrate 10 Tunneling barrier layer and free layer. It is worth noting that, in the magnetic storage structure 621 of another embodiment, from the direction close to the substrate 10 to the direction away from the substrate 10 are the free layer, the magnetic tunneling barrier layer and the reference layer in sequence.
  • the material of the free layer and the reference layer may include cobalt iron boron (CoFeB), and the material of the magnetic tunnel barrier layer may be magnesium oxide (MgO).
  • the magnetic storage structure 621 relies on the quantum tunneling effect to allow electrons to pass through the magnetic tunnel barrier layer, and the tunneling probability of polarized electrons is related to the relative magnetization directions of the reference layer and the free layer.
  • the magnetization direction of the reference layer remains unchanged.
  • the tunneling probability of polarized electrons is high.
  • the magnetic storage structure 621 shows a low resistance state; when the magnetization of the reference layer and the free layer When the direction is opposite, the tunneling probability of polarized electrons is relatively low, and at this time, the magnetic storage structure 621 exhibits a high resistance state.
  • the low resistance state and the high resistance state of the magnetic storage structure 621 are used to represent logic states "1" and "0", thereby realizing data storage.
  • the embodiment of the present application also provides a method for making a semiconductor structure, for making the semiconductor structure in the above embodiment, please refer to Fig. 3, the steps include:
  • Step S101 providing a substrate, where the substrate includes a first array region and a second array region.
  • a peripheral area 13 and an array area adjacent to the peripheral area 13 are arranged on the substrate 10 , the periphery is located on the left side of the substrate 10 in the position shown in the figure, and the array area is located in the substrate 10 in the position shown in the figure.
  • the right part of the array area, and the peripheral area 13 may be disposed on the periphery of the array area.
  • the array area includes a first array area 11 and a second array area 12.
  • the substrate 10 after the substrate 10 is provided, it also includes:
  • Step S102 forming a first storage array composed of a plurality of first storage structures arranged in an array on the first array region, and forming a second storage array composed of a plurality of second storage structures arranged in an array on the second array region.
  • Storage array; the first storage array and the second storage array are formed synchronously.
  • the film layer structure in the first memory structure is formed synchronously with the film layer structure of the same film layer in the second memory structure, so that the first memory array and the second memory array are formed synchronously.
  • the storage principle of the first storage structure in the first storage array is different from the storage principle of the second storage structure in the second storage array.
  • the first storage structure may have storage units of dynamic random access memory
  • the second storage structure For example, there may be a storage unit of magnetic random access memory.
  • This embodiment provides a manufacturing method of a semiconductor structure, including: providing a substrate 10, the substrate 10 includes a first array region 11 and a second array region 12; The first storage array composed of the first storage structure forms a second storage array composed of a plurality of second storage structures arranged in an array on the second array area 12; the first storage array and the second storage array are formed synchronously.
  • the first storage structure and the second storage structure are formed in a distributed manner, and the first storage structure and the second storage structure are formed synchronously on the substrate 10, which is beneficial to simplify the process and improve production efficiency.
  • the first storage structure includes a first bit line structure 21, a first transistor structure and a capacitor structure, the first bit line structure 21 is located below the first transistor, and the capacitor structure is set On the corresponding first transistor;
  • the second storage structure includes a source line structure 22, a second bit line structure 623 and a second transistor structure, the source line structure 22 is located below the second transistor structure, and the second bit line structure 623 is located above the second transistor structure.
  • the step of synchronously forming the first memory array and the second memory array may include: synchronously forming the first bit line structure 21 and the source line structure 22 on the first array area 11 and the second array area 12 .
  • the first isolation structure 211 and the second isolation structure 221 can be formed simultaneously on the first array region 11 and the second array region 12 of the substrate 10 through a deposition process.
  • the first isolation structure 211 and the second isolation structure 221 are used to define the first bit line structure 21 and the source line structure 22 .
  • the first bit line structure 21 and the source line structure 22 are simultaneously formed between adjacent first isolation structures 211 and between adjacent second isolation structures 221 through a deposition process.
  • the direction parallel to the substrate 10 in the illustrated position is the first direction
  • the direction parallel to the substrate 10 and perpendicular to the first direction in the illustrated position is the second direction.
  • the first bit line structure 21 includes a plurality of first bit lines extending along the first direction and arranged at intervals in the second direction
  • the source line structure 22 includes a plurality of first bit lines extending along the first direction and arranged at intervals in the second direction. source line. Further, in order to ensure that the first bit line structure 21 and the source line structure 22 can be deposited and formed at the same time, the first bit line structure 21 and the source line structure 22 are made of the same material.
  • the first transistor structure may further include a plurality of first active pillars 311, and the second transistor structure may further include a plurality of second active pillars 312; the extending direction of the first active pillars 311 is consistent with the substrate 10
  • the surface is vertical, and the projection of the first active column 311 on the substrate 10 is at least partially coincident with the projection of the first bit line on the substrate 10; the extending direction of the second active column 312 is perpendicular to the surface of the substrate 10, and the second The projection of the active pillar 312 on the substrate 10 is at least partially coincident with the projection of the source line on the substrate 10 .
  • the first initial active column and the second initial active column can be formed synchronously on the first bit line structure 21 and the source line structure 22 through a deposition process, in order to make the first initial active column
  • the source pillar and the second initial active pillar can be formed synchronously, and the material of the first initial active pillar and the second initial active pillar is the same.
  • the first active pillar 311 and the second active pillar 312 may be simultaneously formed through three ion implantation techniques.
  • the ion implantation energy and the type of implanted dopant ions in the ion implantation technology can be controlled to form drain regions at the bottom of the first initial active pillar and the second initial active pillar, and then, the ion implantation technology can be controlled Ion implantation energy and the type of implanted dopant ions to form a channel region in the middle of the first initial active column and the second initial active column, and finally, control the ion implantation energy and implantation of dopant ions in the ion implantation technology type to form a source region on top of the first initial active pillar and the second initial active pillar, wherein the type of dopant ions in the drain region may be the same type as that of the source region, for example, dopant ions It may include N-type ions; the type of doping ions in the channel region is different from that in the drain region, for example, the doping ions may include P-type ions.
  • the first transistor structure further includes a plurality of first word lines 321, and the second transistor structure further includes a plurality of second word lines 322; the plurality of first word lines 321 extend along the second direction and The first word lines 321 are arranged at intervals upward, and the first word lines 321 are arranged around the middle sidewall of the first active column 311; a plurality of second word lines 322 extend along the second direction and are arranged at intervals in the first direction, and the second word lines 322 surround the second The middle sidewall of the active column 312 is disposed.
  • the first bit line structure 21 and the source line structure 22 are formed synchronously.
  • first filling region 313 there is a first filling region 313 between adjacent first active pillars 311, and there is a second filling region 323 between adjacent second active pillars 312.
  • first filling region 313 and the second filling region 323 are simultaneously filled with the first insulating material and the second insulating material until the first insulating material and the second insulating material cover the source regions of the first active pillar 311 and the second active pillar 312 .
  • Form the first conductive layer and the second conductive layer simultaneously on the first insulating material and the second insulating material, and make the first conductive layer and the second conductive layer cover the grooves of the first active pillar 311 and the second active pillar 312 road area.
  • Parts of the first conductive layer and the second conductive layer are removed to simultaneously form the first word line 321 and the second word line 322 .
  • An insulating material forms the first insulating structure 314
  • a second insulating material in the second filling region 323 forms the second insulating structure 324 .
  • the materials of the first insulating material and the second insulating material are the same, and in order to form the first word line 321 and the second word line 322 at the same time, The materials of the first conductive layer and the second conductive layer are the same.
  • the first storage structure further includes first contact pads 41 disposed on corresponding first active pillars 311
  • the second storage structure further includes contact pads 41 disposed on corresponding second active pillars 312 .
  • the second contact pad 42 .
  • the first word line 321 and the second word line 322 after synchronously forming the first word line 321 and the second word line 322 on the first bit line structure 21 and the source line structure 22, further includes: The first contact pad 41 and the second contact pad 42 are formed on the 312 synchronously.
  • the first contact pad 41 and the second contact pad 42 can be simultaneously formed on the first active pillar 311 and the second active pillar 312 through a deposition process, and further, can also be formed by The deposition process simultaneously forms a first insulating block 411 and a second insulating block 421 between adjacent first contact pads 41 and between adjacent second contact pads 42 .
  • the materials of the first contact pad 41 and the second contact pad 42 are the same, and in order to ensure that the first insulating block 411 and the second insulating block 421 can Simultaneous deposition and formation, the first insulating block 411 and the second insulating block 421 are made of the same material.
  • a dielectric layer 50 is formed on the second contact pad 42, and a plurality of capacitor holes 51 are formed on the dielectric layer 50.
  • the projection of the capacitor hole 51 on the substrate 10 is located in the first array area 11, and is consistent with the projection of the first contact pad 41 on the substrate 10. overlap at least partially.
  • the capacitive structure may include a lower electrode 611 , an upper electrode 613 and a capacitive dielectric layer 612 , and the capacitive dielectric layer 612 is located between the lower electrode 611 and the upper electrode 613 .
  • part of the capacitor structure includes a lower electrode 611 and a capacitor dielectric layer 612 , the lower electrode 611 covers the hole wall of the capacitor hole 51 , and the capacitor dielectric layer 612 covers the surface of the lower electrode 611 and fills the capacitor hole 51 .
  • the capacitor structure may also include other structures in related technologies, which are not specifically limited in this embodiment of the present application.
  • the magnetic storage structure 621 of this embodiment is a magnetic tunnel junction (Magnetic Tunneling Junction, MTJ), including a reference layer, a magnetic tunneling barrier layer and a free layer, and its specific structure and working principle will not be repeated here.
  • the projection of the contact structure 622 on the substrate 10 is at least partially coincident with the projection of the magnetic storage structure 621 on the substrate 10 , so that the contact structure 622 is electrically connected to the magnetic storage structure 621 .
  • the magnetic storage structure 621 and the contact structure 622 may be formed by a deposition process. Referring to FIG. 13 , a first support structure 6211 is further provided between adjacent magnetic storage structures 621 , and a second support structure 6222 is further provided between adjacent contact structures 622 .
  • the second bit line structure 623 includes a plurality of second bit lines located above the contact structure 622, the plurality of second bit lines extend along the second direction and are arranged at intervals in the first direction; the upper electrode 613 covers the capacitive dielectric layer 612 . Further, in order to ensure that the upper electrode 613 and the second bit line structure 623 can be deposited and formed at the same time, the material of the upper electrode 613 and the second bit line structure 623 is the same.

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Abstract

本申请实施例属于半导体制造技术领域，具体涉及一种半导体结构及半导体结构的制作方法。包括衬底，衬底包括第一阵列区和第二阵列区；第一阵列区上设有多个第一存储结构构成的第一存储阵列；第二阵列区上设有多个第二存储结构构成的第二存储阵列。相比于相关技术中，将不同的存储结构在衬底上进行层叠设置，本实施例中，将第一存储结构和第二存储结构在衬底上进行并排设置，有利于简化工艺制程，提高生产效率。

Description

半导体结构及半导体结构的制作方法
本申请要求于2021年11月30日提交中国专利局、申请号为2021114469522、申请名称为“半导体结构及半导体结构的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构及半导体结构的制作方法。
背景技术
动态随机存储器(DRAM，Dynamic Random Access Memory)包括晶体管结构以及电容结构，晶体管结构中的晶体管与电容结构中的电容电连接，以通过晶体管读取电容内的数据、或者向电容内写入数据。磁性随机访问存储器(MRAM，Magnetic Random Access Memory)包括晶体管结构以及插在两条金属线之间的磁阻隧道结(MTJ，Magnetic Tunnel Junction)，通过控制晶体管结构中的晶体管，改变磁阻隧道结的电阻值，进而读写数据。
相关技术中，为满足半导体存储器的不同使用需求，将磁性随机访问存储器中的存储单元与动态随机存储器中的存储单元集成在一起使用。然而，两种存储单元通常在垂直于衬底的方向上层叠设置，使得工艺制程繁琐，生产效率降低。
发明内容
根据一些实施例，本申请第一方面提供一种半导体结构，包括：衬底，所述衬底包括第一阵列区和第二阵列区；所述第一阵列区上设有多个第一存储结构构成的第一存储阵列；所述第二阵列区上设有多个第二存储结构构成的第二存储阵列。
在一些公开的实施例中，所述第一存储结构包括第一位线结构、第一晶体管结构和电容结构，所述第一位线结构位于所述第一晶体管下方，所述电容结构设置在对应的所述第一晶体管结构上；所述第二存储结构包括源极线结构、第二位线结构和第二晶体管结构，所述源极线结构位于所述第二晶体管结构下方，所述第二位线结构位于所述第二晶体管结构上方；所述第一位线结构和所述源极线结构同层设置。
在一些公开的实施例中，所述第一位线结构包括沿第一方向延伸且在第二方向上间隔设置的多个第一位线，所述第一晶体管结构包括设置在所述第一位线上的多个第一有源柱，所述第一有源柱的延伸方向与所述衬底表面垂直，所述第一有源柱在所述衬底上的投影与所述第一位线在所述衬底上的投影至少部分重合，所述第一方向与所述第二方向垂直；所述源极线结构包括沿第一方向延伸且在第二方向上间隔设置的多个源极线，所述第二晶体管结构包括设置在所述源极线上的多个第二有源柱，所述第 二有源柱的延伸方向与所述衬底表面垂直，所述第二有源柱在所述衬底上的投影与所述源极线在所述衬底上的投影至少部分重合；所述第一有源柱与所述第二有源柱同层设置。
在一些公开的实施例中，所述第一晶体管结构包括沿第二方向延伸且在第一方向上间隔设置的多条第一字线，所述第一字线环绕所述第一有源柱中间侧壁设置；所述第二晶体管结构包括沿第二方向延伸且在第一方向上间隔设置的多条第二字线，所述第二字线环绕所述第二有源柱中间侧壁设置；
所述第一字线与所述第二字线同层设置。
在一些公开的实施例中，所述第一存储结构还包括第一接触垫，所述第一接触垫设置在对应的所述第一有源柱上；所述第二存储结构还包括第二接触垫，所述第二接触垫设置在对应的所述第二有源柱上；所述第一接触垫与所述第二接触垫同层设置。
在一些公开的实施例中，所述电容结构包括下电极、上电极及电容介质层，所述电容介质层位于所述下电极和所述上电极之间，所述上电极与所述第二位线结构同层设置。
在一些公开的实施例中，所述第二存储结构包括接触结构、磁性存储结构，所述磁性存储结构设置在对应的所述第二接触垫上；所述磁性存储结构通过所述接触结构与所述第二位线实现电连接。
在一些公开的实施例中，所述磁性存储结构包括参考层、磁隧穿势垒层以及自由层，所述参考层设置在对应的所述第二接触垫上，所述磁隧穿势垒层位于所述参考层和所述自由层之间。
在一些公开的实施例中，所述第二位线结构包括沿第二方向延伸且在第一方向上间隔设置的多个第二位线。
根据一些实施例，本申请第二方面提供一种半导体结构的制作方法，包括：
提供衬底，所述衬底包括第一阵列区和第二阵列区；在所述第一阵列区上形成多个呈阵列排布的第一存储结构构成的第一存储阵列；在所述第二阵列区上形成多个呈阵列排布的第二存储结构构成的第二存储阵列；所述第一存储阵列和所述第二存储阵列同步形成。
在一些公开的实施例中，所述第一存储结构包括第一位线结构、第一晶体管结构和电容结构，所述第二存储结构包括源极线结构、第二位线结构和第二晶体管结构；在所述第一阵列区和所述第二阵列区上同步形成所述第一位线结构和所述源极线结构；所述第一位线结构位于所述第一晶体管下方，所述电容结构设置在对应的所述第一晶体管上；所述源极线结构位于所述第二晶体管结构下方，所述第二位线结构位于所述第二晶体管结构上方。
在一些公开的实施例中，所述第一晶体管结构包括多个第一有源柱，所述第二晶体管结构包括多个第二有源柱；同步形成所述第一有源柱与所述第二有源柱；所述第一有源柱的延伸方向与所述衬底表面垂直，所述第一有源柱在所述衬底上的投影与所述第一位线在所述衬底上的投影至少部分重合；所述第二有源柱的延伸方向与所述衬底表面垂直，所述第二有源柱在所述衬底上的投影与所述源极线在所述衬底上的投影至少部分重合。
在一些公开的实施例中，所述第一晶体管结构还包括多条第一字线，所述第二晶体管结构还包括多条第二字线；在所述第一位线结构和所述源极线结构上同步形成第一字线与第二字线；多条所述第一字线沿第二方向延伸且在第一方向上间隔设置，所述第一字线环绕所述第一有源柱中间侧壁设置；多条所述第二字线沿第二方向延伸且在第一方向上间隔设置，所述第二字线环绕所述第二有源柱中间侧壁设置。
在一些公开的实施例中，所述第一存储结构还包括设置在对应的所述第一有源柱上的第一接触垫，所述第二存储结构还包括设置在对应的所述第二有源柱上的第二接触垫；在所述第一有源柱和所述第二有源柱上同步形成所述第一接触垫和所述第二接触垫。
在一些公开的实施例中，在所述第一接触垫和所述第二接触垫上形成介质层，所述介质层上具有多个电容孔，所述电容孔在所述衬底的投影位于所述第一阵列区，且与所述第一接触垫在所述衬底的投影至少部分重叠；
在所述电容孔内形成多个部分电容结构；
去除部分所述介质层，以暴露所述第二接触垫；
在所述第二接触垫上依次形成多个磁性存储结构和接触结构。
在一些公开的实施例中，所述电容结构包括下电极、上电极及电容介质层，所述电容介质层位于所述下电极和所述上电极之间，所述第二位线结构包括位于所述接触结构上方的多个第二位线，多个第二位线沿第二方向延伸且在第一方向上间隔设置；在所述电容介质层和所述接触结构上同步形成所述上电极与所述第二位线。
本申请实施例提供一种半导体结构及半导体结构的制作方法。包括衬底，衬底包括第一阵列区和第二阵列区；第一阵列区上设有多个第一存储结构构成的第一存储阵列；第二阵列区上设有多个第二存储结构构成的第二存储阵列。相比于相关技术中，将不同的存储结构在衬底上进行层叠设置，本实施例中，将第一存储结构和第二存储结构在衬底上进行并排设置，有利于简化工艺制程，提高生产效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种半导体结构的结构示意图；
图2为本申请实施例提供的一种衬底的俯视图；
图3为本申请实施例提供的一种半导体结构的制作方法的步骤流程图；
图4为本申请实施例提供的半导体结构的制作方法中同步形成第一位线结构和源极线结构的结构示意图；
图5为本申请实施例提供的半导体结构的制作方法中同步形成第一有源柱与第二有源柱的结构示意图；
图6为本申请实施例提供的半导体结构的制作方法中同步形成第一字线与第二字线的结构示意图；
图7为本申请实施例提供的半导体结构的制作方法中同步形成第一接触垫与第二接触垫的结构示意图；
图8为本申请实施例提供的半导体结构的制作方法中形成介质层的结构示意图；
图9为本申请实施例提供的半导体结构的制作方法中形成部分电容结构的结构示意图；
图10为本申请实施例提供的半导体结构的制作方法中去除部分介质层的结构示意图；
图11为本申请实施例提供的半导体结构的制作方法中形成磁性存储结构的结构示意图；
图12为本申请实施例提供的半导体结构的制作方法中形成接触结构的结构示意图；
图13为本申请实施例提供的半导体结构的制作方法中同步形成上电极与第二位线结构的结构示意图。
具体实施方式
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本申请实施例提供的半导体结构包括衬底，如图1和图2所示，衬底10的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。衬底10上设置有外围区13和与外围区13邻接的阵列区，参照图2，外围区13位于图示位置中的衬底10的左部，阵列区位于图示位置中衬底10的右部，且外围区13可以设置在阵列区的外围，当然，在一些其他的示例中，外围区13与阵列区的相对位置还可以根据实际的需要进行设置，外围区13例如可以用于形成与外围电路配合的配合结构，阵列区例如可以用于形成与存储单元配合的配合结构。其中，阵列区包括第一阵列区11和第二阵列区12，继续参照图2，第二阵列区12可以位于衬底10中阵列区的左部，第一阵列区11可以设置在第二阵列区12的外围。
第一阵列区11上设有多个第一存储结构构成的第一存储阵列，第二阵列区12上设有多个第二存储结构构成的第二存储阵列。本实施例中，第一存储阵列中第一存储结构的存储原理与第二存储阵列中第二存储结构的存储原理不同，第一存储结构例如可以具有动态随机存储器的存储单元，第二存储结构例如可以具有磁性随机访问存储器的存储单元。
值得说明的是，动态随机存储器是一种易失性存储器件，而磁性随机访问存储器是一种非易失性存储器件。通过在同一衬底10上分别设置具有易失性存储特性的第一存储结构和具有非易失性存储特性的第二存储结构，有利于进一步提高半导体结构的灵活存储性能与快速存取的性能。
本申请实施例提供一种半导体结构，包括衬底10，衬底10包括第一阵列区11和第二阵列区12；第一阵列区11上设有多个第一存储结构构成的第一存储阵列；第二阵列区12上设有多个第二存储结构构成的第二存储阵列。相比于相关技术中，将不同的存储结构在衬底10上进行层叠设置，本实施例中，将第一存储结构和第二存储结构在衬底10上进行并排设置，有利于简化工艺制程，减少连线复杂度，提高生产效率。
继续参照图1，在第一阵列区11，第一存储结构可以包括第一位线结构21、第一晶体管结构和电容结构，第一位线结构21位于第一晶体管下方，电容结构设置在对应的第一晶体管结构上。在第二阵列区12，第二存储结构可以包括源极线结构22、第二位线结构623和第二晶体管结构，源极线结构22位于第二晶体管结构下方，第二位线结构623位于第二晶体管结构上方。
本实施例中，第一位线结构21和源极线结构22可以同层设置，第一位线结构21和源极线结构22在垂直于衬底10表面的方向上高度相同，且在平行于衬底10表面的截面内形状相同，以便第一位线结构21和源极线结构22可以同步形成，进而简化半导体结构的工艺制程。
参照图1，图示位置中平行于衬底10的方向为第一方向，图示位置中平行于衬底10且垂直于第一方向的方向为第二方向。第一位线结构21包括沿第一方向延伸且在第二方向上间隔设置的多个第一位线，源极线结构22包括沿第一方向延伸且在第二方向上间隔设置的多个源极线。第一位线和源极线的材质可以相同，以便进一步提高第一位线和源极线的制作效率。第一位线和源极线的材质可以包括掺杂多晶硅、钛、氮化钛以及钨中的一种或者多种组合的导电材料。
如图1所示，相邻的第一位线之间可以具有第一隔离结构211，相邻的源极线之间具有第二隔离结构221，由于第一位线结构21中的第一位线和源极线结构22中的源极线可以同步形成，第一隔离结构211和第二隔离结构221也可以同步形成，且第一隔离结构211和第二隔离结构221可以具有相同的材质，从而进一步简化半导体结构的工艺制程。第一隔离结构211和第二隔离结构221的材质例如可以包括氮化硅、氮氧化硅以及氧化硅中的一种或者多种的组合。
本实施例中，第一晶体管结构包括设置在第一位线上的多个第一有源柱311，第二晶体管结构包括设置在源极线上的多个第二有源柱312，第一有源柱311与第二有源柱312在垂直于衬底10表面的方向上高度相同，且在平行于衬底10表面的截面内形状相同，第一有源柱311与第二有源柱312可以同层设置，以便第一有源柱311与第二有源柱312可以同步形成，进而简化半导体结构的工艺制程。
继续参照图1，第一有源柱311的延伸方向与衬底10表面垂直，第一有源柱311在衬底10上的投影与第一位线在衬底10上的投影至少部分重合，以便第一晶体管结构能够通过第一有源柱311与第一位线电连接。第二有源柱312的延伸方向与衬底10表面垂直，第二有源柱312在衬底10上的投影与源极线在衬底10上的投影至少部分重合，以便第二晶体管结构能够通过第二有源柱312与源极线电连接。第一有源柱311和第二有源柱312的材质可以相同，第一有源柱311和第二有源柱312的材质可以包括硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是碳化硅锗(SiGeC)，砷化铟(InAs)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。第一有源柱311 和第二有源柱312的结构相同，包括位于源区、漏区以及位于源区与漏区之间的沟道区，值得说明的是，本实施例中，源极线与第二有源柱312的源区连接，第一位线与第一有源柱311的源区连接。
本实施例中，第一晶体管结构还包括多条第一字线321，第二晶体管结构还包括多条第二字线322，第一字线321与第二字线322可以同层设置，第一字线321与第二字线322在垂直于衬底10表面的方向上高度相同，且在平行于衬底10表面的截面内形状相同，以便第一字线321与第二字线322可以同步形成，进而简化半导体结构的工艺制程。
参照图1，多条第一字线321沿第二方向延伸且在第一方向上间隔设置，第一字线321环绕第一有源柱311中间侧壁设置，本实施例中，第一字线321环绕第一有源柱311中间的沟道区设置，并且第一字线321与第一有源柱311之间还可以设置有第一栅极介质层。多条第二字线322沿第二方向延伸且在第一方向上间隔设置的，第二字线322环绕第二有源柱312中间侧壁设置，本实施例中，第二字线322环绕第二有源柱312中间的沟道区设置，并且第二字线322与第二有源柱312之间还可以设置有第二栅极介质层。第二栅极介质层与第一栅极介质层的结构与材料相同，第二栅极介质层与第一栅极介质层也可以同步形成。第一有源柱311之间还具有用于隔离相邻第一有源柱311的第一绝缘结构314，第二有源柱312之间还具有用于隔离相邻第二有源柱312的第二绝缘结构324，第一绝缘结构314与第二绝缘结构324的结构与材料相同，可以包括氮化硅、氮氧化硅以及氧化硅中的一种或者多种的组合。第一绝缘结构314与第二绝缘结构324也可以同步形成。
值得说明的是，每条第一字线321均连接不同的第一有源柱311，且相邻的第一字线321之间不相连，相同的，每条第二字线322均连接不同的第二有源柱312，且相邻的第二字线322之间不相连。本领域技术人员可以通过调节第一字线321或者第二字线322的宽度(此处“宽度”是指第一字线321或者第二字线322在第一方向上的宽度)，以使第一字线321或者第二字线322能尽可能多且平均地连接相邻的两个第一有源柱311或者第二有源柱312。
值得说明的是，本实施例中的第一晶体管结构和第二晶体管结构为垂直的全环绕栅极晶体管(Gate-All-Around，GAA)，该结构具有集成性高的特点，有利于提高单位面积内第一存储结构和第二存储结构的数量，以提高排布密度。
本实施例中，第一存储结构还可以包括多个第一接触垫41，第二存储结构还可以包括多个第二接触垫42，第一接触垫41与第二接触垫42可以同层设置，第一接触垫41与第二接触垫42在垂直于衬底10表面的方向上高度相同，且在平行于衬底10表面的截面内形状相同，以便第一接触垫41与第二接触垫42可以同步形成，进而简化半导体结构的工艺制程。
参照图1，第一接触垫41设置在对应的第一有源柱311上，第二接触垫42设置在对应的第二有源柱312上。第一接触垫41与第二接触垫42的材质可以相同，第一接触垫41与第二接触垫42的材质可以包括钨(W)、氮化钨(WN)、硅化钨(WSi)、钛(Ti)、氮化钛(TiNx)中的一种或者多种的组合。相邻的第一接触垫41之间还设置有第一绝缘块411，相邻的第二接触垫42之间还设置有第二绝缘块421，第一绝缘块411与第二 绝缘块421的结构与材料相同，可以包括氮化硅、氮氧化硅以及氧化硅中的一种或者多种的组合。第一绝缘块411与第二绝缘块421也可以同步形成。
如图1所示，第一存储结构中，第一晶体管结构上设置有第一介质层50和电容结构。第一介质层50上设置有贯穿的电容孔51，电容孔51在衬底10上的投影与第一接触垫41在衬底10上的投影至少部分重叠，部分电容结构设置在电容孔51内，以便与第一接触垫41连接。
电容结构可以包括下电极611、上电极613及电容介质层612，电容介质层612位于下电极611和上电极613之间。下电极611覆盖在电容孔51的孔壁，电容介质层612覆盖在下电极611表面，上电极613覆盖在电容介质层612上。当然，电容结构还可以包括相关技术中的其他结构，本申请实施例不进行具体限定。
如图1所示，第二存储结构中，第二晶体管上设置有接触结构622、磁性存储结构621以及第二位线结构623，磁性存储结构621设置在对应的第二接触垫42上；接触结构622设置在对应的磁性存储结构621上，继续参照图1，接触结构622在衬底10上的投影与磁性存储结构621在衬底10上的投影至少部分重合，以便接触结构622与磁性存储结构621电连接。第二位线结构623设置在接触结构622上，磁性存储结构621通过接触结构622与第二位线结构623实现电连接。第二位线结构623包括沿第二方向延伸且在第一方向上间隔设置的多个第二位线。相邻的磁性存储结构621之间还设置有第一支撑结构6211，相邻的接触结构622之间还设置有第二支撑结构6222。
本实施例中，上电极613与第二位线结构623可以同层设置，上电极613与第二位线结构623可以同层设置，上电极613与第二位线结构623在垂直于衬底10表面的方向上高度相同，且在平行于衬底10表面的截面内形状相同，以便上电极613与第二位线结构623可以同步形成，进而简化半导体结构的工艺制程。
如图1所示，本实施例的磁性存储结构621为磁隧道结(Magnetic Tunneling Junction，MTJ)，包括参考层、磁隧穿势垒层以及自由层，参考层设置在对应的第二接触垫42上，磁隧穿势垒层位于参考层和自由层之间，也即，本实施例中，磁性存储结构621由靠近衬底10的方向向远离衬底10的方向依次为参考层、磁隧穿势垒层以及自由层。值得说明的是，在另一种实施例的磁性存储结构621中，由靠近衬底10的方向向远离衬底10的方向依次为自由层、磁隧穿势垒层以及参考层。在一种具体的实现方式中，自由层和参考层的材质可以包括钴铁硼(CoFeB)，磁隧穿势垒层的材质可以为氧化镁(MgO)。
下面简要描述磁性存储结构621的原理：磁性存储结构621依靠量子隧穿效应使得电子通过磁隧穿势垒层，极化电子的隧穿概率和参考层与自由层的相对磁化方向有关。参考层的磁化方向保持不变，当参考层与自由层磁化方向相同时，极化电子的隧穿概率较高，此时，磁性存储结构621表现为低电阻状态；当参考层与自由层磁化方向相反时，极化电子的隧穿概率比较低，此时，磁性存储结构621表现为高电阻状态。利用磁性存储结构621的低电阻状态和高电阻状态来表示逻辑状态“1”和“0”，从而实现数据的存储。
本申请实施例还提供一种半导体结构的制作方法，用于制作上述实施例中的半导 体结构，请参照图3，其步骤包括：
步骤S101、提供衬底，衬底包括第一阵列区和第二阵列区。
如图2所示，衬底10上设置有外围区13和与外围区13邻接的阵列区，外围与位于图示位置中的衬底10的左部，阵列区位于图示位置中衬底10的右部，且外围区13可以设置在阵列区的外围。其中，阵列区包括第一阵列区11和第二阵列区12，继续参照图2，第一阵列区11位于衬底10中阵列区的左部，第二阵列区12设置在第一阵列区11的外围。
本实施例中，在提供衬底10以后，还包括：
步骤S102、在第一阵列区上形成多个呈阵列排布的第一存储结构构成的第一存储阵列，在第二阵列区上形成多个呈阵列排布的第二存储结构构成的第二存储阵列；第一存储阵列和第二存储阵列同步形成。
值得说明的是，本申请实施例通过将第一存储结构中的膜层结构与第二存储结构中同一膜层的膜层结构同步形成，使得第一存储阵列和第二存储阵列同步形成。本实施例中，第一存储阵列中第一存储结构的存储原理与第二存储阵列中第二存储结构的存储原理不同，第一存储结构例如可以具有动态随机存储器的存储单元，第二存储结构例如可以具有磁性随机访问存储器的存储单元。
本实施例提供一种半导体结构的制作方法，包括：提供衬底10，衬底10包括第一阵列区11和第二阵列区12；在第一阵列区11上形成多个呈阵列排布的第一存储结构构成的第一存储阵列，在第二阵列区12上形成多个呈阵列排布的第二存储结构构成的第二存储阵列；第一存储阵列和第二存储阵列同步形成。相比于相关技术中，分布形成第一存储结构和第二存储结构，将第一存储结构和第二存储结构在衬底10上同步形成，有利于简化工艺制程，提高生产效率。
本实施例中，参照图4、图5以及图6，第一存储结构包括第一位线结构21、第一晶体管结构和电容结构，第一位线结构21位于第一晶体管下方，电容结构设置在对应的第一晶体管上；第二存储结构包括源极线结构22、第二位线结构623和第二晶体管结构，源极线结构22位于第二晶体管结构下方，第二位线结构623位于第二晶体管结构上方。第一存储阵列和第二存储阵列同步形成的步骤可以包括：在第一阵列区11和第二阵列区12上同步形成第一位线结构21和源极线结构22。
在一种具体的实施方式中，可以通过沉积的工艺在衬底10的第一阵列区11和第二阵列区12上同时形成第一隔离结构211和第二隔离结构221，第一隔离结构211和第二隔离结构221用于限定为第一位线结构21和源极线结构22。然后再通过沉积的工艺在相邻的第一隔离结构211之间和相邻的第二隔离结构221之间同时形成第一位线结构21和源极线结构22。图示位置中平行于衬底10的方向为第一方向，图示位置中平行于衬底10且垂直于第一方向的方向为第二方向。第一位线结构21包括沿第一方向延伸且在第二方向上间隔设置的多个第一位线，源极线结构22包括沿第一方向延伸且在第二方向上间隔设置的多个源极线。进一步的，为保证第一位线结构21和源极线结构22能够同时沉积形成，第一位线结构21和源极线结构22的材质相同。
本实施例中，第一晶体管结构还可以包括多个第一有源柱311，第二晶体管结构还可以包括多个第二有源柱312；第一有源柱311的延伸方向与衬底10表面垂直，第 一有源柱311在衬底10上的投影与第一位线在衬底10上的投影至少部分重合；第二有源柱312的延伸方向与衬底10表面垂直，第二有源柱312在衬底10上的投影与源极线在衬底10上的投影至少部分重合。
本实施例中，在第一阵列区11和第二阵列区12上同步形成第一位线结构21和源极线结构22以后，在第一位线结构21和源极线结构22上同步形成第一有源柱311与第二有源柱312。
在一种具体的实施方式中，可以通过沉积的工艺在第一位线结构21和源极线结构22上同步形成第一初始有源柱和第二初始有源柱，为使第一初始有源柱与第二初始有源柱能够同步形成，第一初始有源柱和第二初始有源柱的材质相同。在形成第一初始有源柱和第二初始有源柱以后，可以通过三次离子注入技术同时形成第一有源柱311和第二有源柱312。例如，首先，可以控制离子注入技术中离子注入能量和注入掺杂离子的类型，以在第一初始有源柱和第二初始有源柱的底部形成漏区，然后，再控制离子注入技术中离子注入能量和注入掺杂离子的类型，以在第一初始有源柱和第二初始有源柱的中部形成沟道区，最后，再控制离子注入技术中离子注入能量和注入掺杂离子的类型，以在第一初始有源柱和第二初始有源柱的顶部形成源区，其中，漏区的掺杂离子的类型可以与源区的掺杂离子的类型相同，比如，掺杂离子可以包括N型离子；沟道区的掺杂离子与漏区的掺杂离子的类型不同，比如，掺杂离子可以包括P型离子。
本实施例中，第一晶体管结构还包括多条第一字线321，第二晶体管结构还包括多条第二字线322；多条第一字线321沿第二方向延伸且在第一方向上间隔设置，第一字线321环绕第一有源柱311中间侧壁设置；多条第二字线322沿第二方向延伸且在第一方向上间隔设置，第二字线322环绕第二有源柱312中间侧壁设置。
本实施例中，在第一位线结构21和源极线结构22上同步形成第一有源柱311与第二有源柱312以后，在第一位线结构21和源极线结构22上同步形成第一字线321与第二字线322。
在一种具体的实施方式中，相邻的第一有源柱311之间具体第一填充区313，相邻的第二有源柱312之间具有第二填充区323，在第一填充区313和第二填充区323同时填充第一绝缘材料和第二绝缘材料，直至第一绝缘材料和第二绝缘材料覆盖第一有源柱311和第二有源柱312的源区。在第一绝缘材料和第二绝缘材料上同时形成第一导电层和第二导电层，并使第一导电层和第二导电层覆盖第一有源柱311和第二有源柱312的沟道区。去除部分第一导电层和第二导电层以同时形成第一字线321和第二字线322。在形成第一字线321和第二字线322以后，继续向第一填充区313和第二填充区323内填充第一绝缘材料和第二绝缘材料，以使第一填充区313内的第一绝缘材料形成第一绝缘结构314，第二填充区323内的第二绝缘材料形成第二绝缘结构324。值得说明的是，为使第一绝缘结构314和第二绝缘结构324同时形成，第一绝缘材料和第二绝缘材料的材质相同，为使第一字线321和第二字线322同时形成，第一导电层和第二导电层的材质相同。
本实施例，参照图7，第一存储结构还包括设置在对应的第一有源柱311上的第一接触垫41，第二存储结构还包括设置在对应的第二有源柱312上的第二接触垫42。
本实施例中，在第一位线结构21和源极线结构22上同步形成第一字线321与第二字线322以后，还包括：在第一有源柱311和第二有源柱312上同步形成第一接触垫41和第二接触垫42。
在一种具体的实施方式中，可以通过沉积的工艺在在第一有源柱311和第二有源柱312上同时形成第一接触垫41和第二接触垫42，进一步地，也可以通过沉积的工艺在相邻的第一接触垫41之间和相邻的第二接触垫42之间同时形成第一绝缘块411和第二绝缘块421。进一步的，为保证第一接触垫41和第二接触垫42能够同时沉积形成，第一接触垫41和第二接触垫42的材质相同，为保证第一绝缘块411和第二绝缘块421能够同时沉积形成，第一绝缘块411和第二绝缘块421的材质相同。
本实施例中，参照图8，在第一有源柱311和第二有源柱312上同步形成第一接触垫41和第二接触垫42以后，还包括：在第一接触垫41和第二接触垫42上形成介质层50，介质层50上具有多个电容孔51，电容孔51在衬底10的投影位于第一阵列区11，且与第一接触垫41在衬底10的投影至少部分重叠。通过设置介质层50的电容孔51，可以限定出电容结构，同时介质层50还能支撑电容结构，防止倒塌。介质层50遮蔽第二阵列区12，还能够防止第二接触垫42上形成其他膜层结构。
本实施例中，参照图9，在形成介质层50以后，还包括：在电容孔51内形成多个部分电容结构。电容结构可以包括下电极611、上电极613及电容介质层612，电容介质层612位于下电极611和上电极613之间。如图所示，部分电容结构包括下电极611和电容介质层612，下电极611覆盖在电容孔51的孔壁，电容介质层612覆盖在下电极611表面且充满电容孔51。当然，电容结构还可以包括相关技术中的其他结构，本申请实施例不进行具体限定。
本实施例中，参照图10，在电容孔51内形成多个电容结构以后，还包括：去除部分介质层50，以暴露第二接触垫42，进而便于后续在第二接触垫42上形成其他膜层结构。
参照图11和图12，在第二接触垫42上依次形成多个磁性存储结构621和接触结构622。本实施例的磁性存储结构621为磁隧道结(Magnetic Tunneling Junction，MTJ)，包括参考层、磁隧穿势垒层以及自由层，其具体结构以及工作原理在此不再赘述。接触结构622在衬底10上的投影与磁性存储结构621在衬底10上的投影至少部分重合，以便接触结构622与磁性存储结构621电连接。在一种具体的实现方式中，可以通过沉积的工艺形成磁性存储结构621和接触结构622。参照图13，相邻的磁性存储结构621之间还设置有第一支撑结构6211，相邻的接触结构622之间还设置有第二支撑结构6222。
本实施例中，参照图13，在第二接触垫42上依次形成多个磁性存储结构621和接触结构622以后，还包括：在电容介质层612和接触结构622上同步形成上电极613与第二位线结构623。
第二位线结构623包括位于接触结构622上方的多个第二位线，多个第二位线沿第二方向延伸且在第一方向上间隔设置；上电极613覆盖在电容介质层612上。进一步的，为保证上电极613与第二位线结构623能够同时沉积形成，上电极613与第二位线结构623的材质相同。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体结构，包括：衬底，所述衬底包括第一阵列区和第二阵列区；
    所述第一阵列区上设有多个第一存储结构构成的第一存储阵列；所述第二阵列区上设有多个第二存储结构构成的第二存储阵列。
  2. 根据权利要求1所述的半导体结构，其中，所述第一存储结构包括第一位线结构、第一晶体管结构和电容结构，所述第一位线结构位于所述第一晶体管下方，所述电容结构设置在对应的所述第一晶体管结构上；
    所述第二存储结构包括源极线结构、第二位线结构和第二晶体管结构，所述源极线结构位于所述第二晶体管结构下方，所述第二位线结构位于所述第二晶体管结构上方；
    所述第一位线结构和所述源极线结构同层设置。
  3. 根据权利要求2所述的半导体结构，其中，所述第一位线结构包括沿第一方向延伸且在第二方向上间隔设置的多个第一位线，所述第一晶体管结构包括设置在所述第一位线上的多个第一有源柱，所述第一有源柱的延伸方向与所述衬底表面垂直，所述第一有源柱在所述衬底上的投影与所述第一位线在所述衬底上的投影至少部分重合，所述第一方向与所述第二方向垂直；
    所述源极线结构包括沿第一方向延伸且在第二方向上间隔设置的多个源极线，所述第二晶体管结构包括设置在所述源极线上的多个第二有源柱，所述第二有源柱的延伸方向与所述衬底表面垂直，所述第二有源柱在所述衬底上的投影与所述源极线在所述衬底上的投影至少部分重合；
    所述第一有源柱与所述第二有源柱同层设置。
  4. 根据权利要求3所述的半导体结构，其中，所述第一晶体管结构包括沿第二方向延伸且在第一方向上间隔设置的多条第一字线，所述第一字线环绕所述第一有源柱中间侧壁设置；
    所述第二晶体管结构包括沿第二方向延伸且在第一方向上间隔设置的多条第二字线，所述第二字线环绕所述第二有源柱中间侧壁设置；
    所述第一字线与所述第二字线同层设置。
  5. 根据权利要求4所述的半导体结构，其中，所述第一存储结构还包括第一接触垫，所述第一接触垫设置在对应的所述第一有源柱上；
    所述第二存储结构还包括第二接触垫，所述第二接触垫设置在对应的所述第二有源柱上；
    所述第一接触垫与所述第二接触垫同层设置。
  6. 根据权利要求2所述的半导体结构，其中，所述电容结构包括下电极、上电极及电容介质层，所述电容介质层位于所述下电极和所述上电极之间，所述上电极与所述第二位线结构同层设置。
  7. 根据权利要求5所述的半导体结构，其中，所述第二存储结构包括接触结构、磁性存储结构，所述磁性存储结构设置在对应的所述第二接触垫上；所述磁性存储结构通过所述接触结构与所述第二位线实现电连接。
  8. 根据权利要求7所述的半导体结构，其中，所述磁性存储结构包括参考层、磁 隧穿势垒层以及自由层，所述参考层设置在对应的所述第二接触垫上，所述磁隧穿势垒层位于所述参考层和所述自由层之间。
  9. 根据权利要求6所述的半导体结构，其中，所述第二位线结构包括沿第二方向延伸且在第一方向上间隔设置的多个第二位线。
  10. 一种半导体结构的制作方法，包括：
    提供衬底，所述衬底包括第一阵列区和第二阵列区；
    在所述第一阵列区上形成多个呈阵列排布的第一存储结构构成的第一存储阵列，在所述第二阵列区上形成多个呈阵列排布的第二存储结构构成的第二存储阵列；所述第一存储阵列和所述第二存储阵列同步形成。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述第一存储结构包括第一位线结构、第一晶体管结构和电容结构，所述第二存储结构包括源极线结构、第二位线结构和第二晶体管结构；
    在所述第一阵列区和所述第二阵列区上同步形成所述第一位线结构和所述源极线结构；
    所述第一位线结构位于所述第一晶体管下方，所述电容结构设置在对应的所述第一晶体管上；
    所述源极线结构位于所述第二晶体管结构下方，所述第二位线结构位于所述第二晶体管结构上方。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述第一晶体管结构包括多个第一有源柱，所述第二晶体管结构包括多个第二有源柱；
    同步形成所述第一有源柱与所述第二有源柱；
    所述第一有源柱的延伸方向与所述衬底表面垂直，所述第一有源柱在所述衬底上的投影与所述第一位线在所述衬底上的投影至少部分重合；所述第二有源柱的延伸方向与所述衬底表面垂直，所述第二有源柱在所述衬底上的投影与所述源极线在所述衬底上的投影至少部分重合。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，所述第一晶体管结构还包括多条第一字线，所述第二晶体管结构还包括多条第二字线；
    在所述第一位线结构和所述源极线结构上同步形成第一字线与第二字线；
    多条所述第一字线沿第二方向延伸且在第一方向上间隔设置，所述第一字线环绕所述第一有源柱中间侧壁设置；多条所述第二字线沿第二方向延伸且在第一方向上间隔设置，所述第二字线环绕所述第二有源柱中间侧壁设置。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述第一存储结构还包括设置在对应的所述第一有源柱上的第一接触垫，所述第二存储结构还包括设置在对应的所述第二有源柱上的第二接触垫；
    在所述第一有源柱和所述第二有源柱上同步形成所述第一接触垫和所述第二接触垫。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，在所述第一接触垫和所述第二接触垫上形成介质层，所述介质层上具有多个电容孔，所述电容孔在所述衬底的投影位于所述第一阵列区，且与所述第一接触垫在所述衬底的投影至少部分重叠；
    在所述电容孔内形成多个部分电容结构；
    去除部分所述介质层，以暴露所述第二接触垫；
    在所述第二接触垫上依次形成多个磁性存储结构和接触结构。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，
    所述电容结构包括下电极、上电极及电容介质层，所述电容介质层位于所述下电极和所述上电极之间，所述第二位线结构包括位于所述接触结构上方的多个第二位线，多个第二位线沿第二方向延伸且在第一方向上间隔设置；
    在所述电容介质层和所述接触结构上同步形成所述上电极与所述第二位线结构。
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