WO2023097512A1 - Content addressable memory and related method thereof, and electronic device - Google Patents

Abstract

Embodiments of the present application relate to the technical field of storage, and provide a content addressable memory and a related method thereof, and an electronic device, for use in improving the storage density and reducing the area occupied by the memory. Storage units of the content addressable memory comprise m rows and n columns of storage units, m and n are integers greater than or equal to 1, and each storage unit comprises a transistor, a first capacitor and a second capacitor. The control end of the transistor is connected to a first polar plate of the first capacitor and a first polar plate of the second capacitor; a first end of the transistor is connected to a word line, and a second end of the transistor is connected to a matching line; a second polar plate of the first capacitor is connected to a first bit line, and a second polar plate of the second capacitor is connected to a second bit line.

Description

Content-addressable memory and related method and electronic device technical field

The present application relates to the field of storage technologies, and in particular to a content addressable memory, a related method and electronic equipment.

Background technique

Content addressable memory (content addressable memory, CAM) is an important physical device of network equipment. A typical CAM is tri-state content addressable memory (ternary content addressable memory, TCAM), which is mainly used to quickly find access control list (access control list, ACL), routing table and other entries. The traditional TCAM based on static random-access memory (SRAM), each storage unit (memory cell, MC) is composed of 16 transistors (transistor, T), which has the disadvantages of large size and low storage density. .

Contents of the invention

Embodiments of the present application provide a content addressable memory, a related method, and an electronic device, which are used to improve existing problems such as large size and low storage density of the TCAM.

In a first aspect, a content-addressable memory is provided. The content-addressable memory includes m rows and n columns of memory cells, m and n are integers greater than or equal to 1, and each memory cell includes a transistor, a first capacitor, and a second capacitor; Wherein, the control end of the transistor is connected with the first plate of the first capacitor and the first plate of the second capacitor, the first end of the transistor is connected with the word line, the second end of the transistor is connected with the match line, and the second end of the first capacitor is connected with the matching line. The polar plate is connected to the first bit line, and the second polar plate of the second capacitor is connected to the second bit line. When writing data, the first bit line can be used to configure the polarization state of the first capacitor, the second bit line can be used to configure the polarization state of the second capacitor, and the different polarization states of the first capacitor and the second capacitor It can be used to indicate the storage of different data, such as "0" and "1", and the different data combinations stored in the first capacitor and the second capacitor can be used to indicate the "0" state and "1" of the storage unit of the content addressable memory state and fuzzy state; when performing an addressing operation, the word line is set to a first preset voltage, and the match line is precharged to a second preset voltage different from the first preset voltage, according to the keyword (key) value Different from outputting the search signal to the first bit line or the second bit line, when the memory cell stores different states, under the action of the search signal, the transistor will show different states, for example, if the state stored in the memory cell is the same as the keyword Matching or fuzzy matching, the transistor is in the off state, a small current can be read between the matching line and the word line, and the matching line outputs the second preset voltage; if the state stored in the memory unit does not match the keyword, the transistor In the conduction state, a large current can be read between the match line and the word line, and the match line outputs the first preset voltage. According to this characteristic, the addressing operation can be completed. The content addressable memory provided by this application The function of the TCAM can be realized by using two capacitors and one transistor. Compared with the traditional TCAM, the structure of the device is simplified, the occupied area is reduced, and the storage density can be increased.

In a possible implementation, the memory cells in the same row are connected to the same word line, the memory cells in the same row are connected to the same match line, and the data stored in the memory cells in the same row can form a table entry. When the When the data stored in all the storage units of the row matches their corresponding key values, the entry matches the key value. When the data stored in at least one storage unit in the row does not match the corresponding key value, the entry matches the key value. The key value does not match.

In a possible implementation manner, the memory cells in the same column are connected to the same first bit line, and the memory cells in the same column are connected to the same second bit line. The first bit line and the second bit line can be used to write data to the memory cell, and can also be used to apply a search signal to the memory cell, and the memory cells in the same column are connected to the same first bit line and the same second bit line , when performing an addressing operation, the first bit line or the second bit line can simultaneously apply a search signal to all the memory cells in the column, and can address all the memory cells in the column at the same time.

In a possible implementation manner, the content addressable memory further includes multiple first control tubes and multiple second control tubes, each storage unit is correspondingly provided with a first control tube and a second control tube, and the first control tube The control end of the tube and the control end of the second control tube are connected to the control line; the first end of the first control tube is connected to the first bit line, and the second end of the first control tube is connected to the second plate of the first capacitor; the second The first end of the control transistor is connected to the second bit line, the second end of the second control transistor is connected to the second plate of the second capacitor, and the first control transistor is arranged between each memory cell and the first bit line. A second control transistor is arranged between a memory cell and the second bit line. When the first control transistor and the second control transistor are turned on, the memory cell communicates with the first bit line and the second bit line. When the second control tube is turned off, the storage unit is disconnected from the first bit line and the second bit line, and precise read and write control can be realized through the first control tube and the second control tube, and the data is written to the target storage cell At this time, the write voltage is output through the first bit line and the second bit line, and the first control transistor and the second control transistor corresponding to the target storage unit are controlled to conduct, so that data can be written into the target storage unit, and other storage units are controlled to correspond to The first control transistor and the second control transistor are turned off, and the voltages on the first bit line and the second bit line will not rewrite data stored in other memory cells.

In a possible implementation manner, the first capacitor and the second capacitor are ferroelectric capacitors, and using the ferroelectric capacitors to store data can make the content addressable memory have non-volatile characteristics.

In a possible implementation manner, the transistor is a transistor with a vertical channel structure, which can reduce the area occupied by the transistor and is beneficial to increase storage density.

In a second aspect, there is provided a data processing method for a content addressable memory as provided in the first aspect, the method includes: setting the word line to a first preset voltage, and precharging the match line to a second preset voltage, wherein the second The preset voltage is different from the first preset voltage; output a search signal to the first bit line or the second bit line according to the target data; if it is detected that the voltage of the match line of the target memory cell remains at the second preset voltage, then It is determined that the data stored in the target storage unit matches the target data.

In a possible implementation manner, the first capacitor and the second capacitor are ferroelectric capacitors, and when the polarization state of the first capacitor is configured so that the second plate faces the first plate, the polarization state of the second capacitor is configured When the first polar plate is configured to face the second polar plate, the storage unit of the content addressable memory stores the first logic value; when the polarization state of the first capacitor is configured so that the second polar plate faces the first polar plate, the second capacitor When the polarization state of the first capacitor is configured such that the second polar plate faces the first polar plate, the first fuzzy state is stored; when the polarization state of the first capacitor is configured such that the first polar plate faces the second polar plate, the polar When the polarization state is configured so that the second plate faces the first plate, store the second logic value; when the polarization state of the first capacitor is configured as the first plate faces the second plate, the polarization state of the second capacitor It is configured that when the first polar plate faces the second polar plate, the second fuzzy state is stored, and outputting the search signal through the first bit line or the second bit line according to the target data includes: when the target data is a first logic value, the first The bit line is suspended, and the search signal is output through the second bit line; when the target data is the second logic value, the search signal is output through the second bit line, and the second bit line is suspended.

In a possible implementation manner, the memory cell is connected to the first bit line through the first control transistor, and the memory cell is connected to the second bit line through the second control transistor. Before the line outputs the search signal, the method further includes: controlling the first control transistor and the second control transistor to be turned on.

In a third aspect, there is provided a method for writing data into a content addressable memory as provided in the first aspect, comprising: outputting a first write voltage to a first bit line, outputting a second write voltage to a second bit line, and Writing data to be written into the memory cell, wherein the first write voltage is used to configure the polarization state of the first capacitor, and the second write voltage is used to configure the polarization state of the second capacitor; when the polarization state of the first capacitor The state is configured such that the second pole plate faces the first pole plate, the polarization state of the second capacitor is configured such that the first pole plate faces the second pole plate, and the first logic value is written into the storage unit; when the pole of the first capacitor The polarization state is configured such that the second pole plate faces the first pole plate, the polarization state of the second capacitor is configured such that the second pole plate faces the first pole plate, and the first fuzzy state is written into the memory cell; when the first capacitor The polarization state is configured such that the first pole plate faces the second pole plate, the polarization state of the second capacitor is configured such that the second pole plate faces the first pole plate, and the second logic value is written into the storage unit; when the first capacitor The polarization state of the capacitor is configured such that the first pole plate faces the second pole plate, the polarization state of the second capacitor is configured such that the first pole plate faces the second pole plate, and the second fuzzy state is written into the memory cell.

In a possible implementation manner, the content addressable memory further includes a first control pipe and a second control pipe, the control end of the first control pipe and the control end of the second control pipe are connected to the control line; the second control pipe of the first control pipe One end is connected to the first bit line, the second end of the first control tube is connected to the second plate of the first capacitor; the first end of the second control tube is connected to the second bit line, and the second end of the second control tube is connected to the second The second plate of the two capacitors outputs the first writing voltage to the first bit line, and outputs the second writing voltage to the second bit line, so as to write the data to be written to the memory cell, the data writing method further includes: Control the conduction of the first control tube and the second control tube.

In a fourth aspect, there is provided a method for manufacturing a content addressable memory as provided in the first aspect, comprising: forming a first transistor on a substrate, the transistor including a control terminal, a first terminal and a second terminal; forming a second transistor on the transistor A capacitor and a second capacitor, the first capacitor includes a first plate and a second plate, the second capacitor includes a first plate and a second plate, the first plate of the first capacitor, the first plate of the second capacitor The pole plate is electrically connected with the control terminal of the transistor.

In a possible implementation manner, forming the transistor on the substrate includes: forming a first terminal of the transistor on the substrate; forming a second terminal and a control terminal on a side of the first terminal of the transistor away from the substrate, the The second end has a first side perpendicular to the substrate, and the control end is located on a side facing the first side.

In a possible implementation manner, when forming the first capacitor and the second capacitor on the transistor, the steps include:

A metal layer is formed on the transistor, and the metal layer is electrically connected to the control terminal. The metal layer includes the first plate of the first capacitor and the first plate of the second capacitor, and the first plate of the first capacitor is far away from the substrate. Form the first ferroelectric material layer and the second pole plate of the first capacitor in sequence; form the second ferroelectric material layer and the second pole of the second capacitor in sequence on the side of the first plate of the second capacitor away from the substrate plate.

According to a fifth aspect, an electronic device is provided, and the electronic device includes a circuit board and a content-addressable memory connected to the circuit board, where the content-addressable memory is the content-addressable memory as provided in the first aspect.

Description of drawings

Fig. 1 is the hysteresis loop schematic diagram of ferroelectric material;

2 is a schematic circuit diagram of a memory cell of a TCAM in the prior art;

FIG. 3 is a schematic circuit diagram of a storage unit in a content addressable memory provided by an embodiment of the present application;

FIG. 4a is a schematic diagram of a state of a storage unit provided in an embodiment of the present application;

FIG. 4b is a schematic diagram of another state of the storage unit provided by the embodiment of the present application;

Fig. 4c is a schematic diagram of another state of the storage unit provided by the embodiment of the present application;

Fig. 4d is a schematic diagram of another state of the storage unit provided by the embodiment of the present application;

FIG. 5a is a schematic diagram of the state of the addressing operation in which the storage unit stores the first logical value provided by the embodiment of the present application;

FIG. 5b is a schematic diagram of the state of the addressing operation in which the storage unit stores the second logical value provided by the embodiment of the present application;

FIG. 5c is a schematic diagram of the state of the addressing operation in which the memory unit stores a fuzzy state according to the embodiment of the present application;

Fig. 5d is a state schematic diagram of an addressing operation in which a memory unit stores another fuzzy state according to an embodiment of the present application;

FIG. 6 is a schematic circuit diagram of another storage unit in the content addressable memory provided by the embodiment of the present application;

FIG. 7 is a circuit diagram of a memory array formed by a plurality of memory cells provided by an embodiment of the present application;

FIG. 8 is a flow chart of a data writing method provided by an embodiment of the present application;

FIG. 9 is a schematic circuit diagram of another memory array provided by an embodiment of the present application;

FIG. 10 is a block diagram of a data processing method provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of addressing operations of the data processing method provided by the embodiment of the present application;

Figure 12 is a schematic diagram of addressing operations of the data processing method provided in another embodiment of the present application;

FIG. 13 is a functional block diagram of a data processing device provided by an embodiment of the present application;

FIG. 14 is a flowchart of a method for fabricating a content-addressable memory provided by an embodiment of the present application;

15a to 15n are cross-sectional views of the corresponding process structure after each step is completed in a method for manufacturing a content addressable memory provided by the embodiment of the present application;

FIG. 16 is a functional block diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The following describes the embodiments provided by the present application with reference to the accompanying drawings.

In the embodiment of the present application, the transistor can be a metal-oxide-semiconductor field effect transistor (MOSFET), and the transistor is divided into an N (negative, negative) type transistor and a P (positive, positive) transistor. There are two types of transistors. The transistor includes a source (source), a drain (drain) and a gate (gate), and the transistor can be turned on or off by controlling the level input to the gate of the transistor. When the transistor is turned on, the source and drain are turned on to generate a conduction current, and when the gate level of the transistor is different, the magnitude of the conduction current generated between the source and the drain is also different; the transistor is in When turned off, the source and drain do not conduct and no current flows. In the embodiments of the present application, the gate of the transistor is also called the control terminal, the source is called the first terminal, and the drain is called the second terminal; or, the gate is called the control terminal, and the drain is called the second terminal. is called the first terminal, and the source is called the second terminal. In addition, the N-type transistor is turned on when the level of the control terminal is high, the first terminal and the second terminal are turned on, and a conduction current is generated between the first terminal and the second terminal; the level of the N-type transistor at the control terminal is When it is low level, it is turned off, the first terminal and the second terminal are not conducted, and no current is generated. The P-type transistor is turned on when the level of the control terminal is low, and the first and second terminals are turned on to generate a conduction current; the P-type transistor is turned off when the level of the control terminal is high, and the first and second terminals are turned on. The two terminals are not conducting, and no current is generated. In order to describe the embodiments of the present application in detail, the transistors in the embodiments of the present application are all illustrated as N-type transistors, but this is not a limitation to the solutions of the present application.

Ferroelectric capacitors use the characteristics that ferroelectric materials can undergo spontaneous polarization, and the polarization state can be reoriented with the action of an external electric field for data storage.

As shown in FIG. 1 , FIG. 1 shows a schematic diagram of a hysteresis loop of a ferroelectric material. Applying different electric fields to ferroelectric materials can cause them to be in different polarization states (also called polarization directions), and can maintain this polarization state after the electric field is withdrawn. For example, referring to Fig. 1, when an electric field is applied When it comes to a ferroelectric crystal, the central atom stays in the low-energy state position I along the electric field. On the contrary, when the electric field reversal is applied to the same ferroelectric crystal, the central atom moves in the crystal along the direction of the electric field and stays in another state. Low energy state position II. A large number of central atoms move and couple in the unit cell to form a ferroelectric domain. The ferroelectric domain forms a flip charge under the action of an electric field. When there are more flip charges, it can be used to indicate that the data stored in the ferroelectric material is "1". Used to indicate that the stored data is "0". In another case, it can also be used to indicate that the stored data is "0" when the flipped charge is large, and it can be used to indicate that the stored data is "1" when the flipped charge is small. In order to ensure that the applied electric field can reverse the polarization state of the ferroelectric material, the above-mentioned electric field strength should be greater than the coercive field strength Ec of the ferroelectric material. required reverse electric field strength. For example, from position I in Figure 1 to position II in Figure 1, it is necessary to apply an electric field greater than -Ec to the ferroelectric material, and from position II in Figure 1 to position I in Figure 1, it is necessary to apply an electric field greater than +Ec to the ferroelectric material the electric field.

Taking ferroelectric capacitors as an example, ferroelectric capacitors refer to capacitors that use ferroelectric materials as the medium. Ferroelectric capacitors include the first plate, the second plate, and the ferroelectric material between the first plate and the second plate. Layer, since ferroelectric materials have the characteristics of spontaneous polarization, and the polarization direction can be changed by an external electric field, so ferroelectric capacitors made of ferroelectric materials can have different polarization states, and different polarization states can be used for Indicates that different data is stored, such as "0" or "1". Under the action of an external electric field, the polarization state of the ferroelectric capacitor can change. For example, when the ferroelectric capacitor is in the first polarization state, for example, the polarization state is that the first plate is facing the second plate. Under the action of the electric field There are fewer flipping charges; when the ferroelectric capacitor is in the second polarization state, for example, the polarization state is that the second polar plate is facing the first polar plate, more flipping charges are generated under the action of the electric field; or it can also be in the first In the polarized state, there are more flipped charges under the action of the electric field, and in the second polarized state, less flipped charges are generated under the action of the electric field. Different polarization states can be used to indicate that the ferroelectric capacitor stores different data, for example, when the ferroelectric capacitor is in the first polarization state, it is used to indicate that the stored data is "1", when the ferroelectric capacitor is in the second polarization state is used to indicate that the stored data is "0". In another case, the data used to indicate storage is "0" when the ferroelectric capacitor is in the first polarization state, and the data used to indicate storage is "1" when the ferroelectric capacitor is in the second polarization state .

CAM is a content-addressable memory. It is a special storage array. Its working mechanism is to automatically compare an input data item with all data items stored in the CAM at the same time, and distinguish the input data item from the data stored in the CAM. Whether the data item matches, and output the matching information corresponding to the data item. CAM is an important component of network equipment such as switches and routers.

A typical CAM is TCAM, which is developed from CAM. There are only two states of each bit in a general CAM memory, "0" or "1", while each bit in TCAM has three states, except for "0" and "1", there is a third state : The "don't care" state is also known as the fuzzy state, so it is called "three states". The third state enables both exact match search and fuzzy match search.

The CAM can work with the network processor (net processor, NP) to complete functions such as data packet classification and route lookup, and act as a search engine unit. Among them, the network processor is used to extract information from the message, and organize it into a data format consistent with the table to be looked up in the CAM, which is called a keyword (key); in the search phase, the key is sent to all tables in the TCAM and the table to be looked up Items are compared to find memory addresses that match the data.

The traditional TCAM solution is mainly implemented based on the Static Random-Access Memory (SRAM) storage unit, as shown in Figure 2, each TCAM storage unit includes 4 transistors M1, M2, M3, M4 and 2 SRAMs Memory cells D0 and D1. Wherein, the second end of the transistor M1 is connected to the first end of the transistor M3, and the second end of the transistor M2 is connected to the first end of the transistor M4; the first end of the transistor M1 and the first end of the transistor M2 are grounded, and the first end of the transistor M3 is connected to the ground. The second terminal, the second terminal of the transistor M4 is connected to the match line (match line, ML); the control terminal of the transistor M1 is connected to the first search line (search line, SL), and the control terminal of the transistor M2 is connected to the second search line SL! , the control terminal of the transistor M3 is connected to the SRAM storage unit D0; the control terminal of the transistor M4 is connected to the SRAM storage unit D1.

Exemplarily, search line SL, search line SL! It is used to output the search signal, and the match line ML is used to output the signal indicating whether the data stored in the storage unit matches the key. For example, a high level signal is preset to indicate that the data stored in the storage unit matches the key. When performing an addressing operation , Find Line SL, Find Line SL! Output the search signal to address the storage unit, that is, search for the storage unit whose stored data matches the key value. If the matching line ML connected to the storage unit outputs a high level signal, it indicates that the data stored in the storage unit matches the key. The matching line connected to the storage unit outputs a low-level signal, indicating that the data stored in the storage unit does not match the key. As shown in FIG. 2 , taking the SRAM storage unit D0 as an example, it includes six transistors M5 - M10 . The first end of the transistor M5 and the first end of the transistor M6 are connected to the first power supply VDD, the second end of the transistor M5 is connected to the first end of the transistor M7, the second end of the transistor M6 is connected to the first end of the transistor M8, and the second end of the transistor M7 is connected to the first end of the transistor M7. The second terminal, the second terminal of the transistor M8 is connected to the second power supply VSS, the control terminal of the transistor M9 and the control terminal of the transistor M10 are connected to the word line, the first terminal of the transistor M9 is connected to the first bit line (bit line, BL), the transistor The second terminal of M9 is connected to the second terminal of transistor M5 and also connected to the control terminal of transistor M6; the first terminal of transistor M10 is connected to the second bit line BL! , the second terminal of the transistor M10 is connected to the second terminal of the transistor M6, the second terminal of the transistor M10 is also connected to the control terminal of the transistor M5, and the second terminal of the transistor M6 is connected to the first terminal of the transistor M3. The structure of the SRAM storage unit D1 is the same as that of the SRAM storage unit D0, and will not be described in detail, wherein the first end of the transistor M9 of the SRAM storage unit D1 is connected to the third bit line BR, and the first end of the transistor M10 is connected to the fourth bit line. BR! .

The combination of data stored in two SRAM storage units (D0 and D1) is used to represent the three states of TCAM: "0", "1" and "don't care", where the logic value "0" represents a state , the logical value "1" represents a state, and "don't care" represents a state. In the following examples, "X" represents "don't care", which is called the fuzzy state "X". Generally, different data combinations stored in D0 and D1 represent different states, as shown in Table 1.

Table 1

The combination of D0 storing "0" and D1 storing "1" indicates the state of TCAM "0", which matches the key value "0"; the combination of D0 storing "1" and D1 storing "0" indicates the state of TCAM "1", Matches the key value "1"; when D0 and D1 store the same logic value, it indicates the fuzzy state of TCAM, and the combination of both D0 and D1 storing "0" indicates the first fuzzy state of TCAM, which is called fuzzy "X" type 0 ( hereinafter abbreviated as "X0"), "X0" does not match the key value "1" or "0". In addition, the combination of both D0 and D1 storing "1" represents the second fuzzy state "X" of TCAM, which is called For fuzzy "X" type 1 (abbreviated as "X1" in the following), "X1" matches both key values "0" and "1". This matching state is called fuzzy matching. In some other possible implementations , "X1" can also be called the first fuzzy state, and "X0" can be called the second fuzzy state.

TCAM can search and match according to the key and its stored state or data. If the stored state or data matches the key, it will output a corresponding matching signal through the matching line. This process can be called addressing. Before addressing, first define the corresponding relationship between the key value and the applied voltage of the search line, as shown in Table 2:

Table 2

key	SL voltage	SL! Voltage
0	0	1
1	1	0

In Table 2, an SL voltage of 1 means that a high-level signal is output to the first search line SL, and an SL voltage of 0 means that a signal with a voltage of 0 is output to the first search line SL; SL! A voltage of 1 indicates to the second lookup line SL! Output high level signal, SL! A voltage of 0 means to the second lookup line SL! The output voltage is 0 signal. Combining Figure 2 and Table 2, when the key value is 0, a signal with a voltage of 0 is output to the first search line SL, and a signal with a voltage of 0 is output to the second search line SL! Output a high-level signal; when the key value is 1, output a high-level signal to the first search line SL, and output a high-level signal to the second search line SL! The output voltage is 0 signal. At the same time, it is also necessary to define the data matching protocol of TCAM, as shown in Table 3:

table 3

TCAM status	Key=1	Key=0	matching agreement
0	ML=0	ML=1	Data matching when ML=1
1	ML=1	ML=0	Data matching when ML=1
Fuzzy "X" type 0	ML=0	ML=0	Mismatch
Fuzzy "X" Type 1	ML=1	ML=1	fuzzy match

When the TCAM state is "0", if the key value is 1, the matching line ML output signal voltage is 0, if the key value is 0, the matching line ML outputs a high-level signal, that is, when the key value is 0, the TACM state and key match.

When the TCAM state is "1", if the key value is 1, the matching line ML outputs a high-level signal; if the key value is 0, the matching line ML output signal voltage is 0, that is, when the key value is 1, the TACM state and match.

When the TCAM state is fuzzy "X" type 0, no matter the key value is 1 or 0, the output signal voltage of the matching line ML is 0, and the TCAM state does not match the key.

When the TCAM state is fuzzy "X" type 1, no matter the key value is 1 or 0, the output signal of the matching line ML is a high-level signal, and the TCAM state is fuzzy matched with the key.

For example, referring to FIG. 2 , when addressing starts, the match line ML is precharged to a high level, for example, to VDD.

When the TCAM state is "0", D0 stores "0", the transistor M3 is in the on state, D1 stores "1", and the transistor M4 is in the off state. If the key value is 1, the voltage of the first search line SL is high, the transistor M1 is turned on, the current path formed by the transistor M1 and the transistor M3 grounds the matching line ML, and pulls the voltage of the matching line ML down to 0, at this time The TCAM state does not match the key value; if the key value is 0, the voltage of the first search line SL is 0, turning off the transistor M1, and since the transistor M4 is in the off state, there is no current path to pull down the voltage of the matching line ML, matching Line ML maintains a high level, and the TCAM state matches the key value at this time.

When the TCAM state is "1", D0 stores "1", the transistor M3 is in the off state, D1 stores "0", and the transistor M4 is in the on state. If the key value is 1, the second lookup line SL! The voltage of the TCAM is 0, the transistor M2 is turned off, there is no current path to pull down the voltage of the matching line ML, and the matching line ML remains high, at this time, the state of the TCAM matches the key value; if the key value is 0, the second search line SL ! The voltage of the high level turns on the transistor M2, and the current path formed by the transistor M2 and the transistor M4 pulls down the voltage of the matching line ML to 0, and the state of the TCAM does not match the key value.

When the TCAM state is fuzzy "X" type 0 ("X0"), both D0 and D1 store "0", and both the transistor M3 and the transistor M4 are in the on state. If the key value is 1, the voltage of the first search line SL is high, the transistor M1 is turned on, and the current path formed by the transistor M1 and the transistor M3 pulls down the voltage of the matching line ML to 0, and the state of the TCAM does not match the key value; If the key value is 0, the second lookup line SL! The voltage of the high level turns on the transistor M2, the current path formed by the transistor M2 and the transistor M4 grounds the matching line ML, and pulls the voltage of the matching line ML down to 0, so no matter the key value is 0 or 1, there is always a current The path connects the matching line ML to the ground, so that the voltage of the matching line ML becomes 0, so the key value does not match the data stored in the TCAM.

When the state of TCAM is fuzzy "X" type 1 (X1), both D0 and D1 store "1", transistor M3 and transistor M4 are both in the off state, no matter whether the key value is 0 or 1, no current path can be formed to match The voltage of the line ML is pulled down, and the voltage of the matching line ML is kept at a high level, so the key value fuzzily matches with the data stored in the TCAM.

SRAM-based TCAM has fast address search speed and simple operation, but each TCAM storage unit is composed of 4 transistors and two SRAM storage units, that is, each TCAM storage unit requires 16 transistors, which has the advantages of many devices, large footprint, and storage Disadvantages such as low density.

An embodiment of the present application provides a content-addressable memory, each memory cell (memory cell, MC) of the content-addressable memory includes two capacitors and one transistor, that is, it belongs to a single-transistor double-capacity (2capacitor 1transistor, 2C1T) structure, Please refer to FIG. 3, the storage unit MC includes two capacitors (the first capacitor C1 and the second capacitor C2) and a transistor T, and the control terminal of the transistor T is connected to the first plate of the first capacitor C1 and the second capacitor C2. The first plate is connected, and the connection point is a floating node (FN). The first end of the transistor T is connected to the word line WL, and the second end of the transistor T is connected to the match line ML. Exemplarily, the match line ML is used to output a signal indicating whether the data stored in the memory cell MC matches the key value; the first capacitor The second plate of C1 is connected to the first bit line BL, and the second plate of the second capacitor C2 is connected to the second bit line BL! .

In the storage unit MC of the content addressable memory provided by the embodiment of the present application, the first capacitor C1 and the second capacitor C2 are used to store data. Exemplarily, the first capacitor C1 and the second capacitor C2 may be ferroelectric capacitors, But not limited thereto, other types of capacitors may also be used. Ferroelectric capacitors use ferroelectric materials to have spontaneous polarization, and the polarization state can be maintained after the electric field is removed to store data, and has the characteristics of non-volatility.

Different combinations of data stored in the first capacitor C1 and the second capacitor C2 can be used to indicate different states of the CAM. As shown in Table 4:

Table 4

Wherein, when the first capacitor C1 stores the first logic value and the second capacitor C2 stores the second logic value, it can be used to indicate that the state of the content addressable memory is the first logic value; when the first capacitor C1 stores the second logic value , when the second capacitor C2 stores the first logic value, it can be used to indicate that the state of the content addressable memory is the second logic value; when the first capacitor C1 and the second capacitor C2 both store the first logic value, it can be used to indicate The state of the content-addressable memory is the first fuzzy state. When both the first capacitor C1 and the second capacitor C2 store the second logic value, it can be used to indicate that the state of the content-addressable memory is another fuzzy state, that is, the second fuzzy state. In one case, the first logic value can be "0", correspondingly, the second logic value can be "1", the first fuzzy state is "X0", and the second fuzzy state is "X1"; in another In this case, the first logic value may be "1", and correspondingly, the second logic value may be "0", the first fuzzy state is "X1", and the second fuzzy state is "X0".

table 5

As shown in Table 5, when the first capacitor C1 stores "0" and the second capacitor C2 stores "1", it can be used to indicate that the state of the content addressable memory is "0"; when the first capacitor C1 stores " 1", when the second capacitor C2 stores "0", it can be used to indicate that the state of the content addressable memory is "1"; when the first capacitor C1 and the second capacitor C2 both store "0", it can be used to indicate the content The state of the addressable memory is "X0". When the first capacitor C1 and the second capacitor C2 both store "1", it can be used to indicate that the state of the content addressable memory is another fuzzy state "X1".

When performing a write operation, the first bit line BL and the second bit line BL! It is used for outputting a write voltage to write data to be written into the memory cell MC. The first bit line BL can be used to configure the voltage of the second plate of the first capacitor C1 to a preset first write voltage to configure the polarization state of the first capacitor C1, and the second bit line is the same BL! It can be used to configure the voltage of the second plate of the second capacitor C2 to a preset second write voltage, so as to configure the polarization state of the second capacitor C2. When the first capacitor C1 and the second capacitor C2 are in different polarization states, it can be used to indicate that different data are stored in the first capacitor C1 and the second capacitor C2.

In a possible implementation manner, under different first write voltages, the first capacitor C1 can be configured in different polarization states, for example, the polarization state of the first capacitor C1 can be configured in the first Polarization state, wherein the first polarization state is that the first pole plate faces the second pole plate, and the voltage of the second pole plate is lower than the voltage of the first pole plate; or the polarization state of the first capacitor C1 can also be configured as A second polarization state opposite to the first polarization state, the second polarization state is that the second pole plate faces the first pole plate, and the voltage of the second pole plate is higher than the voltage of the first pole plate.

When the polarization state of the first capacitor C1 is the first plate facing the second plate, it can be used to instruct the first capacitor C1 to store the first logic value; when the polarization state of the first capacitor C1 is the second plate facing When the first polar plate is used, it can be used to instruct the first capacitor C1 to store a second logic value opposite to the first logic value. In one case, the first logical value may be "0", and correspondingly, the second logical value may be "1"; in another case, the first logical value may be "1", and correspondingly, the second Two logical values can be "0".

Similarly, under the action of different second writing voltages, the second capacitor C2 can also be configured in different polarization states, for example, the polarization state of the second capacitor C2 can be configured in the first polarization state, wherein the second capacitor C2 can be configured in a first polarization state. A polarization state is that the first pole plate faces the second pole plate, and the voltage of the first pole plate is higher than the voltage of the second pole plate; or the polarization state of the second capacitor C2 can also be configured to be the same as the first polarization state The opposite second polarization state, the second polarization state is that the second pole plate faces the first pole plate, and the voltage of the second pole plate is higher than the voltage of the first pole plate.

When the polarization state of the second capacitor C2 is the first plate facing the second plate, it can be used to instruct the second capacitor C2 to store the first logic value; when the polarization state of the second capacitor C2 is the second plate facing When the first plate is used, it can be used to instruct the second capacitor C2 to store a second logic value opposite to the first logic value. In one case, the first logical value may be "0", and correspondingly, the second logical value may be "1"; in another case, the first logical value may be "1", and correspondingly, the second Two logical values can be "0".

In the embodiment of the present application, the data stored when the polarization direction of the capacitor is the second plate facing the first plate is the first logic value as an example, as shown in Figures 4a to 4d, and Figures 4a to 4d show A schematic diagram of different states of the memory cell MC provided by the embodiment of the present application is shown.

When the polarization state of the first capacitor C1 is configured such that the second plate faces the first plate, the first logical value is stored, and the polarization state of the second capacitor C2 is configured such that the first plate faces the second plate, and the stored The second logic value may be used to indicate that the state of the CAM storage unit MC is the first logic value.

In a possible implementation, the first writing voltage is +Vw, the second writing voltage is -Vw, the polarization state of the first capacitor C1 is configured such that the second plate faces the first plate, and the second The polarization state of the capacitor C2 is configured such that the first plate faces the second plate, the first capacitor C1 stores the first logic value, the second capacitor C2 stores the second logic value, and the state of the CAM storage unit MC is the first logic value value. Wherein, Vw represents the voltage capable of inverting the polarization state of the capacitor.

As shown in Figure 4a, for example, when the first logic value is "0", the second logic value is "1", the first capacitor C1 stores "0", and the second capacitor C2 stores "1", which can be used to indicate the CAM The state of memory cell MC is "0".

When the polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, the second logic value is stored, and the polarization state of the second capacitor C2 is configured such that the second plate faces the first plate, and the storage The first logic value may be used to indicate that the state of the CAM storage unit MC is the second logic value.

In a possible implementation manner, the first writing voltage is -Vw, the second writing voltage is +Vw, the polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, and the second The polarization state of the capacitor C2 is configured such that the second plate faces the first plate, the first capacitor C1 stores the second logic value, the second capacitor C2 stores the first logic value 0, and the state of the CAM storage unit MC is the second logical value.

As shown in Figure 4b, for example, when the first logic value is "0", the second logic value is "1", the first capacitor C1 stores "1", and the second capacitor C2 stores "0", which can be used to indicate the The state of the CAM memory cell MC is "1".

When the polarization state of the first capacitor C1 is configured such that the second plate faces the first plate, the first logic value is stored, and the polarization state of the second capacitor C2 is configured such that the second plate faces the first plate, and the storage The first logical value may be used to indicate that the state of the CAM storage unit MC is the first fuzzy state.

In a possible implementation, the first writing voltage is +Vw, the second writing voltage is +Vw, the polarization state of the first capacitor C1 is configured such that the second plate faces the first plate, and the second The polarization state of the capacitor C2 is configured such that the second plate faces the first plate, the first capacitor C1 stores the first logic value, the second capacitor C2 stores the first logic value, and the state of the CAM storage unit MC is the first fuzzy state.

As shown in Figure 4c, for example, when the first logic value is "0", the first capacitor C1 stores "0", and the second capacitor C2 stores "0", which can be used to indicate that the state of the CAM storage unit MC is "X0" .

When the polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, the second logic value is stored, and the polarization state of the second capacitor C2 is configured such that the first plate faces the second plate, and the storage The second logic value may be used to indicate that the state of the CAM storage unit MC is the second fuzzy state.

In a possible implementation, the first write voltage is -Vw, the second write voltage is -Vw, the polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, and the second The polarization state of the capacitor C2 is configured such that the first plate faces the second plate, the first capacitor C1 stores the second logic value, the second capacitor C2 stores the second logic value, and the state of the CAM storage unit MC is the second fuzzy state.

As shown in Fig. 4d, for example, when the first capacitor C1 stores "1" and the second capacitor C2 stores "1", it can be used to indicate that the state of the CAM storage unit MC is "X1".

In the above embodiment, the first logical value is "0" and the second logical value is "1" for illustration. In some other possible implementations, the first logical value may also be "1", and the second logical value Can also be "0".

It can be seen from the above content that the voltage of the second plate of the first capacitor C1 is configured as the first writing voltage by using the first bit line BL, and the voltage of the second plate of the first capacitor C1 is configured by using the second bit line BL! The voltage of the second plate of the second capacitor C2 is configured as the second write voltage, and different combinations of the first write voltage and the second write voltage can write different data to be written into the CAM memory cell MC, For example "0", "1", "X0" or "X1".

When performing an addressing operation, the first bit line BL or the second bit line BL! It is used to output a preset search signal according to the key value, so as to match the state stored in the CAM storage unit MC with the key value. The output signal of the matching line ML can be used to indicate the matching result. When the matching line ML outputs the matching signal ( For example, when it can be a high level signal), the state stored in the CAM storage unit MC matches the key value, in conjunction with Table 6:

Table 6

key	First bit line BL	Second bit line BL!
0	VR	dangling
1	dangling	VR

Wherein, when the key value is 0, the search signal is output through the first bit line BL, and the second bit line BL! No output signal, in a floating state; when the key value is 1, through the second bit line BL! A search signal is output, and the first bit line BL does not output a signal and is in a floating state. Wherein, the search signal is a signal capable of partially inverting the polarization state of the capacitor, and the voltage of the search signal is Vr, where Vr<Vw.

In the embodiment of the present application, the data stored when the polarization direction of the capacitor is the second plate facing the first plate is determined as the first logic value, and the addressing operations of the CAM in several different states are respectively performed below introduce. When performing an addressing operation, a first preset voltage is output to the word line WL (for example, the first preset voltage is 0), and the match line is precharged to a second preset voltage (for example, the second preset voltage is VDD) .

As shown in Figure 5a, when the state of the CAM storage unit MC is "0", that is, the first capacitor C1 stores "0", and the second capacitor C2 stores "1", the polarization state of the first capacitor C1 is configured as the second pole The plate faces the first plate, the voltage of the second plate of the first capacitor C1 is higher than the voltage of the first plate; the polarization state of the second capacitor C2 is configured so that the first plate faces the second plate, and the second plate faces the second plate. The voltage of the second plate of the capacitor C2 is lower than the voltage of the first plate.

When the key value is "1", combined with Table 6, the second bit line BL! output search signal Vr, when the voltage of the second plate of the second capacitor C2 is lower than the voltage of the first plate, the second bit line BL! A positive voltage signal is output to the second plate of the second capacitor C2, and the polarization state of the second capacitor C2 is partially reversed, resulting in a large decrease in the positive charge stored in the first plate of the second capacitor C2, in order to maintain the charge at FN Balanced, the control terminal of transistor T induces a large amount of extra positive charge. At this time, the control terminal of the transistor T is equivalent to applying a large positive voltage, the transistor T is in the conduction state, and generates a large Ids current (the current between the second terminal and the first terminal of the transistor T), and the matching line ML is connected to the word line WL through the transistor T, and the voltage of the match line ML changes from the second predetermined voltage to the first predetermined voltage on the word line WL.

When the key value is "0", the first bit line BL outputs Vr, and the voltage of the second plate of the first capacitor C1 is higher than the voltage of the first plate, the first bit line BL sends the voltage to the first capacitor C1 The output voltage of the second plate is a positive signal, and the polarization state of the first capacitor C1 is further strengthened, resulting in a small increase in the negative charge of the second plate of the first capacitor C1. In order to maintain the balance of the charge at FN, the control of the transistor T A small amount of extra positive charge is induced at the terminal, at this time, the control terminal of the transistor T is equivalent to applying a small positive voltage to generate a small Ids current, the transistor T is in the off state, and the voltage of the matching line ML is maintained at the first The second predetermined voltage, or the leakage caused by the small Ids current, the voltage of the matching line ML is the third predetermined voltage, and the third predetermined voltage is the difference between the second predetermined voltage and the leakage.

According to the above description, if a smaller Ids is read between the word line WL and the match line ML, that is, when the voltage of the match line ML is maintained at the second preset voltage, the key value=0 and the storage state of CAM is "0". Match, the address where the CAM stores data is the address you are looking for.

As shown in Figure 5b, when the state of the CAM memory cell MC is "1", that is, the first capacitor C1 stores "1", and the second capacitor C2 stores "0", the polarization state of the first capacitor C1 is configured as the first polarity The plate faces the second plate, the voltage of the second plate of the first capacitor C1 is lower than the voltage of the first plate; the polarization state of the second capacitor C2 is configured so that the second plate faces the first plate, and the second The voltage of the second plate of the capacitor C2 is higher than the voltage of the first plate.

When the key value is "1", the second bit line BL! Output Vr, when the voltage of the second plate of the second capacitor C2 is higher than the voltage of the first plate, the polarization state of the second capacitor C2 is further strengthened (the positive charge of the second plate increases slightly), resulting in the first The positive charge stored in the first plate of the second capacitor C2 increases slightly, and in order to maintain the charge balance at FN, the control terminal of the transistor T induces a small amount of additional positive charge. At this time, the control terminal of the transistor T is equivalent to applying a small positive voltage to generate a small Ids current, the transistor T is turned off, and the voltage of the matching line ML is maintained at the second preset voltage.

When the key value is "0", the first bit line BL outputs Vr, and the voltage of the second plate of the first capacitor C1 is lower than the voltage of the first plate, the polarization state of the first capacitor C1 weakens, resulting in The positive charge on the first plate of the first capacitor C1 is greatly reduced. In order to maintain the charge balance at FN, the control terminal of the transistor T induces a large amount of extra positive charge. At this time, the control terminal of the transistor T is equivalent to applying a relatively With a large positive voltage, the transistor T is in a conduction state, which generates a large Ids current, and the voltage of the matching line ML changes from the second preset voltage to the first preset voltage.

According to the above description, if a small Ids current is read between the word line WL and the match line ML, that is, when the voltage of the match line ML is maintained at the second preset voltage, the key value=1 and the storage state of the CAM is “1”. "Match, the address where the CAM stores data is the address you are looking for.

As shown in Figure 5c, when the state of the CAM memory cell MC is "X0", the first capacitor C1 stores "0", the second capacitor C2 stores "0", and the polarization state of the first capacitor C1 is configured as the second plate Facing the first plate, the voltage of the second plate of the first capacitor C1 is higher than the voltage of the first plate; the polarization state of the second capacitor C2 is configured so that the second plate faces the first plate, and the second capacitor The voltage of the second plate of C2 is higher than the voltage of the first plate, the polarity of the first plate of the first capacitor C1 and the first plate of the second capacitor C2 are the same, both are -Vw, so in the transistor T The control terminal induces a positive charge to form a voltage of +2Vw. In this case, no matter the key value is 1 or 0, the transistor T is in the on state, generating a large Ids current, and the voltage on the matching line ML is determined by the second The preset voltage is transformed into a first preset voltage.

According to the above description, when the state stored in CAM is "X0", no matter the key is 0 or 1, a large Ids current can be read between the match line ML and the word line WL, and the voltage of the match line ML changes to the first Preset voltage, at this time the key value does not match the stored data of the CAM.

As shown in Figure 5d, when the state of the CAM memory cell MC is "X1". That is, the first capacitor C1 stores "1", and the second capacitor C2 stores "1". The polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, and the second plate of the first capacitor C1 The voltage is lower than the voltage of the first plate; the polarization state of the second capacitor C2 is configured such that the first plate faces the second plate, and the voltage of the second plate of the second capacitor C2 is lower than the voltage of the first plate. The polarity of the first plate of the first capacitor C1 and the first plate of the second capacitor C2 are the same, both are +Vw, so negative charges are induced at the control terminal of the transistor T to form a voltage of -2Vw, in this case In this case, no matter the key value is "1" or "0", the transistor T is in the off state, only a small Ids current is generated, and the voltage of the matching line ML is maintained at the second preset voltage.

According to the above description, when the state stored in the CAM is "X1", no matter the key is 0 or 1, a small Ids current can be read between the match line ML and the word line WL, and the voltage of the match line ML is maintained at the second Preset voltage, at this time the key value is vaguely matched with the stored data of TCAM.

The content addressable memory provided by the embodiment of the present application can realize the function of TCAM by using two capacitors and one transistor, which greatly simplifies the circuit structure and reduces the The occupied area can increase the storage density.

On the basis of FIG. 3, please refer to FIG. 6. The content addressable memory provided by the embodiment of the present application also includes a plurality of first control pipes and a plurality of second control pipes, and a first control pipe is set corresponding to each storage unit MC. Tw1, and a second control tube Tw2. Wherein, the control ends of the first control transistor Tw1 and the second control transistor Tw2 are connected to the control line CL, the first end of the first control transistor Tw1 is connected to the first bit line BL, and the second end of the first control transistor Tw1 is connected to the first capacitor The second plate of C1; the first end of the second control transistor Tw2 is connected to the second bit line BL! , the second end of the second control transistor Tw2 is connected to the second plate of the second capacitor C2.

The first control transistor Tw1 is used to control the conduction state of the second plate of the first capacitor C1 and the first bit line BL1, and the second control transistor Tw2 is used to control the second plate of the second capacitor C2 and the second bit line In the conduction state of BL2, when the first control transistor Tw1 and the second control transistor Tw2 are turned on, the second plate of the first capacitor C1 is connected to the first bit line BL1, and the second plate of the second capacitor C2 is connected to the first bit line BL1. Two bit line BL! 1 connection, you can pass the first bit line BL1, the second bit line BL! 1 Write data to be written into the selected memory cell MC, or through the first bit line BL1 or the second bit line BL! 1 Output a search signal to the selected memory cell MC.

On the basis of Figure 6, the embodiment of the present application provides a content addressable memory, please refer to Figure 7, the content addressable memory includes m rows and n columns of memory cells MC, m and n are both positive integers greater than or equal to 1 .

Among them, the data stored in a row of memory cells MC constitutes a table entry. In this case, the memory cells MC in the same row are connected to the same match line ML, and the memory cells MC in the same row are connected to the same word line WL. The memory cells MC in the same column are connected to the same control line CL, the memory cells MC in the same column are connected to the same first bit line BL, and the memory cells MC in the same column are connected to the same second bit line BL! .

For example, in conjunction with FIG. 7, the storage cells MC in the first row are connected to the word line WL1, the storage cells MC in the first row are connected to the match line ML1, the storage cells MC in the first row are connected to the control line CL1; the storage cells MC in the second row are connected to the word line WL2, The memory cell MC in the second row is connected to the match line ML2, the memory cell MC in the second row is connected to the control line CL2, the memory cell MC in the m row is connected to the word line WLm, the memory cell MC in the m row is connected to the match line MLm, and the memory cell MC in the m row is connected to the word line WLm. Connect the control line CLm. The memory cell MC in the first column is connected to the first bit line BL1 and the second bit line BL! 1 connection; the memory cell MC in the second column is connected to the first bit line BL2 and the second bit line BL! 2 connection, the memory cell MC in the third column is connected to the first bit line BL3 and the second bit line BL! 3 connection, the memory cell MC in the nth column is connected to the first bit line BLn and the second bit line BL! n connection.

Each storage unit MC can store 1 bit (1 bit) data, such as any one of "0", "1" or "X", and "0", "1" or "X" respectively represent a state, such as The data stored in one row of memory cells MC in the content addressable memory shown in FIG. 7 can form one table entry, m rows of memory cells MC have at most m table entries, and each table entry can store at most n bits of data.

When performing a write operation, for example, the memory cell MC located in the xth row and the yth column is used as the target memory cell MC to perform the write operation, then the first control transistor Tw1 and the second control transistor Tw2 corresponding to the target memory cell MC are controlled conduction, through the first bit line BL and the second bit line BL corresponding to the memory cell MC in the yth column! The first write voltage and the second write voltage are output, and the data to be written is written into the target memory cell MC. For memory cells MC in the yth column, except for the target memory cell MC, the corresponding first control transistor Tw1 and second control transistor Tw2 are in the off state, and the first bit line BL and the second bit line BL! The outputted first write voltage and second write voltage will not rewrite the states stored in memory cells MC other than the target memory cell MC.

One of the advantages of CAM is that it can be quickly searched, and the key value can be compared with all stored entries at the same time, so as to find out the entry that matches the key value. When performing an addressing operation, the first control transistor Tw1 and the second control transistor Tw2 corresponding to all the memory cells MC are controlled to be turned on, so that the addressing operation can be performed on all the memory cells MC in the CAM at the same time.

For example, if the first bit of the key value is 1, then the first bit line BL1 corresponding to the memory cell MC in the first column does not output a signal, and the second bit line BL! 1. Output the search signal Vr to search for the memory cell MC matching the key value in the first column of memory cells MC.

For example, if the second bit of the key value is 0, then the first bit line BL2 corresponding to the second column memory unit outputs the search signal Vr, and the second bit line BL! 1 No signal is output, and the memory cell MC matching the key value in the second column of memory cells MC is searched.

For example, if the nth bit of the key value is 1, then the first bit line BLn corresponding to the memory cell MC in the nth column does not output a signal, and the second bit line BL! n outputs a search signal Vr to search for the memory cell MC matching the key value in the memory cell MC of the nth column.

It can be seen from the foregoing that when a small Ids current is read between the word line WL connected to the memory cell MC and the match line ML, the first terminal and the second terminal of the transistor T are not conducted, and the voltage of the match line ML maintains the second preset voltage. Set the voltage, the word line WL voltage is the first preset voltage, which means that the stored state of the memory cell MC matches the key value; when a larger Ids current is read between the word line WL and the match line ML connected to the memory cell MC At this time, the first terminal and the second terminal of the transistor T are turned on, the match line ML is connected to the word line WL, and the voltage of the match line ML changes to be the same as the voltage of the word line WL, that is, the first preset voltage, which means that the memory The state stored by cell MC does not match the key value.

In the embodiment of the present application, the data stored in a row of memory cells MC constitutes an entry. When the data of each bit of an entry matches (or fuzzily matches) the key value, the word line corresponding to the row of memory cells MC Only a small Ids current is generated between the WL and the match line ML, the transistors T of all the memory cells MC in the row are not turned on, the word line WL maintains a first preset voltage, and the match line ML maintains a second preset voltage; When there is at least one bit of data in an entry that does not match the key value, a large Ids current is generated between the first end and the second end of the transistor T of the memory cell MC, and the first end and the second end of the transistor T is turned on, the match line ML is connected to the word line WL, and the voltage of the match line ML is rewritten by the word line ML to a first preset voltage.

Therefore, in a possible implementation manner, when performing an addressing operation, a first preset voltage (for example, the first preset voltage is 0) is output to the word line WL, and the match line is precharged to a second preset voltage (For example, the second preset voltage is VDD), after the search signal is output, if a relatively small current is read between the match line ML corresponding to a certain row of memory cells MC and the word line WL, the match line ML outputs the second preset voltage. voltage, indicating that the table entry composed of the data stored in the row of memory cells MC matches the key, and the address of the row of memory cells MC is the target address. If a relatively large current is read between the match line ML and the word line WL corresponding to a row of memory cells MC, the match line ML outputs a first preset voltage, indicating that the table entry and key composed of data stored in the row of memory cells MC Mismatch.

Based on the content-addressable memory provided by the embodiment of the present application, the embodiment of the present application also provides a data writing method for writing data into the content-addressable memory provided by the embodiment of the present application. The data writing method includes:

S110: Outputting a first write voltage to a first bit line, and outputting a second write voltage to a second bit line, so as to write data to be written into a memory cell.

Wherein, the first writing voltage is used to configure the polarization state of the first capacitor C1, and the second writing voltage is used to configure the polarization state of the second capacitor C2. The different polarization states of the first capacitor C1 can be used to indicate that the first capacitor C1 stores different data, and the different polarization states of the second capacitor C2 can be used to indicate that the second capacitor C2 stores different data. The first capacitor C1 and the second capacitor C2 can store different data. Different data combinations stored in the two capacitors C2 are used to indicate different states of the content addressable memory.

Exemplarily, when the polarization state of the first capacitor C1 is configured such that the second plate faces the first plate, and the polarization state of the second capacitor C2 is configured such that the first plate faces the second plate, the storage Cell MC writes a first logic value.

When the polarization state of the first capacitor C1 is configured such that the second plate faces the first plate, and the polarization state of the second capacitor C2 is configured such that the second plate faces the first plate, writing to the memory cell MC The first fuzzy state.

When the polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, and the polarization state of the second capacitor C2 is configured such that the second plate faces the first plate, writing to the memory cell MC Second logical value.

When the polarization state of the first capacitor C1 is configured such that the first plate faces the second plate, and the polarization state of the second capacitor C2 is configured such that the first plate faces the second plate, writing to the memory cell MC Second fuzzy state.

For example, the first logical value may be "0", the corresponding second logical value is "1", the first fuzzy state is "X0", the second fuzzy state is "X1", or the first logical value is "1" ", the corresponding second logical value is "0", the first fuzzy state is "X1", and the second fuzzy state is "X0".

In a possible implementation, each storage unit is provided with a first control transistor Tw1 and a second control transistor Tw2, the control terminals of the first control transistor Tw1 and the second control transistor Tw2 are connected to the control line CL, and the first control The first end of the transistor Tw1 is connected to the first bit line BL, the second end of the first control transistor Tw1 is connected to the second plate of the first capacitor C1; the first end of the second control transistor Tw2 is connected to the second bit line BL! , the second end of the second control transistor Tw2 is connected to the second plate of the second capacitor C2. The first control transistor Tw1 is used to control the conduction state of the second plate of the first capacitor C1 and the first bit line BL1, and the second control transistor Tw2 is used to control the second plate of the second capacitor C2 and the second bit line The conduction state of BL2, in this case, as shown in Figure 8, the data writing method provided by the embodiment of the present application also includes:

S100: Control the conduction of the first control tube and the second control tube.

The control terminals of the first control tube Tw1 and the second control tube Tw2 are both connected to the control line CL, and output a fourth preset voltage to the control line CL. When the voltage of the control terminals of the first control tube Tw1 and the second control tube Tw2 is the first At four preset voltages, the first control transistor Tw1 and the second control transistor Tw2 are in the conduction state, the first bit line BL1 conducts with the second plate of the first capacitor C1 through the first control transistor Tw1, and the second bit line BL! 1 Through the conduction between the second control transistor Tw2 and the second plate of the second capacitor C2, the polarization states of the first capacitor C1 and the second capacitor C2 can be configured, and data to be written can be written.

For example, FIG. 9 provides a content-addressable memory including 3 rows and 4 columns of memory cells. If (1, 0, 1, 1) is written to the memory cell located in the second row, the Write "1" to the memory cells in one column, write "0" to the memory cells in the second row and second column, write "1" to the memory cells in the second row and third column, and write "1" to the memory cells in the second row and column, "1" is written into the memory cells of the row and the fourth column.

Output the fourth preset voltage to the control line CL2, control the first control transistor Tw1 and the second control transistor Tw2 corresponding to the second row of memory cells, and connect the second row of memory cells to the corresponding first bit line BL, second bit line BL! conduction.

Then the first write voltage (for example, -Vw) is output to the first bit line BL1, and the second bit line BL! 1 Output the second write voltage (for example, +Vw), write "1" into the memory cell located in the second row and the first column; output the first write voltage (for example, +Vw) to the first bit line BL2 , the second bit line BL! 2 Output the second write voltage (for example, -Vw), write "0" into the memory cells located in the second row and second column; output the first write voltage (for example, -Vw) to the first bit line BL3 , the second bit line BL! 3 Output the second write voltage (for example, +Vw), write "1" into the memory cells located in the second row and third column; output the first write voltage (for example, -Vw) to the first bit line BL4 , the second bit line BL! 4 Output the second write voltage (for example, +Vw), and write "1" into the storage cells located in the second row and the fourth column, thereby completing the writing of data, because the first control transistor Tw1 corresponding to other storage cells , The second control transistor Tw2 is in the off state, and the other memory cells are connected to the first bit line BL and the second bit line BL! It is disconnected, so the data stored in other storage units will not be overwritten.

The embodiment of the present application also provides a data processing method for addressing the content-addressable memory provided in the embodiment of the present application. Referring to FIG. 10, the data processing method includes:

S210: Set the word line to a first preset voltage, and precharge the match line to a second preset voltage, wherein the second preset voltage is different from the first preset voltage.

When performing an addressing operation, the word line WL corresponding to the memory cell to be addressed is set to a first preset voltage, and the match line ML corresponding to the memory cell to be addressed is precharged to a second preset voltage. The set voltage is different from the second preset voltage.

S220: Outputting a search signal to the first bit line or the second bit line according to the target data.

Send data to the first bit line BL or the second bit line BL according to the target data (ie key value)! Output the search signal. In the embodiment of the present application, the data stored in each row of storage units constitutes an entry, and the storage units distributed in the column direction are the collection of storage units that store the same bit data in each entry, such as the first column of storage units. That is, the first entry stores the storage unit of the first bit of data, the second entry stores the storage unit of the first bit of data, and the mth entry stores the storage unit of the first bit of data. By outputting the search signal to the first bit line or the second bit line, the search and match can be performed on the one-bit data stored in the storage unit in the column in all table entries, and the first bit line BL1 or BL1 corresponding to the storage unit in the first column can be sent Second bit line BL! 1 Output the search signal, which can search and match the first bit data of all table entries according to the key value, and send to the first bit line BL2 or the second bit line BL corresponding to the second column of memory cells! 2 Outputting the search signal, the second bit data of all table entries can be searched and matched according to the key value, and sent to the first bit line BLn or the second bit line BL corresponding to the storage unit in the nth column! n outputs the search signal, which can search and match the nth bit data of all table entries according to the key value, so that all data stored in the content addressable memory can be searched and matched at the same time, and the search efficiency is high.

S230: If it is detected that the voltage of the matching line connected to the target storage unit is the second preset voltage, then determine that the data stored in the target storage unit matches the target data.

If it is detected that the voltage of the match line ML connected to the target memory cell is the second preset voltage, that is, the transistor T of the target memory cell is in an off state, only a small current is generated between the match line ML and the word line WL , to determine that the data stored in the target storage unit matches the target data.

In the embodiment of the present application, the data stored in a row of storage units constitutes an entry. When the data of each bit of an entry matches (or fuzzily matches) the key value, the word line WL corresponding to the row of storage units and Only a small Ids current is generated between the matching lines ML, the transistors T of all the memory cells in the row are not turned on, the word line WL maintains the first preset voltage, and the matching line ML outputs the second preset voltage; when a table When there is at least one bit of data in the item that does not match the key value, a large Ids current is generated between the first terminal and the second terminal of the transistor T of the storage unit, and the first terminal and the second terminal of the transistor T are turned on, matching The line ML communicates with the word line WL, and the voltage of the match line ML is rewritten to a first preset voltage by the word line ML. When performing an addressing operation, a first preset voltage (for example, the first preset voltage is 0) is output to the word line WL, and the match line is precharged to a second preset voltage (for example, the second preset voltage is VDD ), after the search signal is output, if a relatively small current is read between the match line ML and the word line WL corresponding to a certain row of memory cells, the match line ML outputs a second preset voltage, indicating that the data stored in the row of memory cells consists of The table entry of matches the key, and the address of the storage unit in this row is the target address. If a relatively large current is read between the match line ML and the word line WL corresponding to a certain row of memory cells, the match line ML outputs the first preset voltage, indicating that the entry of the data stored in the row of memory cells does not match the key .

As shown in Figure 11, Figure 11 shows a schematic addressing schematic diagram of the data processing method provided by the embodiment of the present application. According to the key value, each bit of data is searched and matched. When the data of each bit of a certain entry is When matching (or fuzzy matching) with the key value, it is determined that the data of the entry matches the key value, and the address of the storage unit storing the entry is the target address.

In a possible implementation manner, the above-mentioned first capacitor C1 and second capacitor C2 are ferroelectric capacitors. In the content addressable memory provided in the embodiment of the present application, when the polarization state of the first capacitor C1 is that the second plate faces the first One plate, the polarization state of the second capacitor C2 is that the first plate faces the second plate, and stores the first logic value; when the polarization state of the first capacitor C1 is that the second plate faces the first plate, the second The polarization state of the second capacitor C2 is that the second pole plate faces the first pole plate, and stores the first fuzzy state; when the polarization state of the first capacitor C1 is that the first pole plate faces the second pole plate, the pole of the second capacitor C2 The polarization state is that the second pole plate faces the first pole plate, and stores the second logic value; when the polarization state of the first capacitor C1 is that the first pole plate faces the second pole plate, the polarization state of the second capacitor C2 is the first The plate faces the second plate, storing the second hazy state. In this case, step S220: outputting the search signal to the first bit line or the second bit line according to the target data includes:

S220a: When the target data is the first logic value, the first bit line is suspended, and a search signal is output to the second bit line.

S220b: When the target data is the second logic value, output a search signal to the first bit line, and suspend the second bit line.

For example, in a possible implementation manner, the first logic value is "0", and correspondingly, the second logic value is "1" according to the target data (key) to the first bit line BL or the second bit line BL! Output search signal. As shown in Table 6 above, when the key value is "0", the search signal Vr is output to the first bit line BL, and the second bit line BL! Floating, when the key value is "1", to the second bit line BL! The search signal Vr is output, and the first bit line BL is suspended.

Based on the memory cell array shown in FIG. 7 or FIG. 9, the memory cell MC is connected to the first bit line BL through the first control transistor, and the memory cell MC is connected to the second bit line BL through the second control transistor! Connection, in order to ensure the first bit line BL, the second bit line BL! The search voltage on can be applied to each memory cell MC, referring to FIG. 12, before S220, the data processing method also includes:

S200: Control the conduction of the first control tube and the second control tube.

For example, a fourth preset voltage may be output to the control line, and when the voltage of the control line is the fourth preset voltage, the first control transistor and the second control transistor are in a conduction state.

S200 and S210 may be executed at the same time, or any one may be executed first.

The foregoing mainly introduces the solutions provided by the embodiments of the present application from the perspective of method steps. It can be understood that, in order to realize the above functions, the computer includes hardware structures and/or software modules corresponding to each function. Those skilled in the art should easily realize that, in combination with the modules and algorithm steps of the examples described in the embodiments disclosed herein, the present application can be implemented in the form of a combination of hardware and computer software. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

In the embodiment of the present application, the functional modules of the data processing device may be divided according to the above method example. For example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation. In the case of dividing each functional module corresponding to each function, FIG. 13 shows a data processing device 300, which may be a chip, and is used to execute the above data writing method and data processing method. The data processing device 300 includes:

The data writing unit 310 is configured to output a first writing voltage to the first bit line, and output a second writing voltage to the second bit line, so as to write data to be written into the memory cell.

Referring to FIG. 8 , the data writing unit 310 may be used to execute S110.

In a possible implementation manner, the content addressable memory is provided with a first control transistor and a second control transistor corresponding to each storage unit, and the first control transistor is arranged on the second plate of the first capacitor and the first bit line Between, the second control transistor is arranged between the second plate of the second capacitor and the second bit line, in this case, the content addressable memory also includes a write control unit 320, the write control unit 320 is used to The first control transistor and the second control transistor are controlled to be turned on, so as to write data into the memory cell through the first bit line and the second bit line.

Referring to FIG. 8 , the writing control unit 320 may be used to execute S100 .

Optionally, the data processing device 300 further includes an addressing unit 330, the addressing unit 330 is configured to set the word line WL to a first preset voltage, and precharge the match line ML to a second preset voltage, wherein the second preset The voltage is different from the first preset voltage, and the addressing unit 330 is also used to set the control line CL to the fourth preset voltage to control the conduction of the first control transistor and the second control transistor; the addressing unit 330 is also used to Data to the first bit line BL or the second bit line BL! Outputting a search signal, if it is detected that the voltage of the matching line connected to the target storage unit is the second preset voltage, then it is determined that the data stored in the target storage unit matches the target data.

Referring to FIG. 10 and FIG. 12 , the addressing unit 330 can be used to execute S200 , S210 , S220 , and S230 .

The present application provides a specific manufacturing method for manufacturing the memory cell structure provided by the embodiment of the present application, which will be explained in detail below in conjunction with the accompanying drawings.

Fig. 14 is a block diagram of a method for making a content addressable memory provided by the present application, which specifically includes the following:

S410: Forming a transistor on the substrate, where the transistor includes a control terminal, a first terminal and a second terminal.

S420: Form a first capacitor and a second capacitor on the transistor, the first capacitor includes a first plate and a second plate, the second capacitor includes a first plate and a second plate, the first plate of the first capacitor , the first plate of the second capacitor is electrically connected to the control terminal of the transistor.

The specific process flow involved in the above-mentioned S410 and S420 will be introduced below with reference to the accompanying drawings.

15a to 15n show cross-sectional views of the process structure after each step in the process of manufacturing a memory cell involved in the present application.

As shown in FIG. 15 a , along a direction perpendicular to the substrate, a first metal layer 001 , a first isolation dielectric layer 002 and a second metal layer 003 are sequentially formed above the substrate.

The substrate is a semiconductor substrate, which can be made of materials such as germanium, silicon, silicon germanium, or other III-V compounds.

The first metal layer 001 and the second metal layer 003 here can choose metal materials, such as Au (gold), Ti (titanium), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, One or more of conductive materials such as indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

The first isolation dielectric layer 002 here can be made of insulating materials, such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (trioxide One or more of insulating materials such as diyttrium) and Si3N4 (silicon nitride).

As shown in Figure 15b, a first groove 004 is opened in the stacked first metal layer 001, first isolation dielectric layer 002 and second metal layer 003, and the first groove 004 passes through the second metal layer 003 and the first isolation dielectric layer 002 , the part that penetrates the first metal layer 001 , that is, the first groove 004 only penetrates the second metal layer 003 and the first isolation dielectric layer 002 , but does not penetrate the first metal layer 001 .

As shown in Figure 15c, a first channel material layer 005 is formed on the side of the first groove 004 perpendicular to the substrate, where the first channel material layer 005 can be Si (silicon), poly-Si (p-Si, polysilicon) , amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multi-component compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide) , MoS2 (molybdenum disulfide), WS2 (tungsten disulfide) and other semiconductor channel materials or one or more.

In a possible implementation, the semiconductor channel material can be epitaxially formed on the stacked structure shown in Figure 15b to form the structure shown in Figure 15d, and then through dry etching and other processes, the second metal on the top The semiconductor channel material above the layer 003 and at the bottom of the structure of the first trench 004 is etched away, leaving part of the semiconductor channel material inside the first trench 004 to form the first channel material layer 005 as shown in FIG. 15c.

As shown in FIG. 15e , a gate oxide dielectric layer 006 is formed on the surfaces of the first metal layer 001 , the second metal layer 003 and the first channel material layer 005 .

The gate oxide dielectric layer 006 can be made of SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide) and Si3N4 (nitride One or more of insulating materials such as silicon) and high dielectric materials.

As shown in Fig. 15f, a third metal layer 007 is formed in the remaining space of the first groove 004 to form a transistor, and the top surface of the third metal layer 007 is flush with the top surfaces of the second metal layer 003 and the gate oxide dielectric layer 006.

The optional materials of the third metal layer 007 here can refer to the above-mentioned first metal layer 001 and second metal layer 003 , which will not be repeated here.

In a possible implementation manner, the epitaxial metal material can be formed on the structure shown in FIG. 15e to form the structure shown in FIG. The top surface is flush with the top surfaces of the second metal layer 003 and the gate oxide dielectric layer 006 .

The first metal layer 001 can be used as the first terminal or the second terminal of the transistor, the second metal layer 003 can be used as the second terminal or the first terminal of the transistor, and the third metal layer 007 can be used as the control terminal of the transistor.

Exemplarily, referring to FIG. 15f, the first metal layer 001 is used as the first terminal of the transistor, the second metal layer 003 is used as the second terminal of the transistor, the third metal layer 007 can be used as the control terminal of the transistor, and the second metal layer 003 has The first side 0031 perpendicular to the substrate, the first channel material layer 005 and the third metal layer 007 (that is, the control terminal of the transistor) are arranged on the side facing the first side 0031 of the second metal layer 003, the first The channel material layer 005 is arranged along a direction perpendicular to the substrate, so that the volume occupied by the transistor can be reduced.

As shown in FIG. 15h , a second isolation dielectric layer 008 is formed on the surfaces of the first channel material layer 005 , the gate oxide dielectric layer 006 , the third metal layer 007 and the second metal layer 003 .

Here, the optional material of the second isolation dielectric layer 008 can refer to the above-mentioned first isolation dielectric layer 002 , which will not be repeated here.

As shown in FIG. 15i , a second groove 009 is formed on the second isolation dielectric layer 008 at a position corresponding to the third metal layer 007 . The second groove 009 runs through the second isolation dielectric layer 008 , and the surface of the third metal layer 007 can be exposed through the second groove 009 .

As shown in FIG. 15j , a fourth metal layer 010 is deposited along the surfaces of the second isolation dielectric layer 008 and the third metal layer 007 , and the fourth metal layer 010 forms a third groove 011 . The fourth metal layer 010 is electrically connected to the third metal layer 007 . The fourth metal layer 010 includes the first plate of the first capacitor and the first plate of the second capacitor. For example, a part of the fourth metal layer 010 can be used as the first plate of the first capacitor, and another part can be used as the second capacitor. the first plate.

As shown in FIG. 15k , a third isolation dielectric layer 012 is formed in the third groove 011 formed in the fourth metal layer 010 .

Here, the optional material of the third isolation dielectric layer 012 can refer to the above-mentioned first isolation dielectric layer 002 , which will not be repeated here.

The third isolation dielectric layer 012 is planarized so that the top surface of the third isolation dielectric layer 012 is flush with the top surface of the fourth metal layer 010 .

As shown in FIG. 151 , a ferroelectric material layer 013 and a fifth metal layer 014 are sequentially stacked on the fourth metal layer 010 and the third isolation dielectric layer 012 .

Exemplarily, the above steps are described by taking the fabrication of ferroelectric capacitors as an example. If capacitors of other dielectric materials are fabricated, the ferroelectric material layer 013 should be replaced with other dielectric material layers.

As shown in Figure 15m, a fourth groove 015 is opened on the ferroelectric material layer 013 and the fifth metal layer 014, and the fourth groove 015 separates the structure formed by the ferroelectric material layer 013 and the fifth metal layer 014 into a direction parallel to the substrate. Two parts that are not in contact with each other, wherein the fifth metal layer 014 is separated into the second plate 014a of the first capacitor and the second plate 014b of the second capacitor, and the ferroelectric material layer 013 is separated into the second plate 014b of the first capacitor. The first ferroelectric material layer 013a and the second ferroelectric material layer 013b of the second capacitor.

As shown in FIG. 15n, a fourth isolation dielectric layer 016 is formed in the fourth groove 015 to form the first capacitor and the second capacitor.

Here, the optional material of the fourth isolation dielectric layer 016 can refer to the above-mentioned first isolation dielectric layer 002 , which will not be repeated here.

Wherein, the part of the fourth metal layer 010 corresponding to the second plate 014a of the first capacitor is used as the first plate of the first capacitor, and the part of the fourth metal layer 010 corresponding to the second plate 014b of the second capacitor As the second plate of the second capacitor, the fourth metal layer 010 is connected to the third metal layer 007, that is, the first plate of the first capacitor and the second plate of the second capacitor are connected to the control terminal of the transistor.

The corresponding method for preparing the storage unit is given above, of course, in some other optional implementation manners, other methods may also be used to prepare the structure of the storage unit involved in the present application.

The embodiment of the present application also provides an electronic device, the electronic device includes a circuit board and the content addressable memory as provided in the embodiment of the present application, and the content addressable memory is arranged on the circuit board. FIG. 16 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 500 includes a communication interface 510 , a processor 520 , a memory 530 and a bus 540 . Wherein, the communication interface 510 , the processor 520 , and the memory 530 communicate with each other through the bus 540 . The memory 530 includes a first memory 531 and a second memory 532, and the second memory 532 may specifically be a content addressable memory provided in this embodiment of the present application.

Wherein, the electronic device 500 communicates with other devices through the communication interface 510 . For example: the electronic device 500 receives messages sent by other devices through the communication interface 510 or sends messages to other devices. Exemplarily, the communication interface 510 includes an ingress media access control (media access control, MAC) chip and an egress MAC chip. The electronic device 500 can receive packets through the ingress MAC chip, and send packets through the egress MAC chip.

The processor 520 may be a central processing unit (central processing unit, CPU), or a specific integrated circuit (application specific integrated circuit, ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. The processor 520 is configured to execute executable program codes stored in the first memory 531 , such as computer programs to run programs corresponding to the executable codes.

The first memory 531 is used for storing executable program codes, and the program codes include computer operation instructions. The first memory 531 may include a high-speed random access memory (random access memory, RAM) memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

The second memory 532 may be a content addressable memory provided in this embodiment of the present application.

The bus 540 may be an industry standard architecture (industry standard architecture, ISA) bus, a peripheral component interconnection (peripheral component, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc. The bus 540 can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 16 , but it does not mean that there is only one bus or one type of bus.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (14)

1. A content-addressable memory, characterized in that the content-addressable memory comprises m rows and n columns of memory cells, m and n are integers greater than or equal to 1, and each of the memory cells includes a transistor, a first capacitor and a first capacitor Two capacitors;

   The control end of the transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor, the first end of the transistor is connected to the word line, and the second end of the transistor is connected to the match line, The second plate of the first capacitor is connected to the first bit line, and the second plate of the second capacitor is connected to the second bit line.
2. The content addressable memory according to claim 1, wherein the memory cells in the same row are connected to the same word line, and the memory cells in the same row are connected to the same match line.
3. The content addressable memory according to any one of claims 1-2, characterized in that the memory cells located in the same column are connected to the same first bit line, and the memory cells located in the same column are connected to the same second bit line.
4. The content-addressable memory according to any one of claims 1-3, wherein the content-addressable memory further comprises a plurality of first control pipes and a plurality of second control pipes, and each of the storage units corresponds to One first control tube and one second control tube are provided, the control end of the first control tube and the control end of the second control tube are connected to a control line;

   The first end of the first control transistor is connected to the first bit line, and the second end of the first control transistor is connected to the second plate of the first capacitor;

   A first end of the second control transistor is connected to the second bit line, and a second end of the second control transistor is connected to the second plate of the second capacitor.
5. The content-addressable memory according to any one of claims 1-3, wherein the first capacitor and the second capacitor are ferroelectric capacitors.
6. The content-addressable memory according to any one of claims 1-5, wherein the transistor is a transistor with a vertical channel structure.
7. A data processing method applied to a content-addressable memory, the content-addressable memory includes m rows and n columns of memory cells, m and n are integers greater than or equal to 1, and the memory cells include transistors, first capacitors, and second capacitors , the control end of the transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor, the first end of the transistor is connected to the word line, and the second end of the transistor is connected to the match line , the second plate of the first capacitor is connected to the first bit line, and the second plate of the second capacitor is connected to the second bit line, wherein the method includes:

   setting the word line to a first preset voltage, and precharging the match line to a second preset voltage, wherein the second preset voltage is different from the first preset voltage;

   outputting a search signal to the first bit line or the second bit line according to the target data;

   If it is detected that the voltage of the matching line connected to the target storage unit is the second preset voltage, it is determined that the data stored in the target storage unit matches the target data.
8. The data processing method according to claim 7, wherein the first capacitor and the second capacitor are ferroelectric capacitors, and when the polarization state of the first capacitor is configured such that the second plate faces the first When the polarized state of a polar plate and the second capacitor is that the first polar plate faces the second polar plate, the storage unit of the content addressable memory stores a first logic value;

   When the polarization state of the first capacitor is configured such that the second plate faces the first plate, and the polarization state of the second capacitor is that the second plate faces the first plate, the first fuzzy state is stored;

   When the polarization state of the first capacitor is configured such that the first plate faces the second plate and the polarization state of the second capacitor is configured such that the second plate faces the first plate, storing a second logic value;

   When the polarization state of the first capacitor is configured such that the first polar plate faces the second polar plate, and the polarization state of the second capacitor is configured such that the first polar plate faces the second polar plate, storing the second fuzzy state;

   The outputting the search signal to the first bit line or the second bit line according to the target data includes:

   When the target data is the first logic value, the first bit line is suspended, and the search signal is output to the second bit line;

   When the target data is the second logic value, the search signal is output to the first bit line, and the second bit line is suspended.
9. A data writing method applied to a content-addressable memory, the content-addressable memory includes m rows and n columns of memory cells, m and n are integers greater than or equal to 1, and the memory cells include transistors, first capacitors, and second Capacitor, the control end of the transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor, the first end of the transistor is connected to the word line, and the second end of the transistor is connected to the matching line, the second plate of the first capacitor is connected to the first bit line, and the second plate of the second capacitor is connected to the second bit line, wherein the method includes:

   Outputting a first write voltage to a first bit line, outputting a second write voltage to a second bit line, so as to write data to be written into the memory cell, wherein the first write voltage is used to configure the the polarization state of the first capacitor, the second write voltage is used to configure the polarization state of the second capacitor;

   Wherein, when the polarization state of the first capacitor is configured such that the second plate faces the first plate, and the polarization state of the second capacitor is configured such that the first plate faces the second plate, the storage the cell writes a first logical value;

   When the polarization state of the first capacitor is configured such that the second plate faces the first plate, and the polarization state of the second capacitor is configured such that the second plate faces the first plate, writing to the storage unit into the first fuzzy state;

   When the polarization state of the first capacitor is configured such that the first plate faces the second plate and the polarization state of the second capacitor is configured such that the second plate faces the first plate, writing to the storage unit Enter the second logical value;

   When the polarization state of the first capacitor is configured such that the first plate faces the second plate and the polarization state of the second capacitor is configured such that the first plate faces the second plate, writing to the storage unit into the second fuzzy state.
10. The data writing method according to claim 9, wherein the content addressable memory further comprises a first control pipe and a second control pipe, the control end of the first control pipe, the second control pipe The control end of the first control tube is connected to the control line; the first end of the first control tube is connected to the first bit line, and the second end of the first control tube is connected to the second plate of the first capacitor; the second control tube's The first end is connected to the second bit line, the second end of the second control transistor is connected to the second plate of the second capacitor, the first writing voltage is output to the first bit line, and the second writing voltage is output to the second bit line. Before inputting the voltage to write data to be written to the memory cell, the data writing method further includes:

    Controlling the first control tube and the second control tube to conduct.
11. A method for manufacturing a content-addressable memory, the content-addressable memory includes m rows and n columns of memory cells, m and n are integers greater than or equal to 1, and the memory cells include transistors, first capacitors, and second capacitors, the The control end of the transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor, the first end of the transistor is connected to the word line, the second end of the transistor is connected to the match line, the The second plate of the first capacitor is connected to the first bit line, and the second plate of the second capacitor is connected to the second bit line, wherein the method includes:

    forming a transistor on the substrate, the transistor including a control terminal, a first terminal and a second terminal;

    A first capacitor and a second capacitor are formed on the transistor, the first capacitor includes a first plate and a second plate, the second capacitor includes a first plate and a second plate, the first The first plate of the capacitor and the first plate of the second capacitor are electrically connected to the control terminal of the transistor.
12. The method according to claim 11, wherein said forming a transistor on the substrate comprises:

    forming a first terminal of the transistor on the substrate;

    The second terminal and the control terminal are formed on the side of the first terminal of the transistor away from the substrate, and the second terminal has a first side perpendicular to the substrate, and the control terminal has a first side perpendicular to the substrate. The end is located on the side facing the first side.
13. The method according to claim 11, wherein the forming the first capacitor and the second capacitor on the transistor comprises:

    forming a metal layer on the transistor, the metal layer is electrically connected to the control terminal, and the metal layer includes a first plate of the first capacitor and a first plate of the second capacitor;

    sequentially forming a first ferroelectric material layer and a second plate of the first capacitor on a side of the first plate of the first capacitor away from the substrate;

    A second ferroelectric material layer and a second plate of the second capacitor are sequentially formed on a side of the first plate of the second capacitor away from the substrate.
14. An electronic device, characterized in that the electronic device comprises a circuit board and a content-addressable memory electrically connected to the circuit board, and the content-addressable memory is the content according to any one of claims 1-6 addressing memory.

Images