CN113096710A

CN113096710A - Unit circuit and dynamic tri-state content addressing memory thereof

Info

Publication number: CN113096710A
Application number: CN202110467990.XA
Authority: CN
Inventors: 钟宏涛; 李学清; 曹胜杰; 刘勇攀; 杨华中
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2021-04-28
Filing date: 2021-04-28
Publication date: 2021-07-09
Anticipated expiration: 2041-04-28
Also published as: CN113096710B

Abstract

The invention discloses a unit circuit and a dynamic tri-state content addressable memory thereof. The unit circuit includes: a write operation switch, a nano-electromechanical relay and a search operation switch. The nanoelectromechanical relay includes a gate, a drain, and a source, wherein an on-off state or impedance state between the drain and the source is used to represent the stored data. The writing operation switch is connected with the grid electrode of the nano electromechanical relay so as to write the information stored in the nano electromechanical relay; the search operation switch is connected with the drain electrode or the source electrode of the nano electromechanical relay and is used for detecting whether input data are matched with data stored in the nano electromechanical relay. The invention effectively reduces the write operation power consumption of the tri-state content addressing memory by utilizing the nano electromechanical relay, improves the energy efficiency of the tri-state content addressing memory, and is a dynamic tri-state content addressing memory with low power consumption and low time delay.

Description

Unit circuit and dynamic tri-state content addressing memory thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a unit circuit and a dynamic tri-state content addressable memory thereof.

Background

Today, in the context of large data, many applications require frequent and highly parallel search operations on the data to find whether there is data matching the input, including traditional routing tables, address mapping or translation, emerging machine learning, DNA sequence matching, and so forth. Frequent and highly parallel search operations not only require the system to be computationally intensive, but also require high memory bandwidth and latency. However, due to the limitations of the memory wall, the conventional processor plus memory arrangement often has a large bandwidth and latency bottleneck when facing these applications.

To better meet the frequent and highly parallel search requirement, Ternary Content Addressable Memory (TCAM) is widely used in the scientific and industrial fields. TCAMs are developed from the basis of Content Addressable Memories (CAMs). The basic operations of the CAM include a write operation and a search operation. Each cell of the CAM has two storage states, '0' and '1'. A write operation may change the state of the CAM cell, while a search operation may detect whether the input data matches the stored data. The write operation is performed row by row, that is, only one row in the array can be written at a time. The search operation is performed simultaneously in the whole array, that is, all rows in the array are compared with the input data to judge whether the input data are matched or consistent. If the data stored in a certain row is completely matched with the input data, the address where the row of data is located is returned. It can be seen that the search operation is an operation with high parallelism and completed in the memory, and does not involve the data transportation process. In contrast to the CAM, the TCAM may store an additional don't care ' or X ' independent state in addition to ' 0 ' and ' 1 '. The irrelevant state means that the irrelevant state always matches with the input no matter the data of the input is '0' or '1', which means that the TCAM can not only do exact matching like CAM, but also do fuzzy matching.

At present, a commercial TCAM is mainly based on a CMOS process and a structure of 16 transistors (16Transistor CMOS SRAM-based TCAM, 16T CMOS TCAM) of an SRAM structure, and has an advantage of fast read/write speed, so that the TCAM can be applied to a plurality of scenes sensitive to speed and delay, however, the commercial TCAM also has many disadvantages, which are the same as challenges faced by the SRAM, and the commercial TCAM also has problems of too large cell area and high static leakage power consumption, and as moore's law advances, the Transistor size becomes smaller and smaller, and the problem of static leakage becomes more severe. To overcome these challenges, many active attempts have been made by the academia and industry. One effective way to do this is to utilize nonvolatile Memory devices, such as Magnetic Random Access Memories (MRAMs), memristors (rerams), Ferroelectric Field Effect transistors (fefets), and the like. Cell area of TCAM can be effectively reduced by using nonvolatile memory devices, such as "A3.14 um" published by S.Matsunaga et al in VLSIC 2012²4T-2MTJ-cell full parallel TCAM based on nonvolatile gate logic-in-memory architecture "proposed a 4Transistor plus 2Magnetic Tunnel junctions (4Transistor and 2Magnetic Tunnel junctions, 4T2MTJ) published in JSC 2013 by J.Li et al" 1Mb 0.41 μm²2T-2R cell nonvolatile TCAM with two-bit encoding and locked selected-compensated sensing "proposed a nonvolatile TCAM of 2 transistors plus 2 memristors (2Transistor and 2Resistive Random Access Memory,2T2R)," Design and benchmark of Ferroelectric FET based TCAM "of X.YIn et al on DATE 2017 proposed two nonvolatile TCAMs of 4 transistors plus two Ferroelectric transistors (4Transistor and 2Ferroelectric Field Effect Transistor, 4T2F), and" Anule-2 Fefel-FET based FET (2 TCAM 2) published by X.YIn et al on IEEE TCAS-II 2018. It can be seen that these non-volatile TCAM designs require significantly less devices than the 16T CMOS TCAM and thus can haveCell area is effectively reduced, thereby supporting greater capacity and higher energy efficiency. In addition, data of the nonvolatile device cannot be lost under the condition that the equipment stops supplying power, so that the nonvolatile TCAM can effectively solve the problem of electric leakage of the traditional TCAM based on the CMOS, and further, static electric leakage power consumption is greatly reduced. Despite the many advantages of non-volatile TCAMs, non-volatile TCAMs themselves have many problems and difficulties that are difficult to overcome, such as too high write power consumption, too long write delay, and difficult distinction of '0', '1' states in magnetic tunnel junctions and memristors, and fefets have too high operating voltages, problems of reading and writing information that may damage the stored information inside the cell, and so on, which have limited the development of non-volatile TCAMs to a considerable extent.

In addition to the design of non-volatile TCAMs, the academic and industrial community has also proposed the idea of designing TCAMs using dynamic circuits. For example, the "Dynamic tertiary CAM for hard search engine" published by v.vinogradov et al on Electronics Letters 2014 designs a Dynamic TCAM (5Transistor CMOS Dynamic TCAM, 5T CMOS TCAM) requiring only 5 transistors. The dynamic TCAM design only needs 5 transistors, 11 transistors are reduced compared with 16TCMOS TCAM, and the cell area is effectively reduced. The cost is that frequent refresh operations are required to maintain the data stored in the TCAM cell to ensure that the data is not lost, and the frequent refresh operations not only consume a large amount of refresh power, but also block normal write operations and search operations, affecting performance. And Bhati et al, in "DRAM refresh mechanisms, polarities, and trade-off" published by IEEE Transaction on Computers, indicate that the refresh problem will become more and more severe as the array size continues to increase.

In order to effectively reduce the cost brought by refreshing, A Low-Power Low-consistency Approach for Dynamic Memories published by H.Zhong et al in IEEE TCAS-II 2020 proposes a completely new One-step refreshing operation. The one-step refreshing is that the refreshing operations required by the '0' state and the '1' state in the array are the same, so that the number of times of driving the peripheral circuit when the refreshing operation is executed can be effectively reduced, the refreshing power consumption is reduced, the blockage of the refreshing on the normal access operation can be greatly reduced, and the performance is improved. In terms of specific circuit implementation, only an NMOS transistor for storing data needs to be replaced by a device with hysteresis curve characteristics, and a Nanoelectromechanical Relay (NEM Relay) mentioned in the present invention is a type of device with hysteresis characteristics.

The nano electromechanical relay is an electrically controlled mechanical switch and can be made into 3, 4 or 5 port configurations. The three-terminal nano electromechanical relay consists of a grid (G), a drain (D) and a source (S), and the four-terminal nano electromechanical relay consists of a grid (G), a drain (D), a source (S) and a base (B). The nanoelectromechanical relays have some common characteristics regardless of the number of ports. The nano electromechanical relay is a CMOS compatible device, has hysteresis characteristics, and controls the opening or closing of a channel between a drain and a source through a gate voltage. When the nano-relay is in an off state, a channel between the drain electrode and the grid electrode is separated by air, and the air separation mechanism enables the nano-electromechanical relay to have the characteristic of almost no electric leakage in the off state. In addition, the nano electromechanical relay also has the characteristics of low operating voltage, extremely low write power consumption, extremely low resistance between a drain electrode and a grid electrode in a conducting state, low write delay and the like, so that the unit circuit design based on the nano electromechanical relay can be used for higher access speed than the unit circuit design based on a nonvolatile memory device, and the system performance is further improved. Choe et al, TED 2019, "Ferroelectric-Gated nanoelectrotechnical Nonvolatile Memory Cell" reported operating voltages of less than 1V and lifetimes of up to 10¹³The nano-electromechanical relay of (1); while "Design Technology Co-Optimization for Back-End-of-Line Nonvolulatile NEM Switch Arrays" published by L.P.Tatum et al on TED 2021 reported write energies of only 0.01-0.03 fJ and lifetimes of more than 10¹⁵The nanoelectromechanical relay.

In summary, the conventional TCAM design based on the CMOS and SRAM structures has the problems of an excessively large cell area, high static leakage power consumption, non-ideality of the nonvolatile content TCAM, high operating voltage, high write delay and write power consumption, and frequent and costly refresh operation in the TCAM design based on the CMOS dynamic circuit.

Disclosure of Invention

The invention aims to provide a unit circuit and a dynamic tri-state content addressing memory thereof, in particular to a unit circuit and an array circuit of the dynamic tri-state content addressing memory based on a nano electromechanical relay.

The unit circuit provided by the invention has two different schemes:

the first one is: the circuit elements in the unit circuit comprise a first memory, a second memory, a first switch, a second switch, a third switch and a fourth switch, and the circuit nodes in the unit circuit comprise a first bit line, a second bit line, a first state line, a second state line, a write word line and a match line; the first memory and the second memory are both three-terminal nano electromechanical relays consisting of a grid electrode, a source electrode and a drain electrode, the grid electrode of the first memory is connected with a first bit line through a first switch controlled by a write word line, the drain electrode of the first memory is connected with a matched line through a second switch controlled by a first state line, and the source electrode of the first memory is grounded; the gate of the second memory is connected to the second bit line through a third switch controlled by the write word line, the drain of the second memory is connected to the match line through a fourth switch controlled by the second state line, and the source of the second memory is grounded.

The second method is as follows: circuit elements in the unit circuit comprise a third memory, a fourth memory, a fifth switch, a sixth switch and a seventh switch, and circuit nodes in the unit circuit comprise a first bit line, a second bit line, a first state line, a second state line, a write word line and a match line; the third memory and the fourth memory are four-end nano electromechanical relays consisting of a grid electrode, a source electrode, a drain electrode and a base electrode, the grid electrode of the third memory is connected with a first bit line through a fifth switch controlled by a write word line, the drain electrode of the third memory is connected with a first state line, the source electrode of the third memory is connected with a matched line through a seventh switch controlled by the first state line and a second state line, and the base electrode of the third memory is grounded; the grid electrode of the fourth memory is connected with the second bit line through a sixth switch controlled by the write word line, the drain electrode of the fourth memory is connected with the second state line, the source electrode of the fourth memory is connected with the matched line through a seventh switch controlled by the first state line and the second state line, and the base electrode of the fourth memory is grounded.

The dynamic three-state content addressing memory provided by the invention comprises a word line driver, a write operation/search operation buffer, a refresh operation driver, an encoder and an array circuit, wherein the array circuit at least adopts a unit circuit with the circuit structure, and part or all units of the array circuit are combined into a layout mode of a plurality of rows and a plurality of columns in an electrical connection mode; all write word lines in the array circuit are connected to the word line driver, all match lines are connected to the encoder, all first bit lines and second bit lines are connected to the write operation/search operation buffer and the refresh operation driver, and all first status lines and second status lines are connected to the write operation/search operation buffer.

The invention provides a unit circuit and a dynamic three-state content addressing memory thereof, which have the advantages that: the unit circuit provided by the invention is a unit circuit of a dynamic three-state content addressing memory based on a nano electromechanical relay, and the characteristics of the existing two nano electromechanical relays are utilized to ensure that the corresponding dynamic TCAM design unit has moderate area, low write operation power consumption, lower time delay, low search operation power consumption and higher speed. The dynamic three-state content addressable memory provided by the invention has the advantages of moderate area of a corresponding dynamic TCAM design unit, low write operation power consumption, low delay, low search operation power consumption, high speed, high service life, low refreshing cost and the like by utilizing the characteristics of low operating voltage of a nano electromechanical relay, low write power consumption, very small resistance between a drain electrode and a grid electrode in a conducting state, almost no electric leakage in a turn-off state, low write delay, long service life and the like and simultaneously matching with the hysteresis characteristic of the nano electromechanical relay and the one-step refreshing technology provided by H.ZHong and the like. Therefore, the dynamic tri-state content addressable memory is a content addressable memory which can effectively improve energy efficiency under the condition of low refreshing cost.

Drawings

The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a physical model diagram of a conventional nanoelectromechanical relay, fig. 1(a) is a network model diagram of a three-terminal nanoelectromechanical relay, and fig. 1(b) is a network model diagram of a four-terminal nanoelectromechanical relay.

Fig. 2 is a schematic structural diagram of a cell circuit according to the present invention, fig. 2(a) is a schematic circuit diagram of a 4T2N TCAM cell based on a three-terminal nano electromechanical relay, and fig. 2(b) is a schematic circuit diagram of a 3T2N TCAM cell based on a four-terminal nano electromechanical relay.

Fig. 3 is a circuit schematic of the dynamic tri-state content addressable memory proposed by the present invention.

FIG. 4 is a diagram illustrating a specific implementation of a write operation according to an embodiment of the invention.

Fig. 5 is a schematic diagram illustrating a specific implementation manner of a search operation according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating an implementation of a one-step refresh operation according to an embodiment of the invention.

FIG. 7 is a data diagram of simulation results of write operations according to embodiments of the present invention and prior art schemes.

FIG. 8 is a data diagram illustrating simulation results of a search operation according to some embodiments of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

The cell circuit and the array circuit of the dynamic tri-state content addressable memory based on the nano-electromechanical relay according to the embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows the physical model, circuit symbol and I of the three-port and four-port nano electromechanical relay used in the embodiment of the invention_D-V_GCharacteristic curve of which I_D-V_GThe characteristic curve has a hysteresis characteristic.

The unit circuit of the dynamic three-state content addressing memory based on the nano electromechanical relay has two different structures, wherein the first structure is shown in fig. 2(a), circuit elements in the unit circuit comprise a first memory N1, a second memory N2, a first switch M1, a second switch M2, a third switch M3 and a fourth switch M4, and circuit nodes in the unit circuit comprise a first bit line, a second bit line, a first state line, a second state line, a write word line and a match line; the first memory and the second memory are both three-terminal nano electromechanical relays consisting of grid electrodes, source electrodes and drain electrodes, and stored data are represented by on-off states or impedance states between the drain electrodes and the source electrodes of the nano electromechanical relays. The grid electrode of the first memory N1 is connected with a first bit line through a first switch M1 controlled by a write word line, the drain electrode of the first memory N1 is connected with a match line through a second switch M2 controlled by a first state line, and the source electrode of the first memory N1 is grounded; the gate of the second memory N2 is connected to the second bit line through a third switch M3 controlled by a write word line, the drain of the second memory N2 is connected to the match line through a fourth switch M4 controlled by a second state line, and the source of the second memory N2 is grounded. The first switch, the second switch, the third switch and the fourth switch as in fig. 2(a) are all implemented in the form of transistors. In one embodiment of the invention shown in fig. 2(a), the cell circuit comprises a total of 4 transistors and 2 three-terminal nano-electromechanical relays (4 transistors and 23-terminal NEM relay,4T 2N).

Second, as shown in fig. 2(b), the circuit elements in the unit circuit include a third memory N3, a fourth memory N4, a fifth switch M5, a sixth switch M6, and a seventh switch M7, and the circuit nodes in the unit circuit include a first bit line, a second bit line, a first state line, a second state line, a write word line, and a match line; the third memory and the fourth memory are four-end nano electromechanical relays consisting of a grid electrode, a source electrode, a drain electrode and a base electrode, the grid electrode of the third memory N3 is connected with a first bit line through a fifth switch M5 controlled by a write word line, the drain electrode of the third memory N3 is connected with a first state line, the source electrode of the third memory N3 is connected with a matching line through a seventh switch M7 controlled by the first state line and a second state line, and the base electrode of the third memory N3 is grounded; the gate of the fourth memory N4 is connected to the second bit line through a sixth switch M6 controlled by a write word line, the drain of the fourth memory N4 is connected to the second state line, the source of the fourth memory N4 is connected to the match line through a seventh switch M7 controlled by the first state line and the second state line, and the base of the fourth memory N4 is grounded. The fifth switch, the sixth switch and the seventh switch as shown in fig. 2(b) are all implemented in the form of transistors, and the control signal of the corresponding switch is connected to the gate of the transistor, and the switches are connected to the source and the drain of the transistor respectively. In one embodiment of the invention as shown in fig. 2(b), the cell circuit comprises a total of 3 transistors and 2 four-terminal nano-electromechanical relays (3 transistors and 24-terminal NEM relay,3T 2N).

FIG. 3 is a schematic diagram of the architecture of the dynamic tri-state content addressable memory based on the nano-electromechanical relay according to the present invention, which includes a word line driver for driving a write word line, a write operation/search operation buffer for buffering input data of write operation and search operation, a refresh operation driver for refresh operation, an encoder for encoding output result of a match line, and an encoder, and further includes an array circuit composed of a plurality of unit circuits, wherein the unit circuit at least employs a unit circuit as shown in FIG. 2, and some or all units of the array circuit are electrically connected to form a layout of rows and columns, and a first bit line, a second bit line, a first status line and a second status line of some or all unit circuits in a same column are respectively connected, and the write word line, the refresh word line, the encoder and the encoder of some or all unit circuits in a same row are respectively connected, The match lines are respectively connected; all write word lines in the array circuit are connected to the word line driver, all match lines are connected to the encoder, all first bit lines and second bit lines are connected to the write operation/search operation buffer and the refresh operation driver, and all first status lines and second status lines are connected to the write operation/search operation buffer.

Three basic operations of a nanoelectromechanical relay based dynamic tri-state content addressable memory implementation are described below in conjunction with figure 3: the specific operation modes of the write operation, the search operation and the refresh operation are divided into two unit circuits shown in fig. 2.

FIG. 4 illustrates a specific implementation of a write operation. The writing operation methods of the two unit circuits are consistent. During operation, a certain row in the array is selected for writing operation. The write Word Line (WL) of the selected row is first pulled up to a high level (VDD) and the transistor acting as a write switch is turned on. Placing a first Bit Line (BL) and a second Bit Line (BLB) at a potential corresponding to the written data, wherein if the voltage on the first Bit Line (BL) is pulled up to a high level (VDD), the voltage on the second Bit Line (BLB) is pulled down to a low level (GND), the voltage on the gate of the first memory N1 is at the high level, the voltage on the gate of the second memory N2 is at the low level, and the corresponding storage state is '1'; if the voltage on the first Bit Line (BL) is pulled down to the low level (GND), the voltage on the second Bit Line (BLB) is pulled up to the high level (VDD), and at this time, the voltage on the gate of the first memory N1 is at the low level, the voltage on the gate of the second memory N2 is at the high level, and the corresponding storage state is '0'; if the voltages on the first Bit Line (BL) and the second Bit Line (BLB) are both pulled down to the low level (GND), the voltages on the gates of the first and second memories N1 and N2 are both low, and the storage state is the unrelated item 'X'. FIG. 4(a) shows a schematic diagram of a 4T2N TCAM write operation based on a three-terminal nano-electromechanical relay; fig. 4(b) shows a schematic diagram of 3T2N TCAM write operation based on a four-terminal nano-electromechanical relay.

FIG. 5 illustrates a specific implementation of a search operation. The search operation methods of the two unit circuits are identical. In operation, all rows in the array are selected for a search operation. The Match Lines (ML) of all rows are first pulled up to high (VDD). The first State Line (SL) and the second State Line (SLB) are driven to potentials corresponding to an input state, if the voltage on the first State Line (SL) is pulled down to a low level (GND) and the voltage on the second State Line (SLB) is pulled up to a high level (VDD), the input state is '1', if the voltage on the first State Line (SL) is pulled up to the high level (VDD) and the voltage on the second State Line (SLB) is pulled down to the low level (GND), the input state is '0', and if the voltage on the first State Line (SL) is pulled down to the high level (GND) and the voltage on the second State Line (SLB) is pulled down to the low level (GND), the input state is an unrelated item 'X'. If the input state is the same as the storage state of the storage unit or at least one of the input state and the storage state of the storage unit is 'X', matching occurs, and the voltage on the matching line is unchanged; if the input state is different from the storage state of the memory cell and neither the input state nor the storage state of the memory cell is 'X', a mismatch occurs, and a pull-down path exists, so that the voltage on the match line is pulled down to a low level (GND). If all the cells in a certain row are matched, the voltage on the matched line is finally kept at a high level (VDD) to represent that the stored information in the changed row is completely matched with the input information; on the contrary, if any unit in a row is mismatched, the stored information of the changed row is not completely matched with the input information. The encoder encodes the match line output results on all the rows and finally returns the encoded results. FIG. 5(a) shows a schematic diagram of a 4T2N TCAM search operation based on a three-terminal nano-electromechanical relay; fig. 5(b) shows a schematic diagram of 3T2N TCAM search operation based on a four-terminal nano-electromechanical relay.

FIG. 6 shows the refresh operation process of the dynamic tri-state content addressable memory according to the present invention, wherein the refresh methods of the two array circuits are the same. In order to effectively reduce the cost brought by refreshing, the invention does not adopt the traditional row-by-row refreshing operation method, but adopts the one-step refreshing technology proposed by H.Zhong et al.

When refreshing, all rows in the array are selected to carry out refreshing operation. The voltage on the write Word Line (WL) of all rows is first pulled up to high level (VDD) and the transistor as a write switch is turned on. Placing the voltages on the first Bit Line (BL) and the second Bit Line (BLB) of all columns at a refresh Voltage (V) within the nanoperilay hysteresis window_R)，V_RRequire a Pull-down Voltage (V) greater than the left boundary of the hysteresis window of the nanorelay_PO) A Pull-in Voltage (V) less than the right boundary of the hysteresis window of the nano-relay_PI) I.e., as shown in fig. 6 (a). It can be seen that the same refresh operation can be used for refreshing whether the nanorelay is in the on state or the off state. Furthermore, regardless of whether the state stored in the cell circuit is '0', '1', or 'X', the refresh can be performed in the same manner, i.e., the full array is refreshed synchronously at once. FIG. 6(b) shows a schematic diagram of a 4T2N TCAM refresh operation based on a three-terminal nano-electromechanical relay; fig. 6(c) shows a schematic diagram of 3T2N TCAM refresh operation based on a four-terminal nano-electromechanical relay.

Further, in the embodiment of the present invention, two embodiments and other four existing TCAM schemes include: the power consumption and delay simulation of the write operation and the search operation of the array circuit with the size of 64 x 64 is carried out on dynamic 4T2N TCAM based on a three-terminal nano electromechanical relay, dynamic 3T2NTCAM based on a four-terminal nano electromechanical relay, 16T CMOS TCAM and 5T CMOS TCAM based on CMOS devices, 2T2RTCAM based on a memristor and 2FeFET TCAM based on a ferroelectric transistor.

FIG. 7 is a comparison of simulation data results of write operations according to two embodiments of the present invention and four existing TCAM schemes, wherein FIG. 7(a) is a comparison of delay of write operations and FIG. 7(b) is a comparison of energy consumption required to perform a write operation. As shown in FIG. 7(a), the abscissa is six simulation objects, and the ordinate is the write operation latency (unit: ns). As can be seen from FIG. 7, the minimum write operation delay is 16T CMOS TCAM and 5T CMOS TCAM, which is only 0.5 ns; in the prior art, due to the physical mechanism of nonvolatile devices such as memristors and ferroelectric transistors, the write operation time delay of 2T2R TCAM and 2FeFET TCAM is as long as 10 ns. However, both embodiments 4T2N TCAM and 3T2N TCAM of the invention have a delay of only about 2ns, namely the write delay of the nano-electromechanical relay.

As shown in FIG. 7(b), the abscissa is six simulation objects, and the ordinate is the energy (unit: fJ) consumed by the write-only operation. Since the memristor is a resistance-type device, 2T2R TCAM consumes relatively much energy during the write operation, and 46pJ of energy is consumed to perform the write operation once. For 2FeFET TCAM, since the ferroelectric transistor requires a relatively high operation voltage, 4.7pJ of energy is consumed to perform a write operation once. For 16T CMOS TCAMs and 5T CMOS TCAMs, since the two TCAMs require more transistors and the cell area is relatively large, energy of 0.81pJ and 0.45pJ is required to perform one write operation, respectively. However, the two embodiments of the present invention, 4T2N TCAM and 3T2N TCAM, require only 0.41pJ and 0.35pJ of energy to perform a write operation, respectively.

FIG. 8 is a comparison of simulation data results of search operations according to two embodiments of the present invention and four existing TCAM schemes. Fig. 8(a) is a comparison graph of search operation Delay, fig. 8(b) is a comparison graph of Energy consumption required to perform a search operation, and fig. 8(c) is a comparison graph of Energy consumption required to perform a search operation multiplied by search operation Delay (EDP). As shown in FIG. 8(a), the abscissa is six simulation objects, and the ordinate is search operation delay (unit: ps). Because the on-resistance of the nano electromechanical relay is very small, about only 1k omega, and the cell areas of the 4T2N TCAM and the 3T2N TCAM are small, the 4T2N TCAM only needs 126ps to execute one search operation; the 3T2NTCAM only needs 106ps to perform one search operation. Whereas 16T CMOS TCAM requires 582 ps; 5T CMOS TCAM requires 143 ps; 2T2R TCAM requires 155 ps; the 2FeFET TCAM requires 355 ps.

Further, as shown in FIG. 8(b), the abscissa is six simulation objects, and the ordinate is the consumed energy (unit: fJ) required to perform one search operation. Specifically, a 16T CMOS TCAM requires 1600fJ of energy to perform a search operation; 894fJ energy is needed for the 5T CMOS TCAM to execute one search operation; 2T2R TCAM requires 784fJ of energy to perform a search operation; the 2FeFET TCAM requires 584fJ of energy to perform a search operation; 4T2N TCAM requires 800fJ of energy to perform a search operation; the 3T2N TCAM requires 693fJ of energy to perform a search operation. It can be seen that 4T2N TCAM and 3T2N TCAM perform slightly worse than 2T2R TCAM and 2FeFET TCAM in terms of energy consumption, mainly because 2T2R TCAM and 2FeFET TCAM cell areas are smaller than 4T2N TCAM and 3T2NTCAM, and therefore parasitic capacitances are smaller, which in turn results in less energy being required to perform a search operation.

The EDP of the search operation can be obtained by multiplying the consumed energy for executing the search operation once by the search operation delay. Then, normalization processing is performed based on 3T2N TCAM. Six simulation objects with the abscissa and the normalized search operation EDP with the ordinate can be obtained as shown in fig. 8 (c). Wherein, the EDP of the search operation of 3T2N TCAM is 1; the search operation EDP of the 4T2NTCAM is 1.4; the search operation EDP for the 16T CMOS TCAM is 12.7; the search operation EDP for the 5T CMOS TCAM is 1.8; the search operation EDP of 2T2R TCAM is 1.7; the search operation EDP for 2FeFET TCAM was 2.8.

Furthermore, the terms "first", "second", "third", "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A unit circuit is characterized in that circuit elements in the unit circuit comprise a first memory, a second memory, a first switch, a second switch, a third switch and a fourth switch, and circuit nodes in the unit circuit comprise a first bit line, a second bit line, a first state line, a second state line, a write word line and a match line; the first memory and the second memory are both three-terminal nano electromechanical relays consisting of a grid electrode, a source electrode and a drain electrode, the grid electrode of the first memory is connected with a first bit line through a first switch controlled by a write word line, the drain electrode of the first memory is connected with a matched line through a second switch controlled by a first state line, and the source electrode of the first memory is grounded; the gate of the second memory is connected to the second bit line through a third switch controlled by the write word line, the drain of the second memory is connected to the match line through a fourth switch controlled by the second state line, and the source of the second memory is grounded.

2. The cell circuit of claim 1, wherein the first switch, the second switch, the third switch, and the fourth switch are implemented in the form of transistors.

3. A unit circuit is characterized in that circuit elements in the unit circuit comprise a third memory, a fourth memory, a fifth switch, a sixth switch and a seventh switch, and circuit nodes in the unit circuit comprise a first bit line, a second bit line, a first state line, a second state line, a write word line and a match line; the third memory and the fourth memory are four-end nano electromechanical relays consisting of a grid electrode, a source electrode, a drain electrode and a base electrode, the grid electrode of the third memory is connected with a first bit line through a fifth switch controlled by a write word line, the drain electrode of the third memory is connected with a first state line, the source electrode of the third memory is connected with a matched line through a seventh switch controlled by the first state line and a second state line, and the base electrode of the third memory is grounded; the grid electrode of the fourth memory is connected with the second bit line through a sixth switch controlled by the write word line, the drain electrode of the fourth memory is connected with the second state line, the source electrode of the fourth memory is connected with the matched line through a seventh switch controlled by the first state line and the second state line, and the base electrode of the fourth memory is grounded.

4. The cell circuit of claim 3, wherein the fifth switch, the sixth switch, and the seventh switch are all implemented in the form of transistors.

5. A dynamic ternary content addressable memory, comprising a word line driver, a write operation/search operation buffer, a refresh operation driver and an encoder, characterized in that the dynamic ternary content addressable memory further comprises an array circuit, wherein the array circuit at least adopts a unit circuit with the circuit structure as claimed in claims 1-4, and part or all units of the array circuit are combined into a layout mode of a plurality of rows and a plurality of columns by an electrical connection mode, and the first bit line, the second bit line, the first status line and the second status line of part or all unit circuits in the same column are respectively connected, and the write word line and the match line of part or all unit circuits in the same row are respectively connected; all write word lines in the array circuit are connected to the word line driver, all match lines are connected to the encoder, all first bit lines and second bit lines are connected to the write operation/search operation buffer and the refresh operation driver, and all first status lines and second status lines are connected to the write operation/search operation buffer.