WO2023093210A1 - 为存储器提供备电的方法和相关设备 - Google Patents

为存储器提供备电的方法和相关设备 Download PDF

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Publication number
WO2023093210A1
WO2023093210A1 PCT/CN2022/117591 CN2022117591W WO2023093210A1 WO 2023093210 A1 WO2023093210 A1 WO 2023093210A1 CN 2022117591 W CN2022117591 W CN 2022117591W WO 2023093210 A1 WO2023093210 A1 WO 2023093210A1
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WIPO (PCT)
Prior art keywords
memory
power
notification signal
computer device
module
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PCT/CN2022/117591
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English (en)
French (fr)
Inventor
贺斌
朱小洪
张洪岽
李春勇
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华为技术有限公司
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Publication of WO2023093210A1 publication Critical patent/WO2023093210A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/81—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits

Definitions

  • the present application relates to the field of memory, and more specifically, relates to a method for providing backup power for a memory, a computer device, a memory, a storage system, a computer device, a chip system, and a computer-readable storage medium.
  • the power backup modules of the memory of the storage system are mostly concentrated inside the memory.
  • the backup power module stores power.
  • the storage will rely on the power stored in the backup power module inside the storage for power failure protection.
  • the power-off protection process of the memory can safely write the cached data of the memory to the non-volatile storage medium of the memory, and maintain the integrity of the memory mapping table, so that the memory can be identified and available again after the system restores normal power supply .
  • the capacity of the cache memory (cache) in the memory keeps increasing.
  • the amount of data cached in the cache will also increase, and the power required for the power-off protection process will also increase accordingly.
  • the power stored in the backup power module cannot meet the power required for the power-off protection process. If the power stored in the backup power module is increased, the size of the entire memory will be increased.
  • An embodiment of the present application provides a method for providing backup power for a memory, a computer device, a memory, a storage system, a computer device, a chip system, and a computer-readable storage medium, which can meet the requirements of the power failure of the memory without increasing the size of the memory. Backup capacity requirements during the protection process.
  • a computer device in a first aspect, includes a power supply module, a backup power module and a controller.
  • the controller is used to detect the power supply status of the power supply module, and sends a backup power indication to the backup power module according to the power supply status; the backup power module is used to supply power to the memory connected to the controller according to the backup power indication.
  • the power supply module can supply power to the computer device and the memory.
  • the backup power module can receive the backup power indication from the controller when the controller determines that the power supply module cannot supply power to the controller and the storage, so as to supply power to the controller and the storage.
  • the power backup module can supply power to the controller and the memory in the computer device by receiving the power backup instruction from the controller. Therefore, there is no need to arrange an additional backup power module in the memory, no need to occupy space in the memory, and the size of the memory can be reduced. Moreover, since the backup power module in the computer device has relatively large backup power, it can meet the power demand of the memory during the power-off protection process. That is to say, in the computer device in this embodiment, the backup power module can have relatively large backup power without occupying the space of the memory, so as to meet the power demand of the memory during the power-off protection process.
  • the controller is further configured to send a first notification signal to the memory according to a power supply situation, where the first notification signal is used to instruct the memory to perform power-off protection.
  • the power-off protection of the memory may store the data in the cache memory of the memory into the storage medium of the memory. It should also be understood that when the controller determines that the power supply module cannot supply power to the controller and the storage, the controller may instruct the backup power module to start supplying power, that is, the backup power module supplies power for the controller to send the first notification signal to the storage.
  • the controller may send a first notification signal to the memory when the power supply module fails to supply power to the controller and the memory, so as to enable the memory to perform power-off protection, thereby avoiding loss of cached data in the memory due to power-off.
  • the controller is further configured to receive a second notification signal from the memory, and send an instruction to stop power backup to the power backup module according to the second notification signal, wherein the second The notification signal is used to indicate that the memory has completed the power-off protection; the backup power module is also used to stop supplying power to the memory according to the instruction to stop the backup power.
  • the controller may receive the second notification signal of the memory, and the second notification signal is used to notify the controller that the memory has completed power-off protection. After the controller receives the second notification signal from the memory, it can instruct the backup power module to stop supplying power.
  • the controller may instruct the backup power module to stop supplying power after receiving the second notification signal, so as to prevent the backup power module from continuing to work and wasting power when it is determined that the memory has completed power-off protection.
  • the controller is further configured to receive a third notification signal from the memory; in response to the third notification signal, stop writing data to the memory, and send data to the memory A first notification signal, the first notification signal is used to instruct the memory to perform power-off protection, and the third notification signal is used to instruct the memory to prepare for power-off protection.
  • the third notification signal from the memory indicates that the memory will be disconnected from the computer device, and power-off protection is required.
  • the controller After the controller receives the third notification signal from the memory, it can stop writing data into the memory, so as to prevent the memory from being unable to save the data subsequently written by the controller during the power-off protection process. After the controller stops writing data to the memory, it can send a first notification signal to the memory, instructing the memory to perform power-off protection.
  • the controller may receive a third notification signal from the memory when the memory is about to be disconnected from the computer device, thereby assisting the memory to complete power-off protection.
  • the first notification signal and the second notification signal are transmitted through a same signal interface of the computer device.
  • the first notification signal, the second notification signal and the third notification signal can all be transmitted through the signal interface of the computer device.
  • the interface for transmitting the above-mentioned signals is a low-speed signal interface, and the above-mentioned signals are all low-speed signals.
  • the low-speed signal is a non-high-speed signal
  • the high-speed signal can be a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) signal or a serial attached small computer system interface (serial attached small computer system interface, SAS) signal.
  • PCIE peripheral component interconnect express
  • SAS serial attached small computer system interface
  • the first notification signal, the second notification signal and the third notification signal may be transmitted between the computer device and the memory through a signal interface of the computer device. Therefore, when the power supply module cannot supply power to the controller and the memory and the memory is about to be disconnected from the computer device, the controller can send a notification signal to the memory and obtain a notification signal from the memory relatively quickly.
  • the computer device further includes a combination module, the input terminals of the combination module are respectively connected to the power supply module and the backup power module, and the output terminals of the combination module are connected to the controller and the memory Connected, the combiner module is specifically used to obtain power from the power supply module or backup power module to supply power to the controller or memory.
  • the power supply from the power supply module or the backup power module can be obtained through the combiner module, and supply power to the controller and memory. Therefore, the use of multiple hardware circuits for power supply can be avoided, resulting in waste of space and resources.
  • a memory in a second aspect, includes a control circuit, a cache and a non-volatile storage medium, and the control circuit is used to receive a first notification signal from a computer device connected to the memory, wherein the first notification signal is used to instruct the memory to perform power-off protection; the control circuit , is also used for performing power-off protection according to the first notification signal, so as to write the data in the cache into the non-volatile storage medium, wherein the memory is powered by the computer device during the power-off protection process.
  • the power-off protection of the memory may store the data in the cache memory of the memory into the storage medium of the memory.
  • the memory is protected against power failure by obtaining the power supply and the first notification signal from the computer device. Therefore, there is no need to arrange an additional backup power module in the memory, no need to occupy space in the memory, and the size of the memory can be reduced. Moreover, since the backup power module in the computer device can have relatively large backup power, it can meet the power demand of the memory during the power-off protection process. That is to say, in the memory in this embodiment, there is no need to additionally provide a backup power module, and the power backup module in the computer device connected to the memory can have a relatively large power backup capacity to meet the needs of the memory in the power-off protection process. power demand.
  • control circuit is further configured to send a second notification signal to the computer device, and the second notification signal is used to indicate that the memory has completed power-off protection.
  • the memory may send a second notification signal to the computer device after the power-off protection is completed, so that the computer device can turn off the power supply in time to avoid waste of resources.
  • the first notification signal and the second notification signal are transmitted through a same signal interface of the memory.
  • the first notification signal and the second notification signal can be transmitted between the computer device and the memory through a signal interface of the memory, so that the memory can send the notification signal to the computer device more quickly and obtain information from the computer device. notification signal.
  • control circuit is further configured to send a third notification signal to the computer device, and the third notification signal is used to indicate that the memory is ready for power-off protection.
  • the computer device may send the third notification signal to the computer device when it is determined that the memory is about to be disconnected from the computer device. After the memory sends the third notification signal to the computer device, the memory can receive the first notification signal from the computer device to perform power-off protection.
  • the memory may send a second notification signal to the computer device, indicating that the memory completes the power-off protection.
  • the first notification signal, the second notification signal and the third notification signal can all be transmitted through the same signal interface of the memory.
  • the interface for transmitting the above-mentioned signals is a low-speed signal interface, and the above-mentioned signals are all low-speed signals.
  • the low-speed signal is a non-high-speed signal
  • the high-speed signal can be a PCIE signal or a SAS signal.
  • the memory when the memory is about to be disconnected from the computer device, the memory may send a third notification signal to the computer device, so as to realize power-off protection with the assistance of the computer device.
  • a method for providing backup power for a memory includes: the computer device detects the power supply situation of the power supply module, wherein the computer device includes a power supply module and a backup power module; the computer device supplies power to a memory connected to the computer device through the backup power module in the computer device according to the power supply situation of the power supply module .
  • the computer device when the computer device determines that the power supply module cannot supply power to the computer device and the memory, it can supply power to the computer device and the memory through the backup power module, so as to avoid loss of cached data in the memory due to power failure. Therefore, there is no need to set up an additional backup power module in the memory, no need to occupy the space in the memory, and the size of the memory can be reduced. Moreover, since the backup power module in the computer device has relatively large backup power, it can meet the power demand of the memory during the power-off protection process. That is to say, in the computer device in this embodiment, the backup power module can have relatively large backup power without occupying the space of the memory, so as to meet the power demand of the memory during the power-off protection process.
  • the computer device sends a first notification signal to the memory according to a power supply situation, and the first notification signal is used to instruct the memory to perform power-off protection.
  • the power-off protection of the memory may store the data in the cache memory of the memory into the storage medium of the memory.
  • the computer device when the computer device determines that the power supply module cannot supply power to the computer device and the memory, it can instruct the memory to perform power-off protection, so as to prevent the memory from being unable to store cached data in time due to abnormal power failure.
  • the computer device receives a second notification signal from the memory, and the second notification signal is used to indicate that the memory has completed power-off protection; according to the second notification signal, the computer device, Stop using the backup power module to supply power to the storage.
  • the computer device may instruct the backup power module to stop power supply after receiving the second notification signal, so as to prevent the backup power module from continuing to work and wasting power when it is determined that the memory has completed power-off protection.
  • the computer device receives a third notification signal from the memory, and the third notification signal is used to indicate that the memory is ready for power-off protection; the computer device responds to the third notification signal, Stop writing data into the memory and send a first notification signal to the memory, where the first notification signal is used to instruct the memory to perform power-off protection.
  • the third notification signal from the memory indicates that the memory will be disconnected from the computer device, and power-off protection is required.
  • the computer device may stop writing data to the memory after receiving the third notification signal from the memory, so as to prevent the memory from being unable to save the data subsequently written by the controller during the power-off protection process.
  • the controller can send a first notification signal to the memory, thereby assisting the memory to implement power-off protection.
  • the first notification signal and the second notification signal are transmitted through a same signal interface of the computer device.
  • the first notification signal, the second notification signal and the third notification signal can all be transmitted through the signal interface of the computer device.
  • the interface for transmitting the above-mentioned signals is a low-speed signal interface, and the above-mentioned signals are all low-speed signals.
  • the low-speed signal is a non-high-speed signal
  • the high-speed signal can be a PCIE signal or a SAS signal.
  • the first notification signal, the second notification signal and the third notification signal may be transmitted between the computer device and the memory through a signal interface of the computer device. Therefore, when the power supply module cannot supply power to the controller and the memory and the memory is about to be disconnected from the computer device, the controller can send a notification signal to the memory and obtain a notification signal from the memory relatively quickly.
  • a power-off protection method includes: the memory receives a first notification signal from a computer device connected to the memory, the first notification signal is used to instruct the memory to perform power-off protection; the memory performs power-off protection according to the first notification signal, wherein the memory is powered off Power is supplied by the computer device during the protection process.
  • the power-off protection of the memory may store the data in the cache memory of the memory into the storage medium of the memory.
  • the memory is protected against power failure by obtaining the power supply and the first notification signal from the computer device. Therefore, there is no need to arrange an additional backup power module in the memory, no need to occupy space in the memory, and the size of the memory can be reduced. Moreover, since the backup power module in the computer device can have relatively large backup power, it can meet the power demand of the memory during the power-off protection process. That is to say, in the memory in this embodiment, there is no need to additionally provide a backup power module, and the power backup module in the computer device connected to the memory can have a relatively large power backup capacity to meet the needs of the memory in the power-off protection process. power demand.
  • the memory sends a second notification signal to the computer device, and the second notification signal is used to indicate that the memory has completed power-off protection.
  • the memory may send a second notification signal to the computer device after the power-off protection is completed, so that the computer device can turn off the power supply in time to avoid waste of resources.
  • the first notification signal and the second notification signal are transmitted through a same signal interface of the memory.
  • the first notification signal and the second notification signal can be transmitted between the computer device and the memory through the same signal interface of the memory, so that the memory can send the notification signal to the computer device more quickly and obtain information from the computer. Notification signal for the device.
  • the memory when it determines that it will be disconnected from the computer device, it sends a third notification signal to the computer device, and the third notification signal is used to indicate that the memory is ready to be disconnected. electric protection.
  • the storage device may receive the first notification signal from the computer device and start power-off protection. After the memory completes the power-off protection, the memory may send a second notification signal to the computer device, indicating that the memory has completed the power-off protection.
  • the first notification signal, the second notification signal and the third notification signal can all be transmitted through the same signal interface of the memory.
  • the interface for transmitting the above-mentioned signals is a low-speed signal interface, and the above-mentioned signals are all low-speed signals.
  • the low-speed signal is a non-high-speed signal
  • the high-speed signal can be a PCIE signal or a SAS signal.
  • the memory when the memory is about to be disconnected from the computer device, the memory may send a third notification signal to the computer device, so as to realize power-off protection with the assistance of the computer device.
  • a storage system in a fifth aspect, includes the computer device as described in the first aspect or any possible implementation manner of the first aspect, and the memory as described in the second aspect or any possible implementation manner of the second aspect.
  • a computer device in a sixth aspect, includes a processor, a power supply and a backup power supply.
  • the processor is used to be coupled with the memory, read and execute instructions and/or program codes in the memory, and execute the method described in the third aspect or any possible implementation of the third aspect in combination with the power supply and the backup power supply .
  • a memory in a seventh aspect, includes a processor, the processor is used to be coupled with the memory, read and execute instructions and/or program codes in the memory, so as to execute the method as described in the fourth aspect or any possible implementation manner of the fourth aspect .
  • a chip system in an eighth aspect, includes a logic circuit, which is configured to be coupled with an input/output interface, and transmit data through the input/output interface, so as to execute the method as described in the third aspect or any possible implementation manner of the third aspect.
  • a chip system in a ninth aspect, includes a logic circuit, which is configured to be coupled with an input/output interface, and transmit data through the input/output interface, so as to execute the method as described in the fourth aspect or any possible implementation manner of the fourth aspect.
  • a computer-readable storage medium stores program codes, and when the computer program codes run on the computer, the computer executes the method described in the third aspect or any possible implementation manner of the third aspect.
  • a computer-readable storage medium stores program codes, and when the computer program codes run on the computer, the computer executes the method according to the fourth aspect or any possible implementation manner of the fourth aspect.
  • FIG. 1 is a schematic architecture diagram of a storage system with separate disk control.
  • FIG. 2 is a schematic architecture diagram of a storage system integrating disk and control.
  • Fig. 3 is a schematic system architecture diagram of a storage system.
  • Fig. 4 is a schematic system architecture diagram of a storage system according to an embodiment of the present application.
  • Fig. 5 is a schematic flowchart of a method for providing backup power for a memory according to an embodiment of the present application.
  • Fig. 6 is a schematic flowchart of a method for providing backup power for a memory according to another embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of a memory according to an embodiment of the present application.
  • Fig. 9 is a schematic structural diagram of a storage system according to an embodiment of the present application.
  • FIG. 1 is a schematic architecture diagram of a storage system with separate disk control.
  • a user accesses data through an application program.
  • the computers running these applications are called "application servers".
  • the application server 110 may be a physical machine or a virtual machine. Physical application servers include, but are not limited to, desktops, servers, laptops, and mobile devices.
  • the application server accesses the storage system through the optical fiber switch 120 to access data.
  • the switch 120 is only an optional device, and the application server 110 can also directly communicate with the storage system 130 through the network.
  • the optical fiber switch 120 may also be replaced with an Ethernet switch, an infiniBand switch, or the like.
  • the storage system 130 in FIG. 1 is a centralized storage system.
  • the characteristic of the centralized storage system is that there is a unified entrance, and all data from external devices must pass through this entrance, and this entrance is the engine 140 of the centralized storage system.
  • the engine 140 is the most core component in the centralized storage system, where many advanced functions of the storage system are implemented.
  • controllers in the engine 140 there are one or more controllers in the engine 140 .
  • the engine includes two controllers as an example for illustration.
  • controller 1 fails controller 2 can take over the business of controller 1.
  • controller 2 fails controller 1 can take over the business of controller 2. business, so as to avoid the unavailability of the entire storage system 130 caused by hardware failure.
  • four controllers are deployed in the engine 140, there is a mirror channel between any two controllers, so any two controllers are mutual backups.
  • the engine 140 also includes a front-end interface 141 , a front-end interface 145 , a back-end interface 144 and a back-end interface 148 , wherein the front-end interfaces 141 and 145 are used to communicate with the application server 110 to provide storage services for the application server 110 .
  • the back-end interfaces 144 and 148 are used to communicate with the hard disk 153 to expand the capacity of the storage system. Through the back-end interfaces 144 and 148, the engine 140 can be connected with more hard disks 153, thereby forming a very large storage resource pool.
  • the controller 1 includes at least a processor 142 and a memory 143 .
  • the processor 142 is a central processing unit, used for processing data access requests from outside the storage system (server or other storage systems), and also used for processing requests generated inside the storage system. Exemplarily, when the processor 142 receives the write data request sent by the application server 110 through the front-end port 141 , it will temporarily save the data in the write data request in the memory 143 . When the total amount of data in the memory 143 reaches a certain threshold, the processor 142 sends the data stored in the memory 144 to the hard disk 153 for persistent storage through the back-end port.
  • the memory 143 refers to an internal memory directly exchanging data with the processor. It can read and write data at any time, and the speed is very fast. It is used as a temporary data storage for the operating system or other running programs.
  • Memory includes at least two kinds of memory, for example, memory can be either random access memory or read only memory (ROM).
  • the random access memory is, for example, dynamic random access memory (DRAM), or storage class memory (SCM).
  • DRAM is a semiconductor memory that, like most random access memory (RAM), is a volatile memory device.
  • SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage-class memory can provide faster read and write speeds than memory, but the access speed is slower than DRAM, and the cost is also cheaper than DRAM. .
  • the DRAM and the SCM are only illustrative examples in this embodiment, and the memory may also include other random access memories, such as static random access memory (static random access memory, SRAM) and the like.
  • the read-only memory for example, it may be programmable read-only memory (programmable read only memory, PROM), erasable programmable read-only memory (erasable programmable read only memory, EPROM) and the like.
  • the memory 143 can also be a dual-in-line memory module or a dual-line memory module (dual in-line memory module, DIMM), that is, a module composed of a dynamic random access memory, or a solid state memory (solid state disk). , SSD).
  • the controller 1 can be configured to have a power saving function.
  • the power saving function means that when the system is powered off and then powered on again, the data stored in the internal memory 143 will not be lost.
  • Memory with a power saving function is called non-volatile memory.
  • a software program is stored in the memory 143 , and the processor 142 runs the software program in the memory 143 to manage the memory.
  • the storage is abstracted into a storage resource pool, and then divided into logical unit numbers (logical unit number, LUN) for the server to use.
  • LUN logical unit number
  • the LUN here is actually the storage seen on the server.
  • some centralized storage systems are also file servers themselves, which can provide shared file services for servers.
  • controller 2 (and other controllers not shown in FIG. 1 ) are similar to those of the controller 1 and will not be repeated here.
  • Figure 1 shows a centralized storage system with separate disk control.
  • the engine 140 may not have a storage slot, the hard disk 153 needs to be placed in the hard disk enclosure 150 , and the back-end interface 144 communicates with the hard disk enclosure 150 .
  • the backend interface 144 exists in the engine 140 in the form of an adapter card, and one engine 140 can use two or more backend interfaces to connect multiple memory frames at the same time, such as the backend interfaces 144 and 148 .
  • the adapter card can also be integrated on the motherboard, and at this time the adapter card can communicate with the processor 142 or 146 through the PCIE bus.
  • the storage system may include two or more engines, and redundancy or load balancing is performed between multiple engines.
  • the hard disk enclosure 150 includes a control unit 151 and several hard disks 153 .
  • the control unit 151 may have various forms.
  • the hard disk enclosure 150 belongs to the smart disk enclosure, and as shown in FIG. 1 , the control unit 151 includes a CPU and a memory.
  • the CPU is used to perform operations such as address translation and reading and writing data.
  • the internal memory is used for temporarily storing data to be written into the hard disk 153, or data read from the hard disk 153 to be sent to the controller.
  • the control unit 151 is a programmable electronic component, such as a data processing unit (DPU).
  • DPU data processing unit
  • a DPU has the general purpose and programmability of a CPU, but is more specialized, operating efficiently on network packets, storage requests, or analytics requests.
  • DPUs are distinguished from CPUs by a greater degree of parallelism (the need to process a large number of requests).
  • the DPU here can also be replaced with a processing chip such as a graphics processing unit (graphics processing unit, GPU), an embedded neural network processor (neural-network processing units, NPU).
  • the number of control units 151 can be one, or two or more.
  • the hard disk enclosure 150 includes at least two control units 151 , there may be an ownership relationship between the hard disk 153 and the control units 151 . If there is an ownership relationship between the hard disk 153 and the control unit 151, each controller can only access the memory belonging to it, which often involves forwarding read/write data requests between the control units 151, resulting in a relatively narrow path for data access.
  • the functions of the control unit 151 can be offloaded to the network card 152 .
  • the hard disk enclosure 150 does not have the control unit 151 inside, but the network card 152 completes data reading and writing, address conversion and other computing functions.
  • the network card 152 is an intelligent network card. It can contain CPU and memory.
  • the network card 152 may also have a persistent memory medium, such as persistent memory (persistent memory, PM), or non-volatile random access memory (non-volatile random access memory, NVRAM), or phase change Memory (phase change memory, PCM), etc.
  • the CPU is used to perform operations such as address translation and reading and writing data.
  • the internal memory is used for temporarily storing data to be written into the hard disk 153, or data read from the hard disk 153 to be sent to the controller.
  • the hard disk enclosure 150 may be a SAS storage enclosure, or a non-volatile memory (non-volatile memory express, NVMe) storage enclosure or other types of storage enclosures.
  • the SAS storage box adopts the SAS3.0 protocol, and each box supports 25 pieces of SAS storage.
  • the engine 140 is connected to the hard disk enclosure 150 through an onboard SAS interface or a SAS interface module.
  • the NVMe storage box is more like a complete computer system, and the NVMe storage is inserted in the NVMe storage box.
  • the NVMe storage box is then connected to the engine 140 through the RDMA port.
  • the embodiment of the present application may be applied in the storage system with separate disk and controller shown in FIG. 1 .
  • FIG. 2 is a schematic architecture diagram of a storage system integrating disk and control.
  • the application server 210 and the switch 220 in FIG. 2 are respectively similar to the application server 110 and the switch 120 in FIG. 1 .
  • the storage system 230 in FIG. 2 includes an engine 240 and a hard disk 250, wherein the engine 240 is similar to the engine 140 in FIG. 1 and may include one or more controllers.
  • FIG. 2 is illustrated by taking the engine 240 including two controllers as an example.
  • the engine in Fig. 2 includes a controller 3 and a controller 4, wherein both controllers include a front-end interface, a processor, a memory, and a back-end interface. Similar to Figure 1, there is a mirror channel between the controller 3 and the controller 4, which can serve as backups for each other.
  • Figure 2 shows a centralized storage system with integrated disk control.
  • one or more memories may be included.
  • FIG. 2 is illustrated by taking multiple memories as an example.
  • the storage 250 does not need to be placed in the hard disk enclosure 150 shown in FIG. 1 , and the storage 250 can directly communicate with the controller 3 through the back-end port 244 , or communicate with the controller 4 through the back-end interface 248 .
  • the embodiment of the present application can be applied to the storage system with integrated disk and controller shown in FIG. 2 .
  • Fig. 3 is a schematic system architecture diagram of a storage system.
  • the storage system 300 can be divided into five parts, namely: a controller 310 , a memory 320 , a controller backup power module 330 , a power supply module 340 and a backplane 350 .
  • the controller 310 includes a high-speed control module 311 , a processing module 312 , a cache memory 313 and an internal circuit 314 .
  • the controller 310 may be the controller 1 or the controller 2 in the storage system with separate disk and control shown in FIG. 1 , or the controller 3 or 4 in the storage system with integrated disk and control shown in FIG. 2 .
  • the processor 142 shown in FIG. 1 may include a high-speed control module 311 and a processing module 312 .
  • the processor 146 may include a high-speed control module 311 and a processing module 312 .
  • the processor 242 shown in FIG. 2 may include a high-speed control module 311 and a processing module 312 .
  • the processor 246 may include a high-speed control module 311 and a processing module 312 .
  • the high-speed control module 311 can be directly or indirectly connected to the memory, and transmit high-speed signals between the controller 310 and the memory 320 through a high-speed signal interface, so as to issue services to the memory, such as writing data.
  • the high-speed signal can be a PCIE signal or a SAS signal.
  • the processing module 312 can be a motherboard management controller (baseboard management controller, BMC), a complex programmable logic device (complex programmable logic device, CPLD), or a micro control unit (microcontroller unit, MCU), etc., and can be controlled through a low-speed signal interface.
  • the low-speed signal is transmitted between the device 310 and the memory 320.
  • a low-speed signal is a non-high-speed signal. According to different low-speed signal interfaces, the types of low-speed signals can be different.
  • the Enterprise&Datacenter SSD Form Factor (EDSFF) interface can include undefined signals (manufacturing mode for device, MFG), protocol reserved signals (reserved for future use, RFU), system management bus (system management bus, SMBUS), reset device management interface signal (SMBUS reset, SMBRST#), host lighting signal (light emitting diode, LED), disk power enable signal (power disable, PWRDIS), disk presence signal (present, PRSNT#).
  • undefined signals manufacturing mode for device, MFG
  • protocol reserved signals reserved signals reserved signals (reserved for future use, RFU)
  • system management bus system management bus
  • SMBUS reset device management interface signal SMBUS reset, SMBRST#
  • host lighting signal light emitting diode, LED
  • disk power enable signal power disable, PWRDIS
  • disk presence signal present, PRSNT#.
  • Another example 8639 interface can include: wake-up signal (wake, Wake#), disk power enable (PWRDIS), interface type detection signal (interface detect, IfDet#), disk in-position signal (PRSNT#), status indication signal (activity, ACTIVITY#), reserved signal (reserved), system management bus (SMBUS).
  • the cache memory 313 is a cache memory inside the controller 310 for storing data.
  • the cache memory 313 may be an SRAM, or may be the memory 143 or the memory 147 shown in FIG. 1 , or may be the memory 243 or 247 shown in FIG. 2 .
  • the internal circuit 314 is a hardware circuit inside the controller 310 and can provide circuit support for components inside the controller 310 .
  • the internal circuit 314 may include two power input terminals, wherein the first power input terminal of the internal circuit 314 may be connected to the power supply module 340, and the second power input terminal of the internal circuit 314 may be connected to the controller backup power module 330, so that the power supply Both the module 340 and the controller backup module 330 can provide power for the controller 310 .
  • the memory 320 includes a cache memory 321 , a power backup module 322 , a combiner module 323 and an internal circuit 324 .
  • the cache memory 321 is a cache memory inside the memory 320 and may be an SRAM.
  • a cache with a smaller capacity may have a space of 1 to 10 GB, and a cache with a larger capacity may have a space of 10 to 100 GB, or even higher. If the cache capacity of the memory 320 is small, most of the caches of the storage system are concentrated in the controller 310, and the cache with a smaller capacity inside the memory 320 is only used for the normal operation of the memory itself, that is, the cache memory 313 has a larger capacity cache, the cache memory 321 is a cache with a smaller capacity. At this time, there is no cache access interface between the controller 310 and the memory 320 , and the controller 310 will not occupy the cache resources inside the memory 320 .
  • the memory 320 may provide a cache access interface for the controller 310 to access.
  • the controller 310 may occupy cache resources inside the memory 320 .
  • the cache memory 321 in FIG. 3 may be the control unit 151 in FIG. 1 .
  • the network card 152 may include a CPU and a memory, and at this time, the cache memory 321 in FIG. 3 may be the network card 152 . Therefore, the memory 320 in FIG.
  • the controller 310 in FIG. 3 may include the control unit 151 and the hard disk 153 in FIG. 1 , or may include the network card 152 and the hard disk 153 .
  • the storage 320 may also be the hard disk 250 in FIG. 2 .
  • the controller 310 in FIG. 3 may occupy resources of the cache memory 321 .
  • the controller 310 in FIG. 3 may include the controller 1 and the control unit 151 in FIG. 1 , or may include the controller 1 and the network card 152 in FIG. 1 , or may include the controller 2 and the control unit in FIG. 1 151, or may include the controller 2 and the network card 152 in FIG. 1 .
  • the backup power module 322 can supply power to the memory 320 when the power supply module 340 fails to supply power normally.
  • the memory 320 may write the cached data in the cache memory 321 into a non-volatile storage medium inside the memory.
  • the combining module 323 may include two power input terminals and one power output terminal.
  • the first power input terminal of the combining module 323 is connected to the power supply module 340
  • the second power input terminal of the combining module 323 is connected to the backup power module 322
  • the power output terminal of the combining module 323 is connected to the internal circuit 324 .
  • the combining module 323 can combine the power inputs of the power supply module 340 and the backup power module 322 , so that both the power supply module 340 and the backup power module 322 can supply power for the internal circuit 324 .
  • the internal circuit 324 is a hardware circuit inside the memory 320 and can provide circuit support for components inside the memory 320 .
  • the storage 320 in FIG. 3 may be the hard disk 153 in the storage system with separate disk and control shown in FIG. 1 , or the hard disk 250 in the storage system with integrated disk and control shown in FIG. 2 .
  • the controller backup power module 330 is connected to the internal circuit 314 of the controller 310 and can supply power to the controller 310 when the power supply module 340 cannot supply power to the controller 310 .
  • the power supply module 340 is the power supply of the system 300, and can supply power to the controller 310 and the memory 320 when the power supply module 340 is working normally.
  • the backplane 350 can directly provide a signal path for the controller 310 and the memory 320 , and can also provide a power path for the memory 320 .
  • the high-speed control module 311 in the controller 310 stops sending services to the memory 320 through the high-speed signal interface.
  • the memory 320 starts to implement power loss protection (power loss protection, PLP), that is, the cached data in the cache memory 321 is written into the non-volatile storage medium of the memory 320, and the mapping table of the memory 320 can also be kept intact.
  • the controller power backup module 330 provides power support for the controller 310 to write the cache data in the cache memory 313 to the memory 320, and the power backup module 322 writes the cache data in the cache memory 321 to the memory 320 for the memory 320. Power support is provided in volatile storage media.
  • the backup power module 322 can only provide a backup time of millisecond (ms) level. With the evolution of technology, the cache capacity in the memory 320 is getting larger and larger, and it is more likely that the power stored in the backup power module cannot meet the actual demand. The problem.
  • Fig. 4 is a schematic system architecture diagram of a storage system according to the present application.
  • the storage system 400 may include a controller 410 , a memory 420 , a power backup module 430 , a power supply module 440 , a combiner module 450 and a backplane 460 .
  • the controller 410 includes a high-speed control module 411, a processing module 412, a cache memory 413, a high-speed signal interface 414, a low-speed signal interface 415 and a power supply interface 416.
  • the controller 410 in FIG. 4 may be the controller 1 or the controller 2 in the storage system with separate disk and control shown in FIG. controller4.
  • the processor 142 shown in FIG. 1 may include a high-speed control module 411 and a processing module 412 .
  • the processor 146 may include a high-speed control module 411 and a processing module 412 .
  • the processor 242 shown in FIG. 2 may include a high-speed control module 411 and a processing module 412 .
  • the processor 246 may include a high-speed control module 411 and a processing module 412 .
  • the high-speed control module 411 can implement communication between the controller 410 and the memory 420 through the high-speed signal interface 414, and can also send high-speed signals to the memory 420, that is, deliver services to the memory, such as writing data.
  • the processing module 412 can detect the power supply of the power supply module 440 , and instruct the backup power module 430 to start supplying power when the power supply module 440 cannot supply power to the controller 410 and the memory 420 .
  • the processing module 412 may also instruct the backup power module to stop power supply when it is determined that the memory 420 has completed the power-off protection.
  • the processing module 412 can also notify the upper-layer software through computer software or drivers, and then the upper-layer software notifies the high-speed control module 411, so that the high-speed control module 411 stops sending services to the memory 420 through the high-speed signal interface 414 .
  • the processing module 412 can also realize the communication between the controller 410 and the memory 420 through the low-speed signal interface 415, and send a low-speed signal to the memory 420 to assist the memory 420 in power-off protection.
  • the cache memory 413 is a cache memory inside the controller 410 and can be used to store data.
  • the cache memory 413 may be an SRAM, or may be the memory 143 or the memory 147 shown in FIG. 1 , or may be the memory 243 or 247 shown in FIG. 2 .
  • the high-speed signal interface 414 can transmit high-speed signals between the controller 410 and the memory 420 .
  • the high-speed signal can be a PCIE signal or a SAS signal.
  • the low-speed signal interface 415 can transmit low-speed signals between the controller 410 and the memory 420 .
  • a low-speed signal is a non-high-speed signal.
  • the power interface 416 is connected to the power output terminal 453 of the combiner module 450 to obtain power from the backup power module 430 or the power supply module 440 .
  • the memory 420 includes a control circuit 421 , a non-volatile storage medium 422 , a cache memory 423 , a high-speed signal interface 424 , a low-speed signal interface 425 and a power supply interface 426 .
  • the control circuit 421 can receive a high-speed signal from the controller 410 through the high-speed signal interface 424 to complete data read and write operations.
  • the control circuit 421 can also receive a low-speed signal from the controller 410 through the low-speed signal interface 425, so as to realize power-off protection.
  • the low-speed signal received by the control circuit 421 may be a first notification signal.
  • the first notification signal is used to notify the memory 420 to perform power-off protection when the power supply module 440 cannot supply power to the controller 410 and the memory 420 .
  • the control circuit 421 can also send a low-speed signal to the controller 410 through the low-speed signal interface 425, and the low-speed signal can be the second notification signal or the third notification signal.
  • the second notification signal is used to notify the controller 410 that the memory 420 has completed the power-off protection.
  • the third notification signal is used to notify the controller 410 that the memory 420 is ready for power-off protection when the memory 420 is about to be disconnected from the controller 410 .
  • the power-off protection of the memory 420 can write the data in the cache memory 423 of the memory 420 into the non-volatile storage medium 422 , and can also maintain the integrity of the mapping table of the memory 420 .
  • the non-volatile storage medium 422 is a non-volatile storage medium inside the memory 420, and can realize the data storage function inside the memory.
  • the non-volatile storage medium 422 may be a flash memory (flash), or a PROM, or an EPROM, etc., which is not limited in this embodiment of the present application.
  • the cache memory 423 is a cache memory inside the memory and can be used to store cached data.
  • Cache memory 423 may be SRAM.
  • the memory 420 may include a cache access interface, so that the controller 410 can perform read and write access to the cache memory 423 .
  • the cache memory 423 in FIG. 4 may be the control unit 151 in FIG. 1 .
  • the network card 152 may include CPU and memory, and at this time, the cache memory 423 in FIG. 4 may be the network card 152 . Therefore, the memory 420 in FIG. 4 may include the control unit 151 and the hard disk 153 in FIG. 1 , or may include the network card 152 and the hard disk 153 .
  • the storage 420 can also be the hard disk 250 in FIG. 2 .
  • the high-speed signal interface 424 may be connected to the high-speed signal interface 414 in the controller 410 through the backplane 460 . Through the high-speed signal interface 414 and the high-speed signal interface 424 , high-speed signals can be transmitted between the controller 410 and the memory 420 .
  • the low-speed signal interface 425 may be connected to the low-speed signal interface 415 in the controller 410 through the backplane 460 . Through the low-speed signal interface 415 and the low-speed signal interface 425 , low-speed signals can be transmitted between the controller 410 and the memory 420 .
  • the power interface 426 is connected to the power output terminal 453 of the combiner module 450 to obtain power from the backup power module 430 or the power supply module 440 .
  • the storage 420 in FIG. 4 may be the hard disk 153 in the storage system with separate disk and control shown in FIG. 1 , or the storage 250 in the storage system with integrated disk and control shown in FIG. 2 .
  • the control circuit 421 and the cache memory 423 in FIG. 4 can jointly constitute the control unit 151 or the network card 152 in FIG. 1 , so the control unit 151, the network card 152 and the hard disk 153 in FIG.
  • the memory 420 may further include a switch 427 .
  • the switch 427 is a switch that detects whether the memory 420 is about to be disconnected from the controller 410 . When the switch 427 detects that the memory 420 is not disconnected from the controller 410, the switch 427 may send a stable access signal to the control circuit 421, indicating that the current memory 420 is in a stable access state. When the switch 427 detects that the memory 420 is about to be disconnected from the controller 410, the switch 427 may send a disconnection indication signal to the control circuit 421, indicating that the memory is about to be disconnected.
  • the control circuit 421 may receive a stable access signal from the switch 427 to determine that the memory 420 is stably connected to the controller 410 . The control circuit 421 may also receive a disconnection indication signal from the switch 427 to determine that the memory 420 will be disconnected from the controller 410 .
  • the purpose of controlling the switch 427 can be achieved by flicking open or closing the handle bar 428 .
  • the handle bar 428 can be a switch with a locking property.
  • the handle bar 428 may be closed, so that the switch 427 detects that the memory 420 is not disconnected from the controller 410 .
  • the handle bar 428 can be popped up, so that the switch 427 detects that the memory 420 is about to be disconnected from the controller 410 .
  • the switch 427 may be a photoelectric switch.
  • the memory 420 may also include an indicator light.
  • the indicator light may be used to indicate that the memory 420 is about to be disconnected from the controller 410, or to indicate that the memory is under power-off protection, or to indicate that the memory has completed power-off protection, and the like.
  • the indicator light may be fixedly on or off, or flash at a certain frequency, which is not limited in this embodiment of the present application.
  • the controller 410 may notify the upper-layer software, so that the operation interface of the upper-layer software displays that the memory has started power-off protection or completed power-off protection, etc. .
  • the power backup module 430 may receive a power backup instruction from the controller 410 and supply power to the controller 410 and the memory 420 .
  • the power backup module 430 may start to supply power after receiving the power backup instruction.
  • the power backup module 430 may also receive an instruction to stop power backup from the controller 410 , and stop supplying power to the controller 410 and the memory 420 .
  • the power backup module 430 can stop power supply after receiving the instruction to stop power backup.
  • the power backup module 430 can provide a power backup time of second (s) level, or tens of seconds level.
  • the power supply module 440 is the power supply of the system 400 and can supply power to the controller 410 and the memory 420 during normal operation.
  • the combining module 450 includes a power input terminal 451 , a power input terminal 452 and a power output terminal 453 .
  • the power input terminal 451 of the combiner module 450 is connected to the backup power module 430
  • the power input terminal 452 is connected to the power supply module 440
  • the power output terminal 453 can be connected to the power interface 416 of the controller 410 and the power interface 426 of the memory 420 .
  • the combining module 450 can combine the power input of the backup power module 430 and the power supply module 440 , so that the backup power module 430 or the power supply module 440 can supply power for the controller 410 or the memory 420 .
  • the backplane 460 can provide a signal path for the controller 410 and the memory 420 , and can also provide a power path for the memory 420 .
  • controller 410 and the memory 420 may be integrated, and the backplane 460 may be omitted in this case.
  • the power backup module 430 may be an independent power backup unit outside the controller 410 .
  • the power backup module 430 can be separated from the controller 410 and used as a field replaceable unit (field replace unit, FRU).
  • the power backup module 430 and the controller 410 can also be combined into a FRU unit.
  • controller 410 the backup power module 430, and the power supply module 440 can all be used as a single FRU unit, or any number of them can be combined into a FRU unit.
  • the backup power module in the computer device has relatively large backup power, it can meet the power demand of the memory during the power-off protection process. That is to say, in the storage system shown in FIG. 4 , the backup power module can have relatively large backup power without occupying the storage space, so as to meet the power demand of the storage during the power-off protection process.
  • the storage system in FIG. 4 can also transmit any one of the first notification signal, the second notification signal or the third notification signal through the same low-speed signal interface, so that the computer device and the memory can transmit signals to each other relatively quickly.
  • Fig. 5 is a schematic flowchart of a method for providing backup power for a memory according to the present application.
  • the method in Fig. 5 includes the following contents.
  • the computer device detects that the power supply module cannot supply power normally, and instructs the backup power module to start supplying power.
  • the power supply module works normally, it can supply power to the computer device and the memory connected to the computer device.
  • the power supply module fails to supply power to the computer device and the memory, the computer device can detect that the power supply module cannot supply power normally, and thus instructs the backup power module to start supplying power.
  • the computer device may instruct the backup power module to start supplying power by sending a backup power instruction to the backup power module.
  • the power backup indication can be used to instruct the power backup module to start supplying power.
  • the backup power module supplies power to the computer device and the memory after receiving the backup power indication.
  • the backup power module can supply power for the computer device and the storage in the computer device, so that the backup power module can have a large backup power while not occupying the space of the storage. In this way, the power backup module can meet the power demand of the memory during the power-off protection process.
  • the computer device sends a first notification signal to the memory.
  • the computer device may send a first notification signal to the storage, and the first notification signal may be used to notify the storage to perform power-off protection.
  • the computer device may stop delivering services to the memory, such as writing data. After the computer device stops sending services to the memory, no new data will be written into the memory, and the power-off protection of the memory at this time will not cause data loss. After the computer device stops delivering services to the storage, it may send the first notification signal to the storage.
  • the first notification signal may be sent through a low-speed signal interface of the computer device.
  • the first notification signal may be a fixed high or low level, or a pulse signal for a period of time, which is not specifically limited in this embodiment of the present application.
  • the computer device when the computer device sends the first notification signal to the memory, the computer device may set the memory to state indication 1, which may indicate that the memory is under power-off protection and cannot be pulled out.
  • the status indication 1 may be that the indicator light on the memory is permanently on or blinks at a certain frequency, which is not specifically limited in this embodiment of the present application.
  • the memory receives the first notification signal, and performs power-off protection.
  • the memory After receiving the first notification signal from the computer device, the memory performs power-off protection.
  • the power-off protection process of the memory may write the cached data in the cache inside the memory into the storage medium inside the memory.
  • the storage may set itself as status indication 1, which may indicate that the storage is under power-off protection and cannot be pulled out.
  • the status indication 1 may be that the indicator light on the memory is permanently on or blinks at a certain frequency, which is not limited in this embodiment of the present application.
  • the memory completes power-off protection, and the memory sends a second notification signal to the computer device.
  • the memory After the memory completes power-off protection, that is, all cached data in the internal cache of the memory is written into the non-volatile storage medium inside the memory, and after the mapping table of the memory is completely saved, the memory can send a second notification signal to the computer device.
  • the second notification signal may be used to indicate that the memory has completed power-off protection.
  • the second notification signal may be sent by the memory through a low-speed signal interface.
  • the second notification signal may be a fixed high or low level or a pulse signal for a period of time, which is not limited in this embodiment of the present application.
  • the type of the second notification signal may or may not be the same as that of the first notification signal in steps S520 and S530. That is, the first notification signal and the second notification signal can both be of a fixed high or low level, or both can be a pulse signal for a period of time, or one can be a fixed high or low level, and the other can be a pulse signal for a period of time. This is not limited.
  • the contents of the two may or may not be consistent. That is, when the first notification signal and the second notification signal are both at a fixed high and low level, they may both be at a fixed high level, or both may be at a fixed low level, or one may be at a high level and the other may be at a low level.
  • both the first notification signal and the second notification signal are pulse signals for a certain period of time, they may both be consistent pulse signals or inconsistent pulse signals, which is not limited in this embodiment of the present application.
  • both the first notification signal and the second notification signal can be sent through a low-speed signal interface, so that the computer device and the memory can transmit signals to each other relatively quickly.
  • the memory may set itself as a status indicator 2, which may indicate that the memory has completed the power-off protection and can be pulled out.
  • the status indication 2 may be that the indicator light on the memory is off or flickers at a certain frequency, which is not limited in this embodiment of the present application.
  • the memory can be pulled out after power-off protection is completed.
  • the memory can set itself as status indication 2, indicating that the memory has completed the power-off protection and can be pulled out.
  • the computer device receives a second notification signal, instructing the backup power module to end power supply.
  • the computer device After receiving the second notification signal from the memory, the computer device can instruct the backup power module to stop supplying power.
  • the backup power module may be instructed to stop power supply by sending a power backup stop indication to the power backup module, and the power backup stop indication may be used to instruct the power backup module to stop power supply.
  • the backup power module stops supplying power to the computer device and the memory after receiving the instruction to stop the backup power.
  • the computer device may set the memory to state indication 2, which indicates that the memory has completed power-off protection and can be pulled out.
  • the status indication 2 may be that the indicator light on the memory is off or flickers at a certain frequency, which is not limited in this embodiment of the present application.
  • the computer device can set the memory to state indication 2, indicating that the memory has completed power-off protection and can be pulled out.
  • the computer device may send a power-off signal to the memory.
  • the power-off signal may be a disk power enable signal, which is used to instruct the memory to turn off the power.
  • the memory can be pulled out after disconnecting the power supply.
  • the computer device can set the memory to state indication 2, indicating that the memory has completed power-off protection and can be pulled out.
  • some components in the computer device may still be in working state, such as a high-speed controller or a cache in the controller.
  • an instruction to stop the backup power can be sent to the backup power module to instruct the backup power module to end the power supply.
  • each step in step S520 to step S550 can be powered by the backup power module. Since there is no need to set an additional backup power module in the memory, no space in the memory is occupied, and the size of the memory can be reduced. Moreover, since the backup power module in the computer device has relatively large backup power, it can meet the power demand of the memory during the power-off protection process. That is to say, in this embodiment, the backup power module can have relatively large backup power without occupying the space of the memory, so as to meet the power demand of the memory during the power-off protection process. In the method in FIG. 5 , the first notification signal and the second notification signal can also be transmitted through the same signal interface, so that the computer device and the memory can transmit signals to each other relatively quickly.
  • Fig. 6 is a schematic flowchart of another method for providing backup power for a memory according to the present application.
  • the method in Fig. 6 includes the following contents.
  • the memory acquires a disconnection indication signal.
  • the memory can obtain a disconnection indication signal, indicating that the memory will be disconnected and needs to be prepared for power-off protection.
  • a switch in the memory may send a disconnection indication signal to the memory, and the disconnection indication signal may be a fixed high or low level.
  • the memory may set itself as status indication 3, indicating that the memory is under power-off protection and cannot be pulled out.
  • the status indication 3 may be that the indicator light on the memory is fixedly lit or flashes at a certain frequency, or the status indication 3 may be displayed on the operation interface of the upper layer software, which is not specifically limited in this embodiment of the present application.
  • the switches in the memory may be photoelectric switches.
  • the memory sends a third notification signal to the computer device.
  • the memory may send a third notification signal to the computer device.
  • the third notification signal may be used to indicate that the current memory is about to be disconnected, and power-off protection needs to be prepared.
  • the third notification signal may be sent by the memory through a low-speed signal interface.
  • the third notification signal may be a fixed high or low level, or a pulse signal for a period of time.
  • the computer device receives the third notification signal, and sends the first notification signal to the memory.
  • the computer device may send the first notification signal to the memory, where the first notification signal is used to notify the memory to perform power-off protection.
  • the memory cannot save all the data.
  • the computer device may stop delivering services to the storage.
  • the computer device may send a first notification signal to the storage, instructing the storage to perform power-off protection.
  • the first notification signal may be sent by the computer device through a low-speed signal interface.
  • the first notification signal may be a fixed high or low level, or a pulse signal for a period of time, which is not specifically limited in this embodiment of the present application.
  • the computer device when the computer device sends the first notification signal to the memory, the computer device may set the memory to state indication 3, which may indicate that the memory is under power-off protection and cannot be pulled out.
  • the status indication 3 may be that the indicator light on the memory is fixedly lit or flashes at a certain frequency, or the status indication 3 may be displayed on the operation interface of the upper layer software, which is not specifically limited in this embodiment of the present application.
  • the memory receives the first notification signal, and performs power-off protection.
  • the memory After receiving the first notification signal from the computer device, the memory performs power-off protection.
  • the power-off protection process of the memory may write the cached data in the internal cache of the memory into the storage medium inside the memory.
  • the storage may set itself as status indication 1, which may indicate that the storage is under power-off protection and cannot be pulled out.
  • the status indication 1 may be that the indicator light on the memory is permanently on or blinks at a certain frequency, which is not limited in this embodiment of the present application.
  • the memory After the memory completes the power-off protection, that is, all the cached data in the internal cache of the memory is written into the storage medium inside the memory, and after the mapping table of the memory is saved completely, the memory can send a second notification signal to the computer device.
  • the second notification signal is used to indicate that the memory has completed power-off protection.
  • the second notification signal may be sent by the memory through a low-speed signal interface.
  • the second notification signal may be a fixed high or low level or a pulse signal for a period of time, which is not limited in this embodiment of the present application.
  • the second notification signal may or may not be the same type as the third notification signal and the first notification signal in the above steps. That is, any one or more of the first notification signal, the second notification signal, and the third notification signal may be a fixed high or low level, or any one or more of them may be a pulse signal for a period of time. limited.
  • the contents of the three may or may not be consistent. That is, when the first notification signal, the second notification signal and the third notification signal are all fixed high and low levels, any one or more may be fixed high level, or any one or more may be fixed low level .
  • the first notification signal, the second notification signal and the third notification signal are all pulse signals for a period of time, any one or more of them may be consistent pulse signals, or any one or more of them may be inconsistent pulse signals.
  • the application embodiments do not limit this.
  • the first notification signal, the second notification signal and the third notification signal can all be sent through a low-speed signal interface, so that the computer device and the memory can transmit signals to each other relatively quickly.
  • the memory may set itself as a status indicator 2, which may indicate that the memory has completed the power-off protection and can be pulled out.
  • the status indication 2 may be that the indicator light on the memory is off or flickers at a certain frequency, which is not limited in the embodiment of the present application.
  • the memory can be pulled out after power-off protection is completed.
  • the memory can set itself as status indication 2, indicating that the memory has completed the power-off protection and can be pulled out.
  • the computer device receives a second notification signal.
  • the computer device can set the memory to status indication 4, which indicates that the memory has completed power-off protection and can be pulled out.
  • the status indicator 4 may be that the indicator light on the memory is off or flickers at a certain frequency, or the status indicator 4 may be displayed on the operation interface of the upper layer software, which is not limited in this embodiment of the present application.
  • the computer device may set the state of the memory to state indication 4, indicating that the memory has completed power-off protection and can be pulled out.
  • the computer device may send a power-off signal to the memory.
  • the power-off signal may be a disk power enable signal, which is used to instruct the memory to turn off the power.
  • the memory can be pulled out after disconnecting the power supply.
  • the computer device may set the state of the memory to state indication 4, indicating that the memory has completed power-off protection and can be pulled out.
  • Each step from step S610 to step S660 may be powered by a power supply module.
  • the storage device can send a third notification signal to the computer device to realize power-off protection with the assistance of the computer.
  • the first notification signal, the second notification signal and the third notification signal can also be transmitted through a low-speed signal interface, so that the computer device and the memory can transmit signals to each other relatively quickly.
  • the embodiment of the present application also provides a computer storage medium, the computer storage medium stores program instructions, and when the program is executed, it may include a part or All steps.
  • Fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present application.
  • the computer device 700 includes a controller 710 , a power supply module 720 and a backup power module 730 .
  • the controller 710 may be the controller 410 in FIG. 4 , and the specific functions and beneficial effects of the controller 710 may refer to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the power supply module 720 may be the power supply module 440 in FIG. 4 , and the specific functions and beneficial effects of the power supply module 720 may refer to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the power backup module 730 may be the power backup module 430 in FIG. 4 . The specific functions and beneficial effects of the power backup module 730 can be referred to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the computer device 700 may further include a power interface 741 and a signal interface 742 (not shown in the figure).
  • the power interface 741 can be the power interface 416 in FIG. 4 .
  • the specific functions and beneficial effects of the power interface 741 can be referred to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the signal interface 742 can be the high-speed signal interface 414 or the low-speed signal interface 415 in FIG. 4 .
  • the specific functions and beneficial effects of the signal interface 742 can be referred to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the computer device 700 may further include a combiner module 750 (not shown in the figure).
  • the combiner module 750 may be the combiner module 450 in FIG. 4 .
  • the specific functions and beneficial effects of the combiner module 750 may refer to the embodiment shown in FIG. 4 , which will not be repeated here.
  • Fig. 8 is a schematic structural diagram of a memory according to an embodiment of the present application.
  • the memory 800 includes a control circuit 810 , a cache 820 and a non-volatile storage medium 830 .
  • the control circuit 810 may be the control circuit 421 in FIG. 4 , and the specific functions and beneficial effects of the control circuit 810 may refer to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the cache 820 may be the cache memory 423 in FIG. 4 , and the specific functions and beneficial effects of the cache 820 may refer to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the non-volatile storage medium 830 can be the non-volatile storage medium 422 in FIG. 4 , and the specific functions and beneficial effects of the non-volatile storage medium 830 can be referred to the embodiment shown in FIG. 4 , which will not be repeated here. .
  • the memory 800 may further include a power interface 841 and a signal interface 842 (not shown in the figure).
  • the power interface 841 can be the power interface 426 in FIG. 4 .
  • the specific functions and beneficial effects of the power interface 841 can be referred to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the signal interface 842 can be the high-speed signal interface 424 or the low-speed signal interface 425 in FIG. 4 .
  • the specific functions and beneficial effects of the signal interface 842 can be referred to the embodiment shown in FIG. 4 , which will not be repeated here.
  • the memory 800 may further include a switch 850 (not shown in the figure).
  • the switch 850 may be the switch 428 in FIG. 4 , and the specific functions and beneficial effects of the switch 850 may refer to the embodiment shown in FIG. 4 , which will not be repeated here.
  • Fig. 9 is a schematic structural diagram of a storage system according to an embodiment of the present application.
  • the storage system 900 may include a computer device 910 and a memory 920 .
  • the computer device 910 can be represented as the computer device 700 in FIG. 7
  • the memory 920 can be represented as the memory 800 in FIG. 8 .
  • the embodiment of the present application also provides a chip system, the chip system includes a logic circuit, the logic circuit is used for coupling with the input/output interface, and transmits data through the input/output interface, so as to execute the steps in the above embodiments.
  • the present application also provides a computer program product, the computer program product including: computer program code, when the computer program code is run on the computer, the computer is made to execute each of the above-mentioned embodiments. step.
  • the present application also provides a computer-readable medium, the computer-readable medium stores program codes, and when the program codes are run on a computer, the computer is made to execute each of the above-mentioned embodiments. step.
  • each step of the above-mentioned method can be completed by an integrated logic circuit of hardware in a processor or an instruction or program code in the form of software.
  • the steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software units in the processor.
  • the software unit may be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, no detailed description is given here.
  • the processor in the embodiment of the present application may be an integrated circuit chip, which has a signal processing capability.
  • each step of the above-mentioned method embodiments may be implemented by an integrated logic circuit of hardware in a processor or instructions or program codes in the form of software.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software units in the decoding processor.
  • the software unit may be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: various media that can store program codes such as USB flash drives, mobile memory, read-only memory, random access memory (random access memory, RAM), magnetic disks or optical disks.

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Abstract

一种为存储器提供备电的方法和相关设备。该设备包括：供电模块、备电模块以及控制器，其中：控制器用于检测供电模块的供电情况，并根据供电情况向备电模块发送备电指示，备电模块用于根据备电指示为与控制器连接的存储器供电。根据该设备，计算机装置中的备电模块可以通过接收控制器的备电指示，为控制器和连接计算机装置的存储器供电，从而不用在存储器中设置备电模块，无需占用存储器中的空间，能够减少存储器的尺寸。并且，由于计算机装置中的备电模块具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。

Description

为存储器提供备电的方法和相关设备
本申请要求于2021年11月26日提交中国专利局、申请号为202111422218.2、申请名称为“为存储器提供备电的方法和相关设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储器领域，并且更具体地，涉及一种为存储器提供备电的方法、计算机装置、存储器、存储系统、计算机设备、芯片系统和计算机可读存储介质。
背景技术
目前存储系统的存储器的备电模块多集中在存储器内部。备电模块会存储电量，当系统电源无法为存储器供电时，存储器会依赖存储器内部的备电模块储存的电量进行断电保护。存储器的断电保护过程可以安全地将存储器的缓存数据写入到存储器的非易失性存储介质中，以及保持存储器映射表的完整性，以便在系统恢复正常供电后存储器能够再次被识别且可用。随着技术的演进，存储器中的高速缓冲存储器(cache)的容量不断增加。相应的，cache中缓存的数据量也会增加，断电保护过程中需要的电量也会相应增加。如果按照现有设计，那么备电模块存储的电量无法满足断电保护过程所需的电量，如果增加备电模块的存储电量，那么会增加整个存储器的尺寸。
因此如何满足存储器在断电保护过程中的备电容量需求成为亟待解决的问题。
发明内容
本申请实施例提供一种为存储器提供备电的方法、计算机装置、存储器、存储系统、计算机设备、芯片系统和计算机可读存储介质，可以在不增加存储器的尺寸的基础上满足存储器在断电保护过程中的备电容量需求。
第一方面，提供了一种计算机装置。该计算机装置包括供电模块、备电模块以及控制器。其中，控制器用于检测供电模块的供电情况，并根据供电情况向备电模块发送备电指示；备电模块用于根据备电指示为与控制器连接的存储器供电。
应理解，供电模块可以为计算机装置和存储器供电。备电模块可以在控制器确定供电模块无法为控制器和存储器供电的情况下，接收控制器的备电指示，从而为控制器和存储器供电。
本申请实施例中，备电模块可以在计算机装置中通过接收控制器的备电指示，为控制器和存储器供电。从而不用在存储器中设置额外的备电模块，无需占用存储器中的空间，能够减少存储器的尺寸。并且，由于计算机装置中的备电模块具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。也就是说，本实施例中的计算机装置中，备电模块可以在不占用存储器的空间的基础上，具有较大的备电电量，满足存储器在断电保护过程中的电量需求。
结合第一方面，在第一方面的某些实现方式中，控制器还用于根据供电情况向存储器发送第一通知信号，第一通知信号用于指示存储器进行断电保护。
应理解，存储器的断电保护可以将存储器的高速缓冲存储器中的数据存入存储器的存储介质。还应理解，在控制器确定供电模块无法为控制器和存储器供电时，控制器可以指示备电模块开始供电，即备电模块为控制器向存储器发送第一通知信号供电。
本申请实施例中，控制器可以在供电模块无法为控制器和存储器供电时，向存储器发送第一通知信号，使存储器进行断电保护，从而避免存储器中的缓存数据因掉电而丢失。
结合第一方面，在第一方面的某些实现方式中，控制器还用于接收来自于存储器的第二通知信号，根据第二通知信号向备电模块发送停止备电指示，其中，第二通知信号用于指示存储器已完成断电保护；备电模块还用于根据停止备电指示停止为存储器供电。
应理解，控制器可以接收存储器的第二通知信号，该第二通知信号用于将存储器完成断电保护通知控制器。控制器在接收到来自于存储器的第二通知信号后，可以指示备电模块停止供电。
本申请实施例中，控制器可以在接收到第二通知信号后，指示备电模块停止供电，从而在确定存储器已完成断电保护的情况下，避免备电模块继续工作而浪费电量。
结合第一方面，在第一方面的某些实现方式中，控制器还用于接收来自于存储器的第三通知信号；响应所述第三通知信号，停止向存储器写入数据，并向存储器发送第一通知信号，第一通知信号用于指示存储器进行断电保护，第三通知信号用于指示存储器准备进行断电保护。
应理解，来自于存储器的第三通知信号表示存储器将要与计算机装置断开连接，需要进行断电保护。控制器在接收到来自于存储器的第三通知信号后，可以停止向存储器写入数据，从而避免存储器在断电保护过程中无法将控制器后续写入的数据进行保存。控制器在停止向存储器写入数据后，可以向存储器发送第一通知信号，指示存储器进行断电保护。
本申请实施例中，控制器可以在存储器将要与计算机装置断开连接时，接收来自于存储器的第三通知信号，从而协助存储器完成断电保护。
结合第一方面，在第一方面的某些实现方式中，第一通知信号和第二通知信号通过计算机装置的同一信号接口传输。
应理解，第一通知信号、第二通知信号和第三通知信号都可以通过计算机装置的信号接口传输。还应理解，传输上述信号的接口为低速信号接口，上述信号均为低速信号。低速信号是非高速信号，高速信号可以是高速串行计算机扩展总线标准(peripheral component interconnect express，PCIE)信号或串行连接小型计算机系统接口(serial attached small computer system interface，SAS)信号。
本申请实施例中，可以通过计算机装置的一个信号接口在计算机装置和存储器之间传输第一通知信号、第二通知信号和第三通知信号。从而在供电模块无法为控制器和存储器供电时以及存储器将要与计算机装置断开连接时，使控制器可以较快速地向存储器发送通知信号和获得来自于存储器的通知信号。
结合第一方面，在第一方面的某些实现方式中，计算机装置还包括合路模块，合路模块的输入端分别连接供电模块和备电模块，合路模块的输出端与控制器和存储器相连，合路模块具体用于获取来自于供电模块或备电模块的供电，为控制器或存储器供电。
本申请实施例中，可以通过合路模块获得来自于供电模块或备电模块的供电，并为控 制器和存储器供电。从而可以避免使用多个硬件电路实现供电，造成空间和资源的浪费。
第二方面，提供了一种存储器。该存储器包括控制电路、缓存和非易失性存储介质，控制电路用于接收来自于与存储器连接的计算机装置的第一通知信号，其中第一通知信号用于指示存储器进行断电保护；控制电路，还用于根据第一通知信号进行断电保护，以将缓存中的数据写入非易失性存储介质，其中存储器在断电保护过程中由计算机装置供电。
应理解，存储器的断电保护可以将存储器的高速缓冲存储器中的数据存入存储器的存储介质。
本申请实施例中，存储器通过获得来自于计算机装置的供电和第一通知信号进行断电保护。从而不用在存储器中设置额外的备电模块，无需占用存储器中的空间，能够减少存储器的尺寸。并且，由于计算机装置中的备电模块可以具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。也就是说，本实施例中的存储器中，可以不用额外设置备电模块，而与存储器连接的计算机装置中的备电模块可以具有较大的备电电量，满足存储器在断电保护过程中的电量需求。
结合第二方面，在第二方面的某些实现方式中，控制电路还用于向计算机装置发送第二通知信号，第二通知信号用于指示存储器已完成断电保护。
本申请实施例中，存储器在完成断电保护后可以向计算机装置发送第二通知信号，从而使计算机装置可以及时关闭电源，避免造成资源浪费。
结合第二方面，在第二方面的某些实现方式中，第一通知信号和第二通知信号通过存储器的同一信号接口传输。
本申请实施例中，可以通过存储器的一个信号接口在计算机装置和存储器之间传输第一通知信号和第二通知信号，从而使存储器可以较快速地向计算机装置发送通知信号和获得来自于计算机装置的通知信号。
结合第二方面，在第二方面的某些实现方式中，控制电路还用于向计算机装置发送第三通知信号，第三通知信号用于指示存储器准备进行断电保护。
应理解，计算机装置可以在确定存储器将要与计算机装置断开连接的情况下，向计算机装置发送第三通知信号。存储器向计算机装置发送第三通知信号后，存储器可以接收来自于计算机装置的第一通知信号，进行断电保护。
还应理解，在存储器完成断电保护后，存储器可以向计算机装置发送第二通知信号，表示存储器完成断电保护。
还应理解，第一通知信号、第二通知信号和第三通知信号都可以通过存储器的同一信号接口传输。还应理解，传输上述信号的接口为低速信号接口，上述信号均为低速信号。低速信号是非高速信号，高速信号可以是PCIE信号或SAS信号。
本申请实施例中，在存储器将要与计算机装置断开连接时，存储器可以向计算机装置发送第三通知信号，从而在计算机装置的协助下实现断电保护。
第三方面，提供了一种为存储器提供备电的方法。该方法包括：计算机装置检测供电模块的供电情况，其中，计算机装置包括供电模块和备电模块；计算机装置根据供电模块的供电情况，通过计算机装置中的备电模块为与计算机装置连接的存储器供电。
本申请实施例中，计算机装置可以在确定供电模块无法为计算机装置和存储器供电时，通过备电模块为计算机装置和存储器进行供电，避免存储器中的缓存数据因掉电而丢失。从而不用在存储器中设置额外的备电模块，无需占用存储器中的空间，能够减少存储器的 尺寸。并且，由于计算机装置中的备电模块具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。也就是说，本实施例中的计算机装置中，备电模块可以在不占用存储器的空间的基础上，具有较大的备电电量，满足存储器在断电保护过程中的电量需求。
结合第三方面，在第三方面的某些实现方式中，计算机装置根据供电情况，向存储器发送第一通知信号，第一通知信号用于指示存储器进行断电保护。
应理解，存储器的断电保护可以将存储器的高速缓冲存储器中的数据存入所述存储器的存储介质。
本申请实施例中，计算机装置可以在确定供电模块无法为计算机装置和存储器供电的情况下，指示存储器进行断电保护，避免存储器因为电源异常掉电导致无法及时存储缓存数据。
结合第三方面，在第三方面的某些实现方式中，计算机装置接收来自于存储器的第二通知信号，第二通知信号用于指示存储器已完成断电保护；计算机装置根据第二通知信号，停止使用备电模块为存储器供电。
本申请实施例中，计算机装置可以在接收到第二通知信号后，指示备电模块停止供电，从而在确定存储器已完成断电保护的情况下，避免备电模块继续工作而浪费电量。
结合第三方面，在第三方面的某些实现方式中，计算机装置接收来自于存储器的第三通知信号，第三通知信号用于指示存储器准备进行断电保护；计算机装置响应第三通知信号，停止向存储器中写入数据并向存储器发送第一通知信号，第一通知信号用于指示存储器进行断电保护。
应理解，来自于存储器的第三通知信号表示存储器将要与计算机装置断开连接，需要进行断电保护。
本申请实施例中，计算机装置在接收到来自于存储器的第三通知信号后，可以停止向存储器写入数据，从而避免存储器在断电保护过程中无法将控制器后续写入的数据进行保存。控制器在停止向存储器写入数据后，可以向存储器发送第一通知信号，从而协助存储器实现断电保护。
结合第三方面，在第三方面的某些实现方式中，第一通知信号和第二通知信号通过计算机装置的同一信号接口传输。
应理解，第一通知信号、第二通知信号和第三通知信号都可以通过计算机装置的信号接口传输。还应理解，传输上述信号的接口为低速信号接口，上述信号均为低速信号。低速信号是非高速信号，高速信号可以是PCIE信号或SAS信号。
本申请实施例中，可以通过计算机装置的一个信号接口在计算机装置和存储器之间传输第一通知信号、第二通知信号和第三通知信号。从而在供电模块无法为控制器和存储器供电时以及存储器将要与计算机装置断开连接时，控制器可以较快速地向存储器发送通知信号和获得来自于存储器的通知信号。
第四方面，提供了一种断电保护方法。该方法包括：存储器接收来自于与存储器连接的计算机装置的第一通知信号，第一通知信号用于指示存储器进行断电保护；存储器根据第一通知信号，进行断电保护，其中存储器在断电保护过程中由计算机装置供电。
应理解，存储器的断电保护可以将存储器的高速缓冲存储器中的数据存入存储器的存储介质。
本申请实施例中，存储器通过获得来自于计算机装置的供电和第一通知信号，进行断 电保护。从而不用在存储器中设置额外的备电模块，无需占用存储器中的空间，能够减少存储器的尺寸。并且，由于计算机装置中的备电模块可以具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。也就是说，本实施例中的存储器中，可以不用额外设置备电模块，而与存储器连接的计算机装置中的备电模块可以具有较大的备电电量，满足存储器在断电保护过程中的电量需求。
结合第四方面，在第四方面的某些实现方式中，存储器向计算机装置发送第二通知信号，第二通知信号用于指示存储器已完成断电保护。
本申请实施例中，存储器在完成断电保护后可以向计算机装置发送第二通知信号，从而使计算机装置可以及时关闭电源，避免造成资源浪费。
结合第四方面，在第四方面的某些实现方式中，第一通知信号和第二通知信号通过存储器的同一信号接口传输。
本申请实施例中，可以通过存储器的同一个信号接口在计算机装置和存储器之间传输第一通知信号和第二通知信号，从而使存储器可以较快速地向计算机装置发送通知信号和获得来自于计算机装置的通知信号。
结合第四方面，在第四方面的某些实现方式中，存储器在确定将要与计算机装置断开连接的情况下，向计算机装置发送第三通知信号，第三通知信号用于指示存储器准备进行断电保护。
应理解，存储器向计算机装置发送第三通知信号后，存储器可以接收来自于计算机装置的第一通知信号，开始断电保护。在存储器完成断电保护后，存储器可以向计算机装置发送第二通知信号，表示存储器完成断电保护。
还应理解，第一通知信号、第二通知信号和第三通知信号都可以通过存储器的同一信号接口传输。还应理解，传输上述信号的接口为低速信号接口，上述信号均为低速信号。低速信号是非高速信号，高速信号可以是PCIE信号或SAS信号。
本申请实施例中，在存储器将要与计算机装置断开连接时，存储器可以向计算机装置发送第三通知信号，从而在计算机装置的协助下实现断电保护。
第五方面，提供了一种存储系统。该存储系统包括如第一方面或第一方面的任一种可能的实现方式所述的计算机装置，和如第二方面或第二方面的任一种可能的实现方式所述的存储器。
第六方面，提供了一种计算机设备。该计算机设备包括处理器、供电电源和备电电源。该处理器用于与存储器耦合，读取并执行存储器中的指令和/或程序代码，结合供电电源和备电电源执行如第三方面或第三方面的任一种可能的实现方式所述的方法。
第七方面，提供了一种存储器。该存储器包括处理器，该处理器用于与存储器耦合，读取并执行存储器中的指令和/或程序代码，以执行如第四方面或第四方面的任一种可能的实现方式所述的方法。
第八方面，提供了一种芯片系统。该芯片系统包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过输入/输出接口传输数据，以执行如第三方面或第三方面的任一种可能的实现方式所述的方法。
第九方面，提供了一种芯片系统。该芯片系统包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过输入/输出接口传输数据，以执行如第四方面或第四方面的任一种可能的实现方式所述的方法。
第十方面，提供了一种计算机可读存储介质。计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如第三方面或第三方面的任一种可能的实现方式所述的方法。
第十一方面，提供了一种计算机可读存储介质。计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如第四方面或第四方面的任一种可能的实现方式所述的方法。
附图说明
图1是盘控分离的存储系统的示意性架构图。
图2是盘控一体的存储系统的示意性架构图。
图3是一个存储系统的示意性系统架构图。
图4是根据本申请一个实施例的存储系统的示意性系统架构图。
图5是根据本申请一个实施例的为存储器提供备电的方法的示意性流程图。
图6是根据本申请另一个实施例的为存储器提供备电的方法的示意性流程图。
图7是根据本申请一个实施例的计算机装置的结构示意图。
图8是根据本申请一个实施例的存储器的结构示意图。
图9是根据本申请一个实施例的存储系统的结构示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种存储系统中，例如计算机电脑主机、存储器、固态硬盘、含有中央处理器(central processing unit，CPU)的存储芯片系统等，本申请实施例对此并不限定。
图1是盘控分离的存储系统的示意性架构图。在图1所示的应用场景100中，用户通过应用程序来存取数据。运行这些应用程序的计算机被称为“应用服务器”。应用服务器110可以是物理机，也可以是虚拟机。物理应用服务器包括但不限于桌面电脑、服务器、笔记本电脑以及移动设备。应用服务器通过光纤交换机120访问存储系统以存取数据。然而，交换机120只是一个可选设备，应用服务器110也可以直接通过网络与存储系统130通信。或者，光纤交换机120也可以替换成以太网交换机、无限带宽(infiniBand)交换机等。
图1中的存储系统130是一个集中式存储系统。集中式存储系统的特点是有一个统一的入口，所有从外部设备来的数据都要经过这个入口，这个入口就是集中式存储系统的引擎140。引擎140是集中式存储系统中最为核心的部件，许多存储系统的高级功能都在其中实现。
如图1所示，引擎140中有一个或多个控制器，图1以引擎包含两个控制器为例予以说明。控制器1与控制器2之间具有镜像通道，那么当控制器1将一份数据写入其内存143后，可以通过所述镜像通道将所述数据的副本发送给控制器2，控制器2将所述副本存储在自己本地的内存147中。由此，控制器1和控制器2互为备份，当控制器1发生故障时，控制器2可以接管控制器1的业务，当控制器2发生故障时，控制器1可以接管控制器2的业务，从而避免硬件故障导致整个存储系统130的不可用。当引擎140中部署有4个控制器时，任意两个控制器之间都具有镜像通道，因此任意两个控制器互为备份。
引擎140还包含前端接口141、前端接口145、后端接口144和后端接口148，其中前端接口141和145用于与应用服务器110通信，从而为应用服务器110提供存储服务。而后端接口144和148用于与硬盘153通信，以扩充存储系统的容量。通过后端接口144和148，引擎140可以连接更多的硬盘153，从而形成一个非常大的存储资源池。
在硬件上，如图1所示，控制器1至少包括处理器142、内存143。处理器142是一个中央处理器，用于处理来自存储系统外部(服务器或者其他存储系统)的数据访问请求，也用于处理存储系统内部生成的请求。示例性的，处理器142通过前端端口141接收应用服务器110发送的写数据请求时，会将这些写数据请求中的数据暂时保存在内存143中。当内存143中的数据总量达到一定阈值时，处理器142通过后端端口将内存144中存储的数据发送给硬盘153进行持久化存储。
内存143是指与处理器直接交换数据的内部存储器，它可以随时读写数据，而且速度很快，作为操作系统或其他正在运行中的程序的临时数据存储器。内存包括至少两种存储器，例如内存既可以是随机存取存储器，也可以是只读存储器(read only memory，ROM)。举例来说，随机存取存储器是动态随机存取存储器(dynamic random access memory，DRAM)，或者存储级存储器(storage class memory，SCM)。DRAM是一种半导体存储器，与大部分随机存取存储器(random access memory，RAM)一样，属于一种易失性存储器(volatile memory)设备。SCM是一种同时结合传统储存装置与存储器特性的复合型储存技术，存储级存储器能够提供比存储器更快速的读写速度，但存取速度上比DRAM慢，在成本上也比DRAM更为便宜。然而，DRAM和SCM在本实施例中只是示例性的说明，内存还可以包括其他随机存取存储器，例如静态随机存取存储器(static random access memory，SRAM)等。而对于只读存储器，举例来说，可以是可编程只读存储器(programmable read only memory，PROM)、可抹除可编程只读存储器(erasable programmable read only memory，EPROM)等。另外，内存143还可以是双列直插式存储器模块或双线存储器模块(dual in-line memory module，DIMM)，即由动态随机存取存储器组成的模块，还可以是固态存储器(solid state disk，SSD)。实际应用中，控制器1中可配置多个内存，以及不同类型的内存。本实施例不对内存的数量和类型进行限定。此外，可对内存143进行配置使其具有保电功能。保电功能是指系统发生掉电又重新上电时，内存143中存储的数据也不会丢失。具有保电功能的内存被称为非易失性存储器。
内存143中存储有软件程序，处理器142运行内存143中的软件程序可实现对存储器的管理。例如将存储器抽象化为存储资源池，然后划分为逻辑单元号(logical unit number，LUN)提供给服务器使用等。这里的LUN其实就是在服务器上看到的存储器。当然，一些集中式存储系统本身也是文件服务器，可以为服务器提供共享文件服务。
控制器2(以及其他图1中未示出的控制器)的硬件组件和软件结构与控制器1类似，这里不再赘述。
图1所示的是一种盘控分离的集中式存储系统。在该系统中，引擎140可以不具有存储器槽位，硬盘153需要放置在硬盘框150中，后端接口144与硬盘框150通信。后端接口144以适配卡的形态存在于引擎140中，一个引擎140上可以同时使用两个或两个以上后端接口来连接多个存储器框，例如后端接口144和148。或者，适配卡也可以集成在主板上，此时适配卡可通过PCIE总线与处理器142或146通信。
需要说明的是，图1中只示出了一个引擎140，然而在实际应用中，存储系统中可包 含两个或两个以上引擎，多个引擎之间做冗余或者负载均衡。
硬盘框150包括控制单元151和若干个硬盘153。控制单元151可具有多种形态。一种情况下，硬盘框150属于智能盘框，如图1所示，控制单元151包括CPU和内存。CPU用于执行地址转换以及读写数据等操作。内存用于临时存储将要写入硬盘153的数据，或者从硬盘153读取出来将要发送给控制器的数据。另一种情况下，控制单元151是一个可编程的电子部件，例如数据处理模块(data processing unit，DPU)。DPU具有CPU的通用性和可编程性，但更具有专用性，可以在网络数据包，存储请求或分析请求上高效运行。DPU通过较大程度的并行性(需要处理大量请求)与CPU区别开来。可选的，这里的DPU也可以替换成图形处理模块(graphics processing unit，GPU)、嵌入式神经网络处理器(neural-network processing units，NPU)等处理芯片。通常情况下，控制单元151的数量可以是一个，也可以是两个或两个以上。当硬盘框150包含至少两个控制单元151时，硬盘153与控制单元151之间可具有归属关系。如果硬盘153与控制单元151之间具有归属关系，那么每个控制器只能访问归属于它的存储器，这往往涉及到在控制单元151之间转发读/写数据请求，导致数据访问的路径较长。另外，如果存储空间不足，在硬盘框150中增加新的硬盘153时需要重新绑定硬盘153与控制单元151之间的归属关系，操作复杂，导致存储空间的扩展性较差。因此在另一种实施方式中，控制单元151的功能可以卸载到网卡152上。换言之，在该种实施方式中，硬盘框150内部不具有控制单元151，而是由网卡152来完成数据读写、地址转换以及其他计算功能。此时，网卡152是一个智能网卡。它可以包含CPU和内存。在某些应用场景中，网卡152也可能具有持久化内存介质，如持久性内存(persistent memory，PM)，或者非易失性随机访问存储器(non-volatile random access memory，NVRAM)，或者相变存储器(phase change memory，PCM)等。CPU用于执行地址转换以及读写数据等操作。内存用于临时存储将要写入硬盘153的数据，或者从硬盘153读取出来将要发送给控制器的数据。硬盘框150中的网卡152和硬盘153之间没有归属关系，网卡152可访问该硬盘框150中任意一个硬盘153，因此在存储空间不足时扩展存储器会较为便捷。
按照引擎140与硬盘框150之间通信协议的类型，硬盘框150可能是SAS存储器框，也可能是非易失性存储器(non-volatile memory express，NVMe)存储器框以及其他类型的存储器框。SAS存储器框，采用SAS3.0协议，每个框支持25块SAS存储器。引擎140通过板载SAS接口或者SAS接口模块与硬盘框150连接。NVMe存储器框，更像一个完整的计算机系统，NVMe存储器插在NVMe存储器框内。NVMe存储器框再通过RDMA端口与引擎140连接。本申请的实施例可以应用在图1所示的盘控分离的存储系统中。
图2是盘控一体的存储系统的示意性架构图。图2中的应用服务器210、交换机220分别与图1中的应用服务器110、交换机120类似。图2中的存储系统230包括引擎240和硬盘250，其中引擎240与图1中的引擎140类似，都可以包括一个或多个控制器。图2以引擎240包括两个控制器为例进行说明。图2中引擎包括控制器3和控制器4，其中两个控制器中均包含前端接口、处理器、内存和后端接口。与图1类似，控制器3与控制器4之间具有镜像通道，可以互为备份。图2所示的是一种盘控一体的集中式存储系统。在该系统中，可以包含一个或多个存储器。图2以包含多个存储器为例进行说明。存储器250不需要放置在图1所示的硬盘框150中，存储器250可以直接通过后端端口244与控制器3进行通信，或者通过后端接口248与控制器4进行通信。本申请的实施例可以应用 在图2所示的盘控一体的存储系统中。
图3是一个存储系统的示意性系统架构图。
存储系统300可以分为五部分，分别是：控制器310、存储器320、控制器备电模块330、供电模块340和背板350。
控制器310中包含高速控制模块311、处理模块312、高速缓冲存储器313和内部电路314。控制器310可以是图1所示的盘控分离的存储系统中的控制器1或控制器2，也可以是图2所示的盘控一体的存储系统中的控制器3或控制器4。如图1所示的处理器142可以包括高速控制模块311和处理模块312。类似的，处理器146可以包括高速控制模块311和处理模块312。如图2所示的处理器242可以包括高速控制模块311和处理模块312。类似的，处理器246可以包括高速控制模块311和处理模块312。
高速控制模块311可以直接或间接与存储器相连，通过高速信号接口在控制器310与存储器320之间传输高速信号，从而向存储器下发业务，例如写入数据等。高速信号可以是PCIE信号或SAS信号。
处理模块312可以是主板管理控制器(baseboard management controller，BMC)、复杂可编程逻辑器件(complex programmable logic device，CPLD)、或微控制单元(microcontroller unit，MCU)等，可以通过低速信号接口在控制器310与存储器320之间传输低速信号。低速信号是非高速信号。根据不同的低速信号接口，低速信号的类型可以不同。例如企业和数据中心存储形态(Enterprise&Datacenter SSD Form Factor，EDSFF)接口可以包含规范未定义信号(manufacturing mode for device，MFG)、协议预留信号(reserved for future use，RFU)、系统管理总线(system management bus，SMBUS)、复位设备管理接口信号(SMBUS reset，SMBRST#)、主机点灯信号(light emitting diode，LED)、盘片电源使能信号(power disable，PWRDIS)、盘片在位信号(present，PRSNT#)。又例如8639接口可以包含：唤醒信号(wake，Wake#)、盘片电源使能(PWRDIS)、接口类型检测信号(interface detect，IfDet#)、盘片在位信号(PRSNT#)、状态指示信号(activity，ACTIVITY#)、保留信号(reserved)、系统管理总线(SMBUS)。
高速缓冲存储器313为控制器310内部的高速缓冲存储器，用于存储数据。高速缓冲存储器313可以是SRAM，或者可以是图1所示的内存143或内存147，也可以是图2所示的内存243或247。
内部电路314为控制器310内部的硬件电路，可以为控制器310内部的部件提供电路支持。内部电路314可以包括两个电源输入端，其中内部电路314的第一电源输入端可以与供电模块340相连，内部电路314的第二电源输入端可以与控制器备电模块330相连，从而使供电模块340和控制器备电模块330均可以为控制器310供电。
存储器320中包含高速缓冲存储器321、备电模块322、合路模块323和内部电路324。
高速缓冲存储器321为存储器320内部的高速缓冲存储器，可以是SRAM。较小容量的cache的空间可以为1至10GB，较大容量的cache的空间可以是10至100GB，甚至更高。若存储器320的cache容量较小，则存储系统的大部分cache集中在控制器310中，存储器320内部的较小容量的cache仅用于存储器自身的正常工作，即高速缓冲存储器313为较大容量的cache，高速缓冲存储器321为较小容量的cache。此时控制器310与存储器320之间没有cache访问接口，控制器310不会占用存储器320内部的cache资源。随着存储系统中cache容量的增加，控制器310中的部分cache会移到存储器320中，此时存 储器320中的高速缓冲存储器321容量较大。同时为了降低访问时延，存储器320可以提供cache访问接口以供控制器310访问。控制器310可以占用存储器320内部的cache资源。图3中的高速缓冲存储器321可以是图1中的控制单元151。当图1中的控制单元151的功能卸载到网卡152时，网卡152可以包含CPU和内存，此时图3中的高速缓冲存储器321可以是网卡152。因此图3中的存储器320可以包括图1中的控制单元151和硬盘153，或者可以包括网卡152和硬盘153。存储器320也可以是图2中的硬盘250。当图3中的高速缓冲存储器321容量较大时，图3中的控制器310可以占用高速缓冲存储器321的资源。此时图3中的控制器310可以包括图1中的控制器1和控制单元151，或者可以包括图1中的控制器1和网卡152，也可以包括图1中的控制器2和控制单元151，或者可以包括图1中的控制器2和网卡152。
备电模块322可以在供电模块340无法正常供电时，为存储器320供电。存储器320可以将高速缓冲存储器321中的缓存数据写入存储器内部的非易失性存储介质中。
合路模块323可以包括两个电源输入端和一个电源输出端。其中合路模块323的第一电源输入端与供电模块340相连，合路模块323的第二电源输入端与备电模块322相连，合路模块323的电源输出端与内部电路324相连。合路模块323可以将供电模块340和备电模块322的电源输入进行合路，使供电模块340和备电模块322均可以为内部电路324供电。
内部电路324是存储器320内部的硬件电路，可以为存储器320内部的部件提供电路支持。图3中的存储器320可以是图1所示的盘控分离的存储系统中的硬盘153，也可以是图2所示的盘控一体的存储系统中的硬盘250。
控制器备电模块330与控制器310的内部电路314相连，可以在供电模块340无法为控制器310供电时，为控制器310供电。
供电模块340为系统300的电源，在供电模块340正常工作时可以为控制器310和存储器320供电。
背板350可以为控制器310和存储器320直接提供信号通路，还可以为存储器320提供电源通路。
在图3所示的存储系统中，当图3中供电模块340无法正常供电时，控制器310由控制器备电模块330供电，存储器320由存储器320内的备电模块322供电。此时，控制器310中高速控制模块311会停止通过高速信号接口向存储器320下发业务。存储器320开始执行断电保护(power loss protection，PLP)，即将高速缓冲存储器321中的缓存数据写入存储器320的非易失性存储介质中，还可以将存储器320的映射表保存完整。控制器备电模块330为控制器310将高速缓冲存储器313中的缓存数据写到存储器320中提供电力支持，备电模块322为存储器320将高速缓冲存储器321中的缓存数据写入存储器内部的非易失性存储介质中提供电力支持。备电模块322仅能提供毫秒(millisecond，ms)级的备电时间，随着技术的演进，存储器320中的缓存容量越来越大，更容易出现备电模块中储存的电量无法满足实际需求的问题。
图4是根据本申请一个存储系统的示意性系统架构图。
本申请提供的存储系统400可以包括控制器410、存储器420、备电模块430、供电模块440、合路模块450和背板460。
控制器410中包含高速控制模块411、处理模块412、高速缓冲存储器413、高速信 号接口414、低速信号接口415和电源接口416。图4中的控制器410可以是图1所示的盘控分离的存储系统中的控制器1或控制器2，也可以是图2所示的盘控一体的存储系统中的控制器3或控制器4。如图1所示的处理器142可以包括高速控制模块411和处理模块412。类似的，处理器146可以包括高速控制模块411和处理模块412。如图2所示的处理器242可以包括高速控制模块411和处理模块412。类似的，处理器246可以包括高速控制模块411和处理模块412。
高速控制模块411可以通过高速信号接口414实现控制器410与存储器420之间的通信，还可以向存储器420发送高速信号，即向存储器下发业务，例如写入数据等。
处理模块412可以检测供电模块440的供电情况，在供电模块440无法为控制器410和存储器420供电时，指示备电模块430开始供电。处理模块412还可以在确定存储器420完成断电保护的情况下，指示备电模块停止供电。处理模块412还可以通过计算机软件或驱动通知上层软件，再由上层软件通知高速控制模块411，从而使高速控制模块411停止通过高速信号接口414向存储器420下发业务。处理模块412还可以通过低速信号接口415实现控制器410与存储器420之间的通信，向存储器420发送低速信号，协助实现存储器420进行断电保护。
高速缓冲存储器413是控制器410内部的高速缓冲存储器，可以用于保存数据。高速缓冲存储器413可以是SRAM，或者可以是图1所示的内存143或内存147，也可以是图2所示的内存243或247。
高速信号接口414可以在控制器410与存储器420之间传输高速信号。高速信号可以是PCIE信号或SAS信号。
低速信号接口415可以在控制器410与存储器420之间传输低速信号。低速信号是非高速信号。
电源接口416与合路模块450的电源输出端453相连，获得来自于备电模块430或供电模块440的供电。
存储器420中包含控制电路421、非易失性存储介质422、高速缓冲存储器423、高速信号接口424、低速信号接口425和电源接口426。
控制电路421可以通过高速信号接口424接收来自于控制器410的高速信号完成数据读写操作。控制电路421还可以通过低速信号接口425接收来自于控制器410的低速信号，从而实现断电保护。
控制电路421接收的低速信号可以是第一通知信号。该第一通知信号用于在供电模块440无法为控制器410和存储器420供电时通知存储器420进行断电保护。
控制电路421还可以通过低速信号接口425向控制器410发送低速信号，该低速信号可以是第二通知信号或第三通知信号。该第二通知信号用于通知控制器410存储器420已完成断电保护。该第三通知信号用于在存储器420将要与控制器410断开连接时，通知控制器410存储器420准备进行断电保护。
存储器420的断电保护可以将存储器420的高速缓冲存储器423中的数据写入非易失性存储介质422中，还可以保持存储器420的映射表的完整性。
非易失性存储介质422是存储器420内部的非易失性存储介质，可以实现存储器内部的数据存储功能。非易失性存储介质422可以是闪存(flash)，或者是PROM，或者是EPROM等，本申请实施例对此并不限定。
高速缓冲存储器423是存储器内部的高速缓冲存储器，可以用于存储缓存数据。高速缓冲存储器423可以是SRAM。在高速缓冲存储器423容量较大时，存储器420中可以包括cache访问接口，以使控制器410可以对高速缓冲存储器423进行读写访问。图4中的高速缓冲存储器423可以是图1中的控制单元151。当图1中的控制单元151的功能卸载到网卡152时，网卡152可以包含CPU和内存，此时图4中的高速缓冲存储器423可以是网卡152。因此图4中的存储器420可以包括图1中的控制单元151和硬盘153，或者可以包括网卡152和硬盘153。存储器420也可以是图2中的硬盘250。
高速信号接口424可以通过背板460与控制器410中的高速信号接口414相连。通过高速信号接口414和高速信号接口424，控制器410与存储器420之间可以传输高速信号。
低速信号接口425可以通过背板460与控制器410中的低速信号接口415相连。通过低速信号接口415和低速信号接口425，控制器410与存储器420之间可以传输低速信号。
电源接口426与合路模块450的电源输出端453相连，获得来自于备电模块430或供电模块440的供电。图4中的存储器420可以是图1所示的盘控分离的存储系统中的硬盘153，也可以是图2所示的盘控一体的存储系统中的存储器250。图4中的控制电路421和高速缓冲存储器423可以共同构成图1中的控制单元151或网卡152，因此图1中的控制单元151、网卡152和硬盘153可以共同构成图4中的存储器420。
可选的，在一些实施例中，存储器420还可以包括开关427。开关427是检测存储器420是否将要与控制器410断开连接的开关。当开关427检测到存储器420不与控制器410断开连接时，开关427可以向控制电路421发送稳定接入信号，表示当前存储器420为稳定接入状态。当开关427检测到存储器420将要与控制器410断开连接时，开关427可以向控制电路421发送断开指示信号，表示当前存储器将要断开连接。控制电路421可以接收来自于开关427的稳定接入信号，确定存储器420与控制器410稳定连接。控制电路421还可以接收来自于开关427的断开指示信号，确定存储器420将要与控制器410断开连接。
可选地，在一些实施例中，可以通过将拉手条428弹开或闭合达到控制开关427的目的。拉手条428可以为锁扣性质的开关。当存储器420与控制器410相连时，可以将拉手条428闭合，从而使开关427检测到存储器420不与控制器410断开。当存储器420需要与控制器410断开连接时，可以将拉手条428弹起，从而使开关427检测到存储器420将要与控制器410断开。
可选地，开关427可以为光电开关。
可选地，在一些实施例中，存储器420还可以包括指示灯。指示灯可以用于指示存储器420将要与控制器410断开连接、或者用于指示存储器正在进行断电保护、或者用于指示存储器完成断电保护等。指示灯可以固定点亮或熄灭，也可以按一定频率进行闪烁，本申请实施例对此并不限定。
可选地，在一些实施例中，当存储器420开始断电保护或完成断电保护时，控制器410可以通知上层软件，使上层软件的操作界面显示存储器开始断电保护或完成断电保护等。
备电模块430可以接收来自于控制器410的备电指示，为控制器410和存储器420供电。备电模块430在接收到该备电指示后，可以开始供电。备电模块430还可以接收来自于控制器410的停止备电指示，停止为控制器410和存储器420供电。备电模块430在接 收到该停止备电指示后，可以停止供电。备电模块430可以提供秒(second，s)级，或者数十秒级的备电时间。
供电模块440为系统400的电源，在正常工作时可以为控制器410和存储器420供电。
合路模块450包括电源输入端451、电源输入端452和电源输出端453。其中合路模块450的电源输入端451与备电模块430相连，电源输入端452与供电模块440相连，电源输出端453可以与控制器410的电源接口416和存储器420的电源接口426相连。合路模块450可以将备电模块430和供电模块440的电源输入进行合路，从而使备电模块430或供电模块440均可以为控制器410或存储器420供电。
背板460可以为控制器410和存储器420提供信号通路，还可以为存储器420提供电源通路。
可选地，控制器410与存储器420可以作为一个整体，此时背板460可以省略。
可选地，备电模块430可以是控制器410外部独立的备电单元。备电模块430可以与控制器410分离，单独作为一个现场可更换单元(field replace unit，FRU)。备电模块430也可以与控制器410合为一个FRU单元。
可选地，控制器410、备电模块430、供电模块440均可以单独作为一个FRU单元，也可以任意多个合为一个FRU单元。
在图4的存储系统中，不用在存储器中设置额外的备电模块，无需占用存储器中的空间，能够减少存储器的尺寸。并且，由于计算机装置中的备电模块具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。也就是说，图4的存储系统中，备电模块可以在不占用存储器的空间的基础上，具有较大的备电电量，满足存储器在断电保护过程中的电量需求。图4的存储系统还可以通过同一个低速信号接口传输第一通知信号、第二通知信号或第三通知信号中的任一个，从而使计算机装置和存储器可以较为快速的相互传输信号。
图5是根据本申请一个为存储器提供备电的方法的示意性流程图。图5中的方法包括如下内容。
S510，计算机装置检测到供电模块无法正常供电，指示备电模块开始供电。
供电模块正常工作时，可以为计算机装置和与计算机装置相连的存储器供电。当供电模块无法为计算机装置和存储器供电时，计算机装置可以检测到供电模块无法正常供电，从而指示备电模块开始供电。
可选地，计算机装置可以通过向备电模块发送备电指示来指示备电模块开始供电。该备电指示可以用于指示备电模块开始供电。备电模块接收到该备电指示后为计算机装置和存储器的供电。
备电模块可以在计算机装置中为计算机装置和存储器供电，使备电模块可以在不占用存储器的空间的同时，具有较大的备电电量。从而使备电模块可以满足存储器在断电保护过程中的电量需求。
S520，计算机装置向存储器发送第一通知信号。
当备电模块开始供电后，计算机装置可以向存储器发送第一通知信号，该第一通知信号可以用于通知存储器进行断电保护。
可选地，在向存储器发送第一通知信号前，计算机装置可以停止向存储器下发业务，例如写入数据等。计算机装置停止向存储器下发业务后，存储器中不会再写入新的数据， 此时存储器进行断电保护不会造成数据的丢失。计算机装置停止向存储器下发业务后，可以向存储器发送第一通知信号。
可选地，第一通知信号可以通过计算机装置的低速信号接口发送。
可选地，第一通知信号可以是一个固定的高低电平，也可以是一段时间的脉冲信号，本申请实施例对此不做具体限定。
可选地，在计算机装置向存储器发送第一通知信号时，计算机装置可以将存储器设置为状态指示1，该状态指示1可以表示存储器正在进行断电保护，不可拔出。该状态指示1可以是存储器上的指示灯固定点亮或按一定频率闪烁，本申请实施例对此不做具体限定。
S530，存储器接收第一通知信号，进行断电保护。
存储器接收到来自于计算机装置的第一通知信号后，进行断电保护。存储器的断电保护过程可以将存储器内部的cache中的缓存数据写入存储器内部的存储介质中。
可选地，在存储器接收到来自于计算机装置的第一通知信号后，可以由存储器将自身设置为状态指示1，该状态指示1可以表示存储器正在进行断电保护，不可拔出。该状态指示1可以是存储器上的指示灯固定点亮或按一定频率闪烁，本申请实施例对此并不限定。
S540，存储器完成断电保护，存储器向计算机装置发送第二通知信号。
存储器完成断电保护后，即存储器内部cache中的缓存数据全部写入存储器内部的非易失性存储介质，并且存储器的映射表保存完整后，存储器可以向计算机装置发送第二通知信号。该第二通知信号可以用于指示存储器已经完成断电保护。
可选地，第二通知信号可以由存储器通过低速信号接口发送。
可选地，第二通知信号可以是一个固定的高低电平或一段时间的脉冲信号，本申请实施例对此并不限定。
可选地，第二通知信号与步骤S520、S530中的第一通知信号的类型可以一致，也可以不一致。即第一通知信号与第二通知信号可以都是固定的高低电平，也可以都是一段时间的脉冲信号，或者一个是固定的高低电平，一个是一段时间的脉冲信号，本申请实施例对此并不限定。
可选地，当第一通知信号与第二通知信号的类型一致时，两者的内容可以一致，也可以不一致。即当第一通知信号与第二通知信号都是固定的高低电平时，可以都是固定的高电平，或者都是固定的低电平，或者一个是高电平、一个是低电平。当第一通知信号与第二通知信号都是一段时间的脉冲信号时，可以都是一致的脉冲信号，也可以是不一致的脉冲信号，本申请实施例对此并不限定。
可选地，第一通知信号和第二通知信号均可以通过低速信号接口发送，从而使计算机装置和存储器可以较为快速的相互传输信号。
可选地，存储器完成断电保护后，可以由存储器将自身设置为状态指示2，该状态指示2可以表示存储器已经完成断电保护，可以拔出。该状态指示2可以是存储器上的指示灯熄灭或按一定频率闪烁，本申请实施例对此并不限定。
可选地，若存储器支持带电插拔，存储器在完成断电保护后即可拔出。
可选地，若存储器支持带电插拔，存储器在完成断电保护后可以由存储器将自身设置为状态指示2，表示存储器已经完成断电保护，可以拔出。
S550，计算机装置接收第二通知信号，指示备电模块结束供电。
计算机装置接收到来自于存储器的第二通知信号后，可以指示备电模块停止供电。
可选地，可以通过向备电模块发送停止备电指示来指示备电模块停止供电，该停止备电指示可以用于指示备电模块停止供电。备电模块接收停止备电指示后停止为计算机装置和存储器供电。
可选地，计算机装置接收到来自于存储器的第二通知信号后，可以由计算机装置将存储器设置为状态指示2，该状态指示2表示存储器完成断电保护，可以拔出。该状态指示2可以是存储器上的指示灯熄灭或按一定频率闪烁，本申请实施例对此并不限定。
可选地，若存储器支持带电插拔，则计算机装置接收第二通知信号后，可以由计算机装置将存储器设置为状态指示2，表示存储器完成断电保护，可以拔出。
可选地，若存储器不支持带电插拔，在计算机装置接收第二通知信号后，可以由计算机装置向存储器发送下电信号。该下电信号可以是盘片电源使能信号，用于指示存储器关闭电源。存储器断开电源后即可拔出。
可选地，若存储器不支持带电插拔，在计算机装置向存储器发送下电信号后，可以由计算机装置将存储器设置为状态指示2，表示存储器完成断电保护，可以拔出。
可选地，在计算机装置接收第二通知信号后，计算机装置中可能仍有部分部件处于工作状态，例如控制器中的高速控制器或cache。在计算机装置的部件工作完成后，可以向备电模块发送停止备电指示，指示备电模块结束供电。
在备电模块开始供电后，步骤S520至步骤S550中的各个步骤均可以由备电模块供电。由于不用在存储器中设置额外的备电模块，无需占用存储器中的空间，能够减少存储器的尺寸。并且，由于计算机装置中的备电模块具有较大的备电电量，能够满足存储器在断电保护过程中的电量需求。也就是说，本实施例中，备电模块可以在不占用存储器的空间的基础上，具有较大的备电电量，满足存储器在断电保护过程中的电量需求。在图5的方法中，还可以通过同一个信号接口传输第一通知信号和第二通知信号，从而使计算机装置和存储器可以较为快速的相互传输信号。
图6是根据本申请另一个为存储器提供备电的方法的示意性流程图。图6中的方法包括如下内容。
S610，存储器获取断开指示信号。
在需要断开存储器与计算机装置的连接时，存储器可以获取到断开指示信号，表示存储器将要断开连接，需要准备进行断电保护。
可选地，可以由存储器中的开关向存储器发送断开指示信号，该断开指示信号可以是一个固定的高低电平。
可选地，存储器接收到断开指示信号后，可以由存储器将自身设置为状态指示3，表示存储器正在进行断电保护，不可拔出。该状态指示3可以是存储器上的指示灯固定点亮或按一定频率闪烁，或者该状态指示3可以是上层软件的操作界面进行显示，本申请实施例对此不做具体限定。
可选地，存储器中的开关可以是光电开关。
S620，存储器向计算机装置发送第三通知信号。
当存储器获取到断开指示信号后，存储器可以向计算机装置发送第三通知信号。该第三通知信号可以用于表示当前存储器将要断开连接，需要准备进行断电保护。
可选地，第三通知信号可以由存储器通过低速信号接口发送。
可选地，第三通知信号可以是一个固定的高低电平，也可以是一段时间的脉冲信号。
S630，计算机装置接收第三通知信号，向存储器发送第一通知信号。
计算机装置接收到来自于存储器的第三通知信号后，可以向存储器发送第一通知信号，该第一通知信号用于通知存储器进行断电保护。
可选地，为防止在断电保护期间，计算机装置继续向存储器写入数据，使存储器无法将数据全部保存。计算机装置接收到来自于存储器的第三通知信号后，可以停止向存储器下发业务。计算机装置停止向存储器下发业务后，计算机装置可以向存储器发送第一通知信号，指示存储器进行断电保护。
可选地，第一通知信号可以由计算机装置通过低速信号接口发送。
可选地，该第一通知信号可以是一个固定的高低电平，也可以是一段时间的脉冲信号，本申请实施例对此不做具体限定。
可选地，在计算机装置向存储器发送第一通知信号时，计算机装置可以将存储器设置为状态指示3，该状态指示3可以表示存储器正在进行断电保护，不可拔出。该状态指示3可以是存储器上的指示灯固定点亮或按一定频率闪烁，或者该状态指示3可以是上层软件的操作界面进行显示，本申请实施例对此不做具体限定。
S640，存储器接收第一通知信号，进行断电保护。
存储器接收到来自于计算机装置的第一通知信号后，进行断电保护。存储器的断电保护过程可以将存储器内部cache中的缓存数据写入存储器内部的存储介质中。
可选地，在存储器接收到来自于计算机装置的第一通知信号后，可以由存储器将自身设置为状态指示1，该状态指示1可以表示存储器正在进行断电保护，不可拔出。该状态指示1可以是存储器上的指示灯固定点亮或按一定频率闪烁，本申请实施例对此并不限定。
S650，存储器完成断电保护后，向计算机装置发送第二通知信号。
存储器完成断电保护后，即将存储器内部cache中的缓存数据全部写入存储器内部的存储介质，并且存储器的映射表保存完整后，存储器可以向计算机装置发送第二通知信号。该第二通知信号用于指示存储器已经完成断电保护。
可选地，第二通知信号可以由存储器通过低速信号接口发送。
可选地，第二通知信号可以是一个固定的高低电平或一段时间的脉冲信号，本申请实施例对此并不限定。
可选地，第二通知信号与上述步骤中的第三通知信号、第一通知信号的类型可以一致，也可以不一致。即第一通知信号、第二通知信号和第三通知信号可以任一个或多个是固定的高低电平，也可以任一个或多个是一段时间的脉冲信号，本申请实施例对此并不限定。
可选地，当第一通知信号、第二通知信号与第三通知信号的类型一致时，三者的内容可以一致，也可以不一致。即当第一通知信号、第二通知信号与第三通知信号都是固定的高低电平时，可以任一个或多个是固定的高电平，也可以任一个或多个是固定的低电平。当第一通知信号、第二通知信号与第三通知信号都是一段时间的脉冲信号时，可以任一个或多个是一致的脉冲信号，也可以任一个或多个是不一致的脉冲信号，本申请实施例对此并不限定。
可选地，第一通知信号、第二通知信号与第三通知信号均可以通过低速信号接口发送，从而使计算机装置和存储器可以较为快速的相互传输信号。
可选地，存储器完成断电保护后，可以由存储器将自身设置为状态指示2，该状态指示2可以表示存储器已经完成断电保护，可以拔出。该状态指示2可以是存储器上的指示 灯熄灭或按一定频率闪烁，本申请实施例对此并不限定。
可选地，若存储器支持带电插拔，存储器在完成断电保护后即可拔出。
可选地，若存储器支持带电插拔，存储器在完成断电保护后可以由存储器将自身设置为状态指示2，表示存储器已经完成断电保护，可以拔出。
S660，计算机装置接收第二通知信号。
可选地，计算机装置接收到来自于存储器的第二通知信号后，可以由计算机装置将存储器设置为状态指示4，该状态指示4表示存储器完成断电保护，可以拔出。该状态指示4可以是存储器上的指示灯熄灭或按一定频率闪烁，或者该状态指示4可以是上层软件的操作界面进行显示，本申请实施例对此并不限定。
可选地，若存储器支持带电插拔，则计算机装置接收到第二通知信号后，可以由计算机装置将存储器状态设置为状态指示4，表示存储器完成断电保护，可以拔出。
可选地，若存储器不支持带电插拔，在计算机装置接收到第二通知信号后，计算机装置可以向存储器发送下电信号。该下电信号可以是盘片电源使能信号，用于指示存储器关闭电源。存储器断开电源后即可拔出。
可选地，若存储器不支持带电插拔，在计算机装置向存储器发送下电信号后，可以由计算机装置将存储器状态设置为状态指示4，表示存储器完成断电保护，可以拔出。
步骤S610至步骤S660中的各个步骤可以均由供电模块供电。在存储器需要与计算机装置断开连接时，存储器可以通过向计算机装置发送第三通知信号，在计算机的协助下实现断电保护。在图6的方法中，还可以通过一个低速信号接口传输第一通知信号、第二通知信号和第三通知信号，从而使计算机装置和存储器可以较为快速的相互传输信号。
以上描述了根据本申请实施例的为存储器提供备电的方法，下面分别结合图7至图9描述根据本申请实施例的计算机装置、存储器、存储系统和相关设备。
本申请实施例还提供了一种计算机存储介质，该计算机存储介质中存储有程序指令，所述程序执行时可包括如图5或图6对应实施例中为存储器提供备电的方法的部分或全部步骤。
图7是根据本申请一个实施例的计算机装置的结构示意图。计算机装置700包括控制器710、供电模块720和备电模块730。其中，控制器710可以是图4中的控制器410，控制器710的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。供电模块720可以是图4中的供电模块440，供电模块720的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。备电模块730可以是图4中的备电模块430，备电模块730的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。
在一些实施例中，计算机装置700还可以包括电源接口741和信号接口742(图中未示出)。该电源接口741可以是图4中的电源接口416，该电源接口741的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。该信号接口742可以是图4中的高速信号接口414或低速信号接口415，该信号接口742的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。
在一些实施例中，计算机装置700还可以包括合路模块750(图中未示出)。该合路模块750可以是图4中的合路模块450，该合路模块750的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。
图8是根据本申请一个实施例的存储器的结构示意图。存储器800包括控制电路810、 缓存820和非易失性存储介质830。控制电路810可以是图4中的控制电路421，控制电路810的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。缓存820可以是图4中的高速缓冲存储器423，缓存820的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。非易失性存储介质830可以是图4中的非易失性存储介质422，非易失性存储介质830的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。
在一些实施例中，存储器800还可以包括电源接口841和信号接口842(图中未示出)。该电源接口841可以是图4中的电源接口426，该电源接口841的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。该信号接口842可以是图4中的高速信号接口424或低速信号接口425，该信号接口842的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。
在一些实施例中，存储器800还可以包括开关850(图中未示出)。该开关850可以是图4中的开关428，该开关850的具体功能和有益效果可以参见图4所示的实施例，在此就不再赘述。
图9是根据本申请一个实施例的存储系统的结构示意图。存储系统900可以包括计算机装置910和存储器920。其中计算机装置910可以表现为图7中的计算机装置700，存储器920可以表现为图8中的存储器800。
本申请实施例还提供了一种芯片系统，该芯片系统包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过该输入/输出接口传输数据，以执行上述实施例中的各个步骤。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行上述实施例中的各个步骤。
根据本申请实施例提供的方法，本申请还提供一种计算机可读介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行上述实施例中的各个步骤。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令或程序代码完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件单元组合执行完成。软件单元可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
应注意，本申请实施例中的处理器可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令或程序代码完成。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件单元组合执行完成。软件单元可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及 算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动存储器、只读存储器、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种计算机装置，其特征在于，包括：供电模块、备电模块以及控制器，其中：
    所述控制器，用于检测所述供电模块的供电情况，并根据所述供电情况向所述备电模块发送备电指示；
    所述备电模块，用于根据所述备电指示为与所述控制器连接的存储器供电。
  2. 根据权利要求1所述的装置，其特征在于，所述控制器，还用于根据所述供电情况向所述存储器发送第一通知信号，所述第一通知信号用于指示所述存储器进行断电保护。
  3. 根据权利要求2所述的装置，其特征在于，所述控制器，还用于接收来自于所述存储器的第二通知信号，根据所述第二通知信号向所述备电模块发送停止备电指示，其中，所述第二通知信号用于指示所述存储器已完成所述断电保护；
    所述备电模块，还用于根据所述停止备电指示停止为所述存储器供电。
  4. 根据权利要求1所述的装置，其特征在于，所述控制器，还用于：
    接收来自于所述存储器的第三通知信号；
    响应所述第三通知信号，停止向所述存储器写入数据，并向所述存储器发送第一通知信号，其中，所述第一通知信号用于指示所述存储器进行断电保护，所述第三通知信号用于指示所述存储器准备进行所述断电保护。
  5. 根据权利要求3或4所述的装置，其特征在于，所述第一通知信号和所述第二通知信号通过所述计算机装置的同一信号接口传输。
  6. 根据权利要求1至5中任一项所述的装置，其特征在于，所述装置还包括：
    合路模块，所述合路模块的输入端分别连接所述供电模块和所述备电模块，所述合路模块的输出端与所述控制器和所述存储器相连，
    所述合路模块，具体用于获取来自于所述供电模块或备电模块的供电，为所述控制器或所述存储器供电。
  7. 一种存储器，其特征在于，包括：控制电路、缓存和非易失性存储介质，
    所述控制电路，用于接收来自于与所述存储器连接的计算机装置的第一通知信号，其中，所述第一通知信号用于指示所述存储器进行断电保护；
    所述控制电路，还用于根据所述第一通知信号进行所述断电保护，以将所述缓存中的数据写入所述非易失性存储介质，其中，所述存储器在所述断电保护过程中由所述计算机装置供电。
  8. 根据权利要求7所述的存储器，其特征在于，所述控制电路，还用于向所述计算机装置发送第二通知信号，所述第二通知信号用于指示所述存储器已完成所述断电保护。
  9. 根据权利要求8所述的存储器，其特征在于，所述第一通知信号和所述第二通知信号通过所述存储器的同一信号接口传输。
  10. 根据权利要求7至9中任一项所述的存储器，其特征在于，
    所述控制电路，还用于向所述计算机装置发送第三通知信号，所述第三通知信号用于指示所述存储器准备进行所述断电保护。
  11. 一种为存储器提供备电的方法，其特征在于，所述方法包括：
    计算机装置检测供电模块的供电情况，其中，所述计算机装置包括所述供电模块和备 电模块；
    所述计算机装置根据所述供电模块的供电情况，通过计算机装置中的备电模块为与所述计算机装置连接的存储器供电。
  12. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    所述计算机装置根据所述供电情况，向所述存储器发送第一通知信号，所述第一通知信号用于指示所述存储器进行断电保护。
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    所述计算机装置接收来自于所述存储器的第二通知信号，所述第二通知信号用于指示所述存储器已完成所述断电保护；
    所述计算机装置根据所述第二通知信号，停止使用所述备电模块为所述存储器供电。
  14. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    所述计算机装置接收来自于所述存储器的第三通知信号，所述第三通知信号用于指示所述存储器准备进行断电保护；
    所述计算机装置响应所述第三通知信号，停止向所述存储器中写入数据并向所述存储器发送第一通知信号，所述第一通知信号用于指示所述存储器进行所述断电保护。
  15. 根据权利要求13或14所述的方法，其特征在于，所述第一通知信号和所述第二通知信号通过所述计算机装置的同一信号接口传输。
  16. 一种断电保护方法，其特征在于，所述方法包括：
    存储器接收来自于与所述存储器连接的计算机装置的第一通知信号，所述第一通知信号用于指示所述存储器进行断电保护；
    所述存储器根据所述第一通知信号，进行所述断电保护，其中所述存储器在所述断电保护过程中由所述计算机装置供电。
  17. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    所述存储器向所述计算机装置发送第二通知信号，所述第二通知信号用于指示所述存储器已完成所述断电保护。
  18. 根据权利要求17所述的方法，其特征在于，所述第一通知信号和所述第二通知信号通过所述存储器的同一信号接口传输。
  19. 根据权利要求16至18中任一项所述的方法，其特征在于，所述方法还包括：
    所述存储器在确定将要与所述计算机装置断开连接的情况下，向所述计算机装置发送第三通知信号，所述第三通知信号用于指示所述存储器准备进行所述断电保护。
  20. 一种存储系统，包括：如权利要求1至6中任一项所述的计算机装置，和如权利要求7至10中任一项所述的存储器。
PCT/CN2022/117591 2021-11-26 2022-09-07 为存储器提供备电的方法和相关设备 WO2023093210A1 (zh)

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