WO2023091125A1

WO2023091125A1 - Apparatus and method of a layer 2 recovery mechanism to maintain synchronization for wireless communication

Info

Publication number: WO2023091125A1
Application number: PCT/US2021/059490
Authority: WO
Inventors: Sonali Bagchi; Tianan Tim Ma; Yunhong Li; Su-Lin Low; Chun-I Lee; Yanming Wang; Jinghu Chen
Original assignee: Zeku, Inc.
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2023-05-25

Abstract

According to one aspect of the disclosure, a MAC hardware accelerator of a baseband chip is provided. The medium access control (MAC) hardware accelerator may include a MAC-physical (PHY) layer interface configured to receive, from a PHY layer transmitter (Tx), a request for a first number of bytes for a transport block (TB) associated with a component carrier (CC). The MAC hardware accelerator may obtain a MAC protocol data unit (PDU) from a MAC inline buffer associated with the CC. The MAC -PHY layer interface transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may b implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

Description

APPARATUS AND METHOD OF A LAYER 2 RECOVERY MECHANISM TO MAINTAIN SYNCHRONIZATION FOR WIRELESS COMMUNICATION

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modem terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines a Radio Layer 2 (referred to here as “Layer 2”) as part of the cellular protocol stack structure corresponding to the data plane (DP) (also referred to as the “user plane”), which includes a Service Data Adaptation Protocol (SDAP) layer, a Packet Data Convergence Protocol (PDCP) layer, a Radio Link Control (RLC) layer, and a Medium Access Control (MAC), from top to bottom in the stack.

SUMMARY

[0003] According to one aspect of the disclosure, a MAC hardware accelerator of a baseband chip is provided. The MAC hardware accelerator may include a MAC -physical (PHY) layer interface configured to receive, from a PHY layer transmitter (Tx), a request for a first number of bytes for a transport block (TB) associated with a component carrier (CC). The MAC hardware accelerator may obtain a MAC protocol data unit (PDU) from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. The MAC -PHY layer interface may be configured to transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may be configured to implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

[0004] According to another aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 uC. The Layer 2 uC may be configured to generate one or more packet descriptors associated with a MAC PDU associated with a CC. The Layer 2 uC may send the one or more packet descriptors in a uC memory. The baseband chip may include a MAC hardware accelerator. The MAC hardware accelerator may include a MAC -PHY interface configured to receive, from a PHY layer Tx, a request for a first number of bytes for a TB associated with a CC. The MAC hardware accelerator may obtain a MAC PDU from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. The MAC -PHY layer interface may be configured to transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may be configured to implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

[0005] According to yet another aspect of the disclosure, a method of wireless communication of a baseband chip is provided. The method may include receiving, by a MAC- PHY layer interface, a request for a first number of bytes for a TB associated with a CC from a PHY layer Tx. The method may include obtaining, by a MAC -PHY layer interface, a MAC PDU from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. The method may include transferring, by a MAC -PHY layer interface, the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the method may include implementing, by the MAC -PHY layer interface, a recovery mechanism at an end of the first period to maintain synchronization between a MAC hardware accelerator associated with the MAC -PHY layer interface and the PHY layer Tx.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0008] FIG. 1 illustrates a block diagram of an example baseband chip.

[0009] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0010] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0011] FIG. 4 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0012] FIG. 5A illustrates a detailed block diagram of the exemplary baseband chip and the RF chip depicted in FIG. 4, according to some embodiments of the present disclosure.

[0013] FIG. 5B illustrates a conceptual flow diagram of a first exemplary data flow between Layer 2 microcontroller (uC), a Layer 2 hardware accelerator, and a PHY Tx, according to some embodiments of the present disclosure.

[0014] FIG. 5C illustrates a conceptual flow diagram of a second exemplary data flow between a Layer 2 uC, a Layer 2 hardware accelerator, and a PHY layer Tx, according to some embodiments of the present disclosure.

[0015] FIG. 5D illustrates a conceptual flow diagram of a third exemplary data flow between a Layer 2 uC, a Layer 2 hardware accelerator, and a PHY layer Tx, according to some embodiments of the present disclosure.

[0016] FIG. 5E illustrates a conceptual flow diagram of a second exemplary data flow between a Layer 2 uC, a Layer 2 hardware accelerator, and a PHY layer Tx, according to some embodiments of the present disclosure.

[0017] FIG. 6 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure.

[0018] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0019] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0020] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0021] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0022] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system. As used herein the term “hardware” may refer dedicated circuits, such as application-specific integrated circuits (ASICs), which perform one or more functions, as opposed to a general processor (e.g., a microcontroller unit (MCU)) executing software or firmware codes to perform the functions.

[0023] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as a global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0024] In cellular and/or Wi-Fi communication, Layer 2 is the protocol stack layer responsible for ensuring a reliable, error-free datalink for the wireless modem (referred to herein as a “baseband chip”) of a UE. More specifically, Layer 2 interfaces with Radio Layer 1 (also referred to as “Layer 1” or the “PHY layer”) and Radio Layer 3 (also referred to as “Layer 3” or the “Internet Protocol (IP) layer”), passing data packets up or down the protocol stack structure, depending on whether the data packets are associated with uplink (UL) or downlink (DL) transmissions.

[0025] Furthermore, Layer 2 may perform de-multiplexing/multiplexing, segmentation/reassembly, aggregation/de-aggregation, and sliding window automatic repeat request (ARQ) techniques, among others, to ensure reliable end-to-end data integrity and to provide error-free delivery of data packets. For a UL data packet, Layer 3 data packets (e.g., IP data packets) may be input into the Layer 2 protocol stack, and encoded into MAC protocol data units (PDUs) for transporting to the PHY layer. For a DL data packet, Layer 1 data packets (e.g., PHY layer data packets) may be input into the Layer 2 protocol stack, where Layer 2 data processing operations are performed on the data packets before being passed up to Layer 3. Layer 3 performs IP header extraction, IP checksum, IP tracing, and IP routing and classification, among other things.

[0026] FIG. 1 illustrates a block diagram of an example baseband chip 100. As seen in FIG. 1, the example baseband chip 100 may include PHY subsystem 102 (e.g., residing at a radio frequency (RF) chip) configured to transmit and/or receive data packets over an air interface, a protocol stack 104 (e.g., residing at the baseband chip) that includes a control plane 106 and a data plane 108, Layer 3/Layer 4 subsystems 110, and an application processor (AP)/host 112.

[0027] Control plane 106 performs two main functions: non-access stratum (NAS) function and radio resource control (RRC) function. The NAS function performs network layer control that relates to mobility management, session management, security management, and system selection, just to name a few. The RRC function performs radio resource allocation and configuration, as well as the radio channel control of radio bearers, logical channels, and security (e.g., ciphering, integrity configurations, etc.).

[0028] Data plane 108 performs Layer 2 and Layer 3/4 functions. Layer 2 functions relate to PDU processing. For example, the MAC layer performs multiplexing and demultiplexing, and mapping of logical channels to transport channels. The RLC layer performs ARQ procedures at the radio link level and the error recovery of each logical channel. The PDCP layer performs packet-level processing for data ciphering, integrity, and compression. The SDAP layer performs a quality-of-service (QoS) classification of IP flows to data radio bearers (DRBs).

[0029] Example baseband chip 100 illustrated in FIG. 1 uses a software-centric Layer 2 protocol data stack. Namely, the data stack processing resides on a Layer 2 main processor and uses a limited number of hardware accelerators. Using the example baseband chip 100, the Layer 2 main processor (not shown) may access a data packet by direct memory access (DMA) from a PHY layer memory at PHY subsystem(s) 102. Furthermore, the HW accelerators may DMA a UL data packet to the Layer 3 external memory of Layer 3 subsystem 110.

[0030] In baseband chip 100, Layer 2 data processing (e.g., processing the transport blocks received from Layer 1 (e.g., PHY subsystem 102) in the DL user plane or processing data packets received from Layer 3 in the UL user plane) is usually implemented using software modules executed on a generic baseband processor, such as a central processing unit (CPU) or a digital signal processor (DSP). During processing, data may be frequently transferred between the generic main processor (not shown) and external memory, such as a Layer 3 external DDR memory or Layer 2 buffer), for buffering between each layer. As a result, Layer 2 data processing of example baseband chip 100 suffers from high power consumption, large data buffer, and long process delays.

[0031] Moreover, when a user equipment (UE) is configurated with Carrier Aggregation (CA), multiple Component Carriers (CCs) are typically aggregated for reception and transmission. As such, the UE may receive multiple grants concurrently, one on each CC. These grants may include a DL grant for receiving DL packets or a UL grant for transmitting UL packets. In either case, the UE may use the grant to determine the scheduled time at which a packet may be received or transmitted, as well as the size of the packet (e.g., the number of bytes). [0032] In the DL direction, the DL MAC layer receives code blocks from the PHY subsystem 102 from multiple CCs. The DL MAC layer may then re-order each Transport Block (TB), extract the MACsubPDU headers to obtain the MAC PDUs, and transfer the packet to the RLC and PDCP DP Layer 2 for further processing in each logical channel and associated radio bearers. Once Layer 2 data processing is complete, the packets are sent to Layer 3/Layer 4 subsystems 110, where the QoS flows in each radio bearer are routed to the appropriate application. [0033] Conversely, in the UL direction, the Layer 3/Layer 4 subsystems 110 prepare the UL packets from multiple QoS flows for each DRB, and the UL packets may then be transferred to Layer 2 logical channel queues, ready for transmission. Once the UL MAC layer receives the UL grant in the physical downlink control channel (PDCCH) at the beginning of a slot. For example, the UL grant may be received in a downlink control indicator (DCI) on the PDCCH. The UL grant may allocate resources for the physical uplink shared channel (PUSCH)). The UL grant may indicate that the UL MACPDU is to be transmitted at a time delay equivalent to K2 slots away from the current slot. Typically, K2<1 grants are implied to be serviced for low latency application data, and hence, radio bearers/logical channels (LCs) data are pulled into such grants to be sent out as soon as possible. The UL MAC scheduling algorithm uses a Logical Channel Prioritization (LCP) method to schedule packets from a logical channel (LC) according to allocated grant bytes from a configured maximum bucket size setting.

[0034] In a high-throughput wireless modem, MAC PDU processing may be implemented by data path firmware running on uC clusters. The firmware may communicate command/status information in real-time using control descriptors written to command and status queues located in on-chip shared memory regions. IP packet data may be read by hardware from buffers located in on-chip memory or off-chip memory regions, such as DDR. Then, the IP packet data may be processed at the MAC layer based on the command/status information. Once the MAC PDUs are generated, they may be transferred to Layer 1 (PHY).

[0035] One of the challenges in MAC -PHY transmission in high-throughput applications (e.g., enhanced mobile broadband (eMBB) traffic) is servicing multiple UL MAC PDU in a rnulti- CC configuration in a timely manner. In an underrun situation, a PHY Tx may request a certain number of bytes for transmission associated with a CC, which are not yet available. In other words, the MAC layer may not have enough bytes ready in the CC’s buffer in time for the scheduled UL transmission. An underrun situation may occur for various reasons. For example, an underrun may occur when uC firmware commands are unable to keep up with PHY layer requests for UL data, which may result in an insufficient amount of data at the MAC inline buffer. Moreover, an underrun situation may arise when hardware data transfer is unable to keep up with PHY layer requests for UL data, which may cause insufficient data at the MAC inline buffer, e.g., due to delays such as DMA latency caused by a heavy DDR workload.

[0036] In such situations, a loss of synchronization between the data path control firmware and hardware data transfer at the MAC -PHY interface may occur, which may lead to a packet drop, among other problems. Presently, there is no mechanism by which to recover and/or maintain system synchronization when underrun situations arise.

[0037] Thus, there exists an unmet need for a recovery mechanism that can be implemented when the PHY Tx requests data for a UL transmission that is not yet ready at the MAC layer in time for the scheduled transmission to maintain system synchronization.

[0038] To overcome these and other challenges, the present disclosure provides an exemplary recovery mechanism that may be implemented by a MAC -PHY interface during an underrun situation (also referred to herein as an “exception”). For example, using the exemplary recovery mechanism, the baseband chip of the present disclosure may detect and mitigate exceptions in wireless MAC -PHY transmission and enable efficient and graceful recovery of data flow from the MAC layer to the PHY layer without loss of synchronization between the MAC data path control firmware, hardware accelerator, and the PHY layer. Moreover, the exemplary recovery mechanism may enable hardware logging of control information associated with transmit transactions at the MAC -PHY interface to maintain synchronization during an exception condition. Still further, the exemplary recovery mechanism may enable hardware tracking of data flows from the uC to the MAC hardware accelerator and the MAC hardware accelerator to the PHY Tx. The exemplary recovery mechanism may also be used for real-time transaction logging and dataflow tracking to facilitate system debug and validation. Additional details of the exemplary recovery mechanism are provided below in connection with FIGs. 2-6.

[0039] Although the following processing techniques are described in connection with Layer 2 data processing, the same or similar techniques may be applied to Layer 3 and/or Layer 4 data processing to optimize system synchronization at Layer 3 and/or Layer 4 subsystems without departing from the scope of the present disclosure.

[0040] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0041] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0042] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0043] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0044] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0045] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0046] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[0047] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0048] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0049] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0050] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0051] Referring back to FIG. 2, in some embodiments, the baseband chip of user equipment 202 may implement an exemplary recovery mechanism when a Layer 2 underrun situation occurs. For example, using the exemplary recovery mechanism, user equipment 202 may detect and mitigate exceptions in wireless MAC-PHY transmission and enable efficient and graceful recovery of a data flow from the MAC layer to the PHY layer. This may occur without loss of synchronization between the MAC data path control firmware, hardware accelerator, and the PHY layer. User equipment 202 may implement the exemplary recovery mechanism using various recovery modes described in FIGs. 5B-5E.

[0052] Moreover, the exemplary recovery mechanism may enable hardware logging of control information associated with transmit transactions at the MAC -PHY interface to maintain synchronization of the data flows and communication subsystems of user equipment 202 during an exception condition. Still further, the exemplary recovery mechanism may enable hardware tracking of data flows from the uC to the MAC hardware accelerator and the MAC hardware accelerator to the PHY Tx. The exemplary recovery mechanism may also be used for real-time transaction logging and dataflow tracking to facilitate system debug and validation of user equipment 202. Additional details of the exemplary recovery mechanism are provided below in connection with FIGs. 4, 5A, 5B, 5C, 5D, 5E, and 6.

[0053] FIG. 4 illustrates a block diagram of an apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some embodiments of the present disclosure. Apparatus 400 may be implemented as user equipment 202 of wireless network 200 in FIG. 2. As shown in FIG. 4, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 is implemented by processor 302 and memory 304, and RF chip 404 is implemented by processor 302, memory 304, and transceiver 306, as described above with respect to FIG. 3. Besides the on-chip memory 418 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC, as described above.

[0054] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. Interface 414 of baseband chip 402 may receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via interface 414. RF chip 404, through the transmitter (TX), may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 404.

[0055] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402.

[0056] As seen in FIG. 4, baseband chip 402 may include one or more Layer 2 uCs 420, a uC memory 422, a MAC hardware accelerator 424, and a PHY layer Tx 426 (referred to hereinafter as “PHY Tx 426”). MAC hardware accelerator 424 may implement the exemplary recovery mechanism at its MAC -PHY interface when UL exceptions, such as when the PHY Tx requests a larger number of bytes than are available in a MAC inline buffer, occur. For example, using the exemplary recovery mechanism, MAC hardware accelerator 424 may detect and mitigate exceptions in wireless MAC -PHY transmission and enable efficient and graceful recovery of data flow from the MAC layer to the PHY layer. This may occur without a loss of synchronization between the MAC data path control firmware of Layer 2 uC(s) 420, MAC hardware accelerator 424, and PHY Tx 426. The exemplary recovery mechanism may be implemented using various recovery modes described in connection with FIGs. 5A-5E.

[0057] Moreover, the exemplary recovery mechanism may enable hardware logging of control information associated with transmit transactions at the MAC -PHY interface to maintain synchronization during an exception condition. Still further, the exemplary recovery mechanism may enable hardware tracking of data flows from the uC to the MAC hardware accelerator and the MAC hardware accelerator to the PHY Tx. The exemplary recovery mechanism may also be used for real-time transaction logging and dataflow tracking to facilitate system debug and validation. Additional details of baseband chip 402 and the exemplary recovery mechanism are described below in connection with FIGs. 5A, 5B, 5C, 5D, and 5E.

[0058] FIG. 5A illustrates a detailed block diagram 500 of baseband chip 402 and external memory 408 depicted in FIG. 4, according to some embodiments of the present disclosure. FIG. 5B illustrates a conceptual flow diagram of a first exemplary data flow 525 between Layer 2 uC(s) 420, MAC hardware accelerator 424, and PHY Tx 426, according to some embodiments of the present disclosure. FIG. 5C illustrates a conceptual flow diagram of a second exemplary data flow 535 between Layer 2 uC(s) 420, MAC hardware accelerator 424, and PHY Tx 426, according to some embodiments of the present disclosure. FIG. 5D illustrates a conceptual flow diagram of a third exemplary data flow 545 between Layer 2 uC(s) 420, MAC hardware accelerator 424, and PHY Tx 426, according to some embodiments of the present disclosure. FIG. 5E illustrates a conceptual flow diagram of a fourth exemplary data flow 555 between Layer 2 uC(s) 420, MAC hardware accelerator 424, and PHY Tx 426, according to some embodiments of the present disclosure. FIGs. 5A, 5B, 5C, 5D, and 5E will be described together.

[0059] Referring to FIG. 5 A, baseband chip 402 may include, e.g., Layer 2 uC 420 (e.g., a uC cluster), uC memory 422 (e.g., a shared memory used by each uC in the cluster), MAC hardware accelerator 424, MAC registers 502, one or more MAC processing circuit(s) 504, a MAC inline buffer 506, a MAC-PHY interface 518, a MAC DMA 532, a MAC uC interface 534, and PHY Tx 426. uC memory 422 may include a command/status queue 524, a debug status queue 526, and a data tracking table 528. MAC inline buffer 506 may include a write manager 508, a plurality of CC buffers 510, a read manager 512, a MAC inline buffer status manager 514, and a MAC data tracker 516. MAC -PHY interface 518 may include a finite state machine (FSM) 520 and a transaction log 522. FSM 520 may determine whether to implement the exemplary recovery mechanism to prevent a loss of synchronization between Layer 2 uC(s) 420, MAC processing circuit(s) 504, and MAC -PHY interface 518, among other components depicted in FIG. 5 A. This determination may be made based on available PDUs in MAC inline buffer 506. For example, if CC buffer 510 runs out of PDUs during a TB associated with the corresponding CC, FSM 520 may implement the exemplary recovery mechanism. However, if a threshold number of PDU(s) become available later during the same TB, FSM 520 may return to regular mode and transfer the PDUs to PHY Tx 426. Still referring to FIG. 5A, baseband chip 402 may communicate with external memory 408 via DMA interface 530.

[0060] During wireless communication, PHY Tx 426 may receive a UL grant from a base station associated with a CC. The UL grant may schedule a UL transmission for baseband chip 402. The UL grant may indicate various information, such as the time and/or frequency domain location in which the UL transmission is scheduled, CC identification (CC ID), the byte size of UL transmission, the transport block (TB)/MAC PDU identification (TB ID), retry parameters, etc. Using the information in the UL grant, PHY Tx 426 may perform scheduling operations for the upcoming UL transmission. Moreover, PHY Tx 426 may send the UL grant to Layer 2 uC 420, which generates packet descriptors associated with the UL transmission. These packet descriptors may be maintained in uC memory 422. MAC processing circuit(s) 504 of MAC hardware accelerator 424 may dequeue the packet descriptors from uC memory 422. Based on the grant size in the packet descriptors, MAC processing circuit(s) 504 may obtain data from external memory 408, and perform MAC layer processing of the data to generate one or more MAC PDUs. Once generated, the MAC PDUs may be written to a corresponding CC buffer 510 by write manager 508. Then, when PHY Tx 426 requests a certain number of bytes of TB data for transmission, read manager 512 may read the requested data to MAC -PHY interface 518, which transfers it to PHY Tx 426. Thus, from the time the UL grant is received by PHY Tx 426 until transmission time, there is a synchronized process flow followed by Layer 2 uC(s) 420, MAC hardware accelerator 424 (and the components thereof), and PHY Tx 426.

[0061] However, as mentioned above, underrun situations may occur in which the requested number of bytes are not ready in CC buffer 510. Such situations may occur, e.g., when Layer 2 uC(s) 420 firmware commands are unable to keep up with requests for UL data, when data transfer between external memory 408 and MAC hardware accelerator 424 is unable to keep up with requests for UL data, among others. When this happens, baseband chip 402 may implement an exemplary recovery mechanism to prevent a loss of synchronization between Layer 2 uC(s) 420, MAC processing circuit(s) 504, and MAC -PHY interface 518, among other components depicted in FIG. 5A. The exemplary recovery mechanism may be implemented using various modes, depending on the application. Non-limiting examples of these recovery modes are described below in connection with FIGs. 5B, 5C, 5D, and 5E. One or more of transaction log 522, MAC data tracker 516, data tracking table 528, on-chip memory 418, and/or external memory 408 may be configured to maintain data tracking information to perform debugging if synchronization is lost. It is understood that recovery modes other than those described herein may be used to maintain synchronization during an underrun situation without departing from the scope of the present disclosure.

[0062] As shown in FIGs. 5B, 5C, 5D, and 5E, Layer 2 uC(s) 420 may include Layer 2 firmware 550, MAC hardware accelerator 424 may include Layer 2 hardware 560, and PHY Tx 426 may include Layer 1 hardware 570. Layer 2 hardware 560 may include one or more of, e.g., MAC registers 502, one or more MAC processing circuit(s) 504, a MAC inline buffer 506, a MAC- PHY interface 518, and/or a MAC DMA 532.

[0063] Referring to each of FIGs. 5B-5E, upon receipt of a UL grant, PHY Tx 426 may send (at 501) a grant indication to Layer 2 uC(s) 420. Based on the information included in the grant indication, Layer 2 firmware 550 may generate a plurality of Layer 2 commands that may be maintained in uC memory 422. Layer 2 uC(s) 420 may assert (at 503) a Layer 2 command queue descriptor signal to indicate the start of a TB to MAC processing circuit(s) 504. MAC processing circuit(s) 504 may read Layer 2 commands 540 from command/ status queue 524. MAC processing circuit(s) 504 may use information included in Layer 2 commands 540 to generate one or more MAC PDUs. MAC PDUs may be generated by performing MAC layer processing of data obtained from external memory 408.

[0064] At the transmission time scheduled by the UL grant, PHY Tx 426 may assert (at 505) a PHY ready signal with MAC -PHY interface 518. Then, PHY Tx 426 may assert (at 507) a start request signal to request the number of bytes indicated by the UL grant. PHY Tx 426 may send (at 509) information such as the requested CC ID, TB ID, and the number of bytes to MAC- PHY interface 518. MAC-PHY interface 518 may acknowledge the start request by sending (at 511) a start ack signal to PHY Tx 426. The start ack signal may indicate the start of a first period of the TB. During the first period, MAC -PHY interface 518 may read one or more MAC PDUs from the associated CC buffer 510 via read manager 512. Then, the MAC PDU(s) 542 may be sent to PHY Tx 426 during the first period. Information such as CC ID, TB ID, a data valid signal, and a data strobe signal may also be sent to PHY Tx 426 along with MAC PDU(s) 542.

[0065] However, in an underrun situation, the number of bytes in the available MAC PDU(s) 542 may be fewer than those requested by PHY Tx 426 and indicated by the UL grant. MAC -PHY interface 518 may identify an underrun situation when it receives an indication that the requested number of bytes are not available in the corresponding CC buffer 510 from MAC inline buffer 506, for example. When this happens, MAC-PHY interface 518 may implement a recovery mechanism to maintain synchronization between the various Layer 2 components and/or data flows once the available bytes have been transferred to PHY Tx 426. MAC -PHY interface 518 may initiate the recovery mechanism by asserting (at 513) a MAC error signal at the start of a second period during the TB. The subsequent operations of different recovery modes may vary and are described below in connection with FIGs. 5B, 5C, 5D, and 5E.

[0066] Referring to FIG. 5B, according to a first example recovery mode, MAC -PHY interface 518 may send padding data 544 in the absence of available MAC PDUs during the second period of the TB after the MAC error signal is asserted. Along with padding data 544, MAC -PHY interface 518 may send additional information, such as the CC ID, TB ID, a data valid signal, and/or a data strobe signal, for example. The transfer of padding data 544 may maintain synchronization between PHY Tx 426 and MAC -PHY interface 518 in the absence of TB data/MAC PDU(s).

[0067] Moreover, PHY Tx 426 may take various actions to cause subsequent retransmission of the MAC PDUs absent from the current transmission. For example, these actions may include inserting intentional cyclic redundancy check (CRC) error(s) into the UL transmission, driving the transmit power to zero on the corresponding CC, among others. Still further, Layer 2 hardware 560 may also take various actions to maintain data flow synchronization between Layer 2 uC(s) 420, uC memory 422, and MAC hardware accelerator 424. For example, MAC inline buffer 506 may advance a read pointer for the corresponding CC buffer 510 to the start of the next TB, drop control descriptors in command/status queue 524 until the start of the next TB, generate an interrupt signal that is sent to firmware 550, etc. In so doing, synchronized data flows may be maintained between the various Layer 2 components, hardware, and firmware shown in FIG. 5 A.

[0068] Still referring to FIG. 5B, once the same number of bytes of padding data 544 as those missing from the MAC PDU(s) has been transferred to PHY Tx 426, MAC -PHY interface 518 may de-assert (at 515) the MAC_error signal. At the end of the TB, Layer 2 uC(s) 420 may send (at 517) a Layer 2 command signal indicating an end of the TB. Then, MAC -PHY interface 518 may assert (at 519) a TB end signal at the end of the TB, which is the end of the second period in this example. PHY Tx 426 may de-assert (at 521) the PHY ready signal, and MAC hardware accelerator 424 may send (at 523) a Layer 2 status signal, which indicates the end of the TB, to Layer 2 uC(s) 420. Thus, the first example recovery mode may include transferring padding data 544 for the remainder of the TB, regardless of whether MAC PDUs become available during the second period of the TB.

[0069] Referring to FIG. 5C, according to a second example recovery mode, padding data 544 may also be sent in the event of an underrun situation. However, in this example, padding data 544 is only transferred until a threshold number of MAC PDUs becomes available during the TB. When this happens, MAC -PHY interface 518 may de-assert (at 515) the MAC error signal. Then, the transfer of MAC PDUs 546 to PHY Tx 426 may resume during a third period of the TB. These MAC PDUs 546 may be transferred until the end of the TB or until CC buffer 510 is empty. If CC buffer 510 runs out of MAC PDUs before the end of the TB, padding data 544 may once again be sent.

[0070] However, in some embodiments, the exemplary recovery mechanism may be implemented without the use of padding data. Such embodiments include the third example recovery mode described below in connection with FIG. 5D and the fourth example recovery mode described below in connection with FIG. 5E.

[0071] For example, referring to FIG. 5D, after the MAC error signal is asserted (at 513), MAC -PHY interface 518 may de-assert (at 541) a data valid signal to indicate an absence of additional data during the second period of the TB. If a threshold number of MAC PDUs become available before the end of the TB, MAC -PHY interface 518 may de-assert (at 515) the MAC error signal. Then, during a third period of the TB, the newly available MAC PDUs 546 may be transferred to PHY Tx 426.

[0072] Referring to FIG. 5E, if PHY Tx 426 runs out of buffered MAC PDUs while the data valid signal is still de-asserted, various actions may be taken to maintain synchronization. For example, in some embodiments, PHY Tx 426 may assert a PHY abort signal (not shown) with MAC -PHY interface 518 to end the transmission. However, in some other embodiments, PHY Tx 426 may assert a PHY error signal (at 527) to request MAC -PHY interface 518 resume transmission of MAC PDUs. PHY Tx 426 may de-assert (at 529) the PHY error signal, and MAC- PHY interface 518 may assert (at 531) a MAC clear signal, which indicates the transfer of MAC PDUs may resume. Prior to sending subsequent MAC PDUs 546 during a fourth TB period, MAC- PHY interface 518 may de-assert (at 533) the MAC error signal at the start of the fourth TB period. [0073] Although not shown in FIG. 5E, in some embodiments, if MAC PDUs are still not available when the PHY error signal is asserted (at 527), MAC -PHY interface 518 may continue asserting the MAC error signal and send padding data to PHY Tx 426. The padding data may be sent until the end of the TB, or until a threshold number of MAC PDUs are made available by MAC hardware accelerator 424.

[0074] One or more of MAC data tracker 516, transaction log 522, data tracking table 528, on-chip memory 418, and/or external memory 408 may be used to log transaction information associated with the transactions depicted in FIGs. 5B-5E, among others. The logged transaction information may be used to “debug” the system if data flow synchronization is lost.

[0075] For example, transaction log 522 of MAC -PHY interface 518 may be configured to maintain transaction information for each transaction between MAC -PHY interface 518 and PHY Tx 426. The transaction information may include, e.g., the number of bytes requested by PHY Tx 426, the number of MAC PDUs and/or bytes transferred to MAC -PHY interface 518 by MAC inline buffer 506, the number of MAC PDUs and/or bytes transferred to PHY Tx 426 by MAC- PHY interface 518, error and/or abort signals asserted/de-asserted by MAC -PHY interface 518 and/or PHY Tx 426, etc. This information may also be maintained in a circular data buffer, such as on-chip memory 418 and/or external memory 408. If transactions become unsynchronized between one or more of, e.g., Layer 2 uC(s) 420, uC memory 422, MAC processing circuit(s) 504, MAC inline buffer 506, external memory 408, MAC -PHY interface 518, PHY Tx 426, Layer 2 firmware 550, Layer 2 hardware 560, Layer 1 hardware 570, etc., this information may be used to debug Layer 2 data flows.

[0076] Moreover, transaction log 522 may maintain control information for each MAC- PHY interface 518 and PHY Tx 426 transaction. The control information may include, e.g., a start timestamp of the start of a PHY transmission by PHY Tx 426, an end timestamp of the end of a PHY transmission by PHY Tx 426, TB ID, CC ID, the number of bytes requested by PHY Tx 426, retransmission information, a retransmission flag, a code block group (CBG) retransmission ID, CBG data lengths, counts of error/abort signals that occurred during a TB, etc.

[0077] Register fields may be used by transaction log 522 to specify certain parameters that may be used during debugging. These parameters may include, e.g., a bitmap to enable transaction logging for specified CCs, a base address, queue depth, and write pointer for the circular data buffer (e.g., on-chip memory 418 and/or external memory 408), threshold values for the number of MAC/PHY errors in a transmission that cause MAC -PHY interface 518 to generate interrupts, and/or mask/status fields for interrupts upon abort/error occurrences, just to name a few. [0078] Using the transaction log, debugging may also be performed if any error and/or abort signals are asserted by MAC -PHY interface 518 and/or PHY Tx 426. These errors and/or abort signals may include, e.g., a PHY error signal, a PHY abort signal, a MAC error signal, and/or a MAC abort signal, just to name a few. PHY Tx 426 may assert a PHY error signal when a transaction error occurs. While a PHY error signal is asserted, MAC -PHY interface 518 may pause the transfer of MAC PDUs to PHY Tx 426 until the signal is de-asserted. PHY Tx 426 may assert a PHY abort signal for the remainder of the TB cycle to indicate that it will terminate the current transmission. MAC -PHY interface 518 may assert a MAC error signal to indicate an error (e.g., fewer than the requested number of bytes) has occurred at MAC -PHY interface 518. The MAC error signal may be de-asserted to resume normal transmission during the TB. MAC -PHY interface 518 may assert a MAC abort signal for the remainder of a TB to indicate that the current transmission will be terminated.

[0079] Still referring to FIG. 5 A, MAC hardware accelerator 424 may track hardware data flow for each CC based on TB status and the lengths of packet data read into MAC processing circuit(s) 504 based command/status descriptors from Layer 2 uC(s) 420. Examples of the information tracked by MAC hardware accelerator 424 include, e.g., TB entries indexed by TB ID, TB data length in bytes, retry CBG data lengths indexed by CBG ID, etc. Each TB entry may include status information (e.g., 0/Good, 1/Error, 2/Error recovered, etc.). Register fields may be used to indicate relevant parameters, such as a bitmap to enable a data tracking table for specified CCs, a base address of the buffer used to store data tracking table, a threshold for the number of status errors in tracking table before an interrupt is generated, a threshold for the number of data length errors in tracking table before an interrupt is generated, and/or mask/status fields for interrupt generation based on status/length error threshold(s), etc.

[0080] In some embodiments, the status and TB data length fields of MAC data tracker 516 may be cleared at the start of each TB. When MAC hardware accelerator 424 dequeues a command from command/status queue 524, the TB data length field for a corresponding CC and/or TB may be incremented by the packet length indicated by dequeued command. When PHY Tx 426 requests a certain number of bytes from MAC -PHY interface 518, MAC data tracker 516 and/or transaction log 522 may set a corresponding status field for each error and/or recovery that occurs during a TB. Moreover, when bytes are sent to and/or are transmitted by PHY Tx 426, MAC data tracker 516 and/or transaction log 522 may decrement the TB length associated with the current TB by the transmitted data length. Under normal conditions, the status and length fields may be cleared to zero at the end of each TB. A length error occurs if any of the length fields does not come back to zero at the end of a TB. MAC hardware accelerator 424 may generate interrupts to Layer 2 uC(s) 420 to aid in debugging discrepancies in the data flow coming in and being transmitted out of the MAC layer. Programmable thresholds used to trigger interrupts may be set using the register fields described above.

[0081] FIG. 6 illustrates a flow chart of an exemplary method 600 for wireless communication, according to some embodiments of the present disclosure. Exemplary method 600 may be performed by an apparatus for wireless communication, e.g., such as user equipment 202, node 300, apparatus 400, baseband chip 402, Layer 2 uC 420 (e.g., a uC cluster), uC memory 422 (e.g., a shared memory used by each uC in the cluster), MAC hardware accelerator 424, PHY Tx 426, MAC registers 502, one or more MAC processing circuit(s) 504, a MAC inline buffer 506, a MAC -PHY interface 518, a MAC DMA 532, a MAC uC interface 534, and/or any other circuit/component/unit mentioned herein. Method 600 may include steps 602-612 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 6.

[0082] Referring to FIG. 6, at 602, the apparatus may receive a request for a first number of bytes for a TB associated with a CC from PHY layer Tx. For example, referring to FIG. 5A, MAC -PHY interface 518 may receive a request for a certain number of bytes from PHY Tx 426. The request may include a CC ID and/or TB ID, among others.

[0083] At 604, the apparatus may obtain a MAC PDU from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. For example, referring to FIG. 5 A, MAC -PHY interface 518 may read a MAC PDU from CC buffer 510 via read manager 512.

[0084] At 606, the apparatus may transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. For example, referring to FIGs. 5B-5E, MAC -PHY interface 518 may transfer MAC PDU(s) 542 to PHY Tx 426.

[0085] At 608, the apparatus may determine whether the first number of bytes are available in the MAC inline buffer. For example, referring to FIG. 5 A, MAC -PHY interface 518 may receive an indication from MAC inline buffer 506 that the requested number of bytes are not yet ready in the corresponding CC buffer 510. When the indication is not received, MAC -PHY interface 518 may determine the requested number of bytes are available. When available, the operations may move to 610. Otherwise, when not available, the operations may move to 612.

[0086] At 610, the apparatus may transfer additional MAC PDUs until the requested number of bytes have been sent.

[0087] At 612, the apparatus may implement a recovery mechanism at an end of the first period to maintain synchronization between a MAC hardware accelerator associated with the MAC -PHY layer interface and the PHY layer Tx. For example, referring to FIGs. 5B-5E, MAC- PHY interface 518 may implement the recovery mechanism using one of the example recovery modes described above.

[0088] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0089] According to one aspect of the disclosure, a MAC hardware accelerator of a baseband chip is provided. The MAC hardware accelerator may include a MAC -PHY interface configured to receive, from a PHY layer Tx, a request for a first number of bytes for a TB associated with a CC. The MAC hardware accelerator may obtain a MAC PDU from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. The MAC -PHY layer interface may be configured to transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may be configured to implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

[0090] In some embodiments, the MAC hardware accelerator may obtain a MAC processing circuit. In some embodiments, the MAC processing circuit may be configured to retrieve a packet descriptor from a Layer 2 uC memory. In some embodiments, the MAC processing circuit may be configured to generate the MAC PDU associated with the CC based on the packet descriptor. In some embodiments, the MAC hardware accelerator may include the MAC inline buffer. In some embodiments, the MAC inline buffer may be configured to receive, from the MAC processing circuit, the MAC PDU. In some embodiments, the MAC inline buffer may be configured to maintain the MAC PDU in a CC buffer associated with the CC. In some embodiments, the MAC inline buffer may be configured to receive, from the MAC -PHY layer interface, a request for the first number of bytes from the CC buffer. In some embodiments, the MAC inline buffer may be configured to send the MAC PDU to the MAC -PHY layer interface. In some embodiments, in response to determining that the first number of bytes are unavailable in the CC buffer, the MAC inline buffer may be configured to indicate, to the MAC -PHY layer interface, that the first number of bytes are unavailable.

[0091] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by logging first transactions between a MAC processing circuit and the MAC inline buffer. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by logging second transactions between the MAC inline buffer, the MAC -PHY layer interface, and the PHY layer Tx. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by synchronizing transactions between the MAC processing circuit, the MAC inline buffer, MAC- PHY layer interface, and the PHY layer Tx during or after the recovery mechanism based on the first transactions and the second transactions.

[0092] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a MAC error signal with the PHY layer Tx during a second period associated with a remainder of the TB after the first period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring padding data to the PHY layer Tx during the second period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by deasserting the MAC error signal at an end of the second period. In some embodiments, the end of the second period may be associated with an end associated with the TB. [0093] In some embodiments, in response to the recovery mechanism being implemented, the MAC inline buffer may be configured to advance a read pointer associated with the MAC inline buffer to a subsequent TB.

[0094] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring padding data to the PHY layer Tx during the second period associated with the TB. In some embodiments, in response to determining that additional bytes associated with at least one threshold condition are available in MAC inline buffer, the MAC -PHY layer interface may be configured to implement the recovery mechanism by de-asserting the MAC error signal during a third period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring the additional bytes to the PHY layer Tx during the third period. In some embodiments, the at least one threshold condition may include a programmable number of bytes becoming available in the MAC inline buffer.

[0095] In some embodiments, the MAC inline buffer may be further configured to advance a read pointer associated with the MAC inline buffer by a number of padding data bytes transferred to the PHY layer Tx by the MAC -PHY layer interface.

[0096] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a first MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by de-asserting a data valid signal with the MAC -PHY layer interface during the second period.

[0097] In some embodiments, in response to determining that additional bytes associated with at least one threshold condition are available in the MAC inline buffer, the MAC -PHY layer interface may be configured to implement the recovery mechanism by de-asserting the first MAC error signal during a third period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting the data valid signal during the third period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring the additional bytes to the PHY layer Tx during the third period.

[0098] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by receiving, from the PHY layer Tx, a PHY abort signal indicating an end to a transmission associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by waiting until a subsequent TB to send additional MAC PDUs to PHY layer Tx.

[0099] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by receiving, from the PHY layer Tx, a PHY error signal requesting the MAC -PHY layer interface resume a transfer of MAC PDUs during a third period associated with the TB. In some embodiments, in response to determining additional MAC PDUs are available in the MAC inline buffer upon receipt of the PHY error signal, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring the additional MAC PDUs to the PHY layer Tx. In some embodiments, in response to determining additional MAC PDUs are not available in the MAC inline buffer upon receipt of the PHY error signal, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a second MAC error signal with the PHY layer Tx during a fourth period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring padding data to the PHY layer Tx during the fourth period.

[0100] In some embodiments, the MAC inline buffer may be configured to advance a read pointer associated with the MAC inline buffer based on a number of padding data bytes transferred to the PHY layer Tx by the MAC -PHY layer interface.

[0101] According to another aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 uC. The Layer 2 uC may be configured to generate one or more packet descriptors associated with a MAC PDU associated with a CC. The Layer 2 uC may send the one or more packet descriptors in a uC memory. The baseband chip may include a MAC hardware accelerator. The MAC hardware accelerator may include a MAC -PHY interface configured to receive, from a PHY layer Tx, a request for a first number of bytes for a TB associated with a CC. The MAC hardware accelerator may include a MAC PDU from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. The MAC -PHY layer interface may be configured to transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may be configured to implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

[0102] In some embodiments, the MAC hardware accelerator may include a MAC processing circuit. In some embodiments, the MAC processing circuit may be configured to retrieve a packet descriptor from a Layer 2 uC memory. In some embodiments, the MAC processing circuit may be configured to generate the MAC PDU associated with the CC based on the packet descriptor. In some embodiments, the MAC hardware accelerator may include the MAC inline buffer. In some embodiments, the MAC inline buffer may be configured to receive, from the MAC processing circuit, the MAC PDU. In some embodiments, the MAC inline buffer may be configured to maintain the MAC PDU in a CC buffer associated with the CC. In some embodiments, the MAC inline buffer may be configured to receive, from the MAC -PHY layer interface, a request for the first number of bytes from the CC buffer. In some embodiments, the MAC inline buffer may be configured to send the MAC PDU to the MAC -PHY layer interface. In some embodiments, in response to determining that the first number of bytes are unavailable in the CC buffer, the MAC inline buffer may be configured to indicate, to the MAC -PHY layer interface, that the first number of bytes are unavailable.

[0103] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by logging first transactions between a MAC processing circuit and the MAC inline buffer. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by logging second transactions between the MAC inline buffer, the MAC -PHY layer interface, and the PHY layer Tx. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by synchronizing transactions between the MAC processing circuit, the MAC inline buffer, MAC- PHY layer interface, and the PHY layer Tx during or after the recovery mechanism based on the first transactions and the second transactions.

[0104] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a MAC error signal with the PHY layer Tx during a second period associated with a remainder of the TB after the first period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring padding data to the PHY layer Tx during the second period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by deasserting the MAC error signal at an end of the second period. In some embodiments, the end of the second period may be associated with an end associated with the TB.

[0105] In some embodiments, in response to the recovery mechanism being implemented, the MAC inline buffer may be configured to advance a read pointer associated with the MAC inline buffer to a subsequent TB.

[0106] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring padding data to the PHY layer Tx during the second period associated with the TB. In some embodiments, in response to determining that additional bytes associated with at least one threshold condition are available in MAC inline buffer, the MAC -PHY layer interface may be configured to implement the recovery mechanism by de-asserting the MAC error signal during a third period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring the additional bytes to the PHY layer Tx during the third period. In some embodiments, the at least one threshold condition may include a programmable number of bytes becoming available in the MAC inline buffer.

[0107] In some embodiments, the MAC inline buffer may be further configured to advance a read pointer associated with the MAC inline buffer by a number of padding data bytes transferred to the PHY layer Tx by the MAC -PHY layer interface.

[0108] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a first MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by de-asserting a data valid signal with the MAC -PHY layer interface during the second period.

[0109] In some embodiments, in response to determining that additional bytes associated with at least one threshold condition are available in the MAC inline buffer, the MAC -PHY layer interface may be configured to implement the recovery mechanism by de-asserting the first MAC error signal during a third period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting the data valid signal during the third period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring the additional bytes to the PHY layer Tx during the third period.

[0110] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by receiving, from the PHY layer Tx, a PHY abort signal indicating an end to a transmission associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by waiting until a subsequent TB to send additional MAC PDUs to PHY layer Tx.

[OHl] In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by receiving, from the PHY layer Tx, a PHY error signal requesting the MAC -PHY layer interface resume a transfer of MAC PDUs during a third period associated with the TB. In some embodiments, in response to determining additional MAC PDUs are available in the MAC inline buffer upon receipt of the PHY error signal, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring the additional MAC PDUs to the PHY layer Tx. In some embodiments, in response to determining additional MAC PDUs are not available in the MAC inline buffer upon receipt of the PHY error signal, the MAC -PHY layer interface may be configured to implement the recovery mechanism by asserting a second MAC error signal with the PHY layer Tx during a fourth period associated with the TB. In some embodiments, the MAC -PHY layer interface may be configured to implement the recovery mechanism by transferring padding data to the PHY layer Tx during the fourth period.

[0112] In some embodiments, the MAC inline buffer may be configured to advance a read pointer associated with the MAC inline buffer based on a number of padding data bytes transferred to the PHY layer Tx by the MAC -PHY layer interface.

[0113] According to yet another aspect of the disclosure, a method of wireless communication of a baseband chip is provided. The method may include receiving, by a MAC- PHY layer interface, a request for a first number of bytes for a TB associated with a CC from a PHY layer Tx. The method may include obtaining, by a MAC -PHY layer interface, a MAC PDU from a MAC inline buffer associated with the CC. The MAC PDU may include a second number of bytes less than the first number of bytes. The method may include transferring, by a MAC -PHY layer interface, the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the method may include implementing, by the MAC -PHY layer interface, a recovery mechanism at an end of the first period to maintain synchronization between a MAC hardware accelerator associated with the MAC -PHY layer interface and the PHY layer Tx.

[0114] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0115] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0116] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0117] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0118] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A medium access control (MAC) hardware accelerator of a baseband chip, comprising: a MAC -physical (PHY) layer interface configured to: receive, from a PHY layer transmitter (Tx), a request for a first number of bytes for a transport block (TB) associated with a component carrier (CC); obtain a MAC protocol data unit (PDU) from a MAC inline buffer associated with the CC, the MAC PDU including a second number of bytes less than the first number of bytes; transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB; and in response to determining that the MAC inline buffer does not include the first number of bytes, implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

2. The MAC hardware accelerator of claim 1, further comprising: a MAC processing circuit configured to: retrieve a packet descriptor from a Layer 2 microcontroller (uC) memory; and generate the MAC PDU associated with the CC based on the packet descriptor; and the MAC inline buffer, wherein the MAC inline buffer is configured to: receive, from the MAC processing circuit, the MAC PDU; maintain the MAC PDU in a CC buffer associated with the CC; receive, from the MAC -PHY layer interface, a request for the first number of bytes from the CC buffer; send the MAC PDU to the MAC -PHY layer interface; and in response to determining that the first number of bytes are unavailable in the CC buffer, indicate, to the MAC -PHY layer interface, that the first number of bytes are unavailable.

3. The MAC hardware accelerator of claim 1, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: logging first transactions between a MAC processing circuit and the MAC inline buffer; logging second transactions between the MAC inline buffer, the MAC -PHY layer interface, and the PHY layer Tx; and synchronizing transactions between the MAC processing circuit, the MAC inline buffer, MAC -PHY layer interface, and the PHY layer Tx during or after the recovery mechanism based on the first transactions and the second transactions.

4. The MAC hardware accelerator of claim 1, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: asserting a MAC error signal with the PHY layer Tx during a second period associated with a remainder of the TB after the first period; transferring padding data to the PHY layer Tx during the second period; and de-asserting the MAC error signal at an end of the second period, wherein the end of the second period is associated with an end associated with the TB.

5. The MAC hardware accelerator of claim 4, wherein, in response to the recovery mechanism being implemented, the MAC inline buffer is configured to: advance a read pointer associated with the MAC inline buffer to a subsequent TB.

6. The MAC hardware accelerator of claim 1, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: asserting a MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period; transferring padding data to the PHY layer Tx during the second period associated with the TB; in response to determining that additional bytes associated with at least one threshold condition are available in MAC inline buffer, de-asserting the MAC error signal during a third period associated with the TB; and transferring the additional bytes to the PHY layer Tx during the third period, wherein the at least one threshold condition comprises a programmable number of bytes becoming available in the MAC inline buffer.

7. The MAC hardware accelerator of claim 6, wherein the MAC inline buffer is further configured to: advance a read pointer associated with the MAC inline buffer by a number of padding data bytes transferred to the PHY layer Tx by the MAC-PHY layer interface.

8. The MAC hardware accelerator of claim 1, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: asserting a first MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period; and de-asserting a data valid signal with the MAC -PHY layer interface during the second period.

9. The MAC hardware accelerator of claim 8, wherein the MAC -PHY layer interface is further configured to implement the recovery mechanism by: in response to determining that additional bytes associated with at least one threshold condition are available in the MAC inline buffer, de-asserting the first MAC error signal during a third period associated with the TB; asserting the data valid signal during the third period associated with the TB; and transferring the additional bytes to the PHY layer Tx during the third period.

10. The MAC hardware accelerator of claim 8, wherein the MAC -PHY layer interface is further configured to implement the recovery mechanism by: receiving, from the PHY layer Tx, a PHY abort signal indicating an end to a transmission associated with the TB; and waiting until a subsequent TB to send additional MAC PDUs to PHY layer Tx.

11. The MAC hardware accelerator of claim 8, wherein the MAC -PHY layer interface is further configured to implement the recovery mechanism by: receiving, from the PHY layer Tx, a PHY error signal requesting the MAC -PHY layer interface resume a transfer of MAC PDUs during a third period associated with the TB; in response to determining additional MAC PDUs are available in the MAC inline buffer upon receipt of the PHY error signal, transferring the additional MAC PDUs to the PHY layer Tx; in response to determining additional MAC PDUs are not available in the MAC inline buffer upon receipt of the PHY error signal, asserting a second MAC error signal with the PHY layer Tx during a fourth period associated with the TB; and transferring padding data to the PHY layer Tx during the fourth period.

12. The MAC hardware accelerator of claim 11, wherein the MAC inline buffer is further configured to: advance a read pointer associated with the MAC inline buffer based on a number of padding data bytes transferred to the PHY layer Tx by the MAC -PHY layer interface.

13. A baseband chip, comprising: a Layer 2 microcontroller (uC) configured to: generate one or more packet descriptors associated with a medium access control (MAC) protocol data unit (PDU) associated with a component carrier (CC); and send the one or more packet descriptors in a uC memory; a medium access control (MAC) hardware accelerator comprising: a MAC processing circuit configured to: generate the MAC PDU based on the one or more packet descriptors maintained in the uC memory; and send the MAC PDU to a MAC inline buffer associated with the CC; a MAC -physical (PHY) layer interface configured to: receive, from a PHY layer transmitter (Tx), a request for a first number of bytes for a transport block (TB) associated with the CC; obtain the MAC PDU from the MAC inline buffer associated with the CC, the MAC PDU including a second number of bytes less than the first number of bytes; transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB; and in response to determining that the MAC inline buffer does not include the first number of bytes, implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.

14. The baseband chip of claim 13, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: asserting a MAC error signal with the PHY layer Tx during a second period associated with a remainder of the TB after the first period; transferring padding data to the PHY layer Tx during the second period; and de-asserting the MAC error signal at an end of the second period.

15. The baseband chip of claim 13, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: asserting a MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period; transferring padding data to the PHY layer Tx during the second period associated with the TB; in response to determining that additional bytes associated with at least one threshold condition are available in the MAC inline buffer, de-asserting the MAC error signal during a third period associated with the TB; and transferring the additional bytes to the PHY layer Tx during the third period.

16. The baseband chip of claim 13, wherein the MAC -PHY layer interface is configured to implement the recovery mechanism by: asserting a first MAC error signal with the PHY layer Tx during a second period associated with the TB, the second period following the first period; and de-asserting a data valid signal with the MAC -PHY layer interface during the second period.

17. The baseband chip of claim 16, wherein the MAC -PHY layer interface is further configured to implement the recovery mechanism by: in response to determining that additional bytes associated with at least one threshold condition are available in the MAC inline buffer, de-asserting the first MAC error signal during a third period associated with the TB; asserting the data valid signal during the third period associated with the TB; and transferring the additional bytes to the PHY layer Tx during the third period.

18. The baseband chip of claim 16, wherein the MAC -PHY layer interface is further configured to implement the recovery mechanism by: receiving, from the PHY layer Tx, a PHY abort signal indicating an end to a transmission associated with the TB; and waiting until a subsequent TB to send additional MAC PDUs to PHY layer Tx.

19. The baseband chip of claim 16, wherein the MAC -PHY layer interface is further configured to implement the recovery mechanism by: receiving, from the PHY layer Tx, a PHY error signal requesting the MAC -PHY layer interface resume a transfer of MAC PDUs during a third period associated with the TB; in response to determining additional MAC PDUs are available in the MAC inline buffer upon receipt of the PHY error signal, transferring the additional MAC PDUs to the PHY layer Tx; in response to determining additional MAC PDUs are not available in the MAC inline buffer upon receipt of the PHY error signal, asserting a second MAC error signal with the PHY layer Tx during a fourth period associated with the TB; and transferring padding data to the PHY layer Tx during the fourth period.

20. A method of wireless communication of a baseband chip, comprising: receiving, by a MAC-physical (PHY) layer interface, a request for a first number of bytes for a transport block (TB) associated with a component carrier (CC) from a physical (PHY) layer transmitter (Tx); obtaining, by a MAC -PHY layer interface, a MAC protocol data unit (PDU) from a MAC inline buffer associated with the CC, the MAC PDU including a second number of bytes less than the first number of bytes; transferring, by a MAC -PHY layer interface, the MAC PDU to the PHY layer Tx during a first period associated with the TB; and in response to determining that the MAC inline buffer does not include the first number of bytes, implementing, by the MAC -PHY layer interface, a recovery mechanism at an end of the first period to maintain synchronization between a MAC hardware accelerator associated with the MAC -PHY layer interface and the PHY layer Tx.