WO2023003543A1

WO2023003543A1 - Apparatus and method of power optimized hybrid parallel/pipelined layer 2 processing for packets of different throughput types

Info

Publication number: WO2023003543A1
Application number: PCT/US2021/042443
Authority: WO
Inventors: Su-Lin Low; Chun-I Lee; Yunhong Li; Hausting Hong; Tianan Tim MA; Sonali Bagchi; Sammy Tzu-Kiang PAO; Sheethal KOVOOR; Na CHEN; Sangwon Ki; Youn Ki HONG
Original assignee: Zeku, Inc.
Priority date: 2021-07-20
Filing date: 2021-07-20
Publication date: 2023-01-26
Also published as: WO2023003543A8

Abstract

According to one aspect of the present disclosure, a baseband chip including a downlink (DL) Layer 2 block is disclosed. The DL Layer 2 block may include a set of DL Layer 2 microcontrollers that may activate when an enhanced mobile broadband (eMBB)/normal packet is received. The set of DL Layer 2 microcontrollers may be further configured to perform pipelined processing of the eMBB/normal packet. The set of DL Layer 2 microcontrollers may deactivate when a subsequent eMBB/normal packet is not received after a first period. The DL Layer 2 block may include a set of DL Layer 2 cores that may activate when a ultra-reliable low latency communication (URLLC) packet is received. The set of DL Layer 2 cores may perform parallel processing of the URLLC packet. The set of DL Layer 2 cores may deactivate when a subsequent URLLC packet is not received after a second period.

Description

APPARATUS AND METHOD OF POWER OPTIMIZED HYBRID PARALLEL/PIPELINED LAYER 2 PROCESSING FOR PACKETS OF DIFFERENT THROUGHPUT TYPES

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modem terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines a Radio Layer 2 (referred to here as “Layer 2”) as part of the cellular protocol stack structure corresponding to the data plane (DP) (also referred to as the “user plane”), which includes a Service Data Adaptation Protocol (SDAP) layer, a Packet Data Convergence Protocol (PDCP) layer, a Radio Link Control (RLC) layer, and a Medium Access Control (MAC), from top to bottom in the stack.

SUMMARY

[0003] Embodiments of apparatus and method for Layer 2 packet processing are disclosed herein.

[0004] According to one aspect of the present disclosure, a baseband chip including a downlink (DL) Layer 2 block is disclosed. The DL Layer 2 block may include a first set of logical channel (LC) queues configured to receive first throughput (TP)-type Layer 2 packets. The DL Layer 2 block may further include a second set of LC queues configured to receive second TP -type Layer 2 packets different than the first TP -type Layer 2 packets. The DL Layer 2 block may further include a set of DL Layer 2 microcontrollers (uCs). The set of DL Layer 2 microcontrollers may be configured to activate when a first TP -type Layer 2 packet is received by the first set of LC queues. In some embodiments, the first TP -type Layer 2 packet may be one of the first TP -type Layer 2 packets received by the first set of LC queues. The set of DL Layer 2 microcontrollers may be further configured to perform pipelined DL Layer 2 processing of the first TP -type Layer 2 packet. The set of DL Layer 2 microcontrollers may be further configured to deactivate when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period. The DL Layer 2 block may include a set of DL Layer 2 cores (sCs). The set of DL Layer 2 cores may be configured to activate when a second TP -type Layer 2 packet is received by the second set of LC queues. In some embodiments, the second TP -type Layer 2 packet may be one of the second TP -type Layer 2 packets received by the second set of LC queues. The set of DL Layer 2 cores may be further configured to perform parallel DL Layer 2 processing of the second TP -type Layer 2 packet. The set of DL Layer 2 cores may be further configured to deactivate when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period.

[0005] According to one aspect of the present disclosure, a baseband chip including a UL

Layer 2 block is disclosed. The UL Layer 2 block may include an uplink (UL) Layer 2 hardware accelerator block (ULHWAC). The ULHWAC may be configured to receive, from a PHY layer, a first UL grant specifying one or more grant conditions for a first UL transmission. The ULHWAC may be configured to determine whether the UL transmission is a first TP -type Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions. The UL Layer 2 block may further include a set of UL Layer 2 microcontrollers. The UL Layer 2 microcontrollers may be configured to activate when the UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet. The UL Layer 2 microcontrollers may be configured to perform pipelined UL Layer 2 processing of the first TP -type Layer 2 packet. The UL Layer 2 block may further include a set of UL Layer 2 cores. The set of UL Layer 2 cores may be configured to activate when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet. The set of UL Layer 2 cores may be configured to perform parallel UL Layer 2 processing of the second TP -type Layer 2 packet.

[0006] According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include a set of DL Layer 2 microcontrollers configured to perform pipelined DL Layer 2 processing of a first TP -type DL Layer 2 packet. The baseband chip may further include a set of DL Layer 2 cores configured to perform parallel DL Layer 2 processing of a second TP -type DL Layer 2 packet. The baseband chip may further include a set of UL Layer 2 microcontrollers configured to perform pipelined UL Layer 2 processing of a first TP -type UL Layer 2 packet. The baseband chip may further include a set of UL Layer 2 cores configured to perform parallel UL Layer 2 processing of a second TP -type UL Layer 2 packet.

[0007] According to another aspect of the present disclosure, a method of a baseband chip is disclosed. The method may include receiving, by a first set of LC queues, first TP -type Layer 2 packets. The method may further include receiving, by a second set of LC queues, second TP -type Layer 2 packets different than the first TP -type Layer 2 packets. The method may further include activating a set of DL Layer 2 microcontrollers when a first TP -type Layer 2 packet is received by the first set of LC queues. The method may further include performing, by the set of DL Layer 2 microcontrollers, pipelined DL Layer 2 processing of the first TP -type Layer 2 packet. The method may further include deactivating the set of DL Layer 2 microcontrollers when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period. The method may further include activating a set of DL Layer 2 cores when a second TP -type Layer 2 packet is received by the second set of LC queues. The method may further include performing, by the set of DL Layer 2 cores, parallel DL Layer 2 processing of the second TP -type Layer 2 packet. The method may further include deactivating the set of DL Layer 2 cores when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period. [0008] According to another aspect of the present disclosure, a method of a baseband chip is disclosed. The method may include receiving, by a UL Layer 2 hardware accelerator block, a first UL grant specifying one or more grant conditions for a first UL transmission. The method may further include determining, by the UL Layer 2 hardware accelerator block, whether the UL transmission is a first TP -type Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions. The method may further include activating a set of UL Layer 2 microcontrollers when the UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet. The method may further include performing, by the set of UL Layer 2 microcontrollers, pipelined UL Layer 2 processing of the first TP -type Layer 2 packet. The method may further include activating a set of UL Layer 2 cores when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet. The method may further include performing, by the set of UL Layer 2 cores, parallel UL Layer 2 processing of the second TP -type Layer 2 packet.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0010] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0011] FIG. 2 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0012] FIG. 3A illustrates a detailed block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure.

[0013] FIG. 3B illustrates a detailed block diagram of an exemplary DL Layer 2 hardware accelerator (DLHWAC) of the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure.

[0014] FIG. 3C illustrates a detailed block diagram of a DL Layer 2 block of the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure.

[0015] FIG. 3D illustrates a detailed block diagram of an exemplary UL Layer 2 hardware accelerator (ULHWAC) of the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure.

[0016] FIG. 3E illustrates a detailed block diagram of a UL Layer 2 block of the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure.

[0017] FIG. 4A illustrates a flow chart of a first exemplary method for DL Layer 2 data processing, according to some embodiments of the present disclosure.

[0018] FIG. 4B illustrates a flow chart of a second exemplary method for UL Layer 2 data processing, according to some embodiments of the present disclosure.

[0019] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0020] FIG. 6 illustrates a block diagram of a conventional baseband chip.

[0021] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0022] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0023] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0024] In general, terminology may be understood at least in part from usage in context.

For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0025] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system.

[0026] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0027] In cellular and/or Wi-Fi communication, Layer 2 is the protocol stack layer responsible for ensuring a reliable, error-free datalink for the wireless modem (referred to herein as a “baseband chip”) of a UE. More specifically, Layer 2 interfaces with Radio Layer 1 (also referred to as “Layer 1” or the “physical (PHY) layer”) and Radio Layer 3 (also referred to as “Layer 3” or the “Internet Protocol (IP) layer”), passing data packets up or down the protocol stack structure, depending on whether the data packets are associated with UL or DL transmissions. [0028] Furthermore, Layer 2 may perform de-multiplexing / multiplexing, segmentation / reassembly, aggregation / de-aggregation, and sliding window automatic repeat request (ARQ) techniques, among others, to ensure reliable end-to-end data integrity and in-order error-free delivery of data packets. For a UL data packet, Layer 3 data packets (e.g., IP data packets) may be input into the Layer 2 protocol stack, and encoded into MAC layer packets (e.g., 5G NR) for transporting to the PHY layer. For a DL data packet, Layer 1 data packets (e.g., PHY layer data packets) may be input into the Layer 2 protocol stack, where Layer 2 data processing operations are performed on the data packets before being passed up to Layer 3. Layer 3 performs IP header extraction, IP checksum, IP tracing, and IP routing and classification, among other things.

[0029] FIG. 6 illustrates a block diagram of a conventional baseband chip 600. As seen in

FIG. 6, a conventional baseband chip 600 may include PHY subsystem 602 configured to transmit and/or receive data packets over an air interface, a protocol stack 604 (e.g., residing at the baseband chip) that includes a control plane 606 and a data plane 608, Layer 3/Layer 4 subsystems 610, and an application processor (AP)/host 612.

[0030] Control plane 606 performs two main functions: non-access stratum (NAS) function and radio resource control (RRC) function. The NAS function performs network layer control that relates to mobility management, session management, security management, and system selection, just to name a few. The RRC function performs radio resource allocation and configuration, as well as the radio channel control of radio bearers, logical channels, and security (ciphering, integrity configurations).

[0031] Data plane 608 performs Layer 2 and Layer 3/4 functions. Layer 2 functions relate to PDU processing. For example, the MAC layer performs multiplexing and demultiplexing, and mapping of logical channels to transport channels. The RLC layer performs automatic repeat request (ARQ) procedures at the radio link level and the error recovery of each logical channel. The PDCP layer performs packet-level processing for data ciphering, integrity, and compression. The SDAP layer performs quality-of-service (QoS) classification of IP flows to data radio bearers (DRBs).

[0032] The conventional baseband chip 600 illustrated in FIG. 6 uses a software-centric

Layer 2 protocol data stack. Namely, the data stack processing resides on a Layer 2 main processor and uses a limited number of hardware accelerators. Using the conventional baseband chip 600, the Layer 2 main processor (not shown) may access a data packet by direct memory access (DMA) from a PHY layer memory at the PHY subsystem(s) 602. Furthermore, the HW accelerators may DMA a UL data packet to the Layer 3 external DDR memory of Layer 3 subsystem 610.

[0033] In conventional baseband chip 600, Layer 2 data processing (e.g., processing the transport blocks received from Layer 1 (e.g., PHY subsystem 602) in the DL user plane or processing data packets received from Layer 3 in the UL user plane) is usually implemented using software modules executed on a generic baseband processor, such as a central processing unit (CPU) or a digital signal processor (DSP). During processing, data may be frequently transferred between the generic main processor (not shown) and external memory (Layer 3 external DDR memory or Layer 2 buffer - not shown), e.g., for buffering between each layer. As a result, the known solutions for Layer 2 data processing suffer from high power consumption, large data buffer, and long process delays.

[0034] Moreover, when a user equipment (UE) is configurated with Carrier Aggregation

(CA), multiple Component Carriers (CCs) are typically aggregated for reception and transmission. As such, the UE may receive multiple grants concurrently, one from each CC and cell, which determines the scheduled packets reception and transmission in the downlink and uplink directions, respectively, additional details of which are provided below in connection with FIGs. 7A and 7B. [0035] In the downlink (DL) direction, the DL MAC layer receives code blocks from the

PHY subsystem 602 from multiple CCs. The DL MAC layer may then re-order each Transport Block (TB), extract the MACsubPDU headers to obtain the MAC PDUs, and transfer the packet to the RLC and PDCP DP Layer 2 for further processing in each logical channel and associated radio bearers. Once Layer 2 data processing is complete, the packets are sent to Layer 3/Layer 4 subsystems 610, where the QoS flows in each radio bearer are routed to the appropriate application. [0036] Conversely, in the uplink (UL) direction, the Layer 3/Layer 4 subsystems 610 prepare the UL packets from multiple QoS flows for each data radio bearer (DRB), and the UL packets may then be transferred to Layer 2 logical channel queues, ready for transmission. Once the UL MAC layer receives the UL grant, which allocates resources for the physical uplink shared channel (PUSCH)) using the physical downlink control channel (PDCCH) at the beginning of a slot. For example, the UL grant may be received in a downlink control indicator (DCI) on the PDCCH. The UL grant may inform the UE to transmit the UL MACPDU at a time delay equivalent to K2 slots away from the current slot. Typically, K2<1 grants are implied to be serviced for low latency application data, and hence, radio bearers/logical channels (LCs) data are pulled into such grants to be sent out as soon as possible. The UL MAC scheduling algorithm uses a Logical Channel Prioritization (LCP) method to schedule packets from a logical channel (LC) according to allocated grant bytes from a configured maximum bucket size setting.

[0037] One challenge of conventional data plane 608 processing relates to the power consumption by baseband chip 600, which needs to support different application types, such as high throughput high latency data transfers (enhanced mobile broadband (eMBB) traffic), as well as low latency low data rate applications (ultra-reliable low latency communication (URLLC)). When operating in low data rate applications, the power consumption of conventional baseband chip 600 may not be optimized. For example, in low data rate applications, conventional data plane 608 processing may use resources inefficiently when processing DL/UL Layer 2/Layer 3 data packets, consume power unnecessarily during low data rate transfers, use an increased double data rate (DDR) transfer, an increased data plane interconnect bus transactions during periods of activity, and Layer 2 to Layer 3 data transfers are unoptimized and cause undue delays.

[0038] Thus, there exists an unmet need for a data plane processing technique that optimizes power consumption during both high and low data rate applications.

[0039] To overcome these and other challenges, the present disclosure provides a hybrid parallel/pipelined dynamic packet processing scheme to optimize the Layer 2 data processing path for concurrent multiple QoS flows, radio bearers, LCs, and CCs, as compared to known approaches. The proposed hybrid parallel/pipelined dynamic packet processing scheme employs multiple microcontrollers (uCs) to perform efficient pipelined packet data processing when there is high throughput (TP) (eMBB) or normal traffic. At the same time, the scheme may control a set of parallel smaller processors/cores (sCs) for low TP traffic (e.g., ultra-reliable low latency communication (URLLC)), which may be scalable with the Layer 2 protocol stack. In the absence of traffic for each data type, the UE and/or baseband chip of the present disclosure may optimize power savings by deactivating the uCs, sCs, and memory resources, depending on the traffic type. Additional details of these techniques are provided below in connection with FIGs. 1-5.

[0040] Although the following processing techniques are described in connection with

Layer 2 data processing, the same or similar techniques may be applied to Layer 3 and/or Layer 4 data processing to optimize power consumption at Layer 3 and/or Layer 4 subsystems without departing from the scope of the present disclosure.

[0041] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (IoT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0042] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0043] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0044] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0045] Core network element 106 may connect with a large network, such as the Internet

108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0046] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0047] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5. Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible.

[0048] Transceiver 506 may include any suitable device for sending and/or receiving data.

Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0049] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0050] As shown in FIG. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0051] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0052] Referring back to FIG. 1 , in some embodiments, user equipment 102 may determine when a DL Layer 2 packet of a first TP -type (e.g., eMBB/normal traffic) and/or a second TP -type (e.g., URLLC traffic) is received from an external device, e.g., such as access node 104. When a DL Layer 2 packet of a first TP -type is received, user equipment 102 may activate a set of pipelined uCs to perform high performance packet processing for high TP and normal traffic. This allows efficient distributed pipelined processing of high TP data with Layer 2 hardware acceleration, where the Layer 2 processes are distributed across multiple uCs, each performing dedicated tasks (e.g., MAC tasks, RLC tasks, PDCP tasks, etc.). On the other hand, when a DL Layer 2 packet of the second TP -type is received, user equipment 102 may activate a set of parallel sCs to perform parallel processing mode for low TP or URLLC traffic. Here, each sC may perform tasks associated with the full Layer 2 protocol stack. Moreover, depending on the amount of URLLC traffic, more or fewer of the sCs may be activated or deactivated to process DL Layer 2 packets with the stringent latency requirements while at the same time optimizing power consumption. Still further, when DL Layer 2 packets of both the first TP -type and the second TP -type are received, user equipment 102 may activate the set of pipelined uCs and the set of parallel sCs such that a hybrid combination of parallel and pipelined Layer 2 packet processing may be performed concurrently for the respective traffic types. The orthogonal activate/deactivate control scheme of each of the pipeline mode (first TP -type Layer 2 packets), parallel mode (second TP -type Layer 2 packets), and hybrid mode (first and second TP -type Layer 2 packets) enables dynamically optimized power consumption according to the traffic types. In this way, uCs, sCs, memories, and associated Layer 2 hardware resources may be deactivated if not in use, thereby further optimizing power consumption. Additional details of each of these techniques are provided below in connection with FIGs. 2, 3A-3E, 4A, and 4B.

[0053] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip

202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5. Besides the on-chip memory 218 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG. 2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0054] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204 via interface 214. RF chip 204, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204.

[0055] In the downlink, antenna 210 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202.

[0056] As seen in FIG. 2, baseband chip 202 may include a DL Layer 2 block 220a and a

UL Layer 2 block 220b. DL Layer 2 block 220a may include a DL Layer 2 hardware (HW) accelerator (DLHWAC) that includes different DL Layer 2 circuits (e.g., MAC circuit, RLC circuit, PDCP circuit, etc.) each configured to perform certain tasks in a pipelined fashion. DL Layer 2 block 220a may also include a set of DL Layer 2 uCs each configured to perform a task associated with at least one of the DL Layer 2 circuits of the DLHWAC. For example, a first DL uC (uCl) may perform tasks associated with a PDCP circuit of the HW accelerator, a DL second uC (uC2) may perform tasks associated with an RLC circuit of the HW accelerator, a third DL uC (uC3) may perform tasks associated with a MAC circuit, and so on. The set of DL Layer 2 uCs may be activated when one or more first TP -type DL Layer 2 packets are received in an LC queue of the DLHWAC. Conversely, the set of DL Layer 2 uCs may be deactivated when a first TP -type DL Layer 2 packet is not received by the LC queue after a first period (e.g., 1ms, 5ms, 10ms, etc.). [0057] Moreover, DL Layer 2 block 220a may include a set of DL Layer 2 sCs (also referred to herein as “DL Layer 2 cores”) each configured to perform tasks of the full DL Layer 2 protocol stack. The set of DL Layer 2 sCs may be activated when one or more second TP -type DL Layer 2 packets are received by the LC queue, and deactivated when a subsequent second TP -type DL Layer 2 packet is not received by the LC queue after a second period (e.g., 1ms, 5ms, 10ms, etc.). Also, depending on the amount of second TP -type DL Layer 2 traffic, the number of DL Layer 2 sCs activated/deactivated may be scaled up or down accordingly.

[0058] Still referring to FIG. 2, UL Layer 2 block 220b may include a UL Layer 2 HW accelerator (ULHWAC) that includes different UL Layer 2 circuits (e.g., MAC circuit, RLC circuit, PDCP circuit, etc.) each configured to perform certain tasks in a pipelined fashion. UL Layer 2 block 220b may also include a set of UL Layer 2 uCs each configured to perform a task for the ULHWAC. By way of example, a first UL uC (uCl) may process the packet descriptors from an LCP operation (which ran on a different uC), and programs the ULHWAC for packet transmission. A second UL uC (uC2) may processes the PHY Grantlnd (also referred to herein as a “UL grant”) for a CC, and run the LCP algorithm to retrieve prioritized packet processing from each LC that is eligible for inclusion into this CC’s UL transmission. Each packet descriptor may be composed through the SDAP, PDCP, RLC, and MAC layers, and sent to uCl to be scheduled for UL transmission. Each uC may perform multiple LCP tasks for multiple CCs. In pipeline mode, uC2 may be designated to perform LTE LCP, or 5G LCP if appropriate. In need be, a third UL uC (uC3) may also perform LCP processing and/or 5G LCP tasks. Additional details of these techniques are provided below in connection with FIGs. 3A-3E, 4A, and 4B.

[0059] FIG. 3 A illustrates a detailed block diagram of the exemplary baseband chip 202 of

FIG. 2, according to some embodiments of the present disclosure. FIG. 3B illustrates a detailed block diagram of the exemplary DLHWAC 304a of FIG. 3A, according to some embodiments of the present disclosure. FIG. 3C illustrates a detailed block diagram of the exemplary DL Layer 2 block 220a of the baseband chip 202 of FIG. 3 A, according to some embodiments of the present disclosure. FIG. 3D illustrates a detailed block diagram of an exemplary ULHWAC 304b of the baseband chip 202 of FIG. 3A, according to some embodiments of the present disclosure. FIG. 3E illustrates a detailed block diagram of a UL Layer 2 block 220b of the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure. FIGs. 3A, 3B, 3C, 3D, and 3E will be described together.

[0060] Referring to FIG. 3A, baseband chip 202 may include, e.g., PHY subsystems 302,

DL Layer 2 block 220a, UL Layer 2 block 220b, external DDR memory 324, and AP/Host 326, among others. DL Layer 2 block 220a may include, e.g., a DLHWAC 304a, a set of DL Layer 2 microprocessors (uCs) 318a, a DL uC local shared memory 320a (hereinafter “DL uC memory 320a”), and a set of DL Layer 2 cores (sCs) 322a, among others. DLHWAC 304a may include, e.g., a PHY interface 314a, DL MAC circuit 312a, a DL inline buffer 310a, DL RLC circuit 308a, and PDCP circuit 306a. UL Layer 2 block 220b may include, e.g., a ULHWAC 304b, a set of UL Layer 2 uCs 318b, a UL uC local shared memory 320b (hereinafter “UL uC memory 320b”), and a set of UL Layer 2 sCs 322b, among others. ULHWAC 304b may include, e.g., a PHY interface 314b, UL MAC circuit 312b, a UL inline buffer 310b, UL RLC circuit 308b, and UL PDCP circuit 306b. Although not shown, an inline buffer may be located between each of DL PHY IF 314a and DL MAC circuit 312a and configured to maintain code blocks received from PHY system 302. Moreover, another inline buffer may be located between UL PHY IF 314b and UL MAC circuit 312b and configured to maintain UL Layer 2 packets ready for transmission by PHY system 302. [0061] Still referring to FIG. 3A, the circuits of the DL Layer 2 block 220a may perform

DL Layer 2 packet processing operations that include, e.g., header extractions (MAC circuits), bitmap and window checking operations (RLC circuit), window operations, and ciphering/deciphering, data integrity operations (PDCP circuit). With respect to the first TP -type Layer 2 packets (e.g., eMBB packets and/or normal TP packets), each of the DL and UL blocks 220a, 220b may be controlled on a per-packet level (first TP -type Layer 2 packet) by the set of DL Layer 2 uCs 318a and the set of UL Layer 2 uCs 318b, respectively. The control of these blocks may be accomplished through command and status queues residing in the DL and/or UL uC shared memory 320a, 320b. Each of the set of DL and UL Layer 2 uCs may include one or more processor cores, which may program a corresponding circuit of the DLHWAC 304a and the ULHWAC 304b in a pipelined fashion. In some embodiments, the interworking between the corresponding uCs and DLHWAC 304a and ULHWAC 304b may be accomplished through the command/status queues of the DL uC memory 320a and UL uC memory 320b. When first TP -type Layer 2 packets (e.g., eMBB/normal packets) are received by an LC of inline buffer 310a, the set of DL Layer 2 uCs 318a may be activated.

[0062] With respect to second TP -type Layer 2 packets (e.g., URLLC packets), the set of

DL Layer 2 sCs 322a may be activated when a logical channel (LC) queue of UL inline buffer 310a, 310b receives a Layer 2 packet of the second TP -type. The UL Layer 2 sCs 322b may be activated when a UL grant for second TP -type traffic is received. Each sC in the DL and UL set may include a power-optimized scalable parallel controller/processor/core. Each sC may include a core that is smaller than that of the uC. For example, each sC may be smaller and consume less power than a uC by up to 90% or more. Moreover, each sC core may be configured to run tasks associated with the full Layer 2 protocol stack (e.g., MAC tasks, RLC tasks, PDCP tasks, etc.) and interwork with each of the circuits in DLHWAC 304a and ULHWAC 304B through command and status queues.

[0063] Referring to FIG. 3B, after MAC header extraction at DL MAC circuit 312a, a DL

Layer 2 packet may be input into a corresponding logical channel (LC) queue 330a of inline buffer 310a. Each of the LC queues 330a may be mapped to a corresponding QoS flow 340a. As illustrated in FIG. 3B, a first set of QoS flows/LC queues 350a may be dedicated for eMBB/normal traffic, and a second set of QoS flows/LC queues 350b may be mapped for URLLC traffic. Each DL Layer 2 packet may be mapped to a QoS flow/DRBs 340a with the corresponding priority level, resource traffic type, packet delay budget, and/or latency condition. The RBs, which are categorized as URLLC traffic types, may be identified based on these QoS parameters, which meet user-specified requirements. The QoS flow/LC queue mapping may be identified when baseband chip 202/user equipment 102 connects to the EPC/5GC and DRB set up, for example. The first set of LC queues/QoS flows 350a may be dedicated to the set of DL Layer 2 uCs 318a for the pipelined Layer 2 packet processing. The second set of QoS flows/LC queues 350b may be dedicated to the set of DL Layer 2 sCs 322a for the parallel Layer 2 packet processing.

[0064] Referring to FIG. 3C, the Layer 2 command/status queues are organized into first

TP -type queues 301 and second TP -type queues 303 in the DL uC memory 320a. For the first TP- type Layer 2 packet, uCl may process status queue of DL MAC circuit 312a such that the DL MAC circuit 312a may decode each DL Layer 2 packet. uCl may route the packet to one or more of the DL RLC circuit 308a and/or the DL PDCP circuit 306a. Moreover, uCl may inform uC2 that the packet has been routed to the next circuit in the pipeline. Then, uC2 may program the DL RLC circuit 308a command queues, which may enable DL RLC circuit 308a to perform window checking operation and bitmap processing. Then, uC2 may process the Layer 2 status queue of DL RLC circuit 308a and route the DL Layer 2 packet to DL PDCP circuit 306a and program its command queue so that DL PDCP circuit 306a may perform window checking and bitmap operation, as well as deciphering, de-integrity, and decompression operations. Then, uC3 may run the DL PDCP circuit 306a status queue and route the reordered Layer 2 packet(s) to Layer 3. [0065] Second TP -type Layer 2 packets may be separately processed by the set of DL Layer

2 sCs 322a, each of which may be configured to interwork with each of the DL MAC circuits 310, the DL RLC circuit 308a, and/or the DL PDCP circuit 306a. When a number of second TP -type DL Layer 2 packets are received by LC queues 330a, additional sCs may be activated to ensure URLLC packets are processed in accordance with their stringent latency requirements. Conversely, when the number of second TP -type DL Layer 2 packets received by the LC queues 330a reduces, the number of sCs may be reduced to conserve power and reduce processing overhead.

[0066] Control of the set of DL Layer 2 uCs 318a and DL Layer 2 sCs 322a may be orthogonal, such that when there is only URLLC traffic, the set of DL Layer 2 uCs 318a may be deactivated to optimize power consumption at baseband chip 202. On the other hand, when there is only eMBB/normal traffic, the set of DL Layer 2 sCs 322a may be deactivated to conserve power. Operations of activating/deactivating DL pipelined mode and DL parallel mode are described in connection with FIGs. 3B and 3C.

[0067] For example, referring to FIGs. 3B and 3C, upon initialization, the QoS flows/DRBs

340a and LC queues 330a may be configured based on the TP -type. Once connected, and upon receipt of PHY data code blocks from PHY interface 314a, the DL MAC circuit 312a may concatenate the code blocks to extract MAC protocol data units (MACSubPDUs). Moreover, DL MAC circuit 312a may decode the MAC, RLC, and PDCP headers, such that the packet can be classified into the associated QoS flow/LC queues 350a, 350b, depending on the TP -type.

[0068] In some embodiments, when the current DL PIPELINE MODE of the set of DL

Layer 2 uCs 318a is inactive, and when at least one first TP -type DL Layer 2 packet is received by DL MAC circuit 312a command/status queue, then the DL PIPELINE mode may be activated, and uCl, uC2, and uC3 may be turned on. Then, the DLHWAC 304a and the set of DL Layer 2 uCs 318a process the Layer 2 packet(s) in a pipelined fashion. Here, the voltage and clock frequency of each of the circuits in the DLHWAC 304a may be scaled up.

[0069] In some embodiments, when DL PIPELINE MODE is active, and no subsequent first TP -type DL Layer 2 packets are received from PHY subsystem 302 after a threshold period, then the set of DL Layer 2 uCs 318a may be deactivated to optimize power consumption. In other words, uCl, uC2, and uC3 may be powered down. Here, the voltage and clock frequency of each of the circuits in the DLHWAC 304a are scaled down. Any second TP -type DL Layer 2 packets may continue to be processed in parallel mode by the set of DL Layer 2 sCs 322a.

[0070] In some embodiments, when DL URLLC PARALLEL MODE is active, and when no second TP -type Layer 2 packets are received after a threshold period, then DL URLLC PARALLEL MODE may be deactivated, and the set of DL Layer 2 sCs 322a may be powered down to optimize power consumption. Here, the voltage and clock frequency of each of the circuits in the DLHWAC 304a may be scaled down. Any first TP -type DL Layer 2 packets may continue to be processed in pipeline mode by the set of DL Layer 2 uCs 318a.

[0071] In some embodiment, when DL URLLC PARALLEL MODE is inactive, and when a second TP -type DL Layer 2 packet is received by LC queues 330a, one sC (e.g., such as sCl) may be activated to process the second TP -type DL Layer 2 packet. Here, the voltage and clock frequency of DLHWAC 304a may be scaled up, but in a manner that is proportionally smaller than when the set of DL Layer 2 uCs 318a is activated. This is because the data rate of second TP- type DL Layer 2 packets is lower than that of the first TP -type DL Layer 2 packets.

[0072] In some embodiments, when DL URLLC PARALLEL MODE is active, and when additional second TP -type DL Layer 2 packets are received by LC queues 330a, an evaluation may be made to redistribute DL Layer 2 processing tasks on the sCs by assessing whether the packets in the URLLC MAC queue meet a threshold number. If activating more sCs would be beneficial due to the increased number of second TP -type packets, then the set of DL Layer 2 sCs 322a may be scaled up so that more sCs are activated. However, when fewer sCs are needed, then one or more sCs may be deactivated to reduce power consumption.

[0073] Referring to FIG. 3D, in the UL, a first set of QoS flows/LC queues 350c associated with the eMBB/normal traffic may be mapped together, and a second set of QoS flows/LC queues 350d associated with the URLLC traffic may be mapped together. Each UL Layer 2 packet may be mapped to a corresponding QoS flow based on its priority level, resource traffic type, packet delay budget, and/or latency conditions. The mapping between QoS flows 340b and LC channels 330b may be determined when baseband chip 202/user equipment 102 connects to the EPC/5GC and RB set up, for example.

[0074] The first set of QoS flows/LC queues 350c may be dedicated to the set of UL Layer

2 uCs 318b for the pipelined Layer 2 packet processing operations (e.g., DL MAC circuit 312a, DL RLC circuit 308a, PDCP circuit 306a, etc.), and the second set of QoS flows/LC queues 350d may be dedicated to the set of UL Layer 2 sCs 322b for parallel Layer 2 packet processing operations. During UL transmission, PHY subsystem 302 may send a UL grant associated with a CC ULHWAC 304b. The UL grant may specify grant conditions, e.g., such as the K2, the number of grant bytes, the duration of the scheduled transmission, and the subcarrier spacing (SCS), just to name a few. From the grant conditions, UL MAC circuit 312b may perform LCP processing to retrieve UL Layer 2 packets from the appropriate LC queue 330a, which satisfies the grant conditions. In the example illustrated in FIG. 3D, the LCP for CC0 from UL grant arrives with corresponding URLLC characteristics, UL Layer 2 packets from the second set of QoS flows/LC queues 350d are included in the UL transmission for CC0.

[0075] Referring to FIG. 3E, the Layer 2 command/status queues may be specified as eMBB/normal command/status queues 315 or URLLC command/status queues 317 depending on the LCP characteristics of the CC, which may be identified based on the grant conditions specified by the UL grant. eMBB/normal command/status queues 315 may correspond to the set of UL Layer 2 uCs 318b for pipelined packet processing with the circuits of ULHWAC 304b. On the other hand, URLLC command/status queues 317 may correspond to the set of UL Layer 2 sCs 322b for parallel scalable packet processing with the circuits of ULHWAC 304b.

[0076] More specifically, for eMBB packet processing, uC2 may process the UL grant for a CC and run LCP operations to retrieve prioritized eMBB packets from each LC that are eligible for inclusion into this CC’s UL transmission. Each packet descriptor may be composed through the SDAP, PDCP, RLC, and MAC layers, and sent to uCl, which schedules the UL transmission. A uC may run multiple LCP tasks for multiple CCs. In pipeline mode, uC2 may be designated to run LTE LCP processes or 5G LCP processes, depending on the RAT -type associated with the UL grant. uCl may process packet descriptors from the LCP operations (which ran on uC2) and program the circuits of ULHWAC 304b for UL Layer 2 packet transmission. Similar to uC2, uC3 may perform LCP processing, and when needed, uC3 may be designated to run 5G LCP tasks. [0077] Independently, the set of UL Layer 2 sCs 322b may interwork with ULHWAC 304b through the URLLC command/status queues 317. Each sC may run one or more LCP tasks for a CC’s UL grant, and then compose the URLLC packet descriptors to be programmed onto the ULHWAC 304b through the URLLC command/status queues 317. The number of active sCs may be scalable to include more or fewer cores if the number of CCs increases or decreases, respectively. The set of UL Layer 2 uCs 318b and the set of UL Layer 2 sCs 322b may be orthogonally controlled to activate or deactivate depending on the traffic type. This hybrid architecture allows the set of UL Layer 2 uCs 318b to be powered off completely if there is only URLLC traffic. Conversely, the set of UL Layer 2 sCs 322b can be powered off when there is only eMBB/normal traffic. Operations of activating/deactivating DL pipelined mode and DL parallel mode will now be described in connection with FIGs. 3D and 3E.

[0078] For example, when UL URLLC PARALLEL MODE is active, LCP tasks may begin on one or more sC of the set of UL Layer 2 sCs 322b. When a set of grant conditions are satisfied, the UL grant may be categorized as a URLLC type. These conditions may include one or more of, e.g., K2=0, SCS > URLLC MaxSCS, and grant time < URLLC MaxGrantTime. Here, may specify the slot location of the resources allocated for the UL transmission in terms of K2 distance from where the PDCCH DCI grant was received. When K2=0, this implies that the UL grant schedules resources for a low latency transmission (e.g., URLLC) allocated within the same slot as the UL grant. URLLC MaxSCS may be a configurable user-specified threshold that indicates the maximum allowed SCS to be qualified as a URLLC grant. Each LC may be configured with a A IlowedSC S- isl, which specifies whether this LC is associated with a UL grant that carries the allowed SCS. For a URLLC grant, this SCS may be greater than or equal to this threshold, which indicates the higher subcarrier spacing of URLLC traffic for low latency performance. URLLC MaxGrantTime may be another configurable user-specified threshold that indicates the maximum allowed grant time for the scheduled transmission to qualify as a URLLC grant. Each LC may be configured with a standard specified maxPUSCH-Duration which specifies whether the LC will be transmitted in connection with a UL grant that has a GrantTime less than or equal to the maximum PUSCH duration value. This ensures that the URLLC packets are included for transmission in a UL grant of a CC, which may be of short duration that satisfies low latency performance. Upon receipt of a UL grant from PHY subsystem 302, or if Layer 3 buffer (not shown) or the LC queues 330b level increases, the following schemes may be used to dynamically activate/deactivate the set of UL Layer 2 uCs 318b and/or the set of UL Layer 2 sCs 322b.

[0079] In some embodiments, if the Layer 3 buffer or LC queues 330b exceeds a user- specified UL PIPELINE BUFFER THRESHOLD level, or when a UL grant for a CC is characterized as eMBB, then UL PIPELINE MODE may be activated and the set of UL Layer 2 uCs 318b powered on. More specifically, uCl, uC2, and uC3 are activated. Then, the LCP task for the corresponding CC may be run on either uC2 or uC3. Here, the voltage and clock frequency of ULHWAC 304b are scaled up.

[0080] In some embodiments, when the UL PIPELINE MODE is active, and when a subsequent eMBB/normal UL grant is not received within a threshold period, then the UL PIPELINE MODE may be deactivated, and the set of UL Layer 2 uCs 318b may be powered down. The voltage and/or clock frequency of ULHWAC 304b may be scaled down. Here, if there are any UL grants for URLLC, these LCP tasks may be run on the set of UL Layer 2 sCs 322b. [0081] In some embodiments, when the UL URLLC PARALLEL MODE is active, and when all received UL grants are of the eMBB/normal type, and when there are no UL grants for URLLC traffic for a threshold period, then the UL URLLC PARALLEL MODE may be deactivated, and the set of UL Layer 2 sCs 322b may be deactivated to optimize power. The voltage and/or clock frequency of ULHWAC 304b may be scaled down. Here, the UL grants for eMBB traffic may be processed by the set of UL Layer 2 uCs 318b.

[0082] In some embodiments, when a UL grant for URLLC traffic is received, and when the UL URLLC PARALLEL MODE is inactive, one sC (e g., sCl) of the set of UL Layer 2 sCs 322b may be activated, and the LCP tasks for the UL grant may be run by sCl. Here, the voltage and/or clock frequency of ULHWAC 304b may be scaled up.

[0083] In some embodiments, when a subsequent UL grant for URLLC traffic is received, and when the UL URLLC PARALLEL MODE is active, another sC (e.g., sC2) of the set of UL Layer 2 sCs 322b may be activated, and the LCP tasks for the UL grant may be run by sC2. An evaluation may be made to redistribute UL Layer 2 processing tasks on the sCs by assessing whether the packets in the second set of QoS flowLC queues 350d exceed a threshold number. If activating more sCs would expedite the LCP processing of the UL grants, then the set of UL Layer 2 sCs 322b may be scaled up so that more sCs are active. However, when fewer sCs are needed, then one or more sCs may be deactivated to reduce power consumption.

[0084] FIG. 4A illustrates a flow chart of a first exemplary method 400 for DL Layer 2 data processing, according to some embodiments of the present disclosure. Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, DL Layer 2 block 220a, DLHWAC 304a, the set of DL Layer 2 uCs 318a, the set of DL Layer 2 sCs 322a, and/or node 500. Method 400 may include steps 402-412 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4A.

[0085] Referring to FIG. 4A, at 402, the apparatus may activate a set of DL Layer 2 microcontrollers when a first TP -type Layer 2 packet (e.g., eMBB/normal packet) is received by the first set of LC queues. For example, referring to FIGs. 3 A and 3B, when first TP -type Layer 2 packets (e.g., eMBB/normal packets) are received by an LC of the LC queues 330a of inline buffer 310a, the set of DL Layer 2 uCs 318a may be activated.

[0086] At 404, the apparatus may perform pipelined DL Layer 2 processing of the first TP- type Layer 2 packet. For example, referring to FIG. 3C, the Layer 2 command/status queues are organized into first TP -type queues 301 and second TP -type queues 303 in the DL uC memory 320a. For the first TP -type Layer 2 packet, uC 1 may process status queue of DL MAC circuit 312a such that the DL MAC circuit 312a may decode each DL Layer 2 packet. uCl may route the packet to one or more of the DL RLC circuit 308a and/or the DL PDCP circuit 306a. Moreover, uC 1 may inform uC2 that the packet has been routed to the next circuit in the pipeline. Then, uC2 may program the DL RLC circuit 308a command queues, which may enable DL RLC circuit 308a to perform window checking operation and bitmap processing. Then, uC2 may process the Layer 2 status queue of DL RLC circuit 308a and route the DL Layer 2 packet to DL PDCP circuit 306a and program its command queue so that DL PDCP circuit 306a may perform window checking and bitmap operation, as well as deciphering, de-integrity, and decompression operations. Then, uC3 may run the DL PDCP circuit 306a status queue and route the reordered Layer 2 packet(s) to Layer 3.

[0087] At 406, the apparatus may deactivate the set of DL Layer 2 microcontrollers when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period. For example, referring to FIG. 3 A, when the UL PIPELINE MODE is active, and when a subsequent eMBB/normal UL grant is not received within a threshold period, then the UL PIPELINE MODE may be deactivated, and the set of UL Layer 2 uCs 318b may be powered down. The voltage and/or clock frequency of ULHWAC 304b may be scaled down.

[0088] At 408, the apparatus may activate a set of DL Layer 2 cores when a second TP- type Layer 2 packet is received by the second set of LC queues. For example, referring to FIG. 3 A, when DL URLLC PARALLEL MODE is inactive, and when a second TP -type DL Layer 2 packet is received by LC queues 330a, one sC (e.g., such as sCl) may be activated to process the second TP -type DL Layer 2 packet.

[0089] At 410, the apparatus may perform parallel DL Layer 2 processing of the second

TP -type Layer 2 packet. For example, referring to FIG. 3 A, the set of DL Layer 2 sCs 322a may be activated when a logical channel (LC) queue of UL inline buffer 310a, 310b receives a Layer 2 packet of the second TP -type. The UL Layer 2 sCs 322b may be activated when a UL grant for second TP -type traffic is received. Each sC in the DL and UL set may include a power-optimized scalable parallel controller/processor/core. Each sC may include a core that is smaller than that of the uC. For example, each sC may be smaller and consume less power than a uC by up to 90% or more. Moreover, each sC core may be configured to run tasks associated with the full Layer 2 protocol stack (e.g., MAC tasks, RLC tasks, PDCP tasks, etc.) and interwork with each of the circuits in DLHWAC 304a and ULHWAC 304b through command and status queues.

[0090] At 412, the apparatus may deactivate the set of DL Layer 2 cores when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period. For example, referring to FIG. 3A, when DL URLLC PARALLEL MODE is active, and when no second TP -type Layer 2 packets are received after a threshold period, then DL URLLC PARALLEL MODE may be deactivated, and the set of DL Layer 2 sCs 322a may be powered down to optimize power consumption.

[0091] FIG. 4B illustrates a flow chart of a second exemplary method for UL Layer 2 data processing, according to some embodiments of the present disclosure. Exemplary method 401 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, UL Layer 2 block 220b, the set of UL Layer 2 uCs 318b, the set of UL Layer 2 sCs 322b, and/or node 500. Method 401 may include steps 422-432 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4B.

[0092] Referring to FIG. 4B, at 422, the apparatus may receive a first UL grant specifying one or more grant conditions for a first UL transmission. For example, referring to FIG. 3 A, during UL transmission, PHY subsystem 302 may send a UL grant associated with a CC ULHWAC 304b. The UL grant may specify grant conditions, e.g., such as the K2, the number of grant bytes, the duration of the scheduled transmission, and the subcarrier spacing (SCS), just to name a few. From the grant conditions, UL MAC circuit 312b may perform LCP processing to retrieve UL Layer 2 packets from the appropriate LC queue 330a, which satisfies the grant conditions. In the example illustrated in FIG. 3D, the LCP for CC0 from UL grant arrives with corresponding URLLC characteristics, UL Layer 2 packets from the second set of QoS flows/LC queues 350d are included in the UL transmission for CC0. The UL grant may specify eMBB/normal UL transmission or URLLC UL transmission.

[0093] At 424, the apparatus may determine whether the UL transmission is a first TP -type

Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions. For example, referring to FIG. 3 A, when a set of grant conditions are satisfied, the UL grant may be categorized as a URLLC type. These conditions may include one or more of, e.g., K2=0, SCS > URLLC MaxSCS, and grant time < URLLC MaxGrantTime. Here, may specify the slot location of the resources allocated for the UL transmission in terms of K2 distance from where the PDCCH DCI grant was received. When K2=0, this implies that the UL grant schedules resources for a low latency transmission (e.g., URLLC) allocated within the same slot as the UL grant. URLLC MaxSCS may be a configurable user-specified threshold that indicates the maximum allowed SCS to be qualified as a URLLC grant. Each LC may be configured with a Allow edSCS-List, which specifies whether this LC is associated with a UL grant that carries the allowed SCS. For a URLLC grant, this SCS may be greater than or equal to this threshold, which indicates the higher subcarrier spacing of URLLC traffic for low latency performance. URLLC MaxGrantTime may be another configurable user-specified threshold that indicates the maximum allowed grant time for the scheduled transmission to qualify as a URLLC grant. Each LC may be configured with a standard specified maxPUSCH-Duration which specifies whether the LC will be transmitted in connection with a UL grant that has a GrantTime less than or equal to the maximum PUSCH duration value. This ensures that the URLLC packets are included for transmission in a UL grant of a CC, which may be of short duration that satisfies low latency performance.

[0094] At 426, the apparatus may activate a set of UL Layer 2 microcontrollers when the

UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet. For example, referring to FIG. 3 A, if the Layer 3 buffer or LC queues 330b exceeds a user-specified UL PIPELINE BUFFER THRESHOLD level, or when a UL grant for a CC is characterized as eMBB, then UL PIPELINE MODE may be activated and the set of UL Layer 2 uCs 318b powered on.

[0095] At 428, the apparatus may perform pipelined UL Layer 2 processing of the first TP- type Layer 2 packet. For example, referring to FIG. 3A, for eMBB packet processing, uC2 may process the UL grant for a CC and run LCP operations to retrieve prioritized eMBB packets from each LC that are eligible for inclusion into this CC’ s UL transmission. Each packet descriptor may be composed through the SDAP, PDCP, RLC, and MAC layers, and sent to uCl, which schedules the UL transmission. A uC may run multiple LCP tasks for multiple CCs. In pipeline mode, uC2 may be designated to run LTE LCP processes or 5G LCP processes, depending on the RAT -type associated with the UL grant. uCl may process packet descriptors from the LCP operations (which ran on uC2) and program the circuits of ULHWAC 304b for UL Layer 2 packet transmission. Similar to uC2, uC3 may perform LCP processing, and when needed, uC3 may be designated to run 5GLCP tasks.

[0096] At 430, the apparatus may activate a set of UL Layer 2 cores when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet. For example, referring to FIG. 3 A, when DL URLLC PARALLEL MODE is inactive, and when a second TP -type DL Layer 2 packet is received by LC queues 330a, one sC (e.g., such as sCl) may be activated to process the second TP -type DL Layer 2 packet. Here, the voltage and clock frequency of DLHWAC 304a may be scaled up, but in a manner that is proportionally smaller than when the set of DL Layer 2 uCs 318a is activated. This is because the data rate of second TP- type DL Layer 2 packets is lower than that of the first TP -type DL Layer 2 packets. [0097] At 432, the apparatus may parallel UL Layer 2 processing of the second TP -type

Layer 2 packet. For example, referring to FIG. 3 A, The UL Layer 2 sCs 322b may be activated when a UL grant for second TP -type traffic is received. Each sC in the UL set may include a power-optimized scalable parallel controller/processor/core. Each sC may include a core that is smaller than that of the uC. For example, each sC may be smaller and consume less power than a uC by up to 90% or more. Moreover, each sC core may be configured to run tasks associated with the full Layer 2 protocol stack (e.g., MAC tasks, RLC tasks, PDCP tasks, etc.) and interwork with each of the circuits in ULHWAC 304b through command and status queues.

[0098] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0099] According to one aspect of the present disclosure, a baseband chip including a DL

Layer 2 block is disclosed. The DL Layer 2 block may include a first set of LC queues configured to receive the first TP -type Layer 2 packets. The DL Layer 2 block may further include a second set of LC queues configured to receive second TP -type Layer 2 packets different than the first TP- type Layer 2 packets. The DL Layer 2 block may further include a set of DL Layer 2 microcontrollers (uCs). The set of DL Layer 2 microcontrollers may be configured to activate when a first TP -type Layer 2 packet is received by the first set of LC queues. In some embodiments, the first TP -type Layer 2 packet may be one of the first TP -type Layer 2 packets received by the first set of LC queues. The set of DL Layer 2 microcontrollers may be further configured to perform pipelined DL Layer 2 processing of the first TP -type Layer 2 packet. The set of DL Layer 2 microcontrollers may be further configured to deactivate when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period. The DL Layer 2 block may include a set of DL Layer 2 cores (sCs). The set of DL Layer 2 cores may be configured to activate when a second TP -type Layer 2 packet is received by the second set of LC queues. In some embodiments, the second TP -type Layer 2 packet may be one of the second TP- type Layer 2 packets received by the second set of LC queues. The set of DL Layer 2 cores may be further configured to perform parallel DL Layer 2 processing of the second TP -type Layer 2 packet. The set of DL Layer 2 cores may be further configured to deactivate when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period. [0100] In some embodiments, the baseband chip may further include a Layer 2 hardware accelerator block (DLHWAC). The DLHWAC may include a MAC block configured to perform the first MAC layer processing of the first TP -type Layer 2 packet and the second TP -type Layer 2 packet. The DLHWAC may further include an RLC block configured to perform the first RLC layer processing of the first TP -type Layer 2 packet and the second TP -type Layer 2 packet. The DLHWAC may further include a PDCP block configured to perform the first PDCP layer processing of the first TP -type Layer 2 packet and the second TP -type Layer 2 packet. In some embodiments, the Layer 2 hardware accelerator block may be activated when the first TP -type Layer 2 packet is received by the first set of LC queues or when the second TP -type Layer 2 packet is received by the second set of LC queues. In some embodiments, the Layer 2 hardware accelerator block may be deactivated when the subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after the first period and when the subsequent second TP- type Layer 2 packet is not received by the second set of LC queues after the second period.

[0101] In some embodiments, the set of DL Layer 2 microcontrollers may include a first microcontroller associated with the MAC block and configured to perform second MAC layer processing of the first TP -type Layer 2 packet. In some embodiments, the set of DL Layer 2 microcontrollers may include a second microcontroller associated with the RLC block and configured to perform second RLC layer processing of the first TP -type Layer 2 packet after the first microcontroller completes the second MAC layer processing. In some embodiments, the set of DL Layer 2 microcontrollers may include a third microcontroller associated with the PDCP block and configured to perform second PDCP layer processing of the first TP -type Layer 2 packet after the second microcontroller completes the second RLC layer processing.

[0102] In some embodiments, the set of DL Layer 2 cores may include a first core associated with the MAC block, the RLC block, and the PDCP block and configured to perform second MAC layer processing, second RLC layer processing, and second PDCP layer processing of the second TP -type Layer 2 packet. In some embodiments, the set of DL Layer 2 cores may include a second core associated with the MAC block, the RLC block, and the PDCP block and configured to perform the second MAC layer processing, the second RLC layer processing, and the second PDCP layer processing of a different second TP -type Layer 2 packet. In some embodiments, the first core and the second core may operate concurrently.

[0103] In some embodiments, the second core may be deactivated when second TP -type

Layer 2 packet traffic decreases to a first threshold. In some embodiments, the first core may be deactivated when the second TP -type Layer 2 packet traffic decreases to a second threshold lower than the first threshold.

[0104] In some embodiments, the first TP -type Layer 2 packet may include an eMBB packet. In some embodiments, the second TP -type Layer 2 packet may include a URLLC packet. [0105] According to one aspect of the present disclosure, a baseband chip including a UL

Layer 2 block is disclosed. The UL Layer 2 block may include a UL Layer 2 hardware accelerator block (ULHWAC). The ULHWAC may be configured to receive, from a PHY layer, a first UL grant specifying one or more grant conditions for a first UL transmission. The ULHWAC may be configured to determine whether the UL transmission is a first TP -type Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions. The UL Layer 2 block may further include a set of UL Layer 2 microcontrollers. The UL Layer 2 microcontrollers may be configured to activate when the UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet. The UL Layer 2 microcontrollers may be configured to perform pipelined UL Layer 2 processing of the first TP -type Layer 2 packet. The UL Layer 2 block may further include a set of UL Layer 2 cores. The set of UL Layer 2 cores may be configured to activate when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet. The set of UL Layer 2 cores may be configured to perform parallel UL Layer 2 processing of the second TP -type Layer 2 packet.

[0106] In some embodiments, the set of UL Layer 2 microcontrollers may be further configured to deactivate when a second UL grant specifying a subsequent first TP -type Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a first period. In some embodiments, the set of UL Layer 2 cores may be further configured to deactivate when a third UL Layer 2 grant specifying a subsequent second TP -type Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a second period. [0107] In some embodiments, the set of UL Layer 2 microcontrollers may include a first microcontroller. In some embodiments, the first microcontroller (uC2) may be configured to perform one or more first LCP processes associated with a first RAT. In some embodiments, the first microcontroller may be configured to retrieve the first TP -type Layer 2 packet from an LCP queue based on the LCP processes. In some embodiments, the first microcontroller may be configured to send the first TP -type Layer 2 packet to the UL Layer 2 hardware accelerator block. In some embodiments, the set of UL Layer 2 microcontrollers may include a second microcontroller (uCl). In some embodiments, the second microcontroller may be configured to schedule the transmission of the first TP -type Layer 2 packet for transmission by the UL Layer 2 hardware accelerator block.

[0108] In some embodiments, the set of UL Layer 2 microcontrollers may include a third microcontroller (uC3). In some embodiments, the third microcontroller may be configured to perform one or more second LCP processes associated with a second RAT.

[0109] In some embodiments, the set of UL Layer 2 cores may include a first core associated with a first CC and configured to perform the first LCP for the second TP -type Layer 2 packet when the second TP -type Layer 2 packet is associated with the first CC. In some embodiments, the set of UL Layer 2 cores may include a second core associated with a second CC and configured to perform second LCP processes for the second TP -type Layer 2 packet when the second TP -type Layer 2 packet is associated with the second CC.

[0110] In some embodiments, the second core may be deactivated when the second TP- type Layer 2 packet traffic associated with the second CC decreases to a first threshold. In some embodiments, the first core may be deactivated when the second TP -type Layer 2 packet traffic associated with the first CC decreases to a second threshold lower than the first threshold.

[0111] In some embodiments, the first TP -type Layer 2 packet may include an eMBB packet. In some embodiments, the second TP -type Layer 2 packet may include a URLLC packet. [0112] According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include a set of DL Layer 2 microcontrollers configured to perform pipelined DL Layer 2 processing of a first TP -type DL Layer 2 packet. The baseband chip may further include a set of DL Layer 2 cores configured to perform parallel DL Layer 2 processing of a second TP -type DL Layer 2 packet. The baseband chip may further include a set of UL Layer 2 microcontrollers configured to perform pipelined UL Layer 2 processing of a first TP -type UL Layer 2 packet. The baseband chip may further include a set of UL Layer 2 cores configured to perform parallel UL Layer 2 processing of a second TP -type UL Layer 2 packet.

[0113] In some embodiments, the set of DL Layer 2 microcontrollers may be further configured to activate when the first TP -type DL Layer 2 packet is received by a first set of LC queues. In some embodiments, the set of DL Layer 2 microcontrollers may be further configured to deactivate when a subsequent first TP -type DL Layer 2 packet is not received by the first set of LC queues after a first period.

[0114] In some embodiments, the set of DL Layer 2 cores may be further configured to activate when the second TP -type DL Layer 2 packet is received by a second set of LC queues. In some embodiments, the set of DL Layer 2 cores may be further configured to deactivate when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period.

[0115] In some embodiments, the set of UL Layer 2 microcontrollers may be further configured to activate when a UL Layer 2 hardware accelerator block receives a first UL grant associated with a first TP -type UL Layer 2 packet. In some embodiments, the set of UL Layer 2 microcontrollers may be further configured to deactivate when a second UL grant associated with the first TP -type UL Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a third period.

[0116] In some embodiments, the set of UL Layer 2 cores may be further configured to activate when a UL Layer 2 hardware accelerator block receives a first UL grant associated with a second TP -type UL Layer 2 packet. In some embodiments, the set of UL Layer 2 cores may be further configured to deactivate when a second UL grant associated with the second TP -type UL Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a third period. [0117] According to another aspect of the present disclosure, a method of a baseband chip is disclosed. The method may include receiving, by a first set of LC queues, first TP -type Layer 2 packets. The method may further include receiving, by a second set of LC queues, second TP -type Layer 2 packets different than the first TP -type Layer 2 packets. The method may further include activating a set of DL Layer 2 microcontrollers when a first TP -type Layer 2 packet is received by the first set of LC queues. The method may further include performing, by the set of DL Layer 2 microcontrollers, pipelined DL Layer 2 processing of the first TP -type Layer 2 packet. The method may further include deactivating the set of DL Layer 2 microcontrollers when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period. The method may further include activating a set of DL Layer 2 cores when a second TP -type Layer 2 packet is received by the second set of LC queues. The method may further include performing, by the set of DL Layer 2 cores, parallel DL Layer 2 processing of the second TP -type Layer 2 packet. The method may further include deactivating the set of DL Layer 2 cores when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period. [0118] According to another aspect of the present disclosure, a method of a baseband chip is disclosed. The method may include receiving, by a UL Layer 2 hardware accelerator block, a first UL grant specifying one or more grant conditions for a first UL transmission. The method may further include determining, by the UL Layer 2 hardware accelerator block, whether the UL transmission is a first TP -type Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions. The method may further include activating a set of UL Layer 2 microcontrollers when the UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet. The method may further include performing, by the set of UL Layer 2 microcontrollers, pipelined UL Layer 2 processing of the first TP -type Layer 2 packet. The method may further include activating a set of UL Layer 2 cores when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet. The method may further include performing, by the set of UL Layer 2 cores, parallel UL Layer 2 processing of the second TP -type Layer 2 packet.

[0119] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0120] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0121] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0122] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0123] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A baseband chip, comprising: a first set of logical channel (LC) queues configured to receive first throughput (TP)-type Layer 2 packets; a second set of LC queues configured to receive second TP -type Layer 2 packets different than the first TP -type Layer 2 packets; a set of downlink (DL) Layer 2 microcontrollers configured to: activate when a first TP -type Layer 2 packet is received by the first set of LC queues, the first TP -type Layer 2 packet being one of the first TP -type Layer 2 packets received by the first set of LC queues; and perform pipelined DL Layer 2 processing of the first TP -type Layer 2 packet; and deactivate when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period; a set of DL Layer 2 cores configured to: activate when a second TP -type Layer 2 packet is received by the second set of LC queues, the second TP -type Layer 2 packet being one of the second TP -type Layer 2 packets received by the second set of LC queues; perform parallel DL Layer 2 processing of the second TP -type Layer 2 packet; and deactivate when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period.

2. The baseband chip of claim 1, further comprising a Layer 2 hardware accelerator block including: a medium access control (MAC) block configured to perform first MAC layer processing of the first TP -type Layer 2 packet and the second TP -type Layer 2 packet; a radio link control (RLC) block configured to perform first RLC layer processing of the first TP -type Layer 2 packet and the second TP -type Layer 2 packet; and a packet data convergence protocol (PDCP) block configured to perform first PDCP layer processing of the first TP -type Layer 2 packet and the second TP -type Layer 2 packet, wherein the Layer 2 hardware accelerator block is activated when the first TP -type Layer 2 packet is received by the first set of LC queues or when the second TP -type Layer 2 packet is received by the second set of LC queues, and wherein the Layer 2 hardware accelerator block is deactivated when the subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after the first period and when the subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after the second period.

3. The baseband chip of claim 2, wherein the set of DL Layer 2 microcontrollers comprises: a first microcontroller associated with the MAC block and configured to perform second

MAC layer processing of the first TP -type Layer 2 packet; a second microcontroller associated with the RLC block and configured to perform second RLC layer processing of the first TP -type Layer 2 packet after the first microcontroller completes the second MAC layer processing; and a third microcontroller associated with the PDCP block and configured to perform second PDCP layer processing of the first TP -type Layer 2 packet after the second microcontroller completes the second RLC layer processing.

4. The baseband chip of claim 2, wherein the set of DL Layer 2 cores comprise: a first core associated with the MAC block, the RLC block, and the PDCP block and configured to perform second MAC layer processing, second RLC layer processing, and second PDCP layer processing of the second TP -type Layer 2 packet; and a second core associated with the MAC block, the RLC block, and the PDCP block and configured to perform the second MAC layer processing, the second RLC layer processing, and the second PDCP layer processing of a different second TP -type Layer 2 packet, wherein the first core and the second core operate concurrently.

5. The baseband chip of claim 4, wherein: the second core is deactivated when second TP -type Layer 2 packet traffic decreases to a first threshold, and the first core is deactivated when the second TP -type Layer 2 packet traffic decreases to a second threshold lower than the first threshold.

6 The baseband chip of claim 1, wherein: the first TP -type Layer 2 packet includes an enhanced mobile broadband (eMBB) packet, and the second TP -type Layer 2 packet includes an ultra-reliable low latency communication (URLLC) packet.

7. A baseband chip, comprising: an uplink (UL) Layer 2 hardware accelerator block configured to: receive, from a physical (PHY) layer, a first UL grant specifying one or more grant conditions for a first UL transmission; determine whether the UL transmission is a first TP -type Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions; a set of UL Layer 2 microcontrollers configured to: activate when the UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet; and perform pipelined UL Layer 2 processing of the first TP -type Layer 2 packet; and a set of UL Layer 2 cores configured to: activate when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet; and perform parallel UL Layer 2 processing of the second TP -type Layer 2 packet.

8. The baseband chip of claim 7, wherein: the set of UL Layer 2 microcontrollers is further configured to deactivate when a second UL grant specifying a subsequent first TP -type Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a first period, and the set of UL Layer 2 cores is further configured to deactivate when a third UL Layer 2 grant specifying a subsequent second TP -type Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a second period.

9. The baseband chip of claim 8, wherein the set of UL Layer 2 microcontrollers comprises: a first microcontroller configured to: perform one or more first logical channel prioritization (LCP) processes associated with a first radio access technology (RAT); retrieve the first TP -type Layer 2 packet from an LCP queue based on the LCP processes; and send the first TP -type Layer 2 packet to the UL Layer 2 hardware accelerator block; and a second microcontroller configured to schedule the transmission of the first TP -type Layer 2 packet for transmission by the UL Layer 2 hardware accelerator block.

10. The baseband chip of claim 9, wherein the set of UL Layer 2 microcontrollers further comprises: a third microcontroller configured to perform one or more second LCP processes associated with a second RAT.

11. The baseband chip of claim 7, wherein the set of UL Layer 2 cores comprise: a first core associated with a first CC and configured to perform first logical channel prioritization (LCP) for the second TP -type Layer 2 packet when the second TP -type Layer 2 packet is associated with the first CC; and a second core associated with a second CC and configured to perform second LCP processes for the second TP -type Layer 2 packet when the second TP -type Layer 2 packet is associated with the second CC.

12. The baseband chip of claim 11, wherein: the second core is deactivated when second TP -type Layer 2 packet traffic associated with the second CC decreases to a first threshold, and the first core is deactivated when the second TP -type Layer 2 packet traffic associated with the first CC decreases to a second threshold lower than the first threshold.

13. The baseband chip of claim 7, wherein: the first TP -type Layer 2 packet includes an enhanced mobile broadband (eMBB) packet, and the second TP -type Layer 2 packet includes an ultra-reliable low latency communication (URLLC) packet.

14. A baseband chip, comprising: a set of downlink (DL) Layer 2 microcontrollers configured to perform pipelined DL Layer 2 processing of a first throughput (TP)-type DL Layer 2 packet; a set of DL Layer 2 cores configured to perform parallel DL Layer 2 processing of a second TP -type DL Layer 2 packet; a set of uplink (UL) Layer 2 microcontrollers configured to perform pipelined UL Layer 2 processing of a first TP -type UL Layer 2 packet; and a set of UL Layer 2 cores configured to perform parallel UL Layer 2 processing of a second TP -type UL Layer 2 packet.

15. The baseband chip of claim 14, wherein the set of downlink (DL) Layer 2 microcontrollers is further configured to: activate when the first TP -type DL Layer 2 packet is received by a first set of logical channel (LC) queues; and deactivate when a subsequent first TP -type DL Layer 2 packet is not received by the first set of LC queues after a first period.

16. The baseband chip of claim 14, wherein the set of DL Layer 2 cores is further configured to: activate when the second TP -type DL Layer 2 packet is received by a second set of LC queues; and deactivate when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period.

17. The baseband chip of claim 14, wherein the set of UL Layer 2 microcontrollers is further configured to: activate when a UL Layer 2 hardware accelerator block receives a first UL grant associated with a first TP -type UL Layer 2 packet; and deactivate when a second UL grant associated with the first TP -type UL Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a third period.

18. The baseband chip of claim 14, wherein the set of UL Layer 2 cores is further configured to: activate when a UL Layer 2 hardware accelerator block receives a first UL grant associated with a second TP -type UL Layer 2 packet; and deactivate when a second UL grant associated with the second TP -type UL Layer 2 packet is not received by the UL Layer 2 hardware accelerator block after a third period.

19. A method of a baseband chip, comprising receiving, by a first set of logical channel (LC) queues, first throughput (TP)-type Layer 2 packets; receiving, by a second set of LC queues, second TP -type Layer 2 packets different than the first TP -type Layer 2 packets; activating a set of downlink (DL) Layer 2 microcontrollers when a first TP -type Layer 2 packet is received by the first set of LC queues; performing, by the set of DL Layer 2 microcontrollers, pipelined DL Layer 2 processing of the first TP -type Layer 2 packet; deactivating the set of DL Layer 2 microcontrollers when a subsequent first TP -type Layer 2 packet is not received by the first set of LC queues after a first period; activating a set of DL Layer 2 cores when a second TP -type Layer 2 packet is received by the second set of LC queues; performing, by the set of DL Layer 2 cores, parallel DL Layer 2 processing of the second TP -type Layer 2 packet; and deactivating the set of DL Layer 2 cores when a subsequent second TP -type Layer 2 packet is not received by the second set of LC queues after a second period.

20. A method of a baseband chip, comprising: receiving, by an uplink (UL) Layer 2 hardware accelerator block, a first UL grant specifying one or more grant conditions for a first UL transmission; determining, by the UL Layer 2 hardware accelerator block, whether the UL transmission is a first TP -type Layer 2 packet or a second TP -type Layer 2 packet based at least in part on the one or more grant conditions; activating a set of UL Layer 2 microcontrollers when the UL Layer 2 hardware accelerator block determines that the UL transmission is the first TP -type Layer 2 packet; and perfonning, by the set of UL Layer 2 microcontrollers, pipelined UL Layer 2 processing of the first TP -type Layer 2 packet; activating a set of UL Layer 2 cores when the UL Layer 2 hardware accelerator block determines that the UL transmission is the second TP -type Layer 2 packet; and performing, by the set of UL Layer 2 cores, parallel UL Layer 2 processing of the second

TP -type Layer 2 packet.