WO2023287422A1

WO2023287422A1 - Apparatus and method of architecture resource prediction for low power layer 2 subsystem

Info

Publication number: WO2023287422A1
Application number: PCT/US2021/041892
Authority: WO
Inventors: Su-Lin Low; Na CHEN; Yunhong Li; Tianan Tim MA; Sammy Tzu-Kiang PAO
Original assignee: Zeku, Inc.
Priority date: 2021-07-15
Filing date: 2021-07-15
Publication date: 2023-01-19
Also published as: WO2023287422A8

Abstract

According to one aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 hardware circuit configured to perform Layer 2 packet processing. The baseband chip may also include a resource prediction circuit. The resource prediction circuit may include a resource mapping circuit. The resource mapping circuit may be configured to receive a grant indication associated with one or more grant conditions. The resource mapping circuit may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware circuit. The resource mapping circuit may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware circuit.

Description

APPARATUS AND METHOD OF ARCHITECTURE RESOURCE PREDICTION FOR LOW POWER LAYER 2 SUBSYSTEM

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modem terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines a Radio Layer 2 (referred to here as “Layer 2”) as part of the cellular protocol stack structure corresponding to the data plane (DP) (also referred to as the “user plane”), which includes a Service Data Adaptation Protocol (SDAP) layer, a Packet Data Convergence Protocol (PDCP) layer, a Radio Link Control (RLC) layer, and a Medium Access Control (MAC), from top to bottom in the stack.

SUMMARY

[0003] Embodiments of apparatus and method for Layer 2 packet processing are disclosed herein.

[0004] According to one aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 hardware circuit configured to perform Layer 2 packet processing. The baseband chip may also include a resource prediction circuit. The resource prediction circuit may include a resource mapping circuit. The resource mapping circuit may be configured to receive a grant indication associated with one or more grant conditions. The resource mapping circuit may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware circuit. The resource mapping circuit may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware circuit.

[0005] According to another aspect of the present disclosure, an apparatus of wireless communication is provided. The apparatus may include a Layer 2 hardware block configured to perform Layer 2 packet processing. The apparatus may also include a memory and at least one microcontroller coupled to the memory. The at least one microcontroller may be configured to receive a grant indication associated with one or more grant conditions. The at least one microcontroller may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware block. The at least one microcontroller may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware block based on the resource level ratio indicated by the resource mapping table.

[0006] According to another aspect of the disclosure, a method of wireless communication is disclosed. The method may include performing, by a Layer 2 hardware block, Layer 2 packet processing. The method may include receiving, from a PHY subsystem, a grant indication associated with one or more grant conditions. The method may include identifying, by a resource mapping block, a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware block. The method may include triggering, by the resource mapping block, a resource level change of the set of Layer 2 resources associated with the Layer 2 hardware block.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0009] FIG. 2 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0010] FIG. 3A illustrates a detailed block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure. [0011] FIG. 3B illustrates a detailed block diagram of an exemplary data plane (DP) adaptive resource prediction module (DPM) of the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure.

[0012] FIG. 3C illustrates a graphical illustration of grant levels, count up threshold, count down threshold, and resource level ratios used by the DPM of FIG. 3B, according to some embodiments of the present disclosure.

[0013] FIG. 4 illustrates a flow chart of an exemplary method for DL Layer 2 data processing, according to some embodiments of the present disclosure.

[0014] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0015] FIG. 6 illustrates a block diagram of a conventional baseband chip.

[0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0017] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0018] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0019] In general, terminology may be understood at least in part from usage in context.

For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0020] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system.

[0021] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0022] In cellular and/or Wi-Fi communication, Layer 2 is the protocol stack layer responsible for ensuring a reliable, error-free datalink for the wireless modem (referred to herein as a “baseband chip”) of a UE. More specifically, Layer 2 interfaces with Radio Layer 1 (also referred to as “Layer 1” or the “physical (PHY) layer”) and Radio Layer 3 (also referred to as “Layer 3” or the “Internet Protocol (IP) layer”), passing data packets up or down the protocol stack structure, depending on whether the data packets are associated with UL or DL transmissions. [0023] Furthermore, Layer 2 may perform de-multiplexing / multiplexing, segmentation / reassembly, aggregation / de-aggregation, and sliding window automatic repeat request (ARQ) techniques, among others, to ensure reliable end-to-end data integrity and in-order error-free delivery of data packets. For a UL data packet, Layer 3 data packets (e.g., IP data packets) may be input into the Layer 2 protocol stack, and encoded into MAC layer packets (e.g., 5G NR) for transporting to the PHY layer. For a DL data packet, Layer 1 data packets (e.g., PHY layer data packets) may be input into the Layer 2 protocol stack, where Layer 2 data processing operations are performed on the data packets before being passed up to Layer 3. Layer 3 performs IP header extraction, IP checksum, IP tracing, and IP routing and classification, among other things.

[0024] FIG. 6 illustrates a block diagram of a conventional baseband chip 600. As seen in

FIG. 6, a conventional baseband chip 600 may include PHY subsystem 602 configured to transmit and/or receive data packets over an air interface, a protocol stack 604 (e.g., residing at the baseband chip) that includes a control plane 606 and a data plane 608, Layer 3/Layer 4 subsystems 610, and an application processor (AP)/host 612.

[0025] Control plane 606 performs two main functions: non-access stratum (NAS) function and radio resource control (RRC) function. The NAS function performs network layer control that relates to mobility management, session management, security management, and system selection, just to name a few. The RRC function performs radio resource allocation and configuration, as well as the radio channel control of radio bearers, logical channels, and security (ciphering, integrity configurations).

[0026] Data plane 608 performs Layer 2 and Layer 3/4 functions. Layer 2 functions relate to protocol data unit (PDU) processing. For example, the MAC layer performs multiplexing and demultiplexing, and mapping of logical channels to transport channels. The RLC layer performs automatic repeat request (ARQ) procedures at the radio link level and the error recovery of each logical channel. The PDCP layer performs packet-level processing for data ciphering, integrity, and compression. The SDAP layer performs quality-of-service (QoS) classification of IP flows to data radio bearers (DRBs).

[0027] The conventional baseband chip 600 illustrated in FIG. 6 uses a software-centric

Layer 2 protocol data stack. Namely, the data stack processing resides on a Layer 2 main processor and uses a limited number of hardware accelerators. Using the conventional baseband chip 600, the Layer 2 main processor (not shown) may access a data packet by direct memory access (DMA) from a PHY layer memory at the PHY subsystem(s) 602. Furthermore, the HW accelerators may DMA a UL data packet to the Layer 3 external DDR memory of Layer 3 subsystem 610. [0028] In conventional baseband chip 600, Layer 2 data processing (e.g., processing the transport blocks received from Layer 1 (e.g., PHY subsystem 602) in the DL user plane or processing data packets received from Layer 3 in the UL user plane) is usually implemented using software modules executed on a generic baseband processor, such as a central processing unit (CPU) or a digital signal processor (DSP). During processing, data may be frequently transferred between the generic main processor (not shown) and external memory (Layer 3 external DDR memory or Layer 2 buffer - not shown), e.g., for buffering between each layer. As a result, the known solutions for Layer 2 data processing suffer from high power consumption, large data buffer, and long process delays.

[0029] Moreover, when a user equipment (UE) is configurated with Carrier Aggregation

(CA), multiple Component Carriers (CCs) are typically aggregated for reception and transmission. As such, the UE may receive multiple grants concurrently, one from each CC and cell, which determines the scheduled packets reception and transmission in the downlink and uplink directions, respectively, additional details of which are provided below in connection with FIGs. 7A and 7B. [0030] In the downlink (DL) direction, the DL MAC layer receives code blocks from the

PHY subsystem 602 from multiple CCs. The DL MAC layer may then re-order each Transport Block (TB), extract the MACsubPDU headers to obtain the MAC PDUs, and transfer the packet to the RLC and PDCP DP Layer 2 for further processing in each logical channel and associated radio bearers. Once Layer 2 data processing is complete, the packets are sent to Layer 3/Layer 4 subsystems 610, where the QoS flows in each radio bearer are routed to the appropriate application. [0031] Conversely, in the uplink (UL) direction, the Layer 3/Layer 4 subsystems 610 prepare the UL packets from multiple QoS flows for each data radio bearer (DRB), and the UL packets may then be transferred to Layer 2 logical channel queues, ready for transmission. Once the UL MAC layer receives the UL grant, which allocates resources for the physical uplink shared channel (PUSCH)) using the physical downlink control channel (PDCCH) at the beginning of a slot. For example, the UL grant may be received in a downlink control indicator (DCI) on the PDCCH. The UL grant may inform the UE to transmit the UL MACPDU at a time delay equivalent to K2 slots away from the current slot. Typically, K2<1 grants are implied to be serviced for low latency application data, and hence, radio bearers/logical channels (LCs) data are pulled into such grants to be sent out as soon as possible. The UL MAC scheduling algorithm uses a Logical Channel Prioritization (LCP) method to schedule packets from a logical channel (LC) according to allocated grant bytes from a configured maximum bucket size setting. [0032] One challenge of conventional data plane 608 processing relates to the power consumption by baseband chip 600, which needs to support different application types, such as high throughput high latency data transfers (enhanced mobile broadband (eMBB) traffic), as well as low latency low data rate applications (ultra-reliable low latency communication (URLLC)). When operating in low data rate applications, the power consumption of conventional baseband chip 600 may not be optimized. For example, in low data rate applications, conventional data plane 608 processing may use resources inefficiently when processing DL/UL Layer 2/Layer 3 data packets, consume power unnecessarily during low data rate transfers, use an increased double data rate (DDR) transfer, an increased data plane interconnect bus transactions during periods of activity, and Layer 2 to Layer 3 data transfers are unoptimized and cause undue delays. The lack of power optimization at conventional baseband chip 600 is further exacerbated because the architecture resources (e.g., clock frequency, voltage, number of active memory banks and/or microcontrollers, etc.) used to process Layer 2 data packets are statically configured during RRC configuration, and hence, cannot be dynamically scaled up or down if traffic conditions change. [0033] Thus, there exists an unmet need for a data plane processing technique that optimizes power consumption during both high and low data rate applications.

[0034] To overcome these and other challenges, the present disclosure provides a baseband chip with a resource level mapping table (referred to hereinafter as a “resource mapping table”) that correlates grant conditions (e.g., such as a grant level that indicates a throughput amount) to a resource level ratio of architecture resources used by the Layer 2 hardware blocks. These architecture resources (also referred to herein as “resources”) may include, e.g., clock frequency, voltage, a number of active memory banks, and/or a number of active microcontrollers, just to name a few. The resource level ratio and/or resource level values may enable the baseband chip to tune (increase or decrease) these resources based on an incoming grant to provide power optimization of the Layer 2 hardware block and/or Layer 2 subsystem. In addition, during connection, static parameters (e.g., bandwidth, subcarrier spacing (SCS), number of CCs, QoS profiles, LC bucket rates, and user traffic profiles based on location and/or time-of-day) may be used to adjust the resource level values indicated by the resource mapping table. Still further, the present disclosure may provide a computationally efficient mechanism that enables the baseband chip to filter incoming grant indications associated with a throughput-type (e.g., enhanced mobile broadband (eMBB)). This filtering may enable the baseband chip to predict a customized level of resource usage for different use cases and QoS flow profiles. Still further, for incoming grant indications of the ultra-reliable low latency communication (URLLC) throughput-type, the resource mapping table may be identified without first performing grant filtering. This way the latency requirements of URLLC grants can still easily be met while providing the power optimization disclosed herein. Additional details of these techniques are provided below in connection with FIGs. 1-5.

[0035] Although the following processing techniques are described in connection with

Layer 2 data processing, the same or similar techniques may be applied to Layer 3 and/or Layer 4 data processing to optimize power consumption at Layer 3 and/or Layer 4 subsystems without departing from the scope of the present disclosure.

[0036] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (IoT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0037] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0038] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0039] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0040] Core network element 106 may connect with a large network, such as the Internet

108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0041] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0042] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5. Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible.

[0043] Transceiver 506 may include any suitable device for sending and/or receiving data. Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0044] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0045] As shown in FIG. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. [0046] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0047] Referring back to FIG. 1, in some embodiments, user equipment 102 may include a baseband chip with a resource mapping table that correlates grant conditions (e.g., such as different grant ranges each associated with a different throughput) to a resource level ratio, which may be used to fine tune resources used by the Layer 2 hardware blocks to process Layer 2 data packets. These resources may include, e.g., clock frequency, voltage, the number of active memory banks, and/or the number of active microcontrollers, just to name a few. The resource level ratio may enable the baseband chip of user equipment 102 to tune (increase or decrease) these resources to provide power optimization of the Layer 2 hardware block. In addition, during connection, static parameters (e.g., bandwidth, SCS, number of CCs, QoS flow profiles, LC bucket rates, and user traffic profiles based on location and/or time-of-day) may be used to adjust the resource level values of the resource mapping table. Still further, the present disclosure may provide a computationally efficient mechanism that enables the baseband chip of user equipment 102 to filter incoming grant indications associated with an eMBB throughput-type or a URLLC throughput- type. This filtering may enable the baseband chip of user equipment 102 to predict a customized level of resource usage for different use cases and QoS profiles characteristics. Still further, for incoming grant indications of the URLLC throughput-type, the resource mapping table may be identified without performing grant filtering. This way, the latency requirements of URLLC grants can still easily be met while still providing power optimization by fine-tuning the resource level at the baseband chip. Additional details of each of these techniques are provided below in connection with FIGs. 2, 3A-3E, 4A, and 4B.

[0048] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip

202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5. Besides the on-chip memory 218 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG. 2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0049] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204 via interface 214. RF chip 204, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204.

[0050] In the downlink, antenna 210 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202.

[0051] As seen in FIG. 2, baseband chip 202 may include a DL Layer 2 block 220a and a

UL Layer 2 block 220b. DL Layer 2 block 220a may include a DL Layer 2 hardware (HW) accelerator (DLHWAC) that includes different DL Layer 2 circuits (e.g., MAC circuit, RLC circuit, PDCP circuit, etc.) each configured to perform certain Layer 2 tasks. DL Layer 2 block 220a may also include a set of DL Layer 2 microcontrollers (uCs) each configured to perform a task associated with at least one of the DL Layer 2 circuits of the DLHWAC. A set of memory banks may be used by the DLHWAC and the set of DL Layer 2 uCs for, e.g., command and status queues. Similarly, UL Layer 2 block 220b may include a UL Layer 2 HW accelerator (ULHWAC) that includes different UL Layer 2 circuits (e.g., MAC circuit, RLC circuit, PDCP circuit, etc.) each configured to perform certain Layer 2 tasks. UL Layer 2 block 220b may also include a set of UL Layer 2 uCs each configured to perform a task associated with at least one of the UL Layer 2 circuits of the ULHWAC. A set of memory banks may be used by the ULHWAC and the set of UL Layer 2 uCs for, e.g., command and status queues.

[0052] Still referring to FIG. 2, baseband chip 202 may include a DPM 230. DPM 230 may include a resource mapping table that correlates grant conditions (e.g., such as a grant range that indicates a maximum throughput) to a resource level ratio, which may be used to fine tune resources used by DL Layer 2 block and UL Layer 2 block to process Layer 2 data packets. These resources may include, e.g., clock frequency, voltage, the number of active memory banks, and/or the number of active uCs, just to name a few. The resource level ratio may enable the baseband chip 202 to tune (increase or decrease) these resources to provide power optimization at DL Layer 2 block 220a and/or UL Layer 2 block 220b. In addition, during connection, static parameters (e.g., bandwidth, SCS, number of CCs, QoS profiles, LC bucket rates, and user traffic profiles based on location and/or time-of-day) may be used by DPM 230 to adjust the parameters correlated by the resource mapping table. Still further, DPM 230 may filter certain incoming grant indications associated with an eMBB throughput type. This filtering may enable DPM 230 to predict a customized level of resource usage for different use cases and QoS flow profiles. Still further, for incoming grant indications of the URLLC throughput-type, the resource mapping table may be identified by DPM 230 without performing grant filtering. This way, the latency requirements of URLLC grants can still easily be met while still providing power optimization by fine-tuning the resource level at the DL Layer 2 block 220a and/or UL Layer 2 block 220b.

[0053] In some embodiments, DPM 230 may be implemented as firmware and located in one of the uCs of one or more of DL Layer 2 block 220a or UL Layer 2 block 220b. In some embodiments, DPM 230 may be implemented as hardware within baseband chip 202. When implemented as hardware, DPM 230 may be located in one or more of DL Layer 2 block 220a and/or UL Layer 2 block 220b. In some embodiments, DPM 230 may include a DL DPM configured to process DL grants and a UL DPM configured to process UL grants. In some embodiments, DPM 230 may include a single DPM configured to process both DL grants and UL grants. Additional details of the DPM are provided below in connection with FIGs. 3A-3C and 4. [0054] FIG. 3 A illustrates a detailed block diagram of the exemplary baseband chip 202 of

FIG. 2, according to some embodiments of the present disclosure. FIG. 3B illustrates a detailed block diagram of the exemplary DPM 230 of FIGs. 2 and 3A, according to some embodiments of the present disclosure. FIG. 3C illustrates a graphical illustration 301 of grant levels, count up threshold, count down threshold, and resource level ratios, according to some embodiments of the present disclosure. FIGs. 3A-3C will be described together.

[0055] Referring to FIG. 3A, baseband chip 202 may include, e.g., PHY subsystems 302, a Layer 2 subsystem 350 with a DL Layer 2 block 220a and a UL Layer 2 block 220b, external memory 340, and AP/Host 360, among others. DL Layer 2 block 220a may include, e.g., a DLHWAC 314a, a set of DL uC memory banks 316a (hereinafter “memory banks 316a), and a set of DL Layer 2 microprocessors (uCs) 318a (hereinafter “set of uCs 318a”), among others. DLHWAC 314a may include, e.g., a PHY interface 304a, an inline buffer 306a, MAC circuit 308a, RLC circuit 310a, and PDCP circuit 312a. UL Layer 2 block 220b may include, e.g., a ULHWAC 314b, a set of UL uC memory banks 316b (hereinafter “memory banks 316b”), and a set of UL Layer 2 uCs 318b (hereinafter “set of uCs 318b”), among others. ULHWAC 314b may include, e.g., a PHY interface 304b, an inline buffer 306b, MAC circuit 308b, RLC circuit 310b, and PDCP circuit 312b.

[0056] Still referring to FIG. 3A, Layer 2 subsystem 350 may include DPM 230. In the example depicted in FIG. 3 A, DPM 230 is implemented as firmware within uCl of the set of uCs 318a of DL Layer 2 block 220a. Here, DPM 230 may perform adaptive resource level prediction for both DL grants and UL grants. However, in some embodiments, DPM 230 may be implemented elsewhere within Layer 2 subsystem 350 without departing from the scope of the present disclosure. For example, DPM 230 may be implemented as either firmware or hardware within Layer 2 subsystem 350 but external to both DL Layer 2 block 220a or UL Layer 2 block 220b. Alternatively, DPM 230 may include a DL DPM configured to perform resource level prediction for DL grants and a UL DPM configured to perform resource level prediction for UL grants. In this embodiment, the DL DPM may be located anywhere within DL Layer 2 block 220a, and UL DPM may be located anywhere within UL Layer 2 block 220b. However, in some embodiments, DL DPM and UL DPM are located within Layer 2 subsystem 350 but external to DL Layer 2 block 220a and UL Layer 2 block 220b. Still further, in some embodiments, DL DPM may be located within DL Layer 2 block 220a while UL DPM may be located within Layer 2 subsystem 350 but external to UL Layer 2 block 220b, or vice versa. In any of the above embodiments, DPM 230 may be configured to perform adaptive resource level prediction upon receipt of either a DL grant (received via DCI l) or a UL grant (received via DCI O).

[0057] Each uC of the set of DL and UL Layer 2 uCs 318a, 318b may include one or more small processor cores, which are used to program one or more of the circuits of the DLHWAC 314a or ULHWAC 314b in a pipelined fashion. The interworking between the set of uCs and its associated hardware accelerator may be accomplished through a set of Layer 2 command and status queues, which reside in the set of DL and UL uC memory banks 316a, 316b.

[0058] Moreover, each of the set of uCs 318a and 318b may be implemented as separate power domains and clock frequency domains. These power and clock frequency domains may be individually controlled through dynamic fine-tuning of the voltage levels and clock frequencies based on resource level ratios/resource level values identified by DPM 230 from a resource mapping table. In some embodiments, when no data packets are processed after a threshold period and/or when no DL and/or UL grants are received after a threshold period, clock gating techniques may be implemented to lower the power consumption of baseband chip 202.

[0059] Still further, the number of active uCs in either of the sets of uCs 318a, 318b, the number of active memory banks 316a, 316b, the clock frequency, and/or power/voltage levels may be dynamically adjusted based on the resource level ratio identified by DPM 230 using an associated grant level (e.g., throughput level) indicated by the grant indication. Moreover, by adaptively adjusting the resources used to process Layer 2 data packets, network-on-chip (NoC) resources, e.g., such as bus transactions, access to external memory 340, etc., can also be optimized to minimum levels during low data rate applications. Further details for DPM 230 are provided below in connection with FIGs. 3B and 3C.

[0060] For example, as seen in FIG. 3B, DPM 230 may include, e.g., a resource mapping block 330 (referred to hereinafter as “resource mapping block 330”), a resource table adjustment block 332, and a grant prediction block 334.

[0061] Resource mapping block 330 may be configured to identify a resource mapping table based on the grant level indicated by a grant indication (e.g., a DL grant or a UL grant). From the resource mapping table, resource mapping block 330 may be configured to map the grant level to a corresponding resource level ratio (e.g., 1, 1/2, 1/4, etc.) of the resources used by DL Layer 2 block 220a and/or UL Layer 2 block 220b. Again, examples of these resources may include, e.g., clock frequency, voltage level, number of active memory banks, and number of active uCs, just to name a few. By way of example, a resource level ratio of 1/2 may indicate that each of the resources may be reduced by half. Once the resource level ratio has been identified, resource mapping block 330 may trigger resource reassignment at either the DL or UL Layer 2 block 220a, 220b. A first example resource mapping table is seen below in Table 1.

Table 1: First example Resource Mapping Table

[0062] The Count Down Threshold seen in Table 1 indicates a number of grant level changes that occur before the resource level change decreasing the resource usage is triggered. For example, assume the grant level for a series of consecutive DL grant has remained steady in the grant range of Max/4 - Max/2 for several minutes. Then, after this steady period, a subsequent DL grant is received in the grant range of 0 - Max/4. Here, also assume that the Count Down Threshold for grant level Max/4 is three, namely T3d=3. Thus, before a grant level change is triggered reducing the resource level ratio from 1/2 to 1/4 at the DL Layer 2 block 220a, three consecutive DL grants in the range of 0 - Max/4 are received before this change occurs.

[0063] Similarly, the Count Up Threshold in table 1 indicates a number of grant level changes that occur before the resource level ratio that increases the resource level ratio is triggered. For example, assume the grant level for a series of consecutive DL grant has remained steady in the grant range of Max/4 - Max/2 for several minutes. Then, after this steady period, a subsequent DL grant is received in the grant range of Max/2 - Max. Here, also assume that the Count Up Threshold for grant level Max is three, namely Tlu=3. Thus, before a grant level change is triggered increasing the resource level ratio from 1/2 to 1 at the DL Layer 2 block 220a, three consecutive DL grants in the range of Max/2 - Max are received before this change occurs. The Count Down Threshold and Count Up Threshold may each be monitored using separate counters of DPM 230. The corresponding counter may increment each time a grant indication with a decreased grant level or increased grant level is received.

[0064] In URLLC applications, where instant resource level changes may be desirable, these count thresholds may be set to 0 or 1. Conversely, in eMBB applications where the delay is less critical, it may be desirable to delay the resource level changes appropriately to achieve a more effective low energy output. Hence, count-up threshold may be increased to allow baseband chip 202 to remain in the lower resource state longer, and count down thresholds may also be customized to a smaller value to further optimize power consumption.

[0065] The Resource Level Ratio in Table 1 specifies the ratio with respect to the maximum resources. However, as seen below in Table 2, various resources can be listed as well for each grant/resource level.

Table 2: Second example Resource Mapping Table [0066] Example use of the Count Down Threshold and the Count Up Threshold by resource mapping block 330 is illustrated in FIG. 3C. For example, referring to FIG. 3C, resource mapping block 330 may determine whether, for an input grant indication in the grant range of X, the Count Level Threshold has been met by either the count down counter or count up counter. When the corresponding count threshold has been met, then resource mapping block 330 may trigger a resource level change at either the DL or UL Layer 2 block 220a, 220b. Once the resource level change is triggered, the corresponding counter may be reset to zero.

[0067] Moreover, before static parameters are input into resource table adjustment block

332, the resource mapping table of Table 1 or Table 2 may be initialized with default values (also referred to as “initial resource level values). These default values may be adjusted or replaced with adjusted resource level values after the static parameters are received, e.g., as shown below in Table 3. These static parameters may include, e.g., SCS, bandwidth, number of CCs, QoS flow profiles (e.g., identified by 5QI value in grant indication), user traffic patterns (e.g., location, time of day, etc.), LC bucket rate (e.g., for UL transmission), etc. So before these static parameters are received, an initial set of resource level values may be sent to resource mapping block 330. The grant level and/or the static parameters may be collectively referred to as “grant conditions.” [0068] Then, based on the static parameters, resource table adjustment block 332 may access a resource adjustment table that includes a plurality of resource mapping tables each associated with a different set of static parameters. An example resource level adjustment table is seen below in Table 3. Then, based on the static parameters, resource table adjustment block 332 may identify the appropriate set of adjusted resource level values to convey to resource mapping block 330. As seen in Table 3, the “Resources for each Resource Level Ratio” column illustrates the set of adjusted resource level values that resource table adjustment block 332 identifies based on the static parameters and the grant range. The adjusted resource level values may be communicated to resource mapping block 330, which specifies a resource level change that is predicted for the upcoming Layer 2 data processing operation for the grant indication. With respect to Table 3, in some embodiments, separate tables may be used for DL and UL grant indications.

Table 3: Resource Level Adjustment Table [0069] In some embodiments, DPM 230 may use a user-specific traffic profile pattern to create multiple resource adjustment tables (e.g., such as Table 1) for a learned resource level mapping profile that may be correlated to certain days of the week, times of day, and/or for specific locations where the user travels across the globe.

[0070] In some embodiments, DPM 230 may also include a grant prediction block 334, which may implement a computationally efficient mechanism to calculate a filtered grant. The frequency with which grants may be filtered may be determined by a user-specified sampling frequency. In some embodiments, eMBB grants may be filtered (also referred to as “filtered grants”), while URLLC grants may be unfiltered grants (also referred to as “instant grants”). In some other embodiments, grant filtering for eMBB grants may also be disabled. For low latency URLLC applications, the use of instant grants may be desirable for immediate fine-tuning of Layer 2 resources at short intervals to conserve power and energy. On the other hand, eMBB applications, which are more tolerant to delay, may benefit from less drastic resource level changes with less resource level switching overhead. For such applications, the incoming grant can be smoothed with various key inputs to provide a filtered grant that can be used to trigger more stable resource level changes.

[0071] Referring again to FIG. 3B, grant prediction block 334 may filter a grant indication based on filter inputs. These filter inputs may include, e.g., the current buffer size for one or more of the inline buffers 306a, 306b, the throughput data rates (DL or UL), number of CCs, bandwidth, received signal strength for DL grants, the transmit power for UL transmissions, network signal load, and user-specified sampling frequency, just to name a few. Grant prediction block 334 may generate a filtered grant calculated at current slot n (e.g., for the upcoming transmission/reception in the next slot (n+ 1 )), using a simple infinite impulse response (HR) difference equation, as shown below in Equation (1).

G(n) = F(t). G_A(n-l) +

[l-F(t) ]. [Kl. Q(n) + K2.R(n) + K3.P(n) K4.L(n) K5.E(n) ] ( 1 ), where G(n) is the filtered grant at current slot n, G_A(n-l) the incoming grant that was predicted while at slot (n-1), Q is the total buffer size, R is the DL/UL data rate derived from the number of CCs, BW, etc., P is the received signal power for DL grants or the transmit power for UL grants, L is the network traffic load, E is the previous prediction error, Kl - K5 are input multiply factors (unrelated to the “K” seen above in Tables 1-3), and F(t) is the grant prediction factor function. [0072] The current total buffer size for all LCs is one input, which is requested by the network in a buffer status report. It may be weighted with the largest factor of Kl. The current UL data rate of the transmit carrier channel directly affects the grant size allocated. This may be weighted with K2. The received signal power at baseband chip 202 may affect the grant size allocated by the network. A strong signal may indicate that the network would allocate more grants. This may be weighted with K3. The network traffic load at baseband chip 202 may indicate how busy the network is surrounding user equipment 102, which is sharing the network resources. A heavy load may indicate that the network scheduler would reduce the grant to the user equipment 102. This parameter may be derived from the network traffic load values (e.g., Ec/Io) at user equipment 102. This input may be weighted with K4 and impacts the grant negatively. Lastly, the grant prediction error may be weighted by K5. The grant prediction error E(n) for the current slot n prediction may be defined by Equation (2):

E(n) = [G(n-l) - G_A(n-l)] (2), where the error E(n) depicts the difference between the Predicted Grant and the Actual NW Grant allocated for the prediction interval of slot (n-1).

[0073] Using the techniques described above in connection with FIGs. 3A-3C, baseband chip 202 may optimize the use of architecture resources in processing Layer 2 data packets to provide a significant reduction in power consumption, as compared with known approaches. [0074] FIG. 4 illustrates a flow chart of a first exemplary method 400 for DL Layer 2 data processing, according to some embodiments of the present disclosure. Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, DL Layer 2 block 220a, UL Layer 2 block 220b, the set of DL Layer 2 uCs 318a, the set of UL Layer 2 uCs 318b, DPM 230, Layer 2 subsystem 350, and/or node 500. Method 400 may include steps 402-428 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4.

[0075] Referring to FIG. 4, at 402, the apparatus may initialize a resource mapping table with default parameters. For example, referring to FIG. 3B, before static parameters are input into resource table adjustment block 332, the resource mapping table of Table 1 or Table 2 may be initialized with default values (also referred to as “initial resource level values), which be adjusted or replaced with adjusted resource level values after the static parameters are received, e.g., as shown below in Table 3.

[0076] At 404, the apparatus may run resource table adjustments using static parameters.

For example, referring to FIG. 3B, the default parameters may be adjusted or replaced with adjusted resource level values after the static parameters are received, e.g., as shown below in Table 3. These static parameters may include, e.g., SCS, bandwidth, number of CCs, QoS flow profiles (e.g., identified by 5QI value in grant indication), user traffic patterns (e.g., location, time of day, etc.), LC bucket rate (e.g., for UL transmission), etc. So before these static parameters are received, an initial set of resource level values may be sent to resource mapping block 330. Then, based on the static parameters, resource table adjustment block 332 may access a resource adjustment table that includes a plurality of resource mapping tables each associated with a different set of static parameters. An example resource level adjustment table is seen above in Table 3.

[0077] At 406, the apparatus may update the resource mapping table with the adjusted values. For example, referring to FIG. 3B, based on the static parameters, resource table adjustment block 332 may identify the appropriate set of adjusted resource level values to convey to resource mapping block 330. As seen in Table 3, the “Resources for each Resource Level Ratio” column illustrates the set of adjusted resource level values that resource table adjustment block 332 identifies based on the static parameters and the grant range. Again, these adjusted resource level values may include, e.g., clock frequency, power voltage, the number of active memory banks, and the number of active uCs, among others. These adjusted resource level values may be communicated to resource mapping block 330, which specify a resource level change that is predicted for the upcoming Layer 2 data processing operation associated with the grant indication. With respect to Table 3, in some embodiments, separate tables may be used for DL and UL. [0078] At 408, the apparatus may receive a grant indication (either DL or UL) and determine from the 5QI whether the grant indication is the URLLC type or the eMBB type. When the eMBB type, at 410, the apparatus may filter the grant indication. For example, referring to FIG. 3B, grant prediction block 334 may filter a grant indication based on filter inputs. These filter inputs may include, e.g., the current buffer size for one or more of the inline buffers 306a, 306b, the throughput data rates (DL or UL), number of CCs, bandwidth, received signal strength for DL grants, the transmit power for UL transmissions, network signal load, and user-specified sampling frequency, just to name a few. Grant prediction block 334 may generate a filtered grant calculated at current slot n (for the upcoming transmission/reception in the next slot (n+1)), using a simple HR difference equation, as shown above in Equation (1). Then either the filtered grant or the instant grant is input into the resource mapping block.

[0079] At 412, the apparatus may identify a resource level table based on the instant or filtered grant. For example, referring to FIG. 3B, resource mapping block 330 may be configured to identify a resource mapping table based on the grant level indicated by a grant indication (e.g., a DL grant or a UL grant). From the resource mapping table, resource mapping block 330 may be configured to maps the grant level, among others, to a corresponding resource level ratio (e.g., 1, 1/2, 1/4, etc.) of the resources used by DL Layer 2 block 220a and/or UL Layer 2 block 220b. Again, examples of these resources may include, e.g., clock frequency, voltage level, number of active memory banks, and number of active uCs, just to name a few. By way of example, a resource level ratio of 1/2 may indicate that the resources may be reduced by half. Once the resource level ratio has been identified from the corresponding resource mapping table, resource mapping block 330 may trigger resource reassignment at either the DL or UL Layer 2 block 220a, 220b. Example resource mapping tables are seen above in Tables 1 and 2.

[0080] At 414, the apparatus may determine whether the instant or filtered grant level is greater than the previous grant level. When the new grant level is greater than the previous grant level, at 416, the apparatus may determine whether the count-up threshold has been met. For example, referring to FIG. 3B, the Count Up Threshold in table 1 indicates a number of grant level changes that occur before the resource level ratio that increases the resource level ratio is triggered. For example, assume the grant level for a series of consecutive DL grant has remained steady in the grant range of Max/4 - Max/2 for several minutes. Then, after this steady period, a subsequent DL grant is received in the grant range of Max/2 - Max. Here, also assume that the Count Up Threshold for grant level Max is three, namely Tlu=3. Thus, before a grant level change is triggered, increasing the resource level ratio from 1/2 to 1 at the DL Layer 2 block 220a, three consecutive DL grants in the range of Max/2 - Max are received before this change occurs. The Count Down Threshold and Count Up Threshold may each be monitored using separate counters of DPM 230. The corresponding counter may increment each time a grant indication with a decreased grant level or increased grant level is received. When the count-up threshold has not been met, the count-up counter may be incremented and the operation may return to 408. Otherwise, when the count-up threshold is met, at 420, the apparatus may trigger a resource level change based on the resource mapping table.

[0081] However, when the new grant level is not greater than the previous grant level, at

422, the apparatus may determine whether the new grant level is less than the previous grant level. When the new grant level is less than the previous grant level, at 424, the apparatus may determine whether the count down threshold has been reached. For example, referring to FIG. 3B, The Count Down Threshold seen in Table 1 indicates a number of grant level (e.g., data throughput level) changes that occur before the resource level ratio change that decreases the resource level ratio is triggered. For example, assume the grant level for a series of consecutive DL grants has remained steady in the grant range of Max/4 - Max/2 for several minutes. Then, after this steady period, a subsequent DL grant is received in the grant range of 0 - Max/4. Here, also assume that the Count Down Threshold for grant level Max/4 is three, namely T3d=3. Thus, before a grant level change is triggered, reducing the resource level ratio from 1/2 to 1/4 at the DL Layer 2 block 220a, three consecutive DL grants in the range of 0 - Max/4 are received before this change occurs. When the count down threshold has been reached, at 428, the apparatus may trigger a resource level change. Otherwise, when the count down threshold has not been reached, at 426, the apparatus may increment the count-down counter, and the operations may return to 408 to await a subsequent grant.

[0082] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0083] According to one aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 hardware circuit (e.g., DL Layer 2 block 220a, UL Layer 2 block 220b, Layer 2 subsystem 350) configured to perform Layer 2 packet processing. The baseband chip may also include a resource prediction circuit (e.g., DPM 230). The resource prediction circuit may include a resource mapping circuit. The resource mapping circuit may be configured to receive a grant indication associated with one or more grant conditions. The resource mapping circuit may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware circuit. The resource mapping circuit may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware circuit.

[0084] In some embodiments, the set of Layer 2 resources may include one or more of a clock frequency associated with the Layer 2 hardware circuit, a voltage associated with the Layer 2 hardware circuit, a number of active microcontrollers of the Layer 2 hardware circuit, or a number of active memory banks associated with the Layer 2 hardware circuit.

[0085] In some embodiments, the resource mapping table may correlate a grant level with a count down threshold, a count up threshold, the resource level ratio.

[0086] In some embodiments, the count down threshold may be associated with a number of grant indications received at the grant level that is a decreased grant level as compared to previous grant levels before the first resource level change is triggered to decrease the resource level ratio for the set of Layer 2 resources.

[0087] In some embodiments, the count up threshold may be associated with a number of grant indications received at the grant level that is an increased grant level as compared to previous grant levels before the first resource level change is triggered to increase the resource level ratio for the set of Layer 2 resources.

[0088] In some embodiments, the resource mapping circuit may be configured to obtain a set of default parameters for the resource mapping table while the baseband chip is in idle mode. [0089] In some embodiments, the resource prediction circuit may further include a resource table adjustment circuit. In some embodiments, the resource table adjustment circuit may be configured to receive a set of static parameters when the baseband chip enters connected mode. In some embodiments, the resource table adjustment circuit may be configured to identify a set of adjusted resource level values of the resource mapping table based on the set of static parameters. In some embodiments, the resource table adjustment circuit may be configured to outputting the set of adjusted resource level values to the resource mapping circuit. In some embodiments, the first resource level change may be associated with the set of adjusted resource level values. In some embodiments, the resource mapping circuit further may be configured to identify a set of initial resource level values before the set of adjusted resource level values are received from the resource table adjustment circuit. In some embodiments, the resource mapping circuit further may be configured to trigger a second resource level change of the set of Layer 2 resources associated based on the set of initial resource level values. In some embodiments, the second resource level change may occur before the first resource level change.

[0090] In some embodiments, the set of static parameters may include one or more of SCS,

QoS profiles, LC bucket rates, or a user traffic pattern.

[0091] In some embodiments, the resource prediction circuit may further include a grant prediction circuit. In some embodiments, the grant prediction circuit may be configured to receive an unfiltered grant indication from a PHY subsystem. In some embodiments, the grant prediction circuit may be configured to receive a set of filter inputs. In some embodiments, the grant prediction circuit may be configured to filter the unfiltered grant indication based at least in part on the set of filter inputs to generate a filtered grant indication. In some embodiments, the grant indication received by the resource mapping circuit is the filtered grant indication.

[0092] In some embodiments, the filtered grant indication may be associated with an eMBB traffic type.

[0093] In some embodiments, the grant indication may include an unfiltered grant indication when a traffic type includes a URLLC traffic type.

[0094] According to another aspect of the present disclosure, an apparatus of wireless communication is provided. The apparatus may include a Layer 2 hardware block configured to perform Layer 2 packet processing. The apparatus may also include a memory and at least one microcontroller coupled to the memory. The at least one microcontroller may be configured to receive a grant indication associated with one or more grant conditions. The at least one microcontroller may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware block. The at least one microcontroller may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware block based on the resource level ratio indicated by the resource mapping table.

[0095] In some embodiments, the set of Layer 2 resources may include one or more of a clock frequency associated with the Layer 2 hardware circuit, a voltage associated with the Layer 2 hardware circuit, a number of active microcontrollers of the Layer 2 hardware circuit, or a number of active memory banks associated with the Layer 2 hardware circuit.

[0096] In some embodiments, the resource mapping table may correlate a grant level with a count down threshold, a count up threshold, the resource level ratio.

[0097] In some embodiments, the count down threshold may be associated with a number of grant indications received at the grant level that is a decreased grant level as compared to previous grant levels before the first resource level change is triggered to decrease the resource level ratio for the set of Layer 2 resources.

[0098] In some embodiments, the count up threshold may be associated with a number of grant indications received at the grant level that is an increased grant level as compared to previous grant levels before the first resource level change is triggered to increase the resource level ratio for the set of Layer 2 resources.

[0099] In some embodiments, the at least one microcontroller may be further configured to obtain a set of default parameters for the resource mapping table while the apparatus is in idle mode.

[0100] In some embodiments, the at least one microcontroller may be configured to receive a set of static parameters after entering connected mode. In some embodiments, the at least one microcontroller may be configured to identify a set of adjusted resource level values for the resource mapping table based on the set of static parameters. In some embodiments, the first resource level change may be associated with the set of adjusted resource level values. In some embodiments, the at least one microcontroller may be configured to identify a set of initial resource level values before the set of adjusted resource level values are identified. In some embodiments, the at least one microcontroller may be further configured to trigger a second resource level change of the set of Layer 2 resources based on the set of initial resource level values. In some embodiments, the second resource level change occurs before the first resource level change. [0101] In some embodiments, the set of static parameters includes one or more of SCS,

QoS profiles, LC bucket rates, or a user traffic pattern.

[0102] In some embodiments, the at least one microcontroller may be further configured to receive an unfiltered grant indication from a PHY subsystem. In some embodiments, the at least one microcontroller may be further configured to receive a set of filter inputs. In some embodiments, the at least one microcontroller may be further configured to filter to the unfiltered grant indication based at least in part on the set of filter inputs to generate a filtered grant indication. In some embodiments, the grant indication may be the filtered grant indication.

[0103] According to another aspect of the disclosure, a method of wireless communication is disclosed. The method may include performing, by a Layer 2 hardware block, Layer 2 packet processing. The method may include receiving, from a PHY subsystem, a grant indication associated with one or more grant conditions. The method may include identifying, by a resource mapping block, a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware block. The method may include triggering, by the resource mapping block, a resource level change of the set of Layer 2 resources associated with the Layer 2 hardware block.

[0104] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0105] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0106] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0107] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0108] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A baseband chip, comprising: a Layer 2 hardware circuit configured to perform Layer 2 packet processing; a resource prediction circuit comprising: a resource mapping circuit configured to: receive a grant indication associated with one or more grant conditions; identify a resource mapping table associated with the one or more grant conditions, the resource mapping table indicating a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware circuit; and trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware circuit.

2. The baseband chip of claim 1, wherein the set of Layer 2 resources includes one or more of a clock frequency associated with the Layer 2 hardware circuit, a voltage associated with the Layer 2 hardware circuit, a number of active microcontrollers of the Layer 2 hardware circuit, or a number of active memory banks associated with the Layer 2 hardware circuit.

3. The baseband chip of claim 1, wherein the resource mapping table correlates a grant level with a count down threshold, a count up threshold, the resource level ratio.

4. The baseband chip of claim 3, wherein the count down threshold is associated with a number of grant indications received at the grant level that is a decreased grant level as compared to previous grant levels before the first resource level change is triggered to decrease the resource level ratio for the set of Layer 2 resources.

5. The baseband chip of claim 3, wherein the count up threshold is associated with a number of grant indications received at the grant level that is an increased grant level as compared to previous grant levels before the first resource level change is triggered to increase the resource level ratio for the set of Layer 2 resources.

6 The baseband chip of claim 1, wherein the resource mapping circuit is configured to obtain a set of default parameters for the resource mapping table while the baseband chip is in idle mode.

7. The baseband chip of claim 6, wherein the resource prediction circuit further comprises: a resource table adjustment circuit configured to: receive a set of static parameters when the baseband chip enters connected mode; identify a set of adjusted resource level values of the resource mapping table based on the set of static parameters; and outputting the set of adjusted resource level values to the resource mapping circuit, the first resource level change being associated with the set of adjusted resource level values, wherein the resource mapping circuit further is configured to: identify a set of initial resource level values for use by the Layer 2 hardware circuit before the set of adjusted resource level values are received from the resource table adjustment circuit; and trigger a second resource level change of the set of Layer 2 resources associated based on the set of initial resource level values, wherein the second resource level change occurs before the first resource level change.

8. The baseband chip of claim 7, wherein the set of static parameters includes one or more of subcarrier spacing (SCS), quality-of-service (QoS) profiles, logical channel (LC) bucket rates, or a user traffic pattern.

9. The baseband chip of claim 1, wherein the resource prediction circuit further comprises: a grant prediction circuit configured to: receive an unfiltered grant indication from a physical layer (PHY) subsystem; receive a set of filter inputs; and filter the unfiltered grant indication based at least in part on the set of filter inputs to generate a filtered grant indication, wherein the grant indication received by the resource mapping circuit is the filtered grant indication.

10. The baseband chip of claim 9, wherein the filtered grant indication is associated with an enhanced mobile broadband (eMBB) traffic type.

11. The baseband chip of claim 1, wherein the grant indication includes an unfiltered grant indication when a traffic type includes a ultra-reliable low latency communication (URLLC) traffic type.

12. An apparatus of wireless communication, comprising: a Layer 2 hardware block configured to perform Layer 2 packet processing; a memory; and at least one microcontroller coupled to the memory and configured to: receive a grant indication associated with one or more grant conditions; identify a resource mapping table associated with the one or more grant conditions, the resource mapping table indicating a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware block; and trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware block based on the resource level ratio indicated by the resource mapping table.

13. The apparatus of claim 12, wherein the set of Layer 2 resources includes one or more of a clock frequency associated with the Layer 2 hardware block, a voltage associated with the Layer 2 hardware block, a number of active microcontrollers of the Layer 2 hardware block, or a number of active memory banks associated with the Layer 2 hardware block.

14. The apparatus of claim 12, wherein the resource mapping table correlates a grant level with a count down threshold, a count up threshold, the resource level ratio.

15. The apparatus of claim 14, wherein the count down threshold is associated with a number of grant indications received at the grant level that is a decreased grant level as compared to previous grant levels before the first resource level change is triggered to decrease the resource level ratio for the set of Layer 2 resources.

16. The apparatus of claim 14, wherein the count up threshold is associated with a number of grant indications received at the grant level that is an increased grant level as compared to previous grant levels before the first resource level change is triggered to increase the resource level ratio for the set of Layer 2 resources.

17. The apparatus of claim 12, wherein the at least one microcontroller is further configured to obtain a set of default parameters for the resource mapping table while the apparatus is in idle mode.

18. The apparatus of claim 17, wherein the at least one microcontroller is further configured to: receive a set of static parameters after entering connected mode; identify a set of adjusted resource level values for the resource mapping table based on the set of static parameters, the first resource level change being associated with the set of adjusted resource level values; identify a set of initial resource level values before the set of adjusted resource level values are identified; and trigger a second resource level change of the set of Layer 2 resources based on the set of initial resource level values, wherein the second resource level change occurs before the first resource level change, and wherein the set of static parameters includes one or more of subcarrier spacing (SCS), quality-of-service (QoS) profiles, logical channel (LC) bucket rates, or a user traffic pattern.

19. The apparatus of claim 12, wherein the at least one microcontroller is further configured to: receive an unfiltered grant indication from a physical layer (PHY) subsystem; receive a set of filter inputs; and filter to the unfiltered grant indication based at least in part on the set of filter inputs to generate a filtered grant indication, wherein the grant indication is the filtered grant indication.

20. A method of wireless communication, comprising: performing, by a Layer 2 hardware block, Layer 2 packet processing; receiving, from a physical layer (PHY) subsystem, a grant indication associated with one or more grant conditions; identifying, by a resource mapping block, a resource mapping table associated with the one or more grant conditions, the resource mapping table indicating a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware block; and triggering, by the resource mapping block, a resource level change of the set of Layer 2 resources associated with the Layer 2 hardware block.