WO2023089831A1 - シミュレーションプログラム、シミュレーション方法、および情報処理装置 - Google Patents
シミュレーションプログラム、シミュレーション方法、および情報処理装置 Download PDFInfo
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- the present invention relates to a simulation program, a simulation method, and an information processing device.
- Quantum computer calculations are realized by performing initialization, gate operations, and measurement processing for multiple qubits.
- an error physical error
- quantum computers qubit redundancy is performed in the same way as conventional computers (also called classical computers) in order to identify error qubits and error details.
- a surface code is one of the methods for identifying error qubits and error content using redundant qubits.
- data qubits and ancillary qubits are alternately arranged in a two-dimensional lattice.
- the state of a data qubit among a plurality of qubits (data qubits and auxiliary qubits) arranged in a lattice is encoded into one logical qubit.
- Ancillary qubits are used either for X error detection or for Z error detection per column.
- the quantum computer first properly initializes the logical quantum state, and upon error detection, performs gating operations between one ancillary qubit and the four surrounding data qubits, and an ancillary qubit measurement.
- Quantum computers detect X or Z errors based on the value of the auxiliary qubits. Then, the quantum computer uses the information indicating the type of error and the position information of the data qubit identified as the error location to perform the gate operation of error correction processing on the qubit.
- a quantum error correction method that does not depend on the system size has been proposed.
- Methods have also been proposed for determining and correcting errors in the alignment of qubits that implement quantum algorithms.
- Techniques have also been proposed for correcting fault-tolerant quantum errors in one or more of a plurality of physical qubits based on measurements from at least one flag qubit.
- JP 2014-241484 A Japanese Patent Publication No. 2020-535690 U.S. Patent Application Publication No. 2021/0019223
- error correction may fail even if a surface code is used. Such error correction failures are called logic errors.
- the probability of occurrence of logical errors changes according to the number of qubits in the lattice representing one logical qubit.
- the probability of occurrence of logical errors also changes depending on the rate of occurrence of qubit errors due to environmental noise and the like. Therefore, in order to evaluate the performance of quantum error correction using surface codes, it is conceivable to simulate error correction using surface codes using a classical computer (also called a von Neumann computer). With an actual quantum computer, it is not possible to determine whether there is a logic error without measuring the data qubits themselves, but with a simulation, the location of the error can be determined in advance. Therefore, by simulating the error correction using the surface code under predetermined conditions, it is possible to determine whether or not a logic error occurs under those conditions. This makes it possible to investigate the appropriate number of qubits per logical qubit when applying the surface code to a quantum computer.
- the purpose of this case is to efficiently determine whether or not a logic error has occurred.
- a simulation program causes a computer to perform the following processes.
- the computer generates qubit information representing a two-dimensional lattice in which a plurality of data qubits and a plurality of ancillary qubits are alternately arranged in row and column directions.
- the computer sets error information indicating occurrence of an error in a first data qubit among the plurality of data qubits to the qubit information.
- the computer sets error detection information in which the states of the auxiliary qubits adjacent to the first data qubit in the row or column direction are inverted from the initial values in the qubit information.
- the computer sets error correction information indicating a second data qubit to be subjected to error correction by the surface code based on the error detection information in the qubit information.
- the computer determines a logical error based on the number of data qubits corresponding to either the first data qubit or the second data qubit in one row or one column in the two-dimensional lattice. Determine the presence or absence of occurrence.
- FIG. 10 is a diagram showing an example of measurements using an auxiliary qubit;
- FIG. 3 is a diagram showing an example of a configuration of a quantum bit for performing surface coding;
- FIG. 10 is a diagram showing an example of gate operation for X error detection;
- FIG. 10 is a diagram showing an example of gate operation for Z error detection;
- FIG. 4 is a diagram illustrating mathematical representations of a logical Z operator Lz and a logical X operator Lx;
- FIG. 10 is a diagram showing an example of X error detection; It is a figure which shows an example of error location identification.
- FIG. 10 is a diagram showing an example of a case where an error occurrence location cannot be uniquely specified;
- FIG. 10 is a diagram showing an example of error correction by correcting data qubits other than where the error occurred;
- FIG. 10 is a diagram showing an example of an error correction success pattern; It is a figure which shows an example of the logic error by miscorrection.
- FIG. 10 is a diagram showing an example of logic error determination by searching for an error chain;
- FIG. 10 is a diagram showing an example of logic error determination by searching for an error chain;
- FIG. 10 is a diagram showing an example of logic error determination based on state data of data qubits for one row of two-dimensional lattice;
- FIG. 10 is a diagram for explaining that a logical error occurs when the number of inverted qubits in a vertical row is an odd number;
- FIG. 4 is a diagram showing an example of data qubits used for logic error determination;
- FIG. 4 is a block diagram illustrating the functionality of a computer for performing surface code simulation;
- FIG. 10 is a flowchart showing an example of the procedure of logic error determination processing using surface code simulation;
- FIG. It is a figure which shows an example of simulation conditions.
- FIG. 10 is a flowchart showing an example of the procedure of surface code simulation processing;
- FIG. 7 is a flowchart showing an example of a procedure of logic error (Z error) determination processing; 7 is a flow chart showing an example of the procedure of logic error (X error) determination processing; FIG. 4 is a graph showing the relationship between the number of data qubits on one side of a two-dimensional lattice and the number of searches; FIG.
- the first embodiment is a simulation method for efficiently determining whether or not a logic error occurs when performing an error correction processing simulation using a surface code for quantum bit errors that occur in a quantum computer.
- FIG. 1 is a diagram showing an example of a simulation method according to the first embodiment.
- FIG. 1 shows an information processing apparatus 10 used for implementing the simulation method.
- the information processing device 10 can implement the simulation method by executing a simulation program, for example.
- the information processing device 10 has a storage unit 11 and a processing unit 12 .
- the storage unit 11 is, for example, a memory or a storage device that the information processing device 10 has.
- the processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10 .
- the storage unit 11 stores qubit information 1 indicating a two-dimensional lattice in which a plurality of data qubits and a plurality of auxiliary qubits are alternately arranged in the row direction and the column direction.
- qubits are arranged at regular intervals in a rectangular region, and the qubits arranged along the four sides of the rectangle serve as boundaries of the two-dimensional lattice.
- the two-dimensional lattice shown in the qubit information 1 is, for example, a column in which auxiliary qubits for phase inversion error (Z error) detection are arranged and a column in which auxiliary qubits for bit inversion error (X error) detection are arranged. are provided alternately.
- rows in which the auxiliary qubits for phase inversion error detection are arranged and rows in which the auxiliary qubits for bit inversion error detection are arranged are alternately provided.
- the processing unit 12 receives an input of simulation conditions from the user and generates the quantum bit information 1 according to the simulation conditions.
- the simulation conditions include, for example, the number of qubits in the row direction and the column direction of the two-dimensional lattice, the error rate in the data qubits, and the like.
- the processing unit 12 generates quantum bit information 1 based on the simulation conditions.
- the processing unit 12 then stores the generated quantum bit information 1 in the storage unit 11 .
- the processing unit 12 sets, for the quantum bit information 1, error information indicating the occurrence of an error in the first data quantum bit among the plurality of data quantum bits. For example, the processing unit 12 randomly (randomly) determines the first data qubit to generate an error from among the plurality of data qubits based on a predetermined error rate.
- the error that occurs in the first data qubit is an unintended state reversal (bit reversal or phase reversal) of the data qubit.
- the first data qubit is indicated by striped hatching.
- the processing unit 12 sets error detection information in which the state of the auxiliary qubits adjacent to the first data qubit in the row direction or column direction is inverted from the initial value for the qubit information 1 .
- the processing unit 12 inverts the state of the auxiliary qubit by the number of adjacent first data qubits. So, for example, the auxiliary qubits adjacent to the two first data qubits flip state twice and return to the initial state.
- hatching with a checkered pattern indicates auxiliary processing bits that have been inverted from their initial values.
- the processing unit 12 sets error correction information indicating the second data qubit to be subjected to error correction by the surface code based on the error detection information to the qubit information 1 .
- the processing unit 12 obtains an error occurrence pattern of the data qubits such that the auxiliary qubits are inverted when error detection is performed, for example, based on the arrangement of the auxiliary qubits whose states are inverted.
- the processing unit 12 sets the data qubit in which an error has occurred in the error occurrence pattern as the second data qubit to be subjected to error correction.
- the rectangle of the data qubit to be error-corrected is represented by double lines.
- the processing unit 12 detects a logic error based on the number of data qubits corresponding to either the first data qubit or the second data qubit in one row or one column in the two-dimensional lattice. It is determined whether or not the occurrence of For example, the processing unit 12 determines the number of data qubits (inverted qubits) corresponding to either the first data qubit or the second data qubit in one row or one column in the two-dimensional lattice. is an odd number, it is determined that a logic error has occurred.
- a data qubit corresponding to both the first data qubit and the second data qubit is a correctly corrected data qubit in which an error has occurred, and is not included in the inversion qubit.
- the presence or absence of a logic error is determined based on the number of inverted qubits in the fifth column.
- the number of inverted qubits is "0" (an even number), and it is determined that no logic error has occurred.
- the number of inversion qubits is "2" (an even number), and it is determined that no logic error has occurred.
- the number of inversion qubits is "1" (odd number), and it is determined that a logic error has occurred.
- the borders of the four sides of the two-dimensional lattice have phase inversion error detection
- the processing unit 12 Based on the number of data qubits corresponding to either the first data qubit or the second data qubit in one row or one column in the direction parallel to the rough boundary, the processing unit 12 , to determine whether or not a logic error caused by a phase reversal error has occurred.
- the processing unit 12 determines the number of data qubits corresponding to either the first data qubit or the second data qubit in one row or one column in a direction parallel to the smooth boundary. to determine whether or not a logic error has occurred due to a bit reversal error.
- the processing unit 12 may repeat the setting of error information, the setting of error detection information, the setting of error correction information, and the determination of the presence or absence of occurrence of a logic error a predetermined number of times. In this case, for example, the processing unit 12 calculates the probability of occurrence of a logic error based on the determination result of whether or not a logic error has occurred a predetermined number of times. As a result, the probability of logic error occurrence corresponding to the error rate of the data qubits is obtained.
- the second embodiment is a computer that executes an error correction simulation (hereinafter referred to as a surface code simulation) for randomly occurring errors in a quantum computer and efficiently determines whether or not a logic error occurs. is.
- a surface code simulation an error correction simulation for randomly occurring errors in a quantum computer and efficiently determines whether or not a logic error occurs.
- FIG. 2 is a diagram showing an example of computer hardware for surface code simulation.
- a computer 100 is entirely controlled by a processor 101 .
- a memory 102 and a plurality of peripheral devices are connected to the processor 101 via a bus 109 .
- Processor 101 may be a multiprocessor.
- the processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or a DSP (Digital Signal Processor).
- processor 101 executing a program may be realized by an electronic circuit such as ASIC (Application Specific Integrated Circuit) or PLD (Programmable Logic Device).
- ASIC Application Specific Integrated Circuit
- PLD Programmable Logic Device
- the memory 102 is used as the main storage device of the computer 100.
- the memory 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the processor 101 .
- the memory 102 stores various data used for processing by the processor 101 .
- a volatile semiconductor memory device such as RAM (Random Access Memory) is used.
- Peripheral devices connected to the bus 109 include a storage device 103 , a GPU (Graphics Processing Unit) 104 , an input interface 105 , an optical drive device 106 , a device connection interface 107 and a network interface 108 .
- a storage device 103 a storage device 103 , a GPU (Graphics Processing Unit) 104 , an input interface 105 , an optical drive device 106 , a device connection interface 107 and a network interface 108 .
- GPU Graphics Processing Unit
- the storage device 103 electrically or magnetically writes data to and reads data from a built-in recording medium.
- a storage device 103 is used as an auxiliary storage device for the computer 100 .
- the storage device 103 stores an OS program, application programs, and various data.
- an HDD Hard Disk Drive
- an SSD Solid State Drive
- the GPU 104 is an arithmetic unit that performs image processing, and is also called a graphics controller.
- a monitor 21 is connected to the GPU 104 .
- the GPU 104 displays an image on the screen of the monitor 21 according to instructions from the processor 101 .
- Examples of the monitor 21 include a display device using an organic EL (Electro Luminescence), a liquid crystal display device, and the like.
- a keyboard 22 and a mouse 23 are connected to the input interface 105 .
- the input interface 105 transmits signals sent from the keyboard 22 and mouse 23 to the processor 101 .
- the mouse 23 is an example of a pointing device, and other pointing devices can also be used.
- Other pointing devices include touch panels, tablets, touchpads, trackballs, and the like.
- the optical drive device 106 reads data recorded on the optical disc 24 or writes data to the optical disc 24 using laser light or the like.
- the optical disc 24 is a portable recording medium on which data is recorded so as to be readable by light reflection.
- the optical disc 24 includes DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable)/RW (ReWritable), and the like.
- the device connection interface 107 is a communication interface for connecting peripheral devices to the computer 100 .
- the device connection interface 107 can be connected to the memory device 25 and the memory reader/writer 26 .
- the memory device 25 is a recording medium equipped with a communication function with the device connection interface 107 .
- the memory reader/writer 26 is a device that writes data to the memory card 27 or reads data from the memory card 27 .
- the memory card 27 is a card-type recording medium.
- the network interface 108 is connected to the network 20.
- Network interface 108 transmits and receives data to and from other computers or communication devices via network 20 .
- the network interface 108 is a wired communication interface that is connected by a cable to a wired communication device such as a switch or router.
- the network interface 108 may be a wireless communication interface that communicates with a wireless communication device such as a base station or an access point via radio waves.
- the computer 100 can implement the processing functions of the second embodiment with the above hardware.
- the information processing apparatus 10 shown in the first embodiment can also be realized by hardware similar to the computer 100 shown in FIG.
- the computer 100 implements the processing functions of the second embodiment, for example, by executing a program recorded on a computer-readable recording medium.
- a program describing the processing content to be executed by the computer 100 can be recorded in various recording media.
- a program to be executed by the computer 100 can be stored in the storage device 103 .
- the processor 101 loads at least part of the program in the storage device 103 into the memory 102 and executes the program.
- the program to be executed by the computer 100 can also be recorded in a portable recording medium such as the optical disc 24, memory device 25, memory card 27, or the like.
- a program stored in a portable recording medium can be executed after being installed in the storage device 103 under the control of the processor 101, for example.
- the processor 101 can read and execute the program directly from the portable recording medium.
- FIG. 3 is a diagram explaining a quantum bit.
- a quantum bit is the smallest unit of quantum information corresponding to the smallest unit of information amount in a conventional computer, the "bit" (classical bit).
- a quantum bit takes a quantum mechanical superposition state (quantum state) of “0” and “1”.
- the quantum state of a quantum bit is mathematically represented by a two-dimensional vector as shown in the following equation (1), where
- Quantum gate-based quantum computers perform gate operations on qubits to proceed with computations according to the purpose.
- a gate operation is an operation that changes the quantum state, and is mathematically expressed as applying a matrix operator to the vector of the quantum state.
- a gate operation for example, there is an X gate that performs bit inversion of a quantum bit.
- the operation by the X gate is expressed as a formula as follows.
- Pauli operators include the following three matrix operators.
- the Hadamard operator is used for gate operations that create superposition states on
- the Hadamard operator is represented by Equation (6) below.
- a two-qubit state is represented as the tensor product of a one-qubit state "
- a matrix operator acting on two qubits is, for example, the CNOT operator.
- the CNOT operator bit-flips the other qubit (target qubit) (
- the CNOT operator is represented by the following formula.
- a quantum circuit is used to collectively express gate operations for multiple qubits.
- qubit state transitions are represented by lines, and each gate operation is represented by a corresponding symbol.
- FIG. 4 is a diagram showing an example of a quantum circuit.
- Each horizontal line in quantum circuit 32 corresponds to a quantum bit. Inputs to the qubits are shown to the left of the horizontal line. Above each horizontal line, symbols indicating gate operations for the corresponding qubit are arranged horizontally (from left to right) in chronological order. Symbols 32a, 32b, such as meters to the right of the horizontal lines, indicate measuring operations.
- the X symbol 32c surrounded by a rectangle indicates the Pauli operator "X” (X gate operation).
- the rectangular Z symbol 32d indicates the Pauli operator "Z” (Z gate operation).
- a rectangular H symbol 32e indicates a Hadamard operator "H” (Hadamard gate operation).
- Gate operations for two qubits are written across multiple horizontal lines.
- the symbols 32f and 32g indicating gate operations corresponding to the CNOT operator C X are lines connecting white and black circles with + in them.
- a black circle is placed on the horizontal line of the control qubit, and a white circle with a + in it is placed on the horizontal line of the target qubit.
- the quantum circuit 32 shown in FIG. 4 applies the gate operation "C X (2,1) Z (1) C X (1,2) H (2) X (1) " to two qubits in state
- the gate operations indicated by the quantum circuit 32 are executed in order. At that time, an error may occur in the qubit. To obtain correct calculation results, it is important to be able to detect the occurrence of errors and correct them.
- FIG. 5 is a diagram showing an example of an error occurrence situation in a quantum bit.
- Qubit 33 is subject to various noises. Types of noise include environmental noise, noise during qubit operations, and interference from other qubits. The qubit 33 may unintentionally change state due to noise. Such unintended state changes are qubit errors. Types of errors that occur in quantum bits are classified into the following two types. ⁇ Bit reversal error (X error):
- X error State reversal error
- Z error Phase reversal error
- qubit errors can be corrected by applying the same Pauli operator (X, Z) as the error.
- Such an operation is called quantum error correction.
- X X
- Z Pauli operator
- FIG. 8 The X error is expressed by the following equation (8), and the correction gate operation is expressed by equation (9).
- FIG. 6 is a diagram illustrating an example of quantum bit redundancy.
- FIG. 6 shows an example of redundancy using 8 qubits.
- ⁇ > represented by one quantum bit 34 is represented by the logical quantum state
- the logical qubit 35 is composed of a plurality of qubits 35a-35h.
- the error qubit and the error content are specified by the process of specifying the error qubit and the error content.
- an error correction gate operation is performed on the quantum bit 35h. Error correction corrects the state of logical qubit 35 to the state it would be in if no error had occurred.
- FIG. 7 is a diagram showing an example of measurement using an auxiliary qubit.
- the state of qubit 36 cannot be copied to auxiliary qubit 37 .
- a two-qubit operation is then performed on the qubit 36 and the auxiliary qubit 37 .
- a two-qubit operation changes the state of the auxiliary qubit 37 depending on the state of the qubit 36 .
- By measuring the state of the ancillary qubit 37 a change from the initial state of the ancillary qubit 37 can be detected.
- the state of the qubit 36 can be known from whether or not the auxiliary qubit 37 has changed from the initial state.
- Surface coding is a method for identifying error qubits based on the state of the qubits obtained using the auxiliary qubits.
- a surface code is a typical coding (redundancy) technique in quantum error correction.
- FIG. 8 is a diagram showing an example of the configuration of a quantum bit for performing surface coding.
- quantum bits are arranged in a two-dimensional lattice.
- the data qubits 40a-40f and the auxiliary qubits 41a-41d, 42a-42d are alternately arranged in the row direction and the column direction.
- the auxiliary qubits 41a-41d and 42a-42d are divided into auxiliary qubits 41a-41d for X error detection and auxiliary qubits 42a-42d for Z error detection.
- auxiliary qubits 41a to 41d for X error detection and auxiliary qubits 42a to 42d for Z error detection are alternately arranged for each column.
- the quantum bits shown in FIG. 8 are part of the quantum bits used for error correction using surface codes.
- the quantum number of one side of the two-dimensional lattice containing all the qubits used for error correction (the sum of the data qubits and the auxiliary qubits) is an odd number, and the qubits are arranged at the four corners. is the data qubit (see FIG. 11).
- the logical quantum state is properly initialized, and when an error is detected, a gate operation (two-qubit operation) is performed between one ancillary qubit and four surrounding data qubits, and the ancillary qubit is measured. By doing so, the presence or absence of an error can be detected.
- FIG. 9 is a diagram showing an example of gate operation for X error detection.
- an ancillary qubit 41d is used to detect an error in any of the data qubits 40d, 40e, 40h, and 40f adjacent to the ancillary qubit 41d.
- the identifier of the data qubit 40d is "a”
- the identifier of the data qubit 40e is "b”
- the identifier of the data qubit 40h is "c”
- the identifier of the data qubit 40f is "d”
- the auxiliary qubit 41d 's identifier is 'e'.
- the quantum circuit 43 is shown to perform a CNOT gate operation with the data qubits 40d, 40e, 40h, and 40f as control qubits and the auxiliary qubit 41d as a target qubit.
- Such gating causes the auxiliary qubit 41d to change from its initial state if an X error has occurred in one of the data qubits 40d, 40e, 40h, and 40f.
- FIG. 10 is a diagram showing an example of gate operation for Z error detection.
- an ancillary qubit 42a is used to detect an error in any of the data qubits 40a, 40c, 40d, and 40e adjacent to the ancillary qubit 42a.
- the identifier of the data qubit 40a is "g”
- the identifier of the data qubit 40c is "f”
- the identifier of the auxiliary qubit 42a is "h”.
- the identifier for data qubit 40d is "a” and the identifier for data qubit 40e is "b.”
- Quantum circuit 44 By performing the gate operation shown in the quantum circuit 44 on these qubits, Z error detection of the data qubits 40a, 40c, 40d, and 40e becomes possible.
- Quantum circuit 44 is shown first performing a Hadamard gate operation on auxiliary qubit 42a. Thereafter, a CNOT gate operation is performed with each of the data qubits 40a, 40c, 40d, and 40e as the target qubit and the auxiliary qubit 42a as the control qubit.
- a Hadamard gate operation is performed on the auxiliary qubit 42a. Note that in the situation shown in the quantum circuit 44, in the CNOT gate operation between the data qubit in which the Z error occurred and the auxiliary qubit 42a, contrary to normal, the control qubit A certain auxiliary qubit 42a changes state.
- the auxiliary qubit 42a changes from its initial state.
- the initial state of the ancillary qubit 42a is
- the gate operation for error detection shown in FIG. 9 or 10 changes the states of the data qubit and the auxiliary qubit even when there is no error.
- ⁇ > L are initialized to be the eigenstates of the stabilizer operator (eigenvalues of +1 or -1).
- the stabilizer operator is the product of Z or X operators acting on the four data qubits surrounding the ancillary qubit.
- the stabilizer operator for X error detection shown in FIG. 9 is "Z (i1) Z (i2) Z (i3) Z (i4)
- ⁇ > L ⁇
- i is the index of the auxiliary qubit for X error detection.
- the number to the right of i is the number that distinguishes the data qubits surrounding the ancillary qubit.
- the upper data qubit is "1”
- the left data qubit is "2”
- the lower data qubit is "3”
- the right data qubit is "4".
- Z (i1) denotes the Z operator acting on the data qubit above the i-th ancillary qubit.
- the stabilizer operator for Z error detection shown in FIG. 10 is "X (j1) X (j2) X (j3) X (j4)
- ⁇ > L ⁇
- j is the index of the ancillary qubit for Z error detection.
- the number to the right of j is the number that distinguishes the data qubits surrounding the ancillary qubit.
- Logical operators include logical Z operator Lz and logical X operator Lx. These logical operators satisfy the following properties.
- the first property is that logical operators satisfy commutation relations with all stabilizer operators. For example, for the logical Z operator Lz, let S be the stabilizer operator, and let the logical quantum state
- ⁇ > L
- ⁇ > L ). In this case, from the commutation relation SLz LzS, SLz
- ⁇ > L LzS
- ⁇ > L Lz
- FIG. 11 is a diagram illustrating mathematical representations of the logical Z operator Lz and the logical X operator Lx. Of the left, right, upper and lower boundaries in the array of lattice-like qubits that make up the logic qubits, the boundaries along which auxiliary qubits for X error detection are arranged are called rough boundaries 45 and 46 . Boundaries along which auxiliary qubits for Z-error detection are arranged are called smooth boundaries 47 and 48 .
- the logical Z operator Lz is mathematically represented by the product of the Z operators over the data qubits from one rough boundary 45 to the opposite rough boundary 46 .
- the logical Z operator Lz phase-inverts the logical quantum state (Lz
- 0> L
- 1> L -
- the logical X operator Lx is mathematically represented by the product of the X operators over the data qubits from one smooth boundary 47 to the opposite smooth boundary 48 .
- the logical X operator Lx bit-reverses the logical quantum state (Lx
- 0> L
- 1> L
- FIG. 12 is a diagram showing an example of X error detection. For example, if
- ⁇ ′> L X (i1)
- FIG. 13 is a diagram showing an example of error location identification.
- FIG. 13 shows an example of specifying the error location of the Z error, but it is possible to specify the error location of the X error as well.
- the auxiliary qubits for X error detection are omitted (the same applies to FIGS. 14 to 20).
- the data qubit 51 in which the error occurred is within the same circle as the two auxiliary qubits 52 and 53, respectively.
- the auxiliary qubits 52, 53 are detected to have flipped state by the measurement. Since the states of the ancillary qubits 52 and 53 are inverted, the data qubit 51 located between them is specified as an error occurrence location. Therefore, an error correction operation (Z gate operation) is performed on the data quantum bit 51 .
- FIG. 14 is a diagram showing an example of a case where the error occurrence location cannot be uniquely specified.
- errors occur in two data qubits.
- the position between the data qubits in which the error occurred has a difference of 1 row and 3 columns.
- the states of the four ancillary qubits adjacent to one of the errored data qubits are reversed (the measured information becomes "-1"). Based on the four flipped ancillary qubits, we will attempt to locate the error qubit.
- a first error occurrence pattern 61 is an example of the case where the error occurred data qubit was correctly identified.
- a second error occurrence pattern 62 and a third error occurrence pattern 63 are examples in which the error-caused data qubit cannot be correctly specified.
- FIG. 15 is a diagram showing an example of error correction by correcting data qubits other than where the error occurred.
- errors occur in two data qubits 64 and 65 . These data qubits 64 and 65 are shifted by one row in the row direction and are also shifted by one row in the column direction.
- the error detection flips the state of the ancillary qubit 66 adjacent above the data qubit 64 and the state of the ancillary qubit 67 adjacent to the right of the data qubit 65 .
- the auxiliary qubit 70 adjacent below the data qubit 64 is adjacent to the left of the data qubit 65, so the state is not inverted.
- data qubits 68 and 69 are used in addition to the case where an error occurs in the data qubits 64 and 65. an error may have occurred.
- the error correction operation is performed on the data qubits 68 and 69 instead of the data qubits 64 and 65 in which the error occurs.
- a loop 72 is formed by the error-corrected data qubits 68 and 69 and the error-uncorrected data qubits 64 and 65 .
- Formation of the loop 72 here means that, among the erroneously corrected data qubits and the error-uncorrected data qubits, the data qubits adjacent to the common auxiliary qubit for Z error detection are connected by a line. , a closed curve is formed.
- a loop 72 is formed at .
- the two error-uncorrected data qubits 64 and 65 are both adjacent to the auxiliary qubit 70, so they can be connected by a line.
- Both the uncorrected data qubit 65 and the erroneously corrected data qubit 69 are adjacent to the ancillary qubit 67 and can be connected by a line.
- the two erroneously corrected data qubits 68 and 69 are both adjacent to the ancillary qubit 71 and can be connected by a line.
- Both the erroneously corrected data qubit 68 and the uncorrected data qubit 64 are adjacent to the ancillary qubit 66 and can be connected by a line.
- the lines connecting the uncorrected data qubits 64, 65 and the erroneously corrected data qubits 68, 69 form a closed curve. That is, a loop 72 is formed.
- FIG. 16 is a diagram showing an example of an error correction success pattern.
- the error correction success pattern 75 is a case where the data qubit in which the error occurred and the corrected data qubit completely match.
- Error correction success patterns 76 and 77 are cases where error correction is successful because a loop is formed by an uncorrected data qubit and an erroneously corrected data qubit. In this way, in order to successfully correct an error using a surface code, it is a requirement that the corrected portion and the actual error portion must be exactly the same, or that a loop must be formed.
- the number of corrected data qubits around each of the inverted auxiliary qubits 75a and 75b in the error correction success pattern 75 is "1" (odd number).
- the number of corrected data qubits around the non-inverted ancillary qubit 75c is "0" (an even number).
- the numbers of corrected data qubits around each of the inverted ancillary qubits 76a, 76b in the error correction success pattern 76 are both "1" (odd).
- the number of corrected data qubits around the non-inverted ancillary qubit 76c is "0" (an even number).
- the numbers of corrected data qubits around each of the inverted ancillary qubits 77f and 77g in the error correction success pattern 77 are both "1" (odd number). Also, the number of corrected data qubits around each of the non-inverted auxiliary qubits 77a to 77e is all "2" (an even number).
- FIG. 17 is a diagram showing an example of a logical error caused by erroneous correction.
- a Z error occurs in one data qubit 78a to 78c on the same column.
- the states of the auxiliary qubits 78d-78h adjacent to any of the data qubits 78a-78c on the same column are flipped.
- the error correction operation is performed on the data qubits 78i to 78k other than the data qubits 78a to 78c in which the error has occurred. Even in such error correction, the even-odd constraint is observed.
- the errored data qubits 78a-78c do not match the corrected data qubits 78i-78k, and no loop is formed. That is, it is a logical error due to erroneous correction.
- a logical error occurs, correct calculations cannot be performed. How often logical errors occur in the surface code depends on the number of qubits forming the logical qubit, the error occurrence frequency of each qubit, and the like. In an actual quantum computer, it is impossible to determine whether a logic error occurs or not without measuring the data qubit itself, and it is also impossible to grasp the frequency of occurrence. However, if a classical computer is used to perform an error correction simulation using a surface code, it is possible to determine whether or not a logical error has occurred, since the locations where errors have occurred can be known in advance. Whether or not a logical error has occurred can be determined by searching for a connection (error chain) of data qubits in which an error has occurred.
- a simulation of quantum error correction using a surface code (hereinafter referred to as a surface code simulation) assuming a large-scale quantum computer, it is desirable to be able to efficiently determine whether or not a logic error has occurred.
- FIG. 18 is a diagram showing an example of logic error determination by searching for an error chain.
- the computer searches on a two-dimensional grid to see if an error chain runs from one boundary to the other. Specifically, first, if there is an inverted data qubit among the boundary data qubits, the computer uses that data qubit as the starting point of the search. In the example of FIG. 18, data qubit 78a is the starting point for the search.
- the computer sequentially determines whether or not the data qubits adjacent to the same auxiliary qubit are inverted, starting with the data qubit 78a at the starting point.
- the computer joins a data qubit into an error chain if a data qubit adjacent to the same auxiliary qubit as the data qubit whose state is flipped has its state flipped.
- the computer will then determine that there is a logic error if the error chain eventually continues with the data qubit 78i on the opposite boundary.
- the number of searches increases as the number of errors increases. Also, if the number of data qubits on one side of the two-dimensional lattice is N (N is a natural number), the number of searches increases exponentially when N is sufficiently large. As a result, when performing a large-scale surface code simulation, the logic error judgment takes a long time, and the execution efficiency deteriorates.
- the computer 100 determines whether or not there is a logic error based only on the state data of the data qubits for one row of the two-dimensional lattice.
- FIG. 19 is a diagram showing an example of logic error determination based on state data of data qubits for one row of a two-dimensional lattice. 17 shows three error correction patterns when an error similar to the error occurrence pattern 78 shown in FIG. 17 occurs.
- An error correction success pattern 81-1 is an example of a case where the data qubits 81a to 81c in which errors have occurred are subjected to data correction with a perfect match.
- error correction success pattern 81-2 data correction is performed on data qubits 81a and 81c in which errors have occurred and data qubits 81d to 81f in which no errors have occurred. This is a successful example.
- An error correction failure pattern 81-3 is an example of occurrence of a logic error due to data correction of data quantum bits 81g to 81i in which no error has occurred.
- the state of the data qubit will be one of the following. 1. Error qubits are fully corrected. 2. Inverted qubits (error-uncorrected data qubits and error-corrected data qubits) form a loop. 3. A logic error has occurred.
- the computer investigates whether the number of inverted qubits among the data qubits in one row (rows 82a to 82c to be investigated) of the two-dimensional lattice in FIG. 19 is even or odd. Note that columns 82a to 82c to be investigated are selected from columns in which data qubits exist on smooth boundaries, for example.
- the number of inverted qubits in the investigation target column 82a is "0" (an even number).
- the number of inverted qubits in the column under investigation 82b is "2" (an even number).
- the number of inverted qubits in the column under investigation 82c is "1" (an odd number).
- the computer 100 determines a logic error when the number of inverted qubits in a vertical row is an odd number.
- FIG. 20 is a diagram for explaining that a logic error occurs when the number of inversion qubits in a vertical row is an odd number.
- FIG. 20 shows a state 83 in which the logic Z operator Lz acts on the two-dimensional lattice array, and a state 84 in which the logic X operator Lx acts on the two-dimensional lattice array.
- logic error determination for X errors can also be performed in a similar manner.
- the logical error determination for the X error the logical error is determined based on the data qubits of the first row of the lattice (row to be investigated).
- FIG. 21 is a diagram showing an example of data quantum bits used for logic error determination.
- the rough boundaries are the column-oriented edges and the smooth boundaries are the row-oriented edges.
- any one of the columns with data qubits on smooth boundaries becomes the column under investigation 85 for use in logical error determination of Z errors.
- An arbitrary one of the rows in which data qubits exist on rough boundaries becomes a row to be investigated 86 used for logic error determination of X errors.
- FIG. 22 is a block diagram illustrating the functionality of a computer for performing surface code simulations.
- the computer 100 has a storage section 110 , a surface code simulation management section 120 , an error occurrence state generation section 130 , an error correction section 140 and a logical error determination section 150 .
- the storage unit 110 stores simulation conditions 111 and simulation results 112 .
- the simulation conditions 111 include information such as the size of the two-dimensional lattice and the error rate of quantum bits.
- the simulation result 112 includes information such as logic error rate.
- the surface code simulation management unit 120 manages the progress of the surface code simulation. For example, the input of the simulation conditions 111 is received, and the input simulation conditions 111 are stored in the storage unit 110 . In addition, the surface code simulation management unit 120 causes the error occurrence state generation unit 130, the error correction unit 140, and the logical error determination unit 150 to perform the surface code simulation a predetermined number of times. Furthermore, the surface code simulation management section 120 stores the simulation result 112 in the storage section 110 .
- the error generation state generator 130 generates an X error or Z error in the data qubits in the two-dimensional lattice according to the simulation conditions 111 . Also, the error occurrence state generator 130 inverts the state of the auxiliary qubit according to the error that has occurred.
- the error correction unit 140 performs error correction processing based on the state of the inverted auxiliary qubit.
- the error correction process reverses the state of data qubits that are presumed to be in error.
- the logic error determination unit 150 determines whether or not the state of the logic qubit shown in the two-dimensional lattice after error correction is a logic error.
- the logic error determination section 150 notifies the surface code simulation management section 120 of the determination result.
- each element shown in FIG. 22 can be realized by causing a computer to execute a program module corresponding to the element, for example.
- FIG. 23 is a flow chart showing an example of the procedure of logic error determination processing using surface code simulation. The processing shown in FIG. 23 will be described below along with the step numbers.
- the surface code simulation management unit 120 receives an input of the simulation conditions 111 from the user. When the simulation conditions 111 are input, the surface code simulation management unit 120 stores the simulation conditions 111 in the storage unit 110 .
- the surface code simulation management unit 120 cooperates with the error occurrence state generation unit 130, the error correction unit 140, and the logic error determination unit 150 to execute the surface code simulation.
- the details of the surface code simulation process will be described later (see FIG. 24).
- the surface code simulation provides information indicating whether or not a logic error occurs when error correction is performed using the surface code shown in the simulation conditions 111 .
- Step S103 The surface code simulation management unit 120 determines whether or not the surface code simulation has been repeated a predetermined number of times (eg, 10,000 times). When the number of iterations reaches the predetermined number, the surface code simulation manager 120 advances the process to step S104. If the number of iterations is less than the predetermined number, the surface code simulation manager 120 advances the process to step S102.
- a predetermined number of times eg, 10,000 times.
- the surface code simulation management unit 120 calculates the occurrence rate of logic errors based on the information indicating the presence or absence of logic errors obtained from surface code simulations for a predetermined number of times.
- the occurrence rate of logic errors is, for example, a value obtained by dividing the number of times the surface code simulation determines that a logic error has occurred by the number of repetitions of the surface code simulation.
- the surface code simulation management unit 120 calculates the logical error rate for each error occurrence pattern, for example.
- the logical error occurrence rate in this case is the ratio of data correction patterns determined to be logical errors among a plurality of data correction patterns corresponding to one error occurrence pattern.
- the surface code simulation management section 120 calculates, for example, the average of the logical error rate of each of the plurality of error occurrence patterns as the simulation result 112 . Then, the surface code simulation management section 120 stores the simulation result 112 including the logic error rate in the storage section 110 .
- FIG. 24 is a diagram showing an example of simulation conditions.
- the simulation conditions 111 include, for example, the following data.
- ⁇ Z error rate data Rz ⁇ X error rate data: Rx
- the Z error rate data is data indicating the probability of occurrence of Z errors in the data qubits.
- the X error rate data is data indicating the probability of X errors occurring in the data qubit.
- FIG. 25 is a flow chart showing an example of the procedure of surface symbol simulation processing. The processing shown in FIG. 25 will be described below along with the step numbers.
- the surface code simulation management unit 120 acquires the simulation conditions 111 from the storage unit 110 . Based on the obtained simulation conditions 111, the surface code simulation management unit 120 generates quantum bit information indicating a two-dimensional lattice in which quantum bits are arranged at equal intervals in the row direction and the column direction within a rectangular area.
- the quantum bit information includes state data indicating the quantum state of each quantum bit.
- the surface code simulation manager 120 transmits the generated qubit information to the error generation state generation unit 130 and instructs generation of an error generation state for the data qubits in the two-dimensional lattice.
- Step S112 The error occurrence state generator 130 counts up the variable i one by one from 1 and executes the processing of steps S113 to S115 for each value of i until it reaches N data .
- the error occurrence state generator 130 generates a random number r greater than 0 and less than 1.
- the error occurrence state generator 130 determines whether or not the value of the random number r is smaller than Rz, which indicates the Z error rate. If the value of random number r is smaller than Rz, error occurrence state generator 130 advances the process to step S115. If the value of random number r is equal to or greater than Rz, error occurrence state generation unit 130 advances the process to step S116.
- Step S116 If the value of the variable i has reached N data , the error occurrence state generator 130 advances the process to step S117.
- Step S117 The error occurrence state generator 130 counts up the variable i by 1 in order from 1, and executes the processing of steps S118 to S121 for each value of i until it reaches N data .
- the error occurrence state generator 130 generates a random number r greater than zero and less than one.
- the error occurrence state generator 130 determines whether the value of the random number r is smaller than Rx, which indicates the X error rate. If the value of random number r is smaller than Rx, error occurrence state generator 130 advances the process to step S120. Also, if the value of the random number r is equal to or greater than Rx, the error occurrence state generation unit 130 advances the process to step S121.
- Step S121 If the value of the variable i has reached N data , the error occurrence state generator 130 advances the process to step S122.
- Step S122 The error correction unit 140 performs error correction processing on the data qubits based on the state data of the auxiliary qubits. For example, the error correction unit 140 identifies data qubits in which a Z error or an X error has occurred, as shown in FIG. 14, based on the data qubits whose values have been inverted. Then, the error correction unit 140 performs error correction processing according to the error that has occurred on the data quantum bit that is estimated to have an error. For example, the error correction unit 140 inverts the phase of the data qubit estimated to have the Z error, and inverts the bit of the data qubit estimated to have the X error.
- Step S123 The logic error determination unit 150 performs logic error (Z error) determination processing based on the number of inverted qubits in one column. The details of this process will be described later (see FIG. 26).
- Step S124 The logic error determination unit 150 performs logic error (X error) determination processing based on the number of inverted qubits in one row. The details of this process will be described later (see FIG. 27).
- FIG. 26 is a flow chart showing an example of the procedure of logic error (Z error) determination processing. The processing shown in FIG. 26 will be described below along with the step numbers.
- Step S132 The logic error determination unit 150 sets the number of inverted qubits N r to an initial value of "0".
- the logic error determination unit 150 counts up the variable i by 1 in order from 1, and executes the processing of steps S134 to S135 for each value of i until it reaches Ncc .
- Step S134 The logic error determination unit 150 determines whether or not the value of the state data q i indicating whether or not the i-th data quantum bit is phase-inverted is "1". If the value is "1”, logic error determination unit 150 advances the process to step S135. If the value is "0”, logic error determination unit 150 advances the process to step S136.
- Step S135 The logic error determination unit 150 adds "1" to the number of inverted qubits Nr .
- Step S136 If the value of the variable i has reached Ncc , the logic error determination unit 150 advances the process to step S137.
- Step S137 The logic error determination unit 150 determines whether the number of inversion qubits N r is an odd number. If the number is odd, logic error determination unit 150 advances the process to step S138. If the number is even, logic error determination unit 150 advances the process to step S139.
- Step S138 The logic error determination unit 150 determines that a logic error has occurred, and terminates the logic error determination process.
- the logic error determination unit 150 determines that no logic error has occurred.
- FIG. 27 is a flow chart showing an example of the procedure of logic error (X error) determination processing. The processing shown in FIG. 27 will be described below along with the step numbers.
- Step S142 The logic error determination unit 150 sets the number of inversion qubits N r to an initial value of "0".
- the logical error determination unit 150 counts up the variable i by one from 1 and executes the processing of steps S144 and S145 for each value of i until it reaches N cr .
- Step S144 The logic error determination unit 150 determines whether or not the value of the state data q i indicating whether or not the i-th data quantum bit is inverted is "1". If the value is "1”, logic error determination unit 150 advances the process to step S145. If the value is "0”, logic error determination unit 150 advances the process to step S146.
- Step S145 The logic error determination unit 150 adds "1" to the number of inverted qubits Nr .
- Step S146 If the value of the variable i has reached N cr , the logic error determination unit 150 advances the process to step S147.
- Step S147 The logic error determination unit 150 determines whether the number of inversion qubits N r is an odd number. If the number is odd, logic error determination unit 150 advances the process to step S148. If the number is even, logic error determination unit 150 advances the process to step S149.
- Step S148 The logic error determination unit 150 determines that a logic error has occurred, and terminates the logic error determination process.
- the logic error determination unit 150 determines that no logic error has occurred.
- the above processing is the logic error determination processing for the X error.
- the logic error determination unit 150 can determine whether or not there is a logic error simply by examining the values of the data qubits for one column or one row of the two-dimensional lattice. As a result, efficient logical error determination becomes possible.
- FIG. 28 is a graph showing the relationship between the number of data qubits on one side of a two-dimensional lattice and the number of searches.
- the horizontal axis is the number of data qubits N per side of the two-dimensional lattice
- the vertical axis is the number of searches. The number of searches is counted as one each time the state of one data quantum bit is confirmed.
- a polygonal line 91 in the graph 90 is a polygonal line indicating the number of times of search when logic error determination is performed by searching for an error chain as shown in FIG.
- An approximated curve 92 is an approximated curve for the polygonal line 91 when the logic error determination is performed by searching the error chain.
- a polygonal line is a polygonal line that indicates the number of times of search when logic error determination is performed based on the number of inverted qubits in one column (or one row) of the two-dimensional lattice.
- the error probability in simulated conditions is 20%.
- the number of searches increases exponentially with respect to N. is increasing.
- logical qubits are composed of qubits arranged in a two-dimensional lattice of 5 rows and 11 columns. can be determined.
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Abstract
Description
コンピュータは、複数のデータ量子ビットと複数の補助量子ビットとを行方向および列方向のそれぞれに交互に配置した2次元格子を示す量子ビット情報を生成する。コンピュータは、量子ビット情報に対して、複数のデータ量子ビットのうちの第1のデータ量子ビットにおけるエラー発生を示すエラー情報を設定する。コンピュータは、量子ビット情報に対して、第1のデータ量子ビットに行方向または列方向に隣接する補助量子ビットの状態を初期値から反転させたエラー検知情報を設定する。コンピュータは、量子ビット情報に対して、エラー検知情報に基づく表面符号によるエラー訂正の対象となる第2のデータ量子ビットを示すエラー訂正情報を設定する。そしてコンピュータは、2次元格子における一の行または一の列内の第1のデータ量子ビットと第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、論理エラーの発生の有無を判定する。
本発明の上記および他の目的、特徴および利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
〔第1の実施の形態〕
第1の実施の形態は、量子コンピュータで発生する量子ビットのエラーを表面符号によりエラー訂正処理のシミュレーションを実行した場合における論理エラーの発生の有無を効率的に判定するシミュレーション方法である。
処理部12は、2次元格子における一の行または一の列内の第1のデータ量子ビットと第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、論理エラーの発生の有無を判定する。例えば処理部12は、2次元格子における一の行または一の列内の第1のデータ量子ビットと第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビット(反転量子ビット)の数が奇数の場合に、論理エラーが発生していると判定する。なお第1のデータ量子ビットと第2のデータ量子ビットとの両方に該当するデータ量子ビットは、エラーが発生したものの正しく訂正されたデータ量子ビットであり、反転量子ビットには含まれない。
なお、所定のエラー発生率に基づいて複数のデータ量子ビットの中から無作為にエラーを発生させて第1のデータ量子ビットを決定する場合、論理エラーが発生するか否かは確率的に決まる。そこで処理部12は、エラー情報の設定、エラー検知情報の設定、エラー訂正情報の設定、論理エラーの発生の有無の判定を、所定回数繰り返して実行してもよい。この場合、処理部12は、例えば、所定回数の論理エラーの発生の有無の判定結果に基づいて、論理エラー発生確率を算出する。これによりデータ量子ビットのエラー発生率に応じた論理エラーの発生確率が得られる。
次に第2の実施の形態について説明する。第2の実施の形態は、量子コンピュータにおいてランダムに発生するエラーに対する表面符号による誤り訂正のシミュレーション(以下、表面符号シミュレーションと呼ぶ)を実行し、論理エラーの発生の有無を効率的に判定するコンピュータである。
図3は、量子ビットを説明する図である。量子ビットとは、従来のコンピュータでの情報量の最小単位「ビット」(古典ビット)に対応する量子情報の最小単位である。量子ビットは、「0」と「1」の量子力学的な重ね合わせ状態(量子状態)を取る。量子ビットの量子状態は、数学的には以下の式(1)に示すような2次元ベクトルで表され、|0>,|1>がそれぞれ古典ビットの「0」と「1」の状態に対応する。
2量子ビットの状態は1量子ビット状態のテンソル積「|a>×|b>」(テンソル積×は丸の中に×の記号)と表され、通常|ab>と書かれるこれは2×2の4次元ベクトルである。2量子ビットに作用する行列演算子としては、例えばCNOT演算子がある。
・ビット反転エラー(Xエラー):|0>→|1>、|1>→|0>
・位相反転エラー(Zエラー):|+>→|->、|->→|+>
ビット反転エラーは、数学的には量子状態にパウリ演算子Xを作用させることと同じである。同様に位相反転エラーは、量子状態にパウリ演算子Zを作用させることと同じである。
次に論理量子ビットの計算について説明する。エラー検知は計算の合間に頻繁に行われる処理である。そのため、論理量子状態は初期状態だけでなく、計算中もスタビライザ演算子の固有状態に保たれていなければならない。従って論理量子ビットに対する操作を行う場合、スタビライザ演算子の固有状態を壊すことなく論理量子状態を変化させる演算子が用いられる。それらの演算子は論理演算子と呼ばれている。
第1の性質は、論理演算子はすべてのスタビライザ演算子と交換関係を満たすことである。例えば論理Z演算子Lzに関し、スタビライザ演算子をS、論理量子状態|ψ>LをSの固有状態(S|ψ>L=|ψ>L)とする。この場合、交換関係SLz=LzSより、SLz|ψ>L=LzS|ψ>L=Lz|ψ>Lとなる。Lz|ψ>Lは元の|ψ>Lとは異なるがSの固有状態に保たれている。
図11は、論理Z演算子Lzと論理X演算子Lxの数学的表現を説明する図である。論理量子ビットを構成する格子状の量子ビットの配列における左右および上下の境界のうち、Xエラー検出用の補助量子ビットが並んでいる境界はラフ境界45,46と呼ばれる。またZエラー検出用の補助量子ビットが並んでいる境界はスムーズ境界47,48と呼ばれる。
Z演算子とZ演算子は反交換関係を満たすので、さらに以下の様に変形できる。
「-|ψ’>L」は、固有値が「-1」に変化していることを示している。この固有値の変化は、量子回路43を用いることで、補助量子ビット41dのビット反転として検知できる(|ψ>L=|0000>+|1111>で初期化)。
図16は、エラー訂正成功パターンの例を示す図である。エラー訂正成功パターン75は、エラーが発生したデータ量子ビットと訂正したデータ量子ビットとが完全に一致した場合である。またエラー訂正成功パターン76,77は、エラー未訂正のデータ量子ビットと誤って訂正したデータ量子ビットとでループが形成されていることでエラー訂正に成功した場合である。このように、表面符号でエラー訂正を成功させるには、訂正箇所と実際のエラー箇所が完全一致するか、ループが形成されていることが要件となる。
現時点では100量子ビット以上の量子コンピュータは存在しない。そのため現状では、表面符号を用いた大規模な量子エラー訂正を実機により検証することはできない。ただし、将来的な大規模量子ビットを備えた量子コンピュータの実現に向けて、量子エラー訂正の検討は現時点から進めておくことが重要である。そのため、現状では表面符号を用いた大規模な量子エラー訂正を古典コンピュータによるシミュレーションで再現し、エラー訂正の適切さを検証することが有効となる。
図19は、2次元格子1列分のデータ量子ビットの状態データに基づく論理エラー判定の一例を示す図である。図17に示したエラー発生パターン78と同様のエラーが発生した場合における3通りのエラー訂正パターンを示している。エラー訂正成功パターン81-1は、エラーが発生したデータ量子ビット81a~81cについて、完全一致でデータ訂正を行った場合の例である。エラー訂正成功パターン81-2は、エラーが発生したデータ量子ビット81a,81cとエラーが発生していないデータ量子ビット81d~81fのデータ訂正を行っているが、ループが形成されることでエラー訂正に成功した例である。エラー訂正失敗パターン81-3は、エラーが発生していないデータ量子ビット81g~81iのデータ訂正を行ったことによる論理エラーの発生例である。
1.エラー量子ビットが完全に訂正されている。
2.反転量子ビット(エラー未訂正のデータ量子ビットと誤訂正のデータ量子ビット)がループを形成している。
3.論理エラーが起きている。
図20は、縦一列の反転量子ビット数が奇数の場合に論理エラーとなることを説明する図である。図20には、2次元格子配列に論理Z演算子Lzが作用した状態83と、2次元格子配列に論理X演算子Lxが作用した状態84とが示されている。
・Lzはすべてのスタビライザ演算子と交換関係を満たす。
・LzとLxは反交換関係(LzLx=-LxLz)を満たす。
図22は、表面符号シミュレーションを実施するためのコンピュータの機能を示すブロック図である。コンピュータ100は、記憶部110、表面符号シミュレーション管理部120、エラー発生状態生成部130、エラー訂正部140、および論理エラー判定部150を有する。
図23は、表面符号シミュレーションを利用した論理エラー判定処理の手順の一例を示すフローチャートである。以下、図23に示す処理をステップ番号に沿って説明する。
図24は、シミュレーション条件の一例を示す図である。シミュレーション条件111には、例えば以下のデータが含まれる。
・データ量子ビットの状態データ:qi(i=1,・・・,Ndata)
(Ndataは、データ量子ビットの数)
・補助量子ビットの状態データ:ai(i=1,・・・,Nsub)
(Nsubは、データ量子ビットの数)
・Zエラー率データ:Rz
・Xエラー率データ:Rx
Zエラー率データは、データ量子ビットにおいてZエラーが発生する確率を示すデータである。Xエラー率データは、データ量子ビットにおいてXエラーが発生する確率を示すデータである。
図25は、表面符号シミュレーションの処理の手順の一例を示すフローチャートである。以下、図25に示す処理をステップ番号に沿って説明する。
[ステップS114]エラー発生状態生成部130は、乱数rの値が、Zエラー率を示すRzより小さいか否かを判断する。エラー発生状態生成部130は、乱数rの値がRzより小さければ処理をステップS115に進める。またエラー発生状態生成部130は、乱数rの値がRz以上であれば処理をステップS116に進める。
[ステップS117]エラー発生状態生成部130は、変数iを1から順に1ずつカウントアップしてNdataに達するまでのiの値ごとに、ステップS118~S121の処理を実行する。
[ステップS119]エラー発生状態生成部130は、乱数rの値が、Xエラー率を示すRxより小さいか否かを判断する。エラー発生状態生成部130は、乱数rの値がRxより小さければ処理をステップS120に進める。またエラー発生状態生成部130は、乱数rの値がRx以上であれば処理をステップS121に進める。
[ステップS122]エラー訂正部140は、補助量子ビットの状態データに基づいてデータ量子ビットのエラー訂正処理を行う。例えばエラー訂正部140は、値が反転したデータ量子ビットに基づいて、図14に示したようにZエラーまたはXエラーが発生したデータ量子ビットを特定する。そしてエラー訂正部140は、エラーが発生したと推定されたデータ量子ビットに対して、発生したエラーに応じたエラー訂正処理を行う。例えばエラー訂正部140は、Zエラーが発生したと推定したデータ量子ビットの位相を反転させ、Xエラーが発生したと推定したデータ量子ビットのビットを反転させる。
[ステップS124]論理エラー判定部150は、1行の反転量子ビット数による論理エラー(Xエラー)判定処理を行う。この処理の詳細は後述する(図27参照)。
[ステップS131]論理エラー判定部150は、2次元格子1列(調査対象列)分のデータ量子ビットの状態データqi(i=1,・・・,Ncc)を用意する。Nccは、2次元格子1列分のデータ量子ビットの数である。
[ステップS133]論理エラー判定部150は、変数iを1から順に1ずつカウントアップしてNccに達するまでのiの値ごとに、ステップS134~S135の処理を実行する。
[ステップS136]論理エラー判定部150は、変数iの値がNccに達していれば処理をステップS137に進める。
[ステップS139]論理エラー判定部150は、論理エラーが発生していないと判定する。
図27は、論理エラー(Xエラー)判定処理の手順の一例を示すフローチャートである。以下、図27に示す処理をステップ番号に沿って説明する。
[ステップS143]論理エラー判定部150は、変数iを1から順に1ずつカウントアップしてNcrに達するまでのiの値ごとに、ステップS144~S145の処理を実行する。
[ステップS146]論理エラー判定部150は、変数iの値がNcrに達していれば処理をステップS147に進める。
[ステップS149]論理エラー判定部150は、論理エラーが発生していないと判定する。
このように論理エラー判定部150は、2次元格子の1列または1行分のデータ量子ビットの値を調査するだけで論理エラーの有無を判定することができる。その結果、効率的な論理エラー判定が可能となる。
第2の実施の形態では、5行11列の2次元格子状に配置された量子ビットにより論理量子ビットが構成されているが、行数または列数が変わっても、同様の処理で論理エラーを判定可能である。
10 情報処理装置
11 記憶部
12 処理部
Claims (8)
- 複数のデータ量子ビットと複数の補助量子ビットとを行方向および列方向のそれぞれに交互に配置した2次元格子を示す量子ビット情報を生成し、
前記量子ビット情報に対して、前記複数のデータ量子ビットのうちの第1のデータ量子ビットにおけるエラー発生を示すエラー情報を設定し、
前記量子ビット情報に対して、前記第1のデータ量子ビットに行方向または列方向に隣接する補助量子ビットの状態を初期値から反転させたエラー検知情報を設定し、
前記量子ビット情報に対して、前記エラー検知情報に基づく表面符号によるエラー訂正の対象となる第2のデータ量子ビットを示すエラー訂正情報を設定し、
前記2次元格子における一の行または一の列内の前記第1のデータ量子ビットと前記第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、論理エラーの発生の有無を判定する、
処理をコンピュータに実行させるシミュレーションプログラム。 - 前記論理エラーの発生の有無の判定では、前記2次元格子における一の行または一の列内の前記第1のデータ量子ビットと前記第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数が奇数の場合に、前記論理エラーが発生していると判定する、
請求項1記載のシミュレーションプログラム。 - 前記量子ビット情報の生成では、位相反転エラー検知用の補助量子ビットが配置される列とビット反転エラー検知用の補助量子ビットが配置される列とが交互に設けられた前記2次元格子を示す前記量子ビット情報を生成し、
前記論理エラーの発生の有無の判定では、前記2次元格子の4辺の境界のうち、前記ビット反転エラー検知用の補助量子ビットが配置された境界と平行な方向の一の行または一の列内の前記第1のデータ量子ビットと前記第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、位相反転エラーに起因する前記論理エラーの発生の有無を判定する、
請求項1または2に記載のシミュレーションプログラム。 - 前記量子ビット情報の生成では、位相反転エラー検知用の補助量子ビットが配置される列とビット反転エラー検知用の補助量子ビットが配置される列とが交互に設けられた前記2次元格子を示す前記量子ビット情報を生成し、
前記論理エラーの発生の有無の判定では、前記2次元格子の4辺の境界のうち、前記位相反転エラー検知用の補助量子ビットが配置された境界と平行な方向の一の行または一の列内の前記第1のデータ量子ビットと前記第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、ビット反転エラーに起因する前記論理エラーの発生の有無を判定する、
請求項1から3までのいずれかに記載のシミュレーションプログラム。 - 前記エラー情報の設定では、所定のエラー発生率に基づいて前記複数のデータ量子ビットの中から無作為に、エラーを発生させる前記第1のデータ量子ビットを決定し、
前記エラー情報の設定、前記エラー検知情報の設定、前記エラー訂正情報の設定、前記論理エラーの発生の有無の判定を、所定回数繰り返し実行する、
請求項1から4までのいずれかに記載のシミュレーションプログラム。 - 前記コンピュータに、
前記所定回数の前記論理エラーの発生の有無の判定結果に基づいて、論理エラー発生確率を算出する、
処理を実行させる請求項5記載のシミュレーションプログラム。 - 複数のデータ量子ビットと複数の補助量子ビットとを行方向および列方向のそれぞれに交互に配置した2次元格子を示す量子ビット情報を生成し、
前記量子ビット情報に対して、前記複数のデータ量子ビットのうちの第1のデータ量子ビットにおけるエラー発生を示すエラー情報を設定し、
前記量子ビット情報に対して、前記第1のデータ量子ビットに行方向または列方向に隣接する補助量子ビットの状態を初期値から反転させたエラー検知情報を設定し、
前記量子ビット情報に対して、前記エラー検知情報に基づく表面符号によるエラー訂正の対象となる第2のデータ量子ビットを示すエラー訂正情報を設定し、
前記2次元格子における一の行または一の列内の前記第1のデータ量子ビットと前記第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、論理エラーの発生の有無を判定する、
処理をコンピュータが実行するシミュレーション方法。 - 複数のデータ量子ビットと複数の補助量子ビットとを行方向および列方向のそれぞれに交互に配置した2次元格子を示す量子ビット情報を生成し、前記量子ビット情報に対して、前記複数のデータ量子ビットのうちの第1のデータ量子ビットにおけるエラー発生を示すエラー情報を設定し、前記量子ビット情報に対して、前記第1のデータ量子ビットに行方向または列方向に隣接する補助量子ビットの状態を初期値から反転させたエラー検知情報を設定し、前記量子ビット情報に対して、前記エラー検知情報に基づく表面符号によるエラー訂正の対象となる第2のデータ量子ビットを示すエラー訂正情報を設定し、前記2次元格子における一の行または一の列内の前記第1のデータ量子ビットと前記第2のデータ量子ビットとのいずれか一方に該当するデータ量子ビットの数に基づいて、論理エラーの発生の有無を判定する処理部、
を有する情報処理装置。
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