WO2023084950A1 - 表示装置、表示システム、および表示駆動方法 - Google Patents

表示装置、表示システム、および表示駆動方法 Download PDF

Info

Publication number
WO2023084950A1
WO2023084950A1 PCT/JP2022/037179 JP2022037179W WO2023084950A1 WO 2023084950 A1 WO2023084950 A1 WO 2023084950A1 JP 2022037179 W JP2022037179 W JP 2022037179W WO 2023084950 A1 WO2023084950 A1 WO 2023084950A1
Authority
WO
WIPO (PCT)
Prior art keywords
image
image data
pixel values
pixel
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/037179
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
航太 間瀬
隆行 神田
太郎 市坪
淳仁 森脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to JP2023559474A priority Critical patent/JPWO2023084950A1/ja
Priority to CN202280073249.8A priority patent/CN118215954A/zh
Priority to US18/707,485 priority patent/US12475819B2/en
Priority to EP22892450.2A priority patent/EP4432271A4/en
Publication of WO2023084950A1 publication Critical patent/WO2023084950A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/66—Transforming electric information into light information
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/011—Arrangements for interaction with the human body, e.g. for user immersion in virtual reality
    • G06F3/013—Eye tracking input arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/167—Position within a video image, e.g. region of interest [ROI]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0686—Adjustment of display parameters with two or more screen areas displaying information with different brightness or colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0414—Vertical resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0421—Horizontal resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/30—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
    • H04N19/33—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the spatial domain

Definitions

  • the present disclosure relates to a display device, a display system, and a display driving method for displaying images.
  • Some display devices for example, generate a frame image based on a low-resolution whole image and a high-resolution partial image, and display the generated frame image (for example, Patent Document 1).
  • display devices are desired to have low power consumption, and further reduction in power consumption is expected.
  • a display device includes a receiving circuit, a display section, and a display driving circuit.
  • the receiving circuit receives first image data having one or more pixel values included in a first resolution whole image, a second resolution higher than the first resolution portion of an image range narrower than the whole image. Second image data having one or more pixel values included in the image and third image data having one or more pixel values included in the entire image can be received in this order.
  • the display has a first plurality of pixels, a second plurality of pixels, and a third plurality of pixels.
  • the display driving circuit performs first driving for driving a first plurality of pixels in units of a first number of pixels based on first image data, and performs second driving based on second image data.
  • a display system includes an image generation device and a display device.
  • the image generation device generates first image data having one or more pixel values included in an entire image of a first resolution, an image range narrower than the entire image, and of a second resolution higher than the first resolution.
  • Second image data having one or more pixel values included in the partial image and third image data having one or more pixel values included in the entire image can be transmitted in this order.
  • a display device includes a receiving circuit, a display section, and a display driving circuit.
  • the receiving circuit can receive the first image data, the second image data, and the third image data in this order.
  • the display has a first plurality of pixels, a second plurality of pixels, and a third plurality of pixels.
  • the display driving circuit performs first driving for driving a first plurality of pixels in units of a first number of pixels based on first image data, and performs second driving based on second image data. a second driving of driving the plurality of pixels in units of a second number of pixels smaller than the first number; and driving the third plurality of pixels to the first number based on third image data It is also possible to perform the third driving in which the pixels are driven as a unit.
  • a display driving method includes: first image data having one or more pixel values included in an entire image of a first resolution; Second image data having one or more pixel values included in the partial image with a second resolution higher than the second image data and third image data having one or more pixel values included in the entire image are received in this order. performing a first drive for driving the first plurality of pixels in units of a first number of pixels based on the first image data; and based on the second image data, performing second driving of driving the second plurality of pixels in units of a second number of pixels smaller than the first number; and driving the third plurality of pixels based on third image data; , and a third drive that drives the first number of pixels as a unit.
  • the first image data, the second image data, and the third image data are received in this order.
  • the first image data has one or more pixel values included in the first resolution overall image.
  • the second image data has one or more pixel values included in a partial image having a second resolution higher than the first resolution and having an image range narrower than the entire image.
  • the third image data has one or more pixel values included in the whole image.
  • the first driving the first plurality of pixels are driven in units of the first number of pixels based on the first image data.
  • the second driving the second plurality of pixels are driven in units of a second number of pixels smaller than the first number based on the second image data.
  • the third plurality of pixels are driven in units of the first number of pixels based on the third image data.
  • FIG. 1 is a block diagram showing a configuration example of a display system according to a first embodiment of the present disclosure
  • FIG. 2 is an explanatory diagram showing an example of an image generated by the image generation circuit shown in FIG. 1
  • FIG. 2 is an explanatory diagram showing an operation example of the display system shown in FIG. 1
  • FIG. FIG. 2 is an explanatory diagram showing a transmission band of the display system shown in FIG. 1
  • 2 is a block diagram showing one configuration example of a display panel shown in FIG. 1
  • FIG. 2 is a timing diagram showing an example of input signals of the display controller shown in FIG. 1
  • FIG. 2 is another timing diagram representing an example of input signals of the display controller shown in FIG. 1
  • FIG. 2 is a timing diagram showing an example of output signals of the display controller shown in FIG. 1;
  • FIG. 2 is another timing diagram showing an example of output signals of the display controller shown in FIG. 1;
  • FIG. It is explanatory drawing showing an example of a pixel drive operation.
  • FIG. 11 is an explanatory diagram showing another example of pixel driving operation;
  • 2 is an explanatory diagram showing an example of pixel driving operation in the head mounted display shown in FIG. 1;
  • FIG. 2 is a timing chart showing an example of display operation in the display system shown in FIG. 1;
  • FIG. 3 is a timing chart showing another example of display operation in the display system shown in FIG. 1;
  • FIG. 2 is an explanatory diagram showing an operation example of the display system shown in FIG. 1;
  • FIG. 11 is explanatory drawing showing an example of a pixel drive operation.
  • FIG. 11 is an explanatory diagram showing another example of pixel driving operation
  • 2 is an explanatory diagram showing an example of pixel driving operation in the
  • FIG. 3 is an explanatory diagram showing another example of operation of the display system shown in FIG. 1;
  • FIG. 3 is an explanatory diagram showing another example of operation of the display system shown in FIG. 1;
  • FIG. 3 is an explanatory diagram showing another example of operation of the display system shown in FIG. 1;
  • FIG. 12 is an explanatory diagram showing an operation example of the display system according to the modified example of the first embodiment;
  • FIG. 11 is a block diagram showing a configuration example of a display system according to another modification of the first embodiment;
  • FIG. 21 is an explanatory diagram showing an example of image data included in an image signal in the display system shown in FIG. 20;
  • FIG. 21 is an explanatory diagram showing another example of image data included in an image signal in the display system shown in FIG. 20;
  • FIG. 21 is an explanatory diagram showing another example of image data included in an image signal in the display system shown in FIG. 20;
  • FIG. 21 is an explanatory diagram showing another example of image data included in an image signal in the display system shown in FIG. 20;
  • FIG. FIG. 11 is a table showing an operation example of the display system according to another modification of the first embodiment;
  • FIG. 9 is another table showing an operation example of the display system according to another modification of the first embodiment;
  • 9 is another table showing an operation example of the display system according to another modification of the first embodiment;
  • FIG. 10 is an explanatory diagram showing an operation example of the display system according to another modification of the first embodiment;
  • FIG. 10 is an explanatory diagram showing an operation example of the display system according to another modification of the first embodiment;
  • FIG. 10 is an explanatory diagram showing an operation example of the display system according to another modification of the first embodiment;
  • FIG. 10 is an explanatory diagram showing an operation example of the display system according to another modification of the first embodiment;
  • FIG. 11 is an explanatory diagram showing another example of image data included in an image signal in the display system shown in FIG. 20;
  • FIG. 10 is an explanatory diagram showing an operation example of the display system according to another modification of the first embodiment
  • FIG. 10 is an explanatory diagram showing an example of an image generated by an image generation circuit according to another modification of the first embodiment
  • FIG. 10 is an explanatory diagram showing an operation example of the display system according to another modification of the first embodiment
  • FIG. 11 is an explanatory diagram showing transmission bands of a display system according to another modification of the first embodiment
  • FIG. 11 is a timing chart showing an example of output signals of a display controller according to another modification of the first embodiment
  • FIG. 10 is another timing chart showing an example of output signals of the display controller according to another modification of the first embodiment
  • FIG. 11 is an explanatory diagram showing an example of pixel driving operation according to another modification of the first embodiment
  • FIG. 10 is an explanatory diagram showing another example of pixel driving operation according to another modification of the first embodiment
  • FIG. 11 is a block diagram showing a configuration example of a display system according to a second embodiment
  • FIG. FIG. 37 is an explanatory diagram showing an operation example of the display system shown in FIG. 36
  • FIG. 37 is an explanatory diagram showing transmission bands of the display system shown in FIG. 36
  • 37 is a timing chart showing an example of input signals of the display controller shown in FIG. 36
  • FIG. 37 is another timing chart showing an example of input signals of the display controller shown in FIG. 36
  • FIG. 37 is a timing chart showing an example of output signals of the display controller shown in FIG. 36
  • FIG. 37 is another timing chart showing an example of output signals of the display controller shown in FIG. 36
  • FIG. FIG. FIG. 37 is another timing chart showing an example of output signals of the display controller shown in FIG. 36
  • FIG. FIG. FIG. 37 is another timing chart showing an example of output signals of the display controller shown in FIG. 36;
  • FIG. 37 is an explanatory diagram showing an example of pixel driving operation in the head mounted display shown in FIG. 36;
  • FIG. 11 is an explanatory diagram showing an operation example of a display system according to a modification of the second embodiment;
  • FIG. 11 is an explanatory diagram showing a transmission band of a display system according to a modification of the second embodiment;
  • FIG. FIG. 11 is a timing chart showing an example of output signals of a display controller according to a modification of the second embodiment;
  • FIG. FIG. 11 is another timing chart showing an example of output signals of the display controller according to the modification of the second embodiment;
  • FIG. 11 is an explanatory diagram showing an example of pixel driving operation according to a modification of the second embodiment;
  • FIG. 11 is an explanatory diagram showing another example of the pixel driving operation according to the modification of the second embodiment;
  • FIG. 11 is a perspective view showing an external configuration of a head mounted display according to an application example;
  • FIG. 11 is a perspective view showing an external configuration of another head mounted display according to an application example;
  • FIG. 11 is a front view showing the external configuration of a digital still camera according to another application example;
  • FIG. 11 is a rear view showing the external configuration of a digital still camera according to another application example;
  • FIG. 11 is a rear view showing an external configuration of a television device according to another application example;
  • FIG. 11 is a rear view showing the external configuration of a smartphone according to another application example;
  • FIG. 11 is an explanatory diagram showing a configuration example of a vehicle according to another application example;
  • FIG. 11 is a perspective view showing an external configuration of a head mounted display according to an application example;
  • FIG. 11 is a perspective view showing an external configuration of another head mounted display according to an application
  • FIG. 11 is another explanatory diagram showing a configuration example of a vehicle according to another application example;
  • FIG. 11 is a block diagram showing a configuration example of a display panel according to another modified example;
  • 57 is a circuit diagram showing a configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 57 is a circuit diagram showing another configuration example of the pixel shown in FIG. 56;
  • FIG. 1 shows a configuration example of a display system (display system 1) according to an embodiment. Note that the display device and the display driving method according to the embodiment of the present disclosure are embodied by the present embodiment, so they will be described together.
  • the display system 1 includes an image generation device 10 and a head mounted display 20.
  • the display system 1 is used for augmented reality (AR) and virtual reality (VR).
  • AR augmented reality
  • VR virtual reality
  • the display system 1 is configured to perform foveated rendering, in which the focused area is drawn with high resolution and the other areas are drawn with low resolution.
  • the display system 1 communicates between the image generation device 10 and the head mounted display 20 using HDMI (registered trademark) (High-Definition Multimedia Interface) or MIPI (registered trademark) (Mobile Industry Processor Interface). This is done using an interface such as In this example, this communication is performed by wire communication, but it is not limited to this, and may be performed by wireless communication.
  • the head mounted display 20 displays an image based on the image signal SP transmitted from the image generating device 10.
  • An acceleration sensor 22 (described later) of the head-mounted display 20 detects movements such as orientation of the head-mounted display 20 .
  • the eye tracking sensor 23 of the head mounted display 20 detects which part of the displayed image the user is looking at by detecting the orientation of the eyes of the user wearing the head mounted display 20. .
  • the head-mounted display 20 supplies a detection signal SD containing these detection results to the image generation device 10 .
  • the image generation device 10 generates an image (whole image P1) according to the direction of the head mounted display 20 based on the detection result of the acceleration sensor 22.
  • the image generation device 10 identifies an image (partial image P2) including the portion viewed by the user in the entire image P1 based on the detection result of the eye tracking sensor 23 . Then, the image generation device 10 generates an image signal SP including low-resolution image data representing the entire image P1 and high-resolution image data representing the partial image P2, and transmits the generated image signal SP to the head mounted display 20. It is designed to send.
  • Image generation device 10 is configured to generate an image to be displayed on head-mounted display 20 .
  • the image generation device 10 has an image generation circuit 11 , a transmission circuit 12 and a reception circuit 13 .
  • the image generation circuit 11 is configured to generate an image to be displayed on the head mounted display 20 by performing predetermined processing such as rendering processing.
  • the image generation circuit 11 has a transmission signal generation circuit 18 .
  • the transmission signal generation circuit 18 is configured to generate an image signal SP to be transmitted based on the image generated by the image generation circuit 11 .
  • the image generating circuit 11 generates an entire image P1 showing the scenery in the virtual space according to the direction of the head mounted display 20 based on the detection result of the acceleration sensor 22 included in the data supplied from the receiving circuit 13. .
  • the image generation circuit 11 selects, based on the detection result of the eye tracking sensor 23 included in the data supplied from the reception circuit 13, the user's specifies a partial image P2 indicating the portion viewed by .
  • FIG. 2 shows an example of an image generated by the image generation circuit 11.
  • the squares correspond to multiple pixels in the head mounted display 20 .
  • 32 pixels are arranged horizontally and 32 pixels are arranged vertically.
  • the whole image P1 includes an image of the person 9.
  • FIG. The image generating circuit 11 identifies a partial image P2 including the portion viewed by the user in the entire image P1 based on the detection result of the eye tracking sensor 23 included in the data supplied from the receiving circuit 13. .
  • the partial image P2 includes an image of this person 9's face.
  • the size of the partial image P2 in the horizontal direction (the horizontal direction in FIG.
  • the transmission signal generation circuit 18 generates an image signal SP to be transmitted based on such an image generated by the image generation circuit 11 .
  • FIG. 3 shows an operation example of the display system 1, where (A) shows an image generated by the image generation circuit 11, (B) shows image data included in the image signal SP, and (C). indicates the display driving operation in the head mounted display 20.
  • the transmission signal generation circuit 18 sequentially scans the entire image P1 generated by the image generation circuit 11 from left to right and from top to bottom. Thus, an image signal SP is generated.
  • the transmission signal generation circuit 18 converts the four pixel values arranged in two rows and two columns into one pixel value for the entire image P1, and converts the portion of the entire image P1 that overlaps the partial image P2 to , to generate image data in the image signal SP by outputting one pixel value as it is.
  • the transmission signal generation circuit 18 generates four pixels arranged in two rows and two columns based on 64 pixel values included in the first and second rows of the entire image P1. 16 pixel values for the whole image P1 are generated by converting the values into one pixel value. Thereby, the transmission signal generation circuit 18 generates the image data of the first row in the image signal SP.
  • the transmission signal generation circuit 18 converts four pixel values arranged in two rows and two columns into one pixel value based on the 64 pixel values included in the third and fourth rows of the entire image P1. Thus, 16 pixel values for the entire image P1 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the second row in the image signal SP.
  • the transmission signal generation circuit 18 converts four pixel values arranged in two rows and two columns into one pixel value based on the 64 pixel values included in the fifth and sixth rows of the entire image P1. Thus, 16 pixel values for the entire image P1 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the third row in the image signal SP.
  • the transmission signal generation circuit 18 directly outputs 16 pixel values related to the partial image P2 among the 32 pixel values included in the 5th row of the full image P1, and outputs the 16 pixel values included in the 6th row of the full image P1. Of the 32 pixel values, 16 pixel values related to the partial image P2 are output as they are. Thereby, the transmission signal generation circuit 18 generates the image data of the 4th and 5th rows in the image signal SP.
  • the transmission signal generation circuit 18 converts the four pixel values arranged in two rows and two columns into one pixel value for the entire image P1, and also converts the partial image P2 of the entire image P1 into one pixel value.
  • the resolution of partial image P2 does not change.
  • the resolution of the converted whole image P1 is lower than the resolution of the partial image P2.
  • the transmission signal generating circuit 18 converts four pixel values arranged in two rows and two columns for the entire image P1 into one pixel value. Contains images corresponding to .
  • the transmission signal generation circuit 18 generates the image signal SP by sequentially performing processing from top to bottom. A portion in which the pixel values of one line image and the pixel values of two line images included in the partial image P2 are alternately arranged in the vertical direction is generated.
  • the transmission signal generation circuit 18 generates image data including a plurality of pixel values as shown in FIG. 3(B) based on the image generated by the image generation circuit 11. Then, the transmission signal generation circuit 18 generates an image signal SP including this image data and image position data indicating the position (parameters POSX, POSY) of the partial image P2 in the entire image P1.
  • the transmission circuit 12 ( FIG. 1 ) is configured to transmit the image signal SP supplied from the image generation circuit 11 to the head mounted display 20 .
  • the transmission circuit 12 can transmit the image position data using the data format of the image data, for example, in the blanking period during which the image data is not transmitted in the vertical period V.
  • the transmission circuit 12 may transmit the image position data as the control data, for example, during the blanking period.
  • the transmission circuit 12 may transmit the image position data using a general-purpose interface such as I2C or SPI (Serial Peripheral Interface), which is different from the interface for transmitting the image data.
  • FIG. 4 shows the transmission band in the display system 1.
  • the non-shaded portion indicates the image data for the entire image P1, and the shaded portion indicates the image data for the partial image P2.
  • the image data included in the image signal SP includes 32 rows of image data in this example.
  • the data number NSP is attached to the image data for 32 lines.
  • the image data of each row is image data relating to the entire image P1 or image data relating to the partial image P2.
  • the data number N1 is given to the image data for 16 lines related to the whole image P1
  • the data number N2 is given to the image data for 16 lines related to the partial image P2.
  • the number of pixel values in the image data included in the image signal SP is half the number of pixel values included in the entire image P1. In this way, the display system 1 can halve the amount of image data compared to the case where the whole image P1 before conversion is transmitted as it is.
  • the receiving circuit 13 ( FIG. 1 ) is configured to receive the detection signal SD transmitted from the head mounted display 20 .
  • the receiving circuit 13 supplies the image generating circuit 11 with the data on the detection result of the acceleration sensor 22 and the detection result of the eye tracking sensor 23 included in the detection signal SD.
  • the head mounted display 20 has a receiving circuit 21 , an acceleration sensor 22 , an eye tracking sensor 23 , a processor 24 , a transmitting circuit 25 , a display controller 26 and a display panel 27 .
  • the receiving circuit 21 is configured to receive the image signal SP transmitted from the image generating device 10 .
  • the receiving circuit 21 supplies the image data and image position data included in the image signal SP to the processor 24 .
  • the acceleration sensor 22 is configured to detect movements such as the orientation of the head mounted display 20 .
  • a 6-axis inertial sensor for example, can be used as the acceleration sensor 22 .
  • the display system 1 can generate the entire image P1 according to the orientation of the head mounted display 20 in the virtual space.
  • the eye tracking sensor 23 is configured to detect the orientation of the eyes of the user wearing the head mounted display 20 . Thereby, in the display system 1, it is possible to detect which part of the display image the user is looking at, and to specify the partial image P2 including the part that the user is looking at in the whole image P1. It is possible.
  • the processor 24 is configured to control the operation of the head mounted display 20, and includes, for example, a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). Specifically, the processor 24, for example, performs predetermined image processing based on the image data supplied from the receiving circuit 21, and supplies the image data subjected to the image processing to the display controller 26 together with the image position data. do. The processor 24 also supplies the detection result of the acceleration sensor 22 and the detection result of the eye tracking sensor 23 to the transmission circuit 25 and causes the transmission circuit 25 to transmit these detection results.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the transmission circuit 25 is configured to transmit the detection signal SD including the detection result of the acceleration sensor 22 supplied from the processor 24 and the detection result of the eye tracking sensor 23 to the image generation device 10 .
  • the display controller 26 is configured to control the operation of the display panel 27 based on the image data and image position data supplied from the processor 24 .
  • the display panel 27 is configured to display an image based on control by the display controller 26 .
  • the display panel 27 is an organic EL (Electro Luminescence) display panel in this example. Note that the display panel 27 is not limited to this, and may be, for example, a liquid crystal display panel.
  • FIG. 5 shows a configuration example of the display panel 27.
  • the display panel 27 has a pixel array 31 , a pixel signal generation circuit 32 and a scanning circuit 33 .
  • the pixel array 31 has multiple signal lines SGL, multiple control lines CTL, and multiple pixels PIX.
  • the plurality of signal lines SGL extends in the vertical direction (vertical direction in FIG. 5) and is arranged in parallel in the horizontal direction (horizontal direction in FIG. 5).
  • Each of the plurality of signal lines SGL supplies pixel signals generated by the pixel signal generating circuit 32 to the pixels PIX.
  • the plurality of control lines CTL extend in the horizontal direction (horizontal direction in FIG. 5) and are arranged in parallel in the vertical direction (vertical direction in FIG. 5). Each of the plurality of control lines CTL supplies control signals generated by the scanning circuit 33 to the pixels PIX.
  • a plurality of pixels PIX are arranged in a matrix in the pixel array 31 .
  • Each of the plurality of pixels PIX is controlled based on the control signal supplied via the control line CTL, and the pixel signal supplied via the pixel signal line SGL is written. Thereby, each of the plurality of pixels PIX is configured to emit light with luminance according to the written pixel signal.
  • a row of pixels PIX arranged in the horizontal direction forms a pixel line L. As shown in FIG.
  • the pixel signal generation circuit 32 is configured to generate pixel signals based on image data to be displayed and apply the generated pixel signals to each of the plurality of signal lines SGL.
  • the scanning circuit 33 generates a control signal and applies the generated control signal to each of the plurality of control lines CTL, thereby scanning the plurality of pixels PIX with one or a plurality of pixel lines L as scanning units. It's becoming
  • the receiving circuit 21 corresponds to a specific example of "receiving circuit” in the present disclosure.
  • the converted whole image P1 corresponds to a specific example of the “whole image” in the present disclosure.
  • the partial image P2 corresponds to a specific example of "partial image” in the present disclosure.
  • the pixel array 31 corresponds to a specific example of the "display section” in the present disclosure.
  • the display controller 26, the pixel signal generation circuit 32, and the scanning circuit 33 correspond to a specific example of "display driving circuit” in the present disclosure.
  • the eye tracking sensor 23 corresponds to a specific example of "sensor” in the present disclosure.
  • the transmission circuit 25 corresponds to a specific example of "transmission circuit” in the present disclosure.
  • the receiving circuit 13 of the image generation device 10 receives the detection signal SD transmitted from the head-mounted display 20, and the detection result of the acceleration sensor 22 and the detection result of the eye tracking sensor 23 included in this detection signal SD. Data is supplied to the image generation circuit 11 .
  • the image generating circuit 11 generates an entire image P1 showing the scenery in the virtual space according to the direction of the head mounted display 20 based on the detection result of the acceleration sensor 22 included in the data supplied from the receiving circuit 13. .
  • the image generating circuit 11 generates a partial image P2 including the portion viewed by the user from the entire image P1 based on the detection result of the eye tracking sensor 23 included in the data supplied from the receiving circuit 13. Identify.
  • the transmission signal generation circuit 18 generates an image signal SP to be transmitted based on the image generated by the image generation circuit 11 .
  • the image signal SP includes image data and image position data indicating the position of the partial image P2 in the entire image P1.
  • the transmission circuit 12 transmits this image signal SP to the head mounted display 20 .
  • the receiving circuit 21 of the head mounted display 20 receives the image signal SP transmitted from the image generating device 10 and supplies the image data and image position data included in this image signal SP to the processor 24 .
  • the processor 24 performs predetermined image processing based on the image data supplied from the receiving circuit 21 and supplies the image data subjected to the image processing to the display controller 26 together with the image position data.
  • Display controller 26 controls the operation of display panel 27 based on the image data and image position data supplied from processor 24 .
  • the display panel 27 displays images under the control of the display controller 26 .
  • the acceleration sensor 22 detects movements such as the orientation of the head mounted display 20 .
  • the eye tracking sensor 23 detects the orientation of the eyes of the user wearing the head mounted display 20 .
  • the processor 24 supplies the detection result of the acceleration sensor 22 and the detection result of the eye tracking sensor 23 to the transmission circuit 25 .
  • the transmission circuit 25 transmits a detection signal SD including the detection result of the acceleration sensor 22 and the detection result of the eye tracking sensor 23 supplied from the processor 24 to the image generation device 10 .
  • the image generation circuit 11 presents the scenery in the virtual space according to the direction of the head mounted display 20 based on the detection result of the acceleration sensor 22 included in the data supplied from the reception circuit 13. A full image P1 is generated. Further, the image generating circuit 11 generates a partial image P2 including the portion viewed by the user from the entire image P1 based on the detection result of the eye tracking sensor 23 included in the data supplied from the receiving circuit 13. Identify.
  • the transmission signal generation circuit 18 generates an image signal SP to be transmitted based on the image generated by the image generation circuit 11 . Specifically, the transmission signal generation circuit 18 converts four pixel values arranged in two rows and two columns into one pixel value for the entire image P1. Further, the transmission signal generation circuit 18 outputs the pixel values as they are for the portion of the entire image P1 that overlaps the partial image P2. In this manner, the transmission signal generation circuit 18 generates image data including a plurality of pixel values as shown in FIG. 3B based on the image generated by the image generation circuit 11. FIG. Then, the transmission signal generation circuit 18 generates an image signal SP including this image data and image position data indicating the position (parameters POSX, POSY) of the partial image P2 in the entire image P1.
  • the transmission circuit 12 then transmits the image signal SP supplied from the image generation circuit 11 to the head mounted display 20 .
  • the receiving circuit 21 receives the image signal SP transmitted from the image generating device 10 and supplies the image data and image position data included in this image signal SP to the processor 24 .
  • the processor 24 performs predetermined image processing based on the image data supplied from the receiving circuit 21 and supplies the image data subjected to the image processing to the display controller 26 together with the image position data.
  • FIG. 6 shows an example of signals input to the display controller 26.
  • A shows the waveform of the vertical synchronization signal VS_IN
  • B shows the waveform of the horizontal synchronization signal HS_IN
  • C shows the waveform of the horizontal synchronization signal HS_IN.
  • the waveform of the vertical data enable signal VDE_IN is shown
  • D shows the data signal DATA_IN.
  • the non-shaded portion indicates the image data for the entire image P1
  • the shaded portion indicates the image data for the partial image P2.
  • a pulse occurs in the vertical synchronization signal VS_IN, and the vertical period V starts (FIG. 6(A)). Further, a pulse is generated in the horizontal synchronization signal HS_IN each time the horizontal period H starts ((B) in FIG. 6).
  • the vertical data enable signal VDE_IN changes from low level to high level (FIG. 6(C)).
  • the data signal DATA_IN in the period when the vertical data enable signal VDE_IN is at high level indicates image data ((D) in FIG. 6).
  • the data signal DATA_IN is supplied over 32 horizontal periods H.
  • FIG. 6 also shows data numbers N1 and N2 in addition to the data number NSP.
  • FIG. 7 shows an example of the data signal DATA_IN.
  • the second row of image data included in the image signal SP corresponds to the second image data among the 32 pieces of image data included in the data signal DATA_IN.
  • This image data includes 16 pixel values for the entire image P1.
  • the image data in the fourth row included in the image signal SP corresponds to the fourth image data among the 32 pieces of image data included in the data signal DATA_IN.
  • This image data includes 16 pixel values for the partial image P2.
  • the vertical data enable signal VDE_IN changes from high level to low level (FIG. 6(C)). Then, at timing t4, this vertical period V ends and the next vertical period V starts.
  • the display controller 26 performs predetermined processing based on such image data supplied from the processor 24 to generate a vertical synchronizing signal VS_OUT, a horizontal synchronizing signal HS_OUT, a vertical data enable signal VDE_OUT, and a data signal DATA_OUT. do.
  • FIG. 8 shows an example of signals output from the display controller 26, (A) shows the waveform of the vertical synchronization signal VS_OUT, (B) shows the waveform of the horizontal synchronization signal HS_OUT, and (C) shows the waveform of the horizontal synchronization signal HS_OUT.
  • the waveform of the vertical data enable signal VDE_OUT is shown, and (D) shows the data signal DATA_OUT.
  • the non-shaded portion indicates the image data for the entire image P1
  • the shaded portion indicates the image data for the partial image P2.
  • a pulse occurs in the vertical synchronization signal VS_OUT, and the vertical period V starts ((A) in FIG. 8). Further, a pulse is generated in the horizontal synchronization signal HS_OUT each time the horizontal period H starts ((B) in FIG. 8).
  • the vertical data enable signal VDE_OUT changes from low level to high level (FIG. 8(C)).
  • the display controller 26 outputs 32 pieces of image data as the data signal DATA_OUT over 32 horizontal periods H (FIG. 8(D)). These 32 pieces of image data respectively correspond to the 32 pieces of image data in the data signal DATA_IN ((D) in FIG. 6). In other words, the 32 pieces of image data correspond to the 32 rows of image data included in the image signal SP shown in FIGS.
  • the display controller 26 drives a plurality of pixels PIX in the display panel 27 in units of four pixels PIX arranged in two rows and two columns, based on image data relating to the entire image P1 included in the data signal DATA_OUT. to control. Further, the display controller 26 controls the plurality of pixels PIX in the display panel 27 to be driven in units of one pixel PIX based on the data relating to the partial image P2 included in the data signal DATA_OUT.
  • FIG. 9 shows an example of the data signal DATA_OUT at timings t13 to t17 in FIG. 8 and the display driving operation based on the data signal DATA_OUT.
  • 10 and 11 show an example of the operation of the display panel 27.
  • the display panel 27 performs the display driving operation for the two pixel lines L indicated by the symbol W1 in FIG. 9 during the period from timing t13 to t14.
  • the display controller 26 outputs image data including 16 pixel values of the entire image P1 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "2"
  • the data number N1 is "2”.
  • the scanning circuit 33 scans the plurality of pixels PIX with two pixel lines L as the scanning unit US. Also, the pixel signal generation circuit 32 applies the same pixel signal to two signal lines SGL adjacent to each other. As a result, the same pixel signal is written to the four pixels PIX in the two pixel lines L selected. In this manner, the display panel 27 drives a plurality of pixels PIX with four pixels PIX as a unit UD.
  • the pixel signal generation circuit 32 writes pixel signals relating to the entire image P1 to the two pixel lines L indicated by reference numeral W1 in FIG.
  • the display panel 27 performs the display driving operation for the two pixel lines L indicated by the symbol W2 in FIG. 9 during the period from timing t14 to t17.
  • the display controller 26 outputs image data including 16 pixel values of the entire image P1 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "3"
  • the data number N1 is "3”.
  • the display controller 26 sets the 3rd to 10th pixel values among the 16 pixel values to pixel values indicating black, as shown in FIG.
  • the display panel 27 controls not to write pixel signals to the pixels PIX corresponding to the 3rd to 10th pixel values.
  • the display controller 26 may write pixel signals based on pixel values of "0" to the pixels PIX corresponding to the third to tenth pixel values.
  • the display controller 26 sets the 3rd to 10th pixel values out of the 16 pixel values to pixel values indicating black, but the display controller 26 is not limited to this.
  • the original pixel value may be left as it is without setting to the indicated pixel value.
  • FIG. 12A and 12B show an example of the display driving operation for the two pixel lines L indicated by reference symbol W2 in FIG. , and (C) shows the operation at timings t16 to t17.
  • the pixel signal generation circuit 32 At timings t14 to t15, the pixel signal generation circuit 32 generates pixel signals corresponding to the 1st, 2nd, and 11th to 16th pixel values of the pixels corresponding to these pixel values. Write to PIX. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the display controller 26 In the next period from timing t15 to t16, the display controller 26 outputs image data including 16 pixel values of the partial image P2 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "4" and the data number N2 is "1".
  • the scanning circuit 33 scans the plurality of pixels PIX with one pixel line L as the scanning unit US. Also, the pixel signal generation circuit 32 applies a plurality of pixel signals to the plurality of signal lines SGL. Thereby, one pixel signal is written to one pixel PIX in one selected pixel line L, respectively. In this way, the display panel 27 drives a plurality of pixels PIX with one pixel PIX as a unit UD.
  • the pixel signal generation circuit 32 writes pixel signals corresponding to 16 pixel values to the pixels PIX corresponding to these pixel values. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the display controller 26 outputs image data including 16 pixel values of the partial image P2 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "5" and the data number N2 is "2".
  • the pixel signal generation circuit 32 writes pixel signals corresponding to 16 pixel values to the pixels PIX corresponding to these pixel values. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the pixel signal generation circuit 32 during the period of timings t14 to t17, generates a signal for all of the two pixel lines L indicated by symbol W2 in FIG.
  • a pixel signal related to the entire image P1 or a pixel signal related to the partial image P2 is written to the pixels PIX of the .
  • the display controller 26 and the display panel 27 operate in the same manner after this. Then, at timing t18, the vertical data enable signal VDE_OUT changes from high level to low level (FIG. 8(C)). Then, at timing t19, this vertical period V ends and the next vertical period V starts.
  • FIG. 13 shows an operation example of the display panel 27.
  • the frame rate is 120Hz.
  • the scanning circuit 33 scans from the top to the bottom of the pixel array 31 using one pixel line L or two pixel lines L as a scanning unit.
  • the scanning speed is fast during the period from timing t21 to t22 and from timing t24 to t25, and the scanning speed is slow during the period from timing t22 to t24. That is, during the period from timing t22 to t24, the scanning circuit 33 scans a plurality of pixel lines L corresponding to the position of the partial image P2.
  • the pixel signal generation circuit 32 writes pixel signals to a plurality of pixels PIX related to two pixel lines L in three horizontal periods like the operation during the period from timing t14 to t17, so the scanning speed is slow.
  • the pixel signal generation circuit 32 performs the operation in the period of timings t13 to t14.
  • the scanning speed is high because the pixel signals are written in the pixels PIX of the . In this way, in the display panel 27, scanning is performed with one pixel line L or two pixel lines L as the scanning unit. can be lowered, and power consumption can be reduced.
  • the pixel PIX to which the pixel signal is written emits light for a predetermined period after the pixel signal is written in this example.
  • the display panel 27 displays an image.
  • the latency of the head-mounted display 20 is, for example, the time ⁇ t from timing t21 at which image data input starts until the pixel PIX at the center position in the vertical direction of the display panel 27 starts emitting light.
  • This time ⁇ t is about half the time corresponding to the period T in this example. Specifically, for example, when the period T is 8.3 [msec.], the time ⁇ t can be set to about 4.1 [msec.].
  • FIG. 14 shows another operation example of the display panel 27.
  • the light emission operation of the pixel PIX is different from the example in FIG. That is, in the example of FIG. 13, the display panel 27 emits light according to the scanning timing, but in this example, the pixels PIX in the entire area emit light at the same timing.
  • the time ⁇ t is comparable to the time corresponding to the period T in this example. Specifically, for example, when the period T is 8.3 [msec.], the time ⁇ t can be set to about 8 [msec.].
  • the eye tracking sensor 23 of the head mounted display 20 detects which part of the display image the user is looking at by detecting the orientation of the eyes of the user wearing the head mounted display 20. to detect Based on the detection result of the eye tracking sensor 23, the image generation device 10 identifies an image (partial image P2) including the portion viewed by the user in the entire image P1. Then, the image generation device 10 generates an image signal SP including low-resolution image data representing the entire image P1 and high-resolution image data representing the partial image P2. Therefore, in the image data included in the image signal SP, the positions of the image data relating to the entire image P1 and the image data relating to the partial image P2 can change according to the detection result of the eye tracking sensor 23 .
  • FIG. 15 to 18 show an operation example of the display system 1.
  • FIG. 15 shows the case where the user is looking at the upper left portion of the display image on the display panel 27, and
  • FIG. 17 shows a case where the user is looking at the upper right portion of the display image on the panel 27,
  • FIG. 17 shows a case where the user is looking at the lower left portion of the display image on the display panel 27, and
  • FIG. 2 shows a case in which the lower right portion of the display image of is viewed.
  • FIG. , 16(B) when the user looks at the upper left or upper right of the display image on the display panel 27 (FIGS. 15 and 16), the image data of the partial image P2 in the image signal SP is shown in FIG. , 16(B) above.
  • the image data of the image signal SP for the partial image P2 is shown in FIG. (B), as shown in 18(B), located below.
  • the head-mounted display 20 provides first image data having a plurality of pixel values in one or more line images included in the whole image P1 of the first resolution.
  • Second image data having a plurality of pixel values in a plurality of line images included in the second resolution partial image P2 having a higher second resolution, and having a plurality of pixel values in one or a plurality of line images included in the whole image P1
  • the third image data is received in this order.
  • the head mounted display 20 performs first driving for driving the plurality of pixels PIX in units of four pixels PIX based on the first image data, and drives the plurality of pixels PIX based on the second image data.
  • a second drive for driving the PIX in units of one pixel PIX and a third drive for driving a plurality of pixels PIX in units of four pixels PIX based on the third image data are performed.
  • the head mounted display 20 can perform the display driving operation based on the first image data, the second image data, and the third image data in the order in which they are received. can be omitted. That is, if the head mounted display alternately receives image data for one frame of the entire image P1 and image data for one frame of the partial image P2, the head mounted display receives these two images. A single display image is generated by performing scaling processing and merging processing based on the data. In this case, the head mounted display requires a frame memory.
  • the display driving operation can be performed in the order of reception, so that the frame memory can be omitted, for example.
  • the amount of power consumed by the frame memory can be reduced, so power consumption can be reduced.
  • the head mounted display 20 drives the plurality of pixels PIX in units of one pixel or four pixels, for example, one pixel line L or two pixel lines L are scanned as a scanning unit.
  • the operating frequency can be lowered and the power consumption can be reduced as compared with the case where one pixel line L is used as the scanning unit, for example.
  • the display driving operation can be performed in the order in which the data are received in this way, so that, for example, a frame memory can be omitted. Since the frame memory can be omitted in this way, the time (latency) from the input of the image signal to the display of the image can be shortened.
  • the plurality of pixels are driven in units of four pixels
  • the plurality of pixels are driven in units of one pixel.
  • a second drive for driving and a third drive for driving a plurality of pixels in units of four pixels based on the third image data are performed. Thereby, power consumption can be reduced. Also, the latency can be shortened.
  • the image generation circuit 11 generates a high-resolution whole image P1, specifies a part of this whole image P1 as the partial image P2, and arranges two rows and two columns in the whole image P1.
  • the high resolution whole image P1 is converted into the low resolution whole image P1 by converting four pixel values into one pixel value
  • the present invention is not limited to this.
  • the image generation circuit 11 may generate the low-resolution whole image P1 and the high-resolution partial image P2 separately.
  • the transmission signal generation circuit 18 generates the image data included in the image signal SP based on the low-resolution whole image P1 and the high-resolution partial image P2.
  • the image signal SP includes pixel values of one line image included in the entire image P1 and pixel values of two line images included in the partial image P2. , are alternately arranged in the vertical direction, but the present invention is not limited to this.
  • the pixel values of the two line images included in the full image P1 and the pixel values of the four line images included in the partial image P2 are alternately arranged in the vertical direction. You may make it arrange
  • the transmission signal generation circuit 18 generates four pixels arranged in two rows and two columns based on 64 pixel values included in the first and second rows of the entire image P1. 16 pixel values for the whole image P1 are generated by converting the values into one pixel value. Thereby, the transmission signal generation circuit 18 generates the image data of the first row in the image signal SP.
  • the transmission signal generation circuit 18 converts four pixel values arranged in two rows and two columns into one pixel value based on the 64 pixel values included in the third and fourth rows of the entire image P1. The transformation produces 16 pixel values for the full image P1. Thereby, the transmission signal generation circuit 18 generates the image data of the second row in the image signal SP.
  • the transmission signal generation circuit 18 converts four pixel values arranged in two rows and two columns into one pixel value based on 128 pixel values included in the fifth to eighth rows of the entire image P1.
  • the transform produces 32 pixel values.
  • the transmission signal generation circuit 18 generates the image data of the third and fourth rows in the image signal SP.
  • the transmission signal generation circuit 18 directly outputs 16 pixel values related to the partial image P2 among the 32 pixel values included in the fifth row of the whole image P1, and outputs them to the sixth row of the whole image P1.
  • 16 pixel values related to the partial image P2 out of the 32 pixel values included are output as they are
  • 16 pixel values related to the partial image P2 out of the 32 pixel values included in the 7th row of the whole image P1 are output.
  • 16 pixel values relating to the partial image P2 among the 32 pixel values included in the 8th row of the full image P1 are output as they are.
  • the transmission signal generation circuit 18 generates the image data of the 5th to 8th rows in the image signal SP.
  • the image signal SP has a portion in which the pixel values of the two line images included in the full image P1 and the pixel values of the four line images included in the partial image P2 are alternately arranged in the vertical direction. occur.
  • FIG. 20 shows a configuration example of a display system 1C according to a modification.
  • the display system 1C includes an image generation device 10C and a head mounted display 20C.
  • the image generation device 10C has an image generation circuit 11C.
  • the image generation circuit 11C has an image compression circuit 19C.
  • the image compression circuit 19C is configured to perform compression processing on image data included in the image signal SP generated by the transmission signal generation circuit 18 . Specifically, in the image data included in the image signal SP (for example, FIG. 3B), the image compression circuit 19C sets the following between the image data relating to the entire image P1 and the image data relating to the partial image P2: One row of image data composed of pixel values representing black is inserted, and then each row of image data is compressed using the previous row of image data.
  • VESA DSC Display Stream Compression
  • FIG. 21 shows an example of image data.
  • image data having a black pixel value is inserted into the image data shown in FIG. 3B.
  • the image data on the 1st to 3rd lines are the image data related to the whole image P1
  • the image data on the 4th line is the image data having the inserted black pixel value
  • the image data on the 5th and 6th lines The image data is image data relating to the partial image P2
  • the image data in the seventh row is image data having the inserted black pixel value
  • the image data in the eighth row is the image relating to the entire image P1. Data.
  • the head mounted display 20C has a processor 24C.
  • the processor 24C has an image restoration circuit 29C.
  • the image restoration circuit 29C is configured to perform restoration processing based on the compressed image data. Specifically, the image restoration circuit 29C performs restoration processing on the image data (FIG. 21) included in the image signal SP, and then restores the image data related to the entire image P1 and the image data related to the partial image P2.
  • One line of image data consisting of pixel values indicating black between and is deleted.
  • the display system 1C can reduce compression errors. That is, the image compression circuit 19C utilizes the similarity and continuity of images, and in this example, compresses the line image using the line image one line before. However, there is basically no similarity between the whole image P1 and the partial image P2. Therefore, for example, when the image compression circuit 19C compresses the line image related to the entire image P1 using the line image related to the partial image P2 one line before, there is a possibility that the compression error will increase. . On the other hand, in the display system 1C, since the image data having the pixel value of black is inserted between the image data relating to the entire image P1 and the image data relating to the partial image P2, this compression error can be reduced. . Although the amount of data increases by inserting image data having black pixel values in this way, the amount of data of the image signal SP to be finally transmitted can be reduced by performing compression processing.
  • FIG. 22 shows another example of image data according to this modified example.
  • image data having black pixel values is inserted into the image data shown in FIG. 19B.
  • the image data on the 1st to 4th rows are image data relating to the entire image P1
  • the image data on the 5th row are image data having black pixel values inserted
  • the image data on the 6th to 9th rows are image data relating to the entire image P1.
  • the image data is image data related to the partial image P2
  • the image data of the 10th row is the image data having the inserted black pixel value
  • the image data of the 11th and 12th rows is the image data of the entire image P1. It is the image data which concerns.
  • the data amount of the image data to be inserted can be reduced compared to the example of FIG. 21, so the data amount of the image signal SP to be finally transmitted can be reduced.
  • the image compression circuit 19C compresses the image data of each row using the image data of the previous row, but it is not limited to this. Instead of this, for example, the image compression circuit 19C may compress the image data of each row using the image data one row before and the image data two rows before.
  • FIG. 23 shows another example of image data according to this modified example.
  • the image compression circuit 19C compresses the image data of each row using the image data of one row before and the image data of two rows before
  • the image compression circuit 19C compresses the entire image P1 in advance.
  • Two rows of image data having pixel values representing black are inserted between the image data and the image data of the partial image P2.
  • two lines of image data having black pixel values are inserted into the image data shown in FIG. 3B.
  • the image data on the 1st to 3rd lines are the image data related to the entire image P1
  • the image data on the 4th and 5th lines are the image data having the black pixel values inserted
  • the image data on the 6th and 7th lines The image data of the second line is image data relating to the partial image P2
  • the image data of the eighth and ninth lines are the image data having the inserted black pixel values
  • the image data of the tenth line is the image data of the entire image.
  • This is image data related to P1.
  • the display system 1C can reduce the compression error even when compressing using the immediately preceding two line images.
  • the red image (R), green image (G), and blue image (B) of the full image P1 are low-resolution images. Based on these images, the display panel 27 performs a display drive operation for the entire image P1 in units of four pixels PIX arranged in two rows and two columns. Also, the red image (R), the green image (B), and the blue image (B) of the partial image P2 are high-resolution images. Based on these images, the display panel 27 performs a display drive operation for the partial image P2 in units of one pixel PIX.
  • the bandwidth usage rate in this case is 50%, as in the case of the above embodiment (FIG. 4).
  • the luminance image (Y), the first color difference image (U), and the second color difference image (V) of the entire image P1 are low resolution images.
  • display controller 26 Based on these images, display controller 26 generates a low-resolution red image (R), green image (G), and blue image (B), and display panel 27, based on the generated images, A display drive operation for the entire image P1 is performed using four pixels PIX arranged in two rows and two columns as a unit.
  • the luminance image (Y), the first color difference image (U), and the second color difference image (V) of the partial image P2 are high-resolution images.
  • display controller 26 Based on these images, display controller 26 generates a high resolution red image (R), green image (G), and blue image (B), and display panel 27, based on the generated images, A display drive operation for the partial image P2 is performed in units of one pixel PIX.
  • the bandwidth usage rate in this case is 50%, as in the case of the above embodiment (FIG. 4).
  • the luminance image (Y), the first color difference image (U), and the second color difference image (V) of the entire image P1 are low-resolution images.
  • display controller 26 Based on these images, display controller 26 generates a low-resolution red image (R), green image (G), and blue image (B), and display panel 27, based on the generated images, A display drive operation for the entire image P1 is performed using four pixels PIX arranged in two rows and two columns as a unit.
  • the luminance image (Y) of the partial image P2 is a high resolution image
  • the first color difference image (U) and the second color difference signal (V) are low resolution images.
  • display controller 26 Based on these images, display controller 26 generates a high resolution red image (R), green image (G), and blue image (B), and display panel 27, based on the generated images, A display drive operation for the partial image P2 is performed in units of one pixel PIX.
  • the band utilization rate in this case is 37.5%.
  • case C4 is similar to case C3, but the low-resolution first color difference image (U) and second color difference image (V) in the whole image P1 are used in the partial image P2. ing.
  • FIG. 25 shows an operation example of the display system 1 in case C4.
  • the head-mounted display 20 can generate the image data indicated by symbol W3 in FIG. 26 based on the image data of the third to fifth rows in the image signal SP.
  • the image data in the third row in the image signal SP is low-resolution image data relating to the entire image P1, and includes data Y1 to Y16 indicating luminance values, data U1 to U16 indicating first color difference values, and second It has data V1 to V16 indicating color difference values.
  • the image data in the fourth row in the image signal SP is high-resolution image data relating to the partial image P2, and has only data Y1 to Y16 indicating luminance values.
  • Image data in the fifth row in the image signal SP is high-resolution image data relating to the partial image P2, and has only data Y1 to Y16 indicating luminance values.
  • Data Y17 to Y32 indicating luminance values, which are included in the image data on the 5th line and Y16, are the image data indicated by symbol W3 in FIG.
  • the display controller 26 can generate high-resolution image data of a red image (R), a green image (G), and a blue image (B) for the partial image P2.
  • the display panel 27 performs a display drive operation for the partial image P2 in units of one pixel PIX based on the generated image data.
  • the band utilization rate in this case is 33%.
  • case C4 can be realized by using such a special data format.
  • case C5 (FIG. 24C) can be used when using the normal data format.
  • FIG. 27 shows an operation example of the display system 1 in case C5.
  • the head-mounted display 20 generates image data indicated by reference numeral W3 in FIG. 28 based on the image data of the third and fourth rows in the image signal SP.
  • the third row of image data in the image signal SP includes low-resolution image data relating to the entire image P1 and high-resolution image data relating to the partial image P2.
  • the low-resolution image data for the entire image P1 includes data Y1, Y2, Y11 to Y16 indicating luminance values, data U1 to U16 indicating first color difference values, and data V1 to V16 indicating second color difference values. have.
  • the high-resolution image data for the partial image P2 has data Y3a to Y10a indicating luminance values.
  • the image data in the fourth row is high-resolution image data relating to the partial image P2, and has data Y3b to Y10b, Y3c to Y10c, and Y3d to Y10d indicating luminance values.
  • the subscripts a, b, c, and d in the data Y3a-Y10a, Y3b-Y10b, Y3c-Y10c, Y3d-Y10d are the four pixels PIX arranged in two rows and two columns, as shown in FIG. showing the position.
  • data Y3a indicates the luminance value of the upper left pixel PIX
  • data Y3b indicates the luminance value of the upper right pixel PIX
  • data Y3c indicates the luminance value of the lower left pixel PIX
  • data Y3d indicates the luminance value of the lower right pixel PIX.
  • Y3a to Y10a representing luminance values
  • data U3 to U10 representing first color difference values
  • data V3 to V10 representing second color difference values
  • data V3 to V10 representing second color difference values
  • the display controller 26 can generate high-resolution image data of a red image (R), a green image (G), and a blue image (B) for the partial image P2.
  • the display panel 27 performs a display drive operation for the partial image P2 in units of one pixel PIX based on the generated image data.
  • the band utilization rate in this case is 37.5%.
  • the luminance image (Y) of the entire image P1 is a low-resolution image
  • the first color difference image (U) and the second color difference image (V) are It is a lower resolution image.
  • display controller 26 Based on these images, display controller 26 generates a low-resolution red image (R), green image (G), and blue image (B), and display panel 27, based on the generated images, A display drive operation for the entire image P1 is performed using four pixels PIX arranged in two rows and two columns as a unit.
  • the luminance image (Y) of the partial image P2 is a high resolution image
  • the first color difference image (U) and the second color difference signal (V) are low resolution images.
  • display controller 26 Based on these images, display controller 26 generates a high resolution red image (R), green image (G), and blue image (B), and display panel 27, based on the generated images, A display drive operation for the partial image P2 is performed in units of one pixel PIX.
  • the band utilization rate in this case is 25%.
  • the image generation circuit 11 generates an image of the entire scenery corresponding to the direction of the head-mounted display 20 in the virtual space based on the detection result of the acceleration sensor 22 included in the data supplied from the reception circuit 13. Generate an image P1.
  • the image generation circuit 11 selects, based on the detection result of the eye tracking sensor 23 included in the data supplied from the reception circuit 13, the user's specifies the partial images P2 and P3 indicating the portion viewed by .
  • FIG. 29 shows an example of an image generated by the image generation circuit 11.
  • the image generation circuit 11 Based on the detection result of the eye tracking sensor 23 included in the data supplied from the receiving circuit 13, the image generation circuit 11 generates partial images P2 and P3 including the portion viewed by the user from the entire image P1. Identify.
  • the size of the partial image P2 in the horizontal direction is half the size of the whole image P1 in the horizontal direction
  • the size of the partial image P2 in the vertical direction (the vertical direction in FIG. 29) is half the size of the whole image P1.
  • the size is half the vertical size of the full image P1. That is, the area of the partial image P2 is 1/4 of the area of the full image P1.
  • the horizontal size of the partial image P3 is half the horizontal size of the partial image P2, and the vertical size of the partial image P3 is half the vertical size of the partial image P2. be. That is, the area of the partial image P3 is 1 ⁇ 4 of the area of the partial image P2. In this example, the central position of partial image P3 is the same as the central position of partial image P2.
  • FIG. 30 shows an operation example of the display system 1 according to this modification, where (A) shows an image generated by the image generation circuit 11, and (B) shows image data included in the image signal SP. , and (C) shows the display driving operation in the head mounted display 20 according to this modification.
  • the transmission signal generation circuit 18 scans the entire image P1 generated by the image generation circuit 11 from left to right. , the image signal SP is generated.
  • the transmission signal generation circuit 18 converts the 16 pixel values arranged in 4 rows and 4 columns for the entire image P1 into one pixel value, and converts the portion of the entire image P1 overlapping the partial image P2 to a single pixel value. converts four pixel values arranged in two rows and two columns into one pixel value, and outputs one pixel value as it is for a portion of the entire image P1 that overlaps the partial image P3. , to generate image data in the image signal SP.
  • the transmission signal generation circuit 18 generates 16 pixel values arranged in 4 rows and 4 columns based on 128 pixel values included in the 1st to 4th rows of the entire image P1. are converted into one pixel value to generate eight pixel values for the entire image P1. Thereby, the transmission signal generation circuit 18 generates the image data of the first row in the image signal SP.
  • the transmission signal generation circuit 18 converts 16 pixel values arranged in 4 rows and 4 columns into one pixel value based on 128 pixel values included in the 5th to 8th rows of the entire image P1. By doing so, eight pixel values for the entire image P1 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the second row in the image signal SP.
  • the transmission signal generation circuit 18 is arranged in two rows and two columns based on 32 pixel values related to the partial image P2 among the 64 pixel values included in the fifth and sixth rows of the entire image P1. By converting the four pixel values into one pixel value, eight pixel values of the partial image P2 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the third row in the image signal SP.
  • the transmission signal generation circuit 18 is arranged in two rows and two columns based on 32 pixel values related to the partial image P2 among the 64 pixel values included in the 7th and 8th rows of the entire image P1. By converting the four pixel values into one pixel value, eight pixel values of the partial image P2 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the fourth row in the image signal SP.
  • the transmission signal generation circuit 18 converts 16 pixel values arranged in 4 rows and 4 columns into one pixel value based on 128 pixel values included in the 9th to 12th rows of the entire image P1. By doing so, eight pixel values for the entire image P1 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the fifth row in the image signal SP.
  • the transmission signal generation circuit 18 is arranged in two rows and two columns based on 32 pixel values related to the partial image P2 among the 64 pixel values included in the 9th and 10th rows of the entire image P1. By converting the four pixel values into one pixel value, eight pixel values of the partial image P2 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the sixth row in the image signal SP.
  • the transmission signal generation circuit 18 is arranged in two rows and two columns based on 32 pixel values related to the partial image P2 among the 64 pixel values included in the 11th and 12th rows of the entire image P1. By converting the four pixel values into one pixel value, eight pixel values of the partial image P2 are generated. Thereby, the transmission signal generation circuit 18 generates the image data of the seventh row in the image signal SP.
  • the transmission signal generation circuit 18 directly outputs the eight pixel values related to the partial image P3 among the 32 pixel values included in the 9th row of the whole image P1, and outputs the eight pixel values included in the 10th row of the whole image P1.
  • 8 pixel values related to the partial image P3 out of the 32 pixel values contained in the total image P1 are output as they are, and 8 pixel values related to the partial image P3 out of the 32 pixel values contained in the 11th row of the whole image P1 are output as they are.
  • the transmission signal generation circuit 18 generates the image data of the 8th to 11th rows in the image signal SP.
  • the transmission signal generation circuit 18 converts 16 pixel values arranged in 4 rows and 4 columns into one pixel value for the entire image P1.
  • the transmission signal generation circuit 18 converts four pixel values arranged in two rows and two columns into one pixel value for a portion of the entire image P1 that overlaps the partial image P2. Further, the transmission signal generation circuit 18 outputs the pixel values as they are for the portion of the entire image P1 that overlaps the partial image P3.
  • the resolution of the entire image P1 is lower than the resolution of the partial image P2
  • the resolution of the partial image P2 is lower than the resolution of the partial image P3.
  • the transmission signal generation circuit 18 generates image data including a plurality of pixel values as shown in FIG. 30(B) based on the image generated by the image generation circuit 11. Then, the transmission signal generation circuit 18 generates an image signal SP including this image data and image position data indicating the position (parameters POSX, POSY) of the partial image P2 in the entire image P1.
  • FIG. 31 shows transmission bands in the display system 1 according to this modified example.
  • the image data included in the image signal SP includes 24 rows of image data in this example.
  • data number N1 is assigned to eight lines of image data relating to the entire image P1
  • data number N2 is assigned to eight lines of image data relating to the partial image P2
  • data number N2 is assigned to the partial image P3.
  • a data number N3 is attached to the eight lines of image data.
  • FIG. 32 shows an example of signals output from the display controller 26 according to this modification, where (A) shows the waveform of the vertical synchronizing signal VS_OUT and (B) shows the waveform of the horizontal synchronizing signal HS_OUT. , (C) shows the waveform of the vertical data enable signal VDE_OUT, and (D) shows the data signal DATA_OUT.
  • a pulse occurs in the vertical synchronization signal VS_OUT, and the vertical period V starts (FIG. 32(A)).
  • a pulse is generated in the horizontal synchronization signal HS_OUT each time the horizontal period H starts (FIG. 32(B)).
  • the vertical data enable signal VDE_OUT changes from low level to high level (FIG. 32(C)).
  • the display controller 26 outputs 24 pieces of image data as the data signal DATA_OUT over 24 horizontal periods H (FIG. 32(D)).
  • the display controller 26 drives a plurality of pixels PIX in the display panel 27 in units of 16 pixels PIX arranged in 4 rows and 4 columns based on the image data relating to the entire image P1 included in the data signal DATA_OUT. control to Further, the display controller 26 drives a plurality of pixels PIX in the display panel 27 in units of four pixels PIX arranged in two rows and two columns, based on data relating to the partial image P2 included in the data signal DATA_OUT. control to Further, the display controller 26 controls the plurality of pixels PIX in the display panel 27 to be driven in units of one pixel PIX based on the data related to the partial image P3 included in the data signal DATA_OUT.
  • FIG. 33 shows an example of the data signal DATA_OUT at timings t22 to t33 in FIG. 32 and the display driving operation based on the data signal DATA_OUT.
  • the display panel 27 performs the display drive operation for the four pixel lines L indicated by W4 in FIG. 33 during the period from timing t22 to t23.
  • the display controller 26 outputs image data including eight pixel values of the entire image P1 as the data signal DATA_OUT.
  • the data number NSP of this image data is "1"
  • the data number N1 is "1”.
  • the scanning circuit 33 scans the plurality of pixels PIX with four pixel lines L as the scanning unit US. Also, the pixel signal generation circuit 32 applies the same pixel signal to four signal lines SGL adjacent to each other. As a result, the same pixel signal is written to 16 pixels PIX in the selected four pixel lines L. FIG. In this manner, the display panel 27 drives a plurality of pixels PIX with 16 pixels PIX as a unit UD.
  • the pixel signal generation circuit 32 writes pixel signals relating to the entire image P1 to the four pixel lines L indicated by reference numeral W4 in FIG.
  • the display panel 27 performs the display driving operation for the four pixel lines L indicated by the symbol W5 in FIG. 33 during the period from timing t23 to t26.
  • the display controller 26 outputs image data including eight pixel values of the entire image P1 as the data signal DATA_OUT.
  • the data number NSP of this image data is "2"
  • the data number N1 is "2”.
  • the display controller 26 sets the 2nd to 5th pixel values among the 8 pixel values to pixel values indicating black.
  • the display panel 27 controls not to write pixel signals to the pixels PIX corresponding to the second to fifth pixel values.
  • FIG. 34 shows an example of the display driving operation for the four pixel lines L indicated by symbol W5 in FIG.
  • (C) shows the operation at timings t25 to t26.
  • the pixel signal generation circuit 32 outputs pixel signals corresponding to the 1st, 6th to 8th pixel values to the pixels PIX corresponding to these pixel values. Write. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the display controller 26 In the next period from timing t24 to t25, the display controller 26 outputs image data including eight pixel values of the partial image P2 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "3" and the data number N2 is "1".
  • the pixel signal generation circuit 32 writes pixel signals corresponding to eight pixel values to the pixels PIX corresponding to these pixel values. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the operation during the period from timing t25 to t26 is the same as the operation during the period from timing t24 to t25.
  • the pixel signal generation circuit 32 writes pixel signals corresponding to eight pixel values to the pixels PIX corresponding to these pixel values.
  • the pixel signal generation circuit 32 as shown in FIG. A pixel signal related to the entire image P1 or a pixel signal related to the partial image P2 is written to the pixels PIX of the .
  • the display panel 27 performs the display driving operation for the four pixel lines L indicated by the symbol W6 in FIG. 33 during the period from timing t26 to t33.
  • the display controller 26 outputs image data including eight pixel values of the entire image P1 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "5" and the data number N1 is "3".
  • the display controller 26 sets the 2nd to 5th pixel values among the 8 pixel values to pixel values indicating black.
  • the display panel 27 controls not to write pixel signals to the pixels PIX corresponding to the second to fifth pixel values.
  • FIG. 35 shows an example of the display driving operation for the four pixel lines L indicated by symbol W6 in FIG.
  • C shows the operation at timing t28-t29
  • D shows the operation at timing t29-t30
  • E shows the operation at timing t30-t31
  • F shows the operation at timing t31 to t32
  • G shows the operation at timings t32 to t33.
  • the pixel signal generation circuit 32 outputs pixel signals corresponding to the 1st, 6th to 8th pixel values to the pixels PIX corresponding to these pixel values. Write. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the display controller 26 In the next period from timing t27 to t28, the display controller 26 outputs image data including eight pixel values of the partial image P2 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "6" and the data number N2 is "3".
  • the display controller 26 sets the third to sixth pixel values among the eight pixel values to pixel values indicating black.
  • the display panel 27 controls not to write pixel signals to the pixels PIX corresponding to the third to sixth pixel values.
  • the pixel signal generation circuit 32 At timings t27 to t28, the pixel signal generation circuit 32 generates pixel signals corresponding to the 1st, 2nd, 7th, and 8th pixel values for the pixels corresponding to these pixel values. Write to PIX. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the operation during the period from timing t28 to t29 is the same as the operation during the period from timing t27 to t28.
  • the pixel signal generation circuit 32 generates pixel signals corresponding to the 1st, 2nd, 7th, and 8th pixel values. Write to the pixel PIX that
  • the display controller 26 outputs image data including eight pixel values of the partial image P3 as the data signal DATA_OUT, as shown in FIG.
  • the data number NSP of this image data is "8" and the data number N3 is "1".
  • the display controller 26 recognizes that this image data includes pixel values for the partial image P3.
  • the pixel signal generation circuit 32 writes pixel signals corresponding to eight pixel values to the pixels PIX corresponding to these pixel values. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the pixel signal generation circuit 32 generates eight pixel A pixel signal corresponding to the value is written to the pixel PIX corresponding to these pixel values.
  • the pixel signal generation circuit 32 as shown in FIG. A pixel signal related to the entire image P1, a pixel signal related to the partial image P2, or a pixel signal related to the partial image P3 is written to the pixels PIX of the .
  • the display controller 26 and the display panel 27 operate in the same manner after this. Then, at timing t34, the vertical data enable signal VDE_OUT changes from high level to low level (FIG. 32(C)). Then, at timing t35, this vertical period V ends and the next vertical period V starts.
  • Second Embodiment> a display system 2 according to a second embodiment will be described. This embodiment differs from the first embodiment in the configuration of image data in the pixel signal SP.
  • symbol is attached
  • FIG. 36 shows a configuration example of the display system 2 according to this embodiment.
  • the display system 2 includes an image generation device 40 and a head mounted display 50 .
  • the image generation device 40 has an image generation circuit 41 .
  • the image generation circuit 41 has a transmission signal generation circuit 48 .
  • the transmission signal generation circuit 48 is configured to generate an image signal SP to be transmitted based on the image generated by the image generation circuit 41 .
  • FIG. 37 shows an operation example of the display system 2, where (A) shows an image generated by the image generation circuit 41, (B) shows image data included in the image signal SP, and (C). indicates the display driving operation in the head mounted display 50.
  • FIG. 37 shows an operation example of the display system 2, where (A) shows an image generated by the image generation circuit 41, (B) shows image data included in the image signal SP, and (C). indicates the display driving operation in the head mounted display 50.
  • the transmission signal generation circuit 48 sequentially scans the entire image P1 generated by the image generation circuit 41 from left to right and from top to bottom. Thus, an image signal SP is generated.
  • the transmission signal generation circuit 48 converts four pixel values arranged in two rows and two columns into one pixel value for a portion of the entire image P1 that does not overlap with the partial image P2, and converts four pixel values into one pixel value.
  • the image data in the image signal SP is generated by outputting one pixel value as it is for the portion overlapping the partial image P2.
  • the transmission signal generation circuit 48 generates four pixel values arranged in two rows and two columns based on 64 pixel values included in the first and second rows of the entire image P1. By converting to one pixel value, 16 pixel values are generated for the entire image P1. Then, the transmission signal generation circuit 48 generates eight pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the first row in the image signal SP.
  • the transmission signal generation circuit 48 converts four pixel values arranged in two rows and two columns into one pixel value based on the 64 pixel values included in the third and fourth rows of the entire image P1. Thus, 16 pixel values for the entire image P1 are generated. Then, the transmission signal generation circuit 48 generates eight pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the second row in the image signal SP.
  • the transmission signal generation circuit 48 generates, based on 8 pixel values belonging to the 1st to 4th columns of the 64 pixel values included in the 5th and 6th rows of the entire image P1, the 2nd row and 2nd columns. By converting the arranged four pixel values into one pixel value, two pixel values relating to the entire image P1 are generated.
  • the transmission signal generating circuit 48 directly outputs 16 pixel values related to the partial image P2 among the 32 pixel values included in the fifth row of the entire image P1.
  • the transmission signal generation circuit 48 generates the 2nd row, 2nd column based on the 24 pixel values belonging to the 21st to 32nd columns among the 64 pixel values included in the 5th and 6th rows of the entire image P1.
  • the transmission signal generation circuit 48 By converting the four pixel values arranged in to one pixel value, six pixel values relating to the entire image P1 are generated. Thereby, the transmission signal generation circuit 48 generates the image data of the third row in the image signal SP.
  • the transmission signal generation circuit 48 generates two pixel values indicating black.
  • the transmission signal generation circuit 48 directly outputs 16 pixel values related to the partial image P2 among the 32 pixel values included in the 6th row of the full image P1. Then, the transmission signal generation circuit 48 generates six pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the fourth row in the image signal SP.
  • the transmission signal generation circuit 48 converts four pixel values arranged in two rows and two columns into one pixel value for a portion of the entire image P1 that does not overlap the partial image P2. Therefore, the converted whole image P1 does not include the image corresponding to the partial image P2.
  • the transmission signal generation circuit 48 converts the portion of the whole image P1 that does not overlap with the partial image P2 into a lower resolution whole image P1.
  • the resolution of partial image P2 does not change. As a result, the resolution of the converted whole image P1 is lower than the resolution of the partial image P2.
  • the transmission signal generation circuit 48 generates the image signal SP by sequentially scanning from left to right and from top to bottom. and one or more pixel values of the partial image P2 are alternately arranged.
  • the transmission signal generation circuit 48 generates image data including a plurality of pixel values as shown in FIG. 37(B) based on the image generated by the image generation circuit 41.
  • This image data includes pixel values representing black.
  • the transmission signal generation circuit 48 generates an image signal SP including this image data and image position data indicating the position (parameters POSX, POSY) of the partial image P2 in the entire image P1.
  • FIG. 38 shows the transmission band in the display system 2.
  • the non-shaded portion indicates the image data relating to the entire image P1
  • the shaded portion indicates the image data relating to the partial image P2.
  • Pixel values shaded with dark shading indicate black pixel values.
  • the image data included in the image signal SP includes 24 rows of image data in this example. For convenience of explanation, the data number NSP is given to the image data for 24 lines.
  • the head mounted display 50 (FIG. 36) has a display controller 56.
  • Display controller 56 is configured to control the operation of display panel 27 based on the image data and image position data provided by processor 24 .
  • FIG. 39 shows an example of signals input to the display controller 56, (A) shows the waveform of the vertical synchronization signal VS_IN, (B) shows the waveform of the horizontal synchronization signal HS_IN, and (C) shows the waveform of the horizontal synchronization signal HS_IN.
  • the waveform of the vertical data enable signal VDE_IN is shown, and (D) shows the data signal DATA_IN.
  • a pulse occurs in the vertical synchronization signal VS_IN, and the vertical period V starts (FIG. 39(A)). Further, a pulse is generated in the horizontal synchronization signal HS_IN each time the horizontal period H starts (FIG. 39(B)).
  • the vertical data enable signal VDE_IN changes from low level to high level (FIG. 39(C)).
  • the data signal DATA_IN is supplied over 24 horizontal periods H.
  • FIG. The data signal DATA_IN includes 24 image data corresponding to 24 horizontal periods H.
  • FIG. 40 shows an example of the data signal DATA_IN.
  • the second row of image data included in the image signal SP corresponds to the second image data among the 24 pieces of image data included in the data signal DATA_IN.
  • This image data includes 16 pixel values relating to the entire image P1 and 8 pixel values representing black.
  • the third row of image data included in the image signal SP corresponds to the third image data among the 24 pieces of image data included in the data signal DATA_IN.
  • This image data includes two pixel values for the entire image P1, 16 pixel values for the partial image P2, and six pixel values for the entire image P1.
  • the image data in the fourth row included in the image signal SP corresponds to the fourth image data among the 24 pieces of image data included in the data signal DATA_IN.
  • This image data includes two pixel values representing black, 16 pixel values relating to the partial image P2, and six pixel values representing black.
  • the vertical data enable signal VDE_IN changes from high level to low level (FIG. 39(C)). Then, at timing t44, this vertical period V ends and the next vertical period V starts.
  • the display controller 56 performs predetermined processing based on such image data supplied from the processor 24 to generate a vertical synchronizing signal VS_OUT, a horizontal synchronizing signal HS_OUT, a vertical data enable signal VDE_OUT, and a data signal DATA_OUT. do.
  • FIG. 41 shows an example of signals output from the display controller 56.
  • (A) shows the waveform of the vertical synchronizing signal VS_OUT
  • (B) shows the waveform of the horizontal synchronizing signal HS_OUT
  • (C) shows the waveform of the horizontal synchronizing signal HS_OUT.
  • the waveform of the vertical data enable signal VDE_OUT is shown
  • (D) shows the data signal DATA_OUT.
  • the non-shaded portion indicates the image data related to the full image P1
  • the shaded portion indicates the image data related to the partial image P2.
  • a pulse occurs in the vertical synchronization signal VS_OUT, and the vertical period V starts ((A) in FIG. 41).
  • a pulse is generated in the horizontal synchronization signal HS_OUT each time the horizontal period H starts (FIG. 41(B)).
  • the vertical data enable signal VDE_OUT changes from low level to high level (FIG. 41(C)).
  • the display controller 56 outputs 24 pieces of image data as the data signal DATA_OUT over 24 horizontal periods H (FIG. 41(D)). These 24 image data correspond to the 24 image data in the data signal DATA_IN (FIG. 39(D)). In other words, these 24 pieces of image data correspond to 24 rows of image data included in the image signal SP shown in FIGS.
  • the display controller 56 drives a plurality of pixels PIX in the display panel 27 in units of four pixels PIX arranged in two rows and two columns, based on image data relating to the entire image P1 included in the data signal DATA_OUT. to control. Further, the display controller 56 controls the plurality of pixels PIX in the display panel 27 to be driven in units of one pixel PIX based on the data related to the partial image P2 included in the data signal DATA_OUT.
  • FIG. 42 shows an example of the data signal DATA_OUT at timings t53 to t56 in FIG. 41 and the display driving operation based on the data signal DATA_OUT.
  • the display panel 27 performs the display drive operation for the two pixel lines L indicated by W7 in FIG. 42 during the period from timing t53 to t54.
  • the display controller 56 As shown in FIG. Output as DATA_OUT.
  • the data number NSP of this image data is "2".
  • the pixel signal generation circuit 32 writes pixel signals relating to the entire image P1 to the two pixel lines L indicated by reference numeral W7 in FIG.
  • the display panel 27 performs the display driving operation for the two pixel lines L indicated by the symbol W8 in FIG. 42 during the period from timing t54 to t56.
  • Image data including these 16 pixel values and the 19th to 24th pixel values of the entire image P1 are output as the data signal DATA_OUT.
  • the data number NSP of this image data is "3".
  • display controller 56 recognizes that this image data includes pixel values for partial image P2.
  • FIG. 43 shows an example of the display driving operation for the two pixel lines L indicated by symbol W8 in FIG. shows the behavior in As shown in FIG. 43A, at timings t54 to t55, the pixel signal generation circuit 32 writes pixel signals corresponding to the 1st to 24th pixel values to the pixels PIX corresponding to these pixel values.
  • the display controller 56 In the next period from timing t55 to t66, the display controller 56, as shown in FIG. and six pixel values representing black at the 19th to 24th pixel values are output as the data signal DATA_OUT.
  • the data number NSP of this image data is "4".
  • the pixel signal generation circuit 32 At timings t55 to t56, the pixel signal generation circuit 32 generates pixel signals corresponding to 16 pixel values of the 3rd to 18th pixels to the pixel PIX corresponding to these pixel values. write to Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the pixel signal generation circuit 32 as shown in FIGS. 43(A) and 43(B), during the period of timings t54 to t56, the two pixel lines L indicated by the symbol W8 in FIG. A pixel signal related to the entire image P1 or a pixel signal related to the partial image P2 is written to the pixels PIX of the .
  • the display controller 56 and the display panel 27 operate in the same manner after this. Then, at timing t57, the vertical data enable signal VDE_OUT changes from high level to low level (FIG. 41(C)). Then, at timing t58, this vertical period V ends and the next vertical period V starts.
  • the head-mounted display 50 provides the first image data having one or more pixel values included in the whole image P1 of the first resolution, the second image data higher than the first resolution.
  • the second image data having one or more pixel values included in the resolution partial image P2 and the third image data having one or more pixel values included in the full image P1 are received in this order.
  • the head mounted display 20 performs first driving for driving the plurality of pixels PIX in units of four pixels PIX based on the first image data, and drives the plurality of pixels PIX based on the second image data.
  • PIX is driven in units of two pixels PIX
  • third driving is performed in which a plurality of pixels PIX are driven in units of four pixels PIX based on the third image data.
  • the first driving is driving based on the 1st and 2nd pixel values
  • the second driving is driving based on the 3rd to 18th pixel values
  • the third driving is , 19th to 24th pixel values. Accordingly, the head mounted display 50 can perform the display driving operation based on the first image data, the second image data, and the third image data in the order in which they are received. can be omitted. As a result, power consumption can be reduced in the head mounted display 50 .
  • the first image data having one or more pixel values included in the entire image of the first resolution, the partial image having the second resolution higher than the first resolution, and the The second image data having one or more pixel values included in the entire image and the third image data having one or more pixel values included in the entire image are received in this order. Then, based on the first image data, the plurality of pixels are driven in units of four pixels, and based on the second image data, the plurality of pixels are driven in units of two pixels. A second drive for driving and a third drive for driving a plurality of pixels in units of four pixels based on the third image data are performed. Thereby, power consumption can be reduced. Other effects are the same as in the first embodiment.
  • the image generation circuit 41 generates a virtual A whole image P1 showing the scenery in space according to the orientation of the head mounted display 50 is generated.
  • the image generation circuit 41 selects, based on the detection result of the eye tracking sensor 23 included in the data supplied from the reception circuit 13, the user's view of the landscape corresponding to the direction of the head-mounted display 50 in the virtual space. specifies the partial images P2 and P3 indicating the portion viewed by .
  • FIG. 44 shows an operation example of the display system 2 according to this modification, where (A) shows an image generated by the image generation circuit 41, and (B) shows image data included in the image signal SP. , and (C) shows the display driving operation in the head mounted display 50 according to this modification.
  • the transmission signal generation circuit 48 scans the entire image P1 generated by the image generation circuit 41 from left to right. , the image signal SP is generated.
  • the transmission signal generation circuit 48 converts 16 pixel values arranged in 4 rows and 4 columns into one pixel value for a portion of the entire image P1 that does not overlap with the partial image P2, and converts the pixel values of the entire image P1.
  • the four pixel values arranged in two rows and two columns are converted into one pixel value, and the partial image For the portion overlapping P3, the image data in the image signal SP is generated by outputting one pixel value as it is.
  • the transmission signal generation circuit 48 generates 16 pixel values arranged in 4 rows and 4 columns based on 128 pixel values included in the 1st to 4th rows of the entire image P1. are converted into one pixel value to generate eight pixel values for the entire image P1. Then, the transmission signal generation circuit 48 generates eight pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the first row in the image signal SP.
  • the transmission signal generation circuit 48 generates 4 rows and 4 columns based on 16 pixel values belonging to the 1st to 4th columns among the 128 pixel values included in the 5th to 8th rows of the entire image P1. By converting the 16 pixel values arranged in , into one pixel value, one pixel value relating to the entire image P1 is generated.
  • the transmission signal generation circuit 48 generates 4 pixels arranged in 2 rows and 2 columns based on 32 pixel values related to the partial image P2 among the 64 pixel values included in the 5th and 6th rows of the entire image P1. By converting one pixel value into one pixel value, eight pixel values relating to the partial image P2 are generated.
  • the transmission signal generating circuit 48 is arranged in 4 rows and 4 columns based on 48 pixel values belonging to the 21st to 32nd columns among the 128 pixel values included in the 5th to 8th rows of the entire image P1. By converting the resulting 16 pixel values into one pixel value, three pixel values of the entire image P1 are generated. Then, the transmission signal generation circuit 48 generates three pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the second row in the image signal SP.
  • the transmission signal generation circuit 48 generates one pixel value indicating black.
  • the transmission signal generation circuit 48 generates 4 pixels arranged in 2 rows and 2 columns based on 32 pixel values related to the partial image P2 among the 64 pixel values included in the 7th and 8th rows of the entire image P1. By converting one pixel value into one pixel value, eight pixel values relating to the partial image P2 are generated. Then, the transmission signal generation circuit 48 generates seven pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the third row in the image signal SP.
  • the transmission signal generation circuit 48 generates 4 rows and 4 columns based on 16 pixel values belonging to the 1st to 4th columns among the 128 pixel values included in the 9th to 12th rows of the entire image P1. By converting the 16 pixel values arranged in , into one pixel value, one pixel value relating to the entire image P1 is generated.
  • the transmission signal generation circuit 48 is arranged in 2 rows and 2 columns based on 8 pixel values belonging to the 5th to 8th columns of the 64 pixel values included in the 9th and 10th rows of the entire image P1. Two pixel values of the partial image P2 are generated by converting the four pixel values into one pixel value.
  • the transmission signal generation circuit 48 directly outputs eight pixel values related to the partial image P3 among the 32 pixel values included in the ninth row of the entire image P1.
  • the transmission signal generation circuit 48 is arranged in two rows and two columns based on eight pixel values belonging to the 17th to 20th columns of the 64 pixel values included in the 9th and 10th rows of the entire image P1.
  • Two pixel values of the partial image P2 are generated by converting the four pixel values into one pixel value.
  • the transmission signal generation circuit 48 generates the 4th row, 4th column based on the 48 pixel values belonging to the 21st to 32nd columns among the 128 pixel values included in the 9th to 12th rows of the entire image P1.
  • the transmission signal generation circuit 48 By converting the 16 pixel values arranged in to one pixel value, three pixel values relating to the entire image P1 are generated.
  • the transmission signal generation circuit 48 generates the image data of the fourth row in the image signal SP.
  • the transmission signal generation circuit 48 generates three pixel values indicating black.
  • the transmission signal generating circuit 48 directly outputs eight pixel values related to the partial image P3 among the 32 pixel values included in the tenth row of the entire image P1. Then, the transmission signal generation circuit 48 generates five pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the fifth row in the image signal SP.
  • the transmission signal generation circuit 48 generates one pixel value indicating black.
  • the transmission signal generation circuit 48 is arranged in 2 rows and 2 columns based on 8 pixel values belonging to the 5th to 8th columns of the 64 pixel values included in the 11th and 12th rows of the entire image P1.
  • Two pixel values of the partial image P2 are generated by converting the four pixel values into one pixel value.
  • the transmission signal generating circuit 48 directly outputs eight pixel values related to the partial image P3 among the 32 pixel values included in the 11th row of the entire image P1.
  • the transmission signal generation circuit 48 is arranged in two rows and two columns based on eight pixel values belonging to the 17th to 20th columns of the 64 pixel values included in the 11th and 12th rows of the entire image P1.
  • Two pixel values of the partial image P2 are generated by converting the four pixel values into one pixel value. Then, the transmission signal generation circuit 48 generates three pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the sixth row in the image signal SP.
  • the transmission signal generation circuit 48 generates three pixel values indicating black.
  • the transmission signal generation circuit 48 directly outputs eight pixel values related to the partial image P3 among the 32 pixel values included in the 12th row of the entire image P1. Then, the transmission signal generation circuit 48 generates five pixel values representing black. Thereby, the transmission signal generation circuit 48 generates the image data of the seventh row in the image signal SP.
  • the transmission signal generation circuit 48 converts 16 pixel values arranged in 4 rows and 4 columns into one pixel value for a portion of the entire image P1 that does not overlap with the partial image P2. Further, the transmission signal generation circuit 48 converts four pixel values arranged in two rows and two columns into one pixel value for a portion of the entire image P1 that overlaps the partial image P2 but does not overlap the partial image P3. Convert to The transmission signal generation circuit 48 outputs the pixel values as they are for the portion of the entire image P1 that overlaps the partial image P3. As a result, in the image signal SP, the resolution of the entire image P1 is lower than the resolution of the partial image P2, and the resolution of the partial image P2 is lower than the resolution of the partial image P3.
  • the transmission signal generation circuit 48 generates image data including a plurality of pixel values as shown in FIG. 44(B) based on the image generated by the image generation circuit 41. Then, the transmission signal generation circuit 48 generates an image signal SP including this image data and image position data indicating the position (parameters POSX, POSY) of the partial image P2 in the entire image P1.
  • FIG. 45 shows transmission bands in the display system 2 according to this modified example.
  • the image data included in the image signal SP includes 16 rows of image data in this example.
  • the display system 2 can reduce the amount of image data compared to the case where the entire image P1 before conversion is transmitted as it is.
  • FIG. 46 shows an example of signals output from the display controller 56.
  • A shows the waveform of the vertical synchronizing signal VS_OUT
  • B shows the waveform of the horizontal synchronizing signal HS_OUT
  • C shows the waveform of the horizontal synchronizing signal HS_OUT.
  • the waveform of the vertical data enable signal VDE_OUT is shown
  • D shows the data signal DATA_OUT.
  • a pulse occurs in the vertical synchronization signal VS_OUT, and the vertical period V starts (FIG. 46(A)). Further, a pulse is generated in the horizontal synchronization signal HS_OUT each time the horizontal period H starts (FIG. 46(B)).
  • the vertical data enable signal VDE_OUT changes from low level to high level (FIG. 46(C)).
  • the display controller 56 outputs 16 pieces of image data as the data signal DATA_OUT over 16 horizontal periods H (FIG. 46(D)).
  • the display controller 56 drives a plurality of pixels PIX in the display panel 27 in units of 16 pixels PIX arranged in 4 rows and 4 columns based on the image data related to the entire image P1 included in the data signal DATA_OUT. control to The display controller 56 drives the plurality of pixels PIX in the display panel 27 in units of four pixels PIX arranged in two rows and two columns, based on image data relating to the partial image P2 included in the data signal DATA_OUT. to control. Further, the display controller 56 controls the plurality of pixels PIX in the display panel 27 to drive one pixel PIX as a unit based on the data related to the partial image P3 included in the data signal DATA_OUT.
  • FIG. 47 shows an example of the data signal DATA_OUT at timings t62 to t69 in FIG. 46 and the display driving operation based on the data signal DATA_OUT.
  • the display panel 27 performs the display driving operation for the four pixel lines L indicated by W9 in FIG. 47 during the period from timing t62 to t63.
  • the pixel signal generation circuit 32 writes pixel signals relating to the entire image P1 to the two pixel lines L indicated by reference numeral W9 in FIG.
  • the display panel 27 performs the display driving operation for the four pixel lines L indicated by reference numeral W10 in FIG. 47 during the period from timing t63 to t65.
  • the display controller 56 In the period from timing t63 to t64, the display controller 56, as shown in FIG. 3 pixel values of the entire image P1 at the 10th to 12th pixels, and four pixel values of black at the 13th to 16th pixels are output as the data signal DATA_OUT.
  • the data number NSP of this image data is "2".
  • FIG. 48 shows an example of the display driving operation for the four pixel lines L indicated by symbol W10 in FIG. shows the behavior in As shown in FIG. 48A, at timings t63 to t64, the pixel signal generation circuit 32 writes pixel signals corresponding to the 1st to 12th pixel values to the pixels PIX corresponding to these pixel values.
  • the display controller 56 In the next period from timing t64 to t65, the display controller 56, as shown in FIG. and seven pixel values representing black at the 10th to 16th pixels are output as the data signal DATA_OUT.
  • the pixel signal generation circuit 32 outputs pixel signals corresponding to eight pixel values, 2nd to 9th, to the pixels PIX corresponding to these pixel values. Write. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the pixel signal generation circuit 32 as shown in FIGS. 48A and 48B, during the period from timing t63 to t65, all four pixel lines L indicated by symbol W10 in FIG. A pixel signal related to the entire image P1 or a pixel signal related to the partial image P2 is written to the pixels PIX of the .
  • the display panel 27 performs the display driving operation for the four pixel lines L indicated by the symbol W11 in FIG. 47 during the period from timing t65 to t69.
  • the display controller 56 First, in the period from timing t65 to t66, the display controller 56, as shown in FIG. the 4th to 11th pixel values of the partial image P3, the 12th and 13th pixel values of the partial image P1, and the 14th to 16th pixel values of the full image P1.
  • the image data including the three pixel values is output as the data signal DATA_OUT.
  • the data number NSP of this image data is "4".
  • FIG. 49 shows an example of the display driving operation for the four pixel lines L indicated by symbol W11 in FIG. (C) shows the operation at timings t67 to t68, and (D) shows the operation at timings t68 to t69.
  • the pixel signal generation circuit 32 writes pixel signals corresponding to the 1st to 16th pixel values to the pixels PIX corresponding to these pixel values.
  • the display controller 56 In the next period from timing t66 to t67, the display controller 56, as shown in FIG. image data including one pixel value and five pixel values representing black at the 12th to 16th pixel values are output as the data signal DATA_OUT.
  • the data number NSP of this image data is "5".
  • the pixel signal generation circuit 32 outputs pixel signals corresponding to the eight pixel values of the 4th to 11th pixels to the pixels PIX corresponding to these pixel values. Write. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the display controller 56 In the next period from timing t67 to t68, the display controller 56, as shown in FIG. 8 pixel values of the partial image P3 at the 4th to 11th pixel values, 2 pixel values of the partial image P1 at the 12th and 13th pixels, and 3 pixels representing black at the 14th to 16th pixels
  • the image data including the values are output as the data signal DATA_OUT.
  • the data number NSP of this image data is "6".
  • the pixel signal generation circuit 32 writes pixel signals corresponding to the 2nd to 13th pixel values to the pixels PIX corresponding to these pixel values. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the display controller 56 In the next period from timing t68 to t69, the display controller 56, as shown in FIG. image data including one pixel value and five pixel values representing black at the 12th to 16th pixel values are output as the data signal DATA_OUT.
  • the data number NSP of this image data is "7".
  • the pixel signal generation circuit 32 outputs pixel signals corresponding to the eight pixel values of the 4th to 11th pixels to the pixels PIX corresponding to these pixel values. Write. Also, the pixel signal generation circuit 32 does not write pixel values to pixels PIX other than these pixels PIX.
  • the pixel signal generation circuit 32 as shown in FIGS. 49A to 49D, during the period of timings t65 to t69, all the four pixel lines L indicated by symbol W11 in FIG. A pixel signal related to the entire image P1, a pixel signal related to the partial image P2, or a pixel signal related to the partial image P3 is written to the pixels PIX of the .
  • the display controller 56 and the display panel 27 operate in the same manner after this. Then, at timing t70, the vertical data enable signal VDE_OUT changes from high level to low level (FIG. 46(C)). Then, at timing t71, this vertical period V ends and the next vertical period V starts.
  • Modifications 1-1 and 1-4 of the first embodiment may be applied to the display system 2 according to the above embodiment.
  • FIG. 50 shows an example of the appearance of the head mounted display 110.
  • the head-mounted display 110 has, for example, ear hooks 112 on both sides of an eyeglass-shaped display 111 to be worn on the user's head.
  • the technology according to the above embodiments and the like can be applied to such a head mounted display 110 .
  • FIG. 51 shows an example of the appearance of another head mounted display 120.
  • the head-mounted display 120 is a transmissive head-mounted display having a body portion 121 , an arm portion 122 and a lens barrel portion 123 .
  • This head mounted display 120 is attached to glasses 128 .
  • the body section 121 has a control board and a display section for controlling the operation of the head mounted display 120 .
  • the display section emits image light for a display image.
  • the arm portion 122 connects the body portion 121 and the lens barrel portion 123 and supports the lens barrel portion 123 .
  • the lens barrel section 123 projects the image light supplied from the body section 121 via the arm section 122 toward the user's eyes via the lens 129 of the spectacles 128 .
  • the technology according to the above embodiments and the like can be applied to such a head mounted display 120 .
  • the head mounted display 120 is a so-called light guide plate type head mounted display, it is not limited to this, and may be, for example, a so-called bird bath type head mounted display.
  • This Birdbus-type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information towards a mirror, which reflects the light towards the user's eye. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.
  • FIG. 52A and 52B show an example of the appearance of the digital still camera 130, FIG. 52A showing a front view and FIG. 52B showing a rear view.
  • This digital still camera 130 is a lens-interchangeable single-lens reflex camera, and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. have.
  • the imaging lens unit 312 is an interchangeable lens unit, and is provided near the center of the front surface of the camera body 311 .
  • the grip portion 133 is provided on the front left side of the camera main body portion 311, and the photographer grips this grip portion 133. As shown in FIG.
  • the monitor 134 is provided on the left side of the center of the rear surface of the camera body 131 .
  • the electronic viewfinder 135 is provided above the monitor 14 on the back of the camera body 131 . By looking through the electronic viewfinder 135, the photographer can view the optical image of the subject guided from the photographing lens unit 132 and determine the composition.
  • the technology according to the above embodiments and the like can be applied to the electronic viewfinder 135 .
  • FIG. 53 shows an example of the appearance of the television device 140.
  • Television apparatus 140 has image display screen portion 141 including front panel 142 and filter glass 143 .
  • the technology according to the above embodiments and the like can be applied to the video display screen unit 141 .
  • FIG. 54 shows an example of the appearance of smartphone 150 .
  • the smartphone 150 has a display unit 151 that displays various types of information, and an operation unit 152 that includes buttons and the like for receiving operation input by the user.
  • the technology according to the above embodiments and the like can be applied to this display unit 151 .
  • FIG. 55A and 55B show a configuration example of a vehicle to which the technology of the present disclosure is applied.
  • FIG. 55A shows an example of the inside of the vehicle viewed from the rear of the vehicle 200
  • FIG. 1 shows an example of the interior of a vehicle viewed from the left rear of the vehicle.
  • the vehicle of FIGS. 55A and 55B has a center display 201, a console display 202, a head-up display 203, a digital rear mirror 204, a steering wheel display 205, and a rear entertainment display 106.
  • the center display 201 is arranged on the dashboard 261 at a location facing the driver's seat 262 and the front passenger's seat 263 .
  • FIG. 55A shows an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the front passenger's seat 263 side, but the screen size and arrangement location of the center display 201 are not limited to this.
  • Center display 201 can display information detected by various sensors. As a specific example, the center display 201 displays an image captured by an image sensor, an image of the distance to obstacles in front of and to the sides of the vehicle measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. can be displayed.
  • Center display 201 can be used, for example, to display at least one of safety-related information, operation-related information, lifelogs, health-related information, authentication/identification-related information, and entertainment-related information.
  • Safety-related information is information based on sensor detection results, such as dozing off detection, looking away detection, tampering detection by children in the car, seatbelt wearing status, and occupant abandonment detection.
  • the operation-related information is information of a gesture related to the operation of the occupant detected using a sensor. Gestures may include operations of various facilities in the vehicle, such as operations of an air conditioner, a navigation device, an AV (Audio Visual) device, a lighting device, and the like.
  • the lifelog includes lifelogs of all crew members. For example, the lifelog includes activity records of each passenger. By acquiring and storing the lifelog, it is possible to check what kind of condition the occupant was in when the accident occurred.
  • Health-related information includes occupant body temperature detected using a temperature sensor and occupant health information inferred based on the detected body temperature. Alternatively, information on the health condition of the occupant may be inferred based on the occupant's face imaged by an image sensor. Also, information on the health condition of the crew member may be estimated based on the content of the crew member's response obtained by having a conversation with the crew member using automatic voice.
  • the authentication/identification-related information includes information such as a keyless entry function that performs face authentication using a sensor, and a seat height and position automatic adjustment function for face identification.
  • the entertainment-related information includes operation information of the AV apparatus by the passenger detected by the sensor, content information to be displayed suitable for the passenger detected and recognized by the sensor, and the like.
  • the console display 202 can be used, for example, to display lifelog information.
  • Console display 202 is located near shift lever 265 on center console 264 between driver's seat 262 and passenger's seat 263 .
  • a console display 202 is also capable of displaying information sensed by various sensors. Also, the console display 202 may display an image of the surroundings of the vehicle captured by an image sensor, or may display an image of the distance to obstacles around the vehicle.
  • the head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262 .
  • the heads-up display 203 can be used to display at least one of safety-related information, operation-related information, lifelogs, health-related information, authentication/identification-related information, and entertainment-related information, for example. Since the head-up display 203 is often placed virtually in front of the driver's seat 262, it displays information directly related to vehicle operation, such as vehicle speed, fuel level, and battery level. Suitable for
  • the digital rear mirror 204 can display not only the rear of the vehicle, but also the state of the passengers in the rear seats, so it can be used, for example, to display the lifelog information of the passengers in the rear seats.
  • the steering wheel display 205 is arranged near the center of the steering wheel 267 of the vehicle.
  • Steering wheel display 205 can be used, for example, to display at least one of safety-related information, operation-related information, lifelogs, health-related information, authentication/identification-related information, and entertainment-related information.
  • life log information such as the driver's body temperature and information regarding the operation of AV equipment and air conditioning equipment.
  • the rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the front passenger's seat 263, and is for viewing by passengers in the rear seats.
  • Rear entertainment display 206 can be used, for example, to display at least one of safety-related information, operation-related information, lifelogs, health-related information, authentication/identification-related information, and entertainment-related information.
  • the rear entertainment display 206 may display, for example, information relating to the operation of AV equipment and air conditioning equipment, or the results of measuring the body temperature of passengers in the rear seats with the temperature sensor 5 .
  • center display 201 console display 202, head-up display 203, digital rear mirror 204, steering wheel display 205, and rear entertainment display 206.
  • the head mounted display 20 is provided with the acceleration sensor 22 and the eye tracking sensor 23, but the present invention is not limited to this, and for example, these sensors may not be provided.
  • the image generation circuit 11 identifies the portion of the entire image P1 where the image changes as the partial image P2.
  • the present technology has been applied to a head-mounted display in the above embodiments and the like, it is not limited to this, and can be applied to various electronic devices capable of displaying images, such as monitors and projectors. .
  • This technology can be applied not only to the closed systems shown in the above embodiments and the like, but also to video see-through systems and mixed reality systems.
  • This technology can also be applied to various simulators such as flight simulators, gaming, and projection mapping.
  • the display panel 27 shown in FIG. 5 is used, but the present invention is not limited to this.
  • the display panel 27E according to this modification will be described in detail below.
  • FIG. 56 shows a configuration example of the display panel 27E.
  • the display panel 27E has a pixel array 31E, a pixel signal generation circuit 32, a scanning circuit 33, and a drive circuit 34E.
  • the pixel array 31E has multiple signal lines SGL, multiple control lines CTL, multiple control lines WSEN, and multiple pixels PIX.
  • the plurality of control lines WSEN extend in the vertical direction (the vertical direction in FIG. 56) and are arranged side by side in the horizontal direction (the horizontal direction in FIG. 56).
  • Each of the plurality of control lines WSEN supplies control signals generated by the drive circuit 34E to the pixels PIX.
  • the drive circuit 34E generates a control signal and applies the generated control signal to a plurality of control lines WSEN, thereby selecting a pixel PIX to which the pixel signal generated by the pixel signal generation circuit 32 is written, out of the plurality of pixels PIX. It is configured to control which pixels PIX are written to.
  • FIG. 57 shows a configuration example of the pixel PIX.
  • a pixel array having the pixels PIX has a control line WSL.
  • Control lines CTL shown in FIG. 56 include this control line WSL.
  • the pixel PIX has transistors MN01 to MN03, a capacitor C01, and a light emitting element EL.
  • the transistors MN01 to MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
  • the transistor MN01 has a gate connected to the control line WSEN, a drain connected to the signal line SGL, and a source connected to the drain of the transistor MN02.
  • the transistor MN02 has a gate connected to the control line WSL, a drain connected to the source of the transistor MN01, and a source connected to the gate of the transistor MN03 and the capacitor C01.
  • One end of the capacitor C01 is connected to the source of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to the source of the transistor MN03 and the anode of the light emitting element EL.
  • the transistor MN03 has a gate connected to the source of the transistor MN02 and one end of the capacitor C01, a drain connected to the power supply line VCCP, and a source connected to the other end of the capacitor C01 and the anode of the light emitting element EL.
  • the light emitting element EL is, for example, an organic EL light emitting element, and has an anode connected to the source of the transistor MN03 and the other end of the capacitor C01, and a cathode connected to the power supply line Vcath.
  • the voltage across the capacitor C01 is set based on the pixel signal supplied from the signal line SGL by turning on the transistors MN01 and MN02.
  • the transistor MN03 causes a current corresponding to the voltage across the capacitor C01 to flow through the light emitting element EL.
  • the light emitting element EL emits light based on the current supplied from the transistor MN03.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the display controller 26 displays a plurality of pixels PIX on the display panel 27E based on the image data of the entire image P1 during the period from timing t14 to t15, as shown in FIG. 12(A). Control is performed to drive four pixels PIX as a unit.
  • the scanning circuit 33 of the display panel 27E scans the plurality of pixels PIX with two pixel lines L as the scanning unit US.
  • the drive circuit 34E activates (high level) all the control lines WSEN.
  • the pixel signal generation circuit 32 applies the same pixel signal to two signal lines SGL adjacent to each other. As a result, the same pixel signal is written to the four pixels PIX in the two pixel lines L selected. In this manner, the display panel 27E drives a plurality of pixels PIX with four pixels PIX as a unit UD.
  • the display controller 26 controls the display panel 27E based on the image data of the partial image P2 and the data on the position of this partial image P2 during the period from timing t15 to t16.
  • the plurality of pixels PIX in are controlled to be driven in units of one pixel PIX.
  • the scanning circuit 33 of the display panel 27E scans the plurality of pixels PIX with one pixel line L as the scanning unit US.
  • the drive circuit 34E activates (high level) the plurality of control lines WSEN related to the area corresponding to the partial image P2, and deactivates (low level) the other plurality of control lines WSEN.
  • the pixel signal generation circuit 32 applies a plurality of pixel signals to a plurality of signal lines SGL related to a region corresponding to the partial image P2 among the plurality of signal lines SGL.
  • a plurality of pixel signals are written to a plurality of pixels PIX related to the area corresponding to the partial image P2.
  • pixel signals are not written to the plurality of pixels PIX related to areas other than the area corresponding to the partial image P2.
  • the display panel 27E drives a plurality of pixels PIX with one pixel PIX as a unit UD.
  • the display controller 26 controls the display panel 27E based on the image data of the partial image P2 and the data on the position of this partial image P2 during the period from timing t16 to t17.
  • the plurality of pixels PIX in the plurality of pixels PIX arranged in the region corresponding to the partial image P2 are controlled to be driven in units of one pixel PIX. This operation is the same as the operation during the period from timing t15 to t16 shown in FIG. 12(B).
  • the configuration of the pixel PIX is not limited to the example of FIG. Some examples are given below.
  • FIG. 58 shows another configuration example of the pixel PIX.
  • a pixel array having this pixel PIX has a control line WSL, a control line DSL, and a control line AZSL.
  • Control lines CTL shown in FIG. 56 include these control lines WSL, DSL and AZSL.
  • This pixel PIX has transistors MP11 and MP12, capacitors C11 and C12, transistors MP13 to MP15, and a light emitting element EL.
  • the transistors MP11 to MP15 are P-type MOSFETs.
  • the transistor MP11 has a gate connected to the control line WSEN, a source connected to the signal line SGL, and a drain connected to the source of the transistor MP12.
  • the transistor MP12 has a gate connected to the control line WSL, a source connected to the drain of the transistor MP11, and a drain connected to the gate of the transistor MP14 and the capacitor C12.
  • One end of the capacitor C11 is connected to the power supply line VCCP, and the other end is connected to the capacitor C12, the drain of the transistor MP13, and the source of the transistor MP14.
  • One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14.
  • the transistor MP13 has a gate connected to the control line DSL, a source connected to the power supply line VCCP, and a drain connected to the source of the transistor MP14, the other end of the capacitor C11, and one end of the capacitor C12.
  • the transistor MP14 has a gate connected to the drain of the transistor MP12 and the other end of the capacitor C12, a source connected to the drain of the transistor MP13, the other end of the capacitor C11 and one end of the capacitor C12, and a drain connected to the anode of the light emitting element EL and the transistor.
  • the transistor MP15 has a gate connected to the control line AZSL, a source connected to the drain of the transistor MP14 and the anode of the light emitting element EL, and a drain connected to the power supply line VSS.
  • the voltage across the capacitor C12 is set based on the pixel signal supplied from the signal line SGL by turning on the transistors MP11 and MP12.
  • the transistor MP13 is turned on and off based on the signal on the control line DSL.
  • the transistor MP14 causes a current corresponding to the voltage across the capacitor C12 to flow through the light emitting element EL while the transistor MP13 is on.
  • the light emitting element EL emits light based on the current supplied from the transistor MP14.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the transistor MP15 is turned on and off based on the signal on the control line AZSL. While the transistor MP15 is on, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage of the power supply line VSS.
  • FIG. 59 shows another configuration example of the pixel PIX.
  • a pixel array having the pixels PIX has a control line WSL, a control line DSL, and a control line AZSL.
  • Control lines CTL shown in FIG. 56 include these control lines WSL, DSL and AZSL.
  • This pixel PIX has transistors MN21 and MN22, a capacitor C21, transistors MN23 to MN25, and a light emitting element EL.
  • the transistors MN21 to MN25 are N-type MOSFETs.
  • the transistor MN21 has a gate connected to the control line WSEN, a drain connected to the signal line SGL, and a source connected to the drain of the transistor MN22.
  • the transistor MN22 has a gate connected to the control line WSL, a drain connected to the source of the transistor MN21, and a source connected to the gate of the transistor MN24 and the capacitor C21.
  • One end of the capacitor C21 is connected to the source of the transistor MN22 and the gate of the transistor MN24, and the other end is connected to the source of the transistor MN24, the drain of the transistor MN25 and the anode of the light emitting element EL.
  • the transistor MN23 has a gate connected to the control line DSL, a drain connected to the power supply line VCCP, and a source connected to the drain of the transistor MN24.
  • the gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, and the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light emitting element EL.
  • the transistor MN25 has a gate connected to the control line AZSL, a drain connected to the source of the transistor MN24, the other end of the capacitor C21 and the anode of the light emitting element EL, and a source connected to the power supply line VSS.
  • the voltage across the capacitor C21 is set based on the pixel signal supplied from the signal line SGL by turning on the transistors MN21 and MN22.
  • the transistor MN23 is turned on and off based on the signal on the control line DSL.
  • the transistor MN24 causes a current corresponding to the voltage across the capacitor C21 to flow through the light emitting element EL while the transistor MN23 is on.
  • the light emitting element EL emits light based on the current supplied from the transistor MN24.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the transistor MN25 is turned on and off based on the signal on the control line AZSL. While the transistor MN25 is on, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage of the power supply line VSS.
  • FIG. 60 shows another configuration example of the pixel PIX.
  • a pixel array having this pixel PIX has a control line WSL, a control line DSL, and control lines AZSL1 and AZSL2.
  • Control lines CTL shown in FIG. 56 include control lines WSL, DSL, AZSL1 and AZSL2.
  • This pixel PIX has transistors MP31 and MP32, a capacitor C31, transistors MP33 to MP36, and a light emitting element EL.
  • the transistors MP31 to MP36 are P-type MOSFETs.
  • the transistor MP31 has a gate connected to the control line WSEN, a source connected to the signal line SGL, and a drain connected to the source of the transistor MP32.
  • the transistor MP32 has a gate connected to the control line WSL, a source connected to the drain of the transistor MP31, and a drain connected to the gate of the transistor MP33, the source of the transistor MP34, and the capacitor C31.
  • One end of the capacitor C31 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP32, the gate of the transistor MP33, and the source of the transistor MP34.
  • Transistor MP34 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP32, a gate of transistor MP33 and the other end of capacitor C31, and a drain connected to the drain of transistor MP33 and the source of transistor MP35.
  • the transistor MP35 has a gate connected to the control line DSL, a source connected to the drains of the transistors MP33 and MP34, and a drain connected to the source of the transistor MP36 and the anode of the light emitting element EL.
  • the transistor MP36 has a gate connected to the control line AZSL2, a source connected to the drain of the transistor MP35 and the anode of the light emitting element EL, and a drain connected to the power supply line VSS.
  • the voltage across the capacitor C31 is set based on the pixel signal supplied from the signal line SGL by turning on the transistors MP31 and MP32.
  • the transistor MP35 is turned on and off based on the signal on the control line DSL.
  • the transistor MP33 causes a current corresponding to the voltage across the capacitor C31 to flow through the light emitting element EL while the transistor MP35 is on.
  • the light emitting element EL emits light based on the current supplied from the transistor MP33.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the transistor MP34 is turned on and off based on the signal on the control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other.
  • the transistor MP36 is turned on and off based on the signal on the control line AZSL2. During the period in which the transistor MP36 is on, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage of the power supply line VSS.
  • FIG. 61 shows another configuration example of the pixel PIX.
  • a pixel array having this pixel PIX has control lines WSL1 and WSL2, a control line DSL, control lines AZSL1 and AZSL2, signal lines SGL1 and SGL2, capacitors C48 and C49, and a transistor MP49.
  • the control lines CTL shown in FIG. 56 include control lines WSL1, WSL2, DSL, AZSL1 and AZSL2.
  • Signal lines SGL shown in FIG. 56 include signal lines SGL1 and SGL2.
  • One end of the capacitor C48 is connected to the signal line SGL1, and the other end is connected to the power supply line VSS.
  • One end of the capacitor C49 is connected to the signal line SGL1, and the other end is connected to the signal line SGL2.
  • the transistor MP49 is a P-type MOSFET, and has a gate connected to the control line WSL2, a source connected to the signal line SGL1, and a drain connected to the signal line SGL2.
  • the pixel PIX has transistors MP41 and MP42, a capacitor C41, transistors MP43 to MP46, and a light emitting element EL.
  • the transistors MP41 to MP46 are P-type MOSFETs.
  • the transistor MP41 has a gate connected to the control line WSEN, a source connected to the signal line SGL2, and a drain connected to the source of the transistor MP42.
  • the transistor MP42 has a gate connected to the control line WSL1, a source connected to the drain of the transistor MP41, and a drain connected to the gate of the transistor MP43 and the capacitor C41.
  • One end of the capacitor 41 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP42 and the gate of the transistor MP43.
  • the transistor MP43 has a gate connected to the drain of the transistor MP42 and the other end of the capacitor C41, a source connected to the power supply line VCCP, and a drain connected to the sources of the transistors MP44 and MP45.
  • the transistor MP44 has a gate connected to the control line AZSL1, a source connected to the drain of the transistor MP43 and a source of the transistor MP45, and a drain connected to the signal line SGL2.
  • the transistor MP45 has a gate connected to the control line DSL, a source connected to the drain of the transistor MP43 and the source of the transistor MP44, and a drain connected to the source of the transistor MP46 and the anode of the light emitting element EL.
  • the transistor MP46 has a gate connected to the control line AZSL2, a source connected to the drain of the transistor MP45 and the anode of the light emitting element EL, and a drain connected to the power supply line VSS.
  • the voltage across the capacitor C41 is set based on the pixel signal supplied from the signal line SGL1 via the capacitor C49 by turning on the transistors MP41 and MP42.
  • the transistor MP45 is turned on and off based on the signal on the control line DSL.
  • the transistor MP43 causes a current corresponding to the voltage across the capacitor C41 to flow through the light emitting element EL while the transistor MP45 is on.
  • the light emitting element EL emits light based on the current supplied from the transistor MP43.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the transistor MP44 is turned on and off based on the signal on the control line AZSL1.
  • transistor MP44 While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other.
  • the transistor MP46 is turned on and off based on the signal on the control line AZSL2. While the transistor MP46 is on, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage of the power supply line VSS.
  • FIG. 62 shows another configuration example of the pixel PIX.
  • a pixel array having the pixels PIX has a control line WSL, a control line DSL, a control line AZSL, signal lines SGL1 and SGL2, and control units 70 and 80.
  • FIG. Control lines CTL shown in FIG. 56 include control lines WSL, DSL and AZSL.
  • Signal lines SGL shown in FIG. 56 include signal lines SGL1 and SGL2.
  • the control unit 70 has transistors MN71 and MP72, a capacitor C71, and a transistor MP73.
  • the transistor MN71 is an N-type MOSFET, and the transistors MP72 and MP73 are P-type MOSFETs.
  • a control signal is supplied to the gate of the transistor MN71, the drain is connected to the source of the transistor MP72 and the signal line SGL1, and the source is connected to the drain of the transistor MP72, the capacitor C71, and the drain of the transistor MP73.
  • a control signal is supplied to the gate of the transistor MP72, the source is connected to the drain of the transistor MN71 and the signal line SGL1, and the drain is connected to the source of the transistor MN71, the capacitor C71, and the drain of the transistor MP73.
  • Transistors MN71 and MP72 form a transmission gate.
  • One end of the capacitor C71 is connected to the source of the transistor MN71, the drain of the transistor MP72, and the drain of the transistor MP73, and the other end is connected to the signal line SGL2.
  • the transistor MP73 has a gate connected to the control line REFL, a source connected to the power supply line Vref, and a drain connected to the source of the transistor MN71, the drain of the transistor MP72, and the capacitor C71.
  • the control unit 80 has transistors MN81 and MP82, a capacitor C81, and transistors MP83, MN84, MP85 and MP86.
  • the transistors MN81 and MN84 are N-type MOSFETs
  • the transistors MP82, MP83, MP85 and MP86 are P-type MOSFETs.
  • the transistor MN81 has a gate supplied with a control signal, a drain connected to the source of the transistor MP82 and the signal line SGL1, and a source connected to the drain of the transistor MP82.
  • a control signal is supplied to the gate of the transistor MP82, the source is connected to the drain of the transistor MN81 and the signal line SGL1, and the drain is connected to the source of the transistor MN81.
  • Transistors MN81 and MP82 form a transmission gate.
  • a pixel signal generated by the pixel signal generation circuit 32 is supplied to the source of the transistor MN81 and the drain of the transistor MP82.
  • One end of the capacitor C81 is connected to the signal line SGL1, and the other end is connected to the power supply line VSS.
  • the transistor MP83 has a gate supplied with a control signal, a drain connected to the source of the transistor MN84 and the signal line SGL2, and a source connected to the drain of the transistor MN84 and the power supply line Vorst.
  • a control signal is supplied to the gate of the transistor MN84, the source is connected to the drain of the transistor MP83 and the signal line SGL2, and the drain is connected to the source of the transistor MP83 and the power supply line Vorst.
  • Transistors MP83 and MN84 form a transmission gate.
  • the transistor MP85 has a gate connected to the control line INIL, a drain connected to the signal line SGL2, and a source connected to the power supply line Vini.
  • the transistor MP86 has a gate connected to the control line ELL, a drain connected to the signal line SGL2, and a source connected to the power supply line Vel.
  • the pixel PIX has transistors MP91 and MP92, a capacitor C91, transistors MP93 to MP96, and a light emitting element EL.
  • the transistors MP91 to MP96 are P-type MOSFETs.
  • the transistor MP91 has a gate connected to the control line WSEN, a source connected to the signal line SGL2, and a drain connected to the source of the transistor MP92.
  • the transistor MP92 has a gate connected to the control line WSL, a source connected to the drain of the transistor MP91, and a drain connected to the gate of the transistor MP93 and the capacitor C91.
  • One end of the capacitor 91 is connected to the power supply line Vel, and the other end is connected to the drain of the transistor MP92 and the gate of the transistor MP93.
  • the transistor MP93 has a gate connected to the drain of the transistor MP92 and the other end of the capacitor C91, a source connected to the power supply line Vel, and a drain connected to the sources of the transistors MP94 and MP95.
  • the gate of transistor MP94 is connected to control line AZSL
  • the source is connected to the drain of transistor MP93 and the source of transistor MP95
  • the drain is connected to signal line SGL2.
  • the transistor MP95 has a gate connected to the control line DSL, a source connected to the drain of the transistor MP93 and the source of the transistor MP94, and a drain connected to the source of the transistor MP96 and the anode of the light emitting element EL.
  • the transistor MP96 has a gate connected to the control line AZSL, a source connected to the drain of the transistor MP95 and the anode of the light emitting element EL, and a drain connected to the power supply line VSS.
  • the pixel PIX when the transistors MP91 and MP92 are turned on, the pixel signal supplied via the transistors MN81 and MP82, the signal line SGL1, the transistors MN71 and MP72, the capacitor C71, and the signal line SGL2 is changed. Based on this, the voltage across capacitor C91 is set.
  • the transistor MP95 is turned on and off based on the signal on the control line DSL.
  • the transistor MP93 causes a current corresponding to the voltage across the capacitor C91 to flow through the light emitting element EL while the transistor MP95 is on.
  • the light emitting element EL emits light based on the current supplied from the transistor MP93.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • Transistors MP94 and MP96 are turned on and off based on the signal on control line AZSL. While transistor MP94 is on, the drain of transistor MP93 and the source of transistor MP95 are connected to signal line SGL2. While the transistor MP96 is on, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage of the power supply line Vorst.
  • the transistor MP85 is turned on and off based on the signal on the control line INIL
  • the transistor MP86 is turned on and off based on the signal on the control line ELL
  • the transistor MP73 is turned on and off based on the signal on the control line REFL.
  • the transistor MP85 When the transistor MP85 is turned on, the voltage of the signal line SGL2 is set to the voltage of the power supply line Vini, and when the transistor MP86 is turned on, the voltage of the signal line SGL2 is set to the voltage of the power supply line Vel.
  • the transistor MP73 When the transistor MP73 is turned on, one end of the capacitor C71 is initialized by setting it to the voltage of the power supply line Vref.
  • FIG. 63 shows another configuration example of the pixel PIX.
  • a pixel array having this pixel PIX has a control line WSL, a control line DSL, and control lines AZSL1 and AZSL2.
  • Control lines CTL shown in FIG. 56 include control lines WSL, DSL, AZSL1 and AZSL2.
  • This pixel PIX has transistors MP51 to MP54, a capacitor C51, transistors MP55 to MP60, and a light emitting element EL.
  • the transistors MP51-MP60 are P-type MOSFETs.
  • the transistor MP51 has a gate connected to the control line WSEN, a source connected to the signal line SGL, and a drain connected to the source of the transistor MP52.
  • the transistor MP52 has a gate connected to the control line WSL, a source connected to the drain of the transistor MP51, and a drain connected to the drain of the transistor MP53 and the source of the transistor MP54.
  • the transistor MP53 has a gate connected to the control line DSL, a source connected to the power supply line VCCP, and a drain connected to the drain of the transistor MP52 and the source of the transistor MP54.
  • the gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57 and capacitor C51, the source is connected to the drains of transistors MP52 and MP53, and the drain is connected to the sources of transistors MP58 and MP59.
  • Capacitor C51 may include two capacitors connected in parallel with each other.
  • the transistor MP55 has a gate connected to the control line AZSL1, a source connected to the gate of the transistor MP54, a drain of the transistor MP57 and the other end of the capacitor C51, and a drain connected to the source of the transistor MP56.
  • the transistor MP56 has a gate connected to the control line AZSL1, a source connected to the drain of the transistor MP55, and a drain connected to the power supply line VSS.
  • the transistor MP57 has a gate connected to the control line WSL, a drain connected to the gate of the transistor MP54, a source of the transistor MP55 and the other end of the capacitor C51, and a source connected to the drain of the transistor MP58.
  • the transistor MP58 has a gate connected to the control line WSL, a drain connected to the drain of the transistor MP57, and a source connected to the drain of the transistor MP54 and the source of the transistor MP59.
  • the transistor 59 has a gate connected to the control line DSL, a source connected to the drain of the transistor MP54 and the source of the transistor MP58, and a drain connected to the source of the transistor MP60 and the anode of the light emitting element EL.
  • the transistor MP60 has a gate connected to the control line AZSL2, a source connected to the drain of the transistor MP59 and the anode of the light emitting element EL, and a drain connected to the power supply line VSS.
  • the voltage across the capacitor C51 is set based on the pixel signal supplied from the signal line SGL by turning on the transistors MP51, MP52, MP54, MP58, and MP57.
  • the transistors MP53 and MP59 are turned on and off based on the signal on the control line DSL.
  • the transistor MP54 causes a current corresponding to the voltage across the capacitor C51 to flow through the light emitting element EL while the transistors MP53 and MP59 are on.
  • the light emitting element EL emits light based on the current supplied from the transistor MP54.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the transistors MP55 and MP56 are turned on and off based on the signal on the control line AZSL1.
  • the voltage of the gate of the transistor MP54 is initialized by setting it to the voltage of the power supply line VSS.
  • the transistor MP60 is turned on and off based on the signal on the control line AZSL2. While the transistor MP60 is on, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage of the power supply line VSS.
  • FIG. 64 shows another configuration example of the pixel PIX.
  • a pixel array having the pixels PIX has control lines WSENN, WSENP, control lines WSNL, WSPL, control lines AZL, and control lines DSL.
  • Control line WSEN shown in FIG. 56 includes control lines WSENN and WSENP.
  • Control line CTL shown in FIG. 56 includes control lines WSNL, WSPL, AZL and DSL.
  • the signal on the control line WSENN and the signal on the control line WSENP are signals inverted from each other.
  • the signal on the control line WSNL and the signal on the control line WSPL are signals inverted from each other.
  • the pixel PIX has transistors MN61, MP62, MN63, MP64, capacitors C61, C62, transistors MN65 to MN67, and a light emitting element EL.
  • Transistors MN61, MN63, MN65 to MN67 are N-type MOSFETs, and transistors MP62 and MP64 are P-type MOSFETs.
  • the transistor MN61 has a gate connected to the control line WSENN, a drain connected to the signal line SGL and the source of the transistor MP62, and a source connected to the drains of the transistors MP62, MN63 and MP64.
  • the transistor MP62 has a gate connected to the control line WSENP, a source connected to the signal line SGL and the drain of the transistor MN61, and a drain connected to the sources of the transistors MN61, MN63, and MP64.
  • the gate of the transistor MN63 is connected to the control line WSNL, the drain is connected to the source of the transistor MN61, the drain of the transistor MP62, and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gates of the transistor MN65.
  • the transistor MP64 has a gate connected to the control line WSPL, a source connected to the source of the transistor MN61, a drain of the transistor MP62 and a drain of the transistor MN63, and a drain connected to the source of the transistor MN63, the capacitors C61 and C62 and the gates of the transistor MN65.
  • connected to Capacitor C61 is configured using, for example, a MOM (Metal Oxide Metal) capacitor, and has one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to power supply line VSS2. be done.
  • MOM Metal Oxide Metal
  • capacitor C61 may be configured using, for example, a MOS capacitor or an MIM (Metal Insulator Metal) capacitor.
  • Capacitor C62 is configured using a MOS capacitor, for example, and has one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to power supply line VSS2.
  • the capacitor C62 may be configured using, for example, an MOM capacitor or an MIM capacitor.
  • the gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67.
  • the transistor MN66 has a gate connected to the control line AZL, a drain connected to the sources of the transistors MN65 and MN67, and a source connected to the power supply line VSS1.
  • the transistor MN67 has a gate connected to the control line DSL, a drain connected to the source of the transistor MN65 and a drain of the transistor MN66, and a source connected to the anode of the light emitting element EL.
  • the pixel PIX In the pixel PIX, at least one of the transistors MN61 and MP62 is turned on, and at least one of the transistors MN63 and MP64 is turned on. , the voltage across the capacitors C61 and C62 is set.
  • the transistor MN67 is turned on and off based on the signal on the control line DSL.
  • the transistor MN65 causes a current corresponding to the voltage across the capacitors C61 and C62 to flow through the light emitting element EL while the transistor MN67 is on.
  • the light emitting element EL emits light based on the current supplied from the transistor MP65.
  • the pixel PIX emits light with luminance according to the pixel signal.
  • the transistor MN66 may be turned on and off based on the signal on the control line AZL. Further, the transistor MN66 may function as a resistive element having a resistance value according to the signal on the control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.
  • This technology can be configured as follows. According to the present technology having the following configuration, power consumption can be reduced.
  • first image data having one or more pixel values included in a whole image of a first resolution, a partial image of a narrower image range than the whole image and a second resolution higher than the first resolution; a receiving circuit capable of receiving second image data having one or more pixel values included and third image data having one or more pixel values included in the entire image in this order; a display portion having a first plurality of pixels, a second plurality of pixels, and a third plurality of pixels; a first drive for driving the first plurality of pixels in units of a first number of pixels based on the first image data; and a second drive based on the second image data.
  • a display device comprising: a display drive circuit capable of performing a third drive of driving one pixel as a unit.
  • the one or more pixel values in the first image data are a plurality of pixel values in one or more line images included in the entire image; the one or more pixel values in the second image data are a plurality of pixel values in one or more line images included in the partial image;
  • the display device wherein the display driving circuit can sequentially perform the first driving, the second driving, and the third driving in this order.
  • the receiving circuit is In a first period, the first image data can be received; In a second period after the first period, predetermined image data representing one or more line images having predetermined pixel values can be received; In a third period after the second period, the second image data can be received; In a fourth period after the third period, the predetermined image data can be received, The display device according to any one of (2) to (4), wherein the third image data can be received in a fifth period after the fourth period.
  • the data received by the receiving circuit is subjected to compression processing,
  • the image restoration circuit is capable of performing restoration processing based on the reception result of the reception circuit,
  • the one or more pixel values in the first image data are one or more pixel values in one line image included in the whole image; the one or more pixel values in the second image data are one or more pixel values in one line image included in the partial image;
  • the display drive circuit can simultaneously perform the first drive, the second drive, and the third drive.
  • Each of the first image data, the second image data, and the third image data includes one or more pixel values indicating the luminance of the first color, one or more pixel values indicating the luminance of the second color.
  • the display device according to any one of (1) to (9), having a plurality of pixel values and one or a plurality of pixel values indicating luminance of the third color.
  • Each of the first image data, the second image data, and the third image data includes one or more pixel values indicating luminance, one or more pixel values indicating first color difference, and The display device according to any one of (1) to (9) above, which has one or more pixel values indicating a color difference of 2.
  • the second image data has one or more pixel values indicating luminance, one or more pixel values indicating first color difference, and one or more pixel values indicating second color difference; the number of one or more pixel values indicating the first color difference is less than the number of one or more pixel values indicating the luminance;
  • the display device according to any one of (1) to (9), wherein the number of one or more pixel values indicating the second color difference is smaller than the number of one or more pixel values indicating the luminance.
  • Each of the first image data and the third image data includes one or more pixel values indicating luminance, one or more pixel values indicating first color difference, and one or more pixel values indicating second color difference.
  • Each of the first image data and the third image data includes one or more pixel values indicating luminance, one or more pixel values indicating first color difference, and one or more pixel values indicating second color difference. has a pixel value of the number of one or more pixel values indicating the first color difference is less than the number of one or more pixel values indicating the luminance;
  • the display device according to any one of (1) to (9), wherein the number of one or more pixel values indicating the second color difference is smaller than the number of one or more pixel values indicating the luminance.
  • the display device includes a sensor capable of detecting which part of the display area of the display unit the user is observing; a transmission circuit capable of transmitting the detection result of the sensor to an image generation device capable of transmitting the first image data, the second image data, and the third image data;
  • the display device according to any one of (1) to (14), wherein the partial image is an image corresponding to the detection result of the sensor.
  • first image data having one or more pixel values included in a whole image of a first resolution, a partial image of a narrower image range than the whole image and a second resolution higher than the first resolution; an image generation device capable of transmitting second image data having one or more pixel values included and third image data having one or more pixel values included in the entire image in this order; a display device and The display device a receiving circuit capable of receiving the first image data, the second image data, and the third image data in this order; a display portion having a first plurality of pixels, a second plurality of pixels, and a third plurality of pixels; a first drive for driving the first plurality of pixels in units of a first number of pixels based on the first image data; and a second drive based on the second image data.
  • the image generation device can generate a frame image of the second resolution, can specify the partial image in the frame image, and can perform scanning in a first direction based on the frame image.
  • the display device includes a sensor capable of detecting which part of the display area of the display unit the user is observing; a transmission circuit capable of transmitting the detection result of the sensor to the image generation device;
  • the display system according to (17), wherein the image generation device can receive the detection result of the sensor transmitted from the transmission circuit, and can specify the partial image based on the detection result of the sensor.
  • first image data having one or more pixel values included in a whole image of a first resolution, a partial image of a narrower image range than the whole image and a second resolution higher than the first resolution; receiving second image data having one or more pixel values included and third image data having one or more pixel values included in the overall image in this order; performing a first drive of driving a first plurality of pixels in units of a first number of pixels based on the first image data; performing a second drive of driving a second plurality of pixels in units of a second number of pixels smaller than the first number based on the second image data; and a third drive of driving the third plurality of pixels in units of the first number of pixels based on the third image data.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Signal Processing (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
PCT/JP2022/037179 2021-11-10 2022-10-04 表示装置、表示システム、および表示駆動方法 Ceased WO2023084950A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2023559474A JPWO2023084950A1 (https=) 2021-11-10 2022-10-04
CN202280073249.8A CN118215954A (zh) 2021-11-10 2022-10-04 显示装置、显示系统及显示驱动方法
US18/707,485 US12475819B2 (en) 2021-11-10 2022-10-04 Display device, display system, and display driving method
EP22892450.2A EP4432271A4 (en) 2021-11-10 2022-10-04 DISPLAY DEVICE, DISPLAY SYSTEM AND DISPLAY CONTROL METHOD

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021183508 2021-11-10
JP2021-183508 2021-11-10

Publications (1)

Publication Number Publication Date
WO2023084950A1 true WO2023084950A1 (ja) 2023-05-19

Family

ID=86335518

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/037179 Ceased WO2023084950A1 (ja) 2021-11-10 2022-10-04 表示装置、表示システム、および表示駆動方法

Country Status (5)

Country Link
US (1) US12475819B2 (https=)
EP (1) EP4432271A4 (https=)
JP (1) JPWO2023084950A1 (https=)
CN (1) CN118215954A (https=)
WO (1) WO2023084950A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250232719A1 (en) * 2024-01-11 2025-07-17 Canon Kabushiki Kaisha Light emitting device, display device, photoelectric conversion device, electronic apparatus, illumination device, and moving body

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003219346A (ja) * 2002-01-17 2003-07-31 Seiko Epson Corp 画像データ生成装置、画像表示装置、画像データ生成方法、画像表示方法、画像データ生成プログラムを記録した媒体、画像表示プログラムを記録した媒体、画像データ生成プログラムおよび画像表示プログラム
JP2009122599A (ja) * 2007-11-19 2009-06-04 Fujifilm Corp 画像表示装置
JP2019197224A (ja) 2016-02-09 2019-11-14 株式会社ソニー・インタラクティブエンタテインメント 映像表示システム
JP2020504959A (ja) * 2016-12-29 2020-02-13 株式会社ソニー・インタラクティブエンタテインメント 視線追跡を用いたｖｒ、低遅延、無線ｈｍｄビデオストリーミングのためのフォービエイテッドビデオリンク
JP2020523688A (ja) * 2017-06-09 2020-08-06 株式会社ソニー・インタラクティブエンタテインメント フォービエイテッド（中心窩）レンダリングシステムのための時間的スーパーサンプリング
US20210089119A1 (en) * 2019-09-19 2021-03-25 Ati Technologies Ulc Multi-stream foveal display transport
US20210141449A1 (en) * 2017-09-27 2021-05-13 Apple Inc. Visual artifact mitigation of dynamic foveated displays
JP2021183508A (ja) 2020-05-22 2021-12-02 柳井紙工株式会社 組み立て式紙箱

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10475370B2 (en) * 2016-02-17 2019-11-12 Google Llc Foveally-rendered display
KR102028997B1 (ko) * 2017-11-29 2019-10-07 엘지디스플레이 주식회사 헤드 마운트 디스플레이 장치
US10720124B2 (en) * 2018-01-15 2020-07-21 Microsoft Technology Licensing, Llc Variable pixel rate display interfaces
WO2019209257A1 (en) * 2018-04-24 2019-10-31 Hewlett-Packard Development Company, L.P. Display devices including switches for selecting column pixel data

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003219346A (ja) * 2002-01-17 2003-07-31 Seiko Epson Corp 画像データ生成装置、画像表示装置、画像データ生成方法、画像表示方法、画像データ生成プログラムを記録した媒体、画像表示プログラムを記録した媒体、画像データ生成プログラムおよび画像表示プログラム
JP2009122599A (ja) * 2007-11-19 2009-06-04 Fujifilm Corp 画像表示装置
JP2019197224A (ja) 2016-02-09 2019-11-14 株式会社ソニー・インタラクティブエンタテインメント 映像表示システム
JP2020504959A (ja) * 2016-12-29 2020-02-13 株式会社ソニー・インタラクティブエンタテインメント 視線追跡を用いたｖｒ、低遅延、無線ｈｍｄビデオストリーミングのためのフォービエイテッドビデオリンク
JP2020523688A (ja) * 2017-06-09 2020-08-06 株式会社ソニー・インタラクティブエンタテインメント フォービエイテッド（中心窩）レンダリングシステムのための時間的スーパーサンプリング
US20210141449A1 (en) * 2017-09-27 2021-05-13 Apple Inc. Visual artifact mitigation of dynamic foveated displays
US20210089119A1 (en) * 2019-09-19 2021-03-25 Ati Technologies Ulc Multi-stream foveal display transport
JP2021183508A (ja) 2020-05-22 2021-12-02 柳井紙工株式会社 組み立て式紙箱

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4432271A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250232719A1 (en) * 2024-01-11 2025-07-17 Canon Kabushiki Kaisha Light emitting device, display device, photoelectric conversion device, electronic apparatus, illumination device, and moving body

Also Published As

Publication number Publication date
US12475819B2 (en) 2025-11-18
EP4432271A1 (en) 2024-09-18
JPWO2023084950A1 (https=) 2023-05-19
EP4432271A4 (en) 2025-02-19
US20250029522A1 (en) 2025-01-23
CN118215954A (zh) 2024-06-18

Similar Documents

Publication Publication Date Title
US9766458B2 (en) Image generating system, image generating method, and information storage medium
JP2009531979A (ja) 立体メガネシャッタを制御するシステム、方法、及びコンピュータプログラム製品
CN109427283B (zh) 图像产生方法和使用该方法的显示装置
US20110012904A1 (en) System, method, and computer program product for controlling stereo glasses shutters
WO2023084950A1 (ja) 表示装置、表示システム、および表示駆動方法
CN114860062B (zh) 图像的显示方法、装置、可读介质和电子设备
JP7826307B2 (ja) 表示装置、表示システム、および表示駆動方法
WO2023176166A1 (ja) 表示装置及び電子機器
US20190122643A1 (en) Image processing system, image processing apparatus, and program
WO2023100468A1 (ja) 表示装置、表示システム、および表示方法
KR102422036B1 (ko) 낮은 레이턴시 가상 현실을 구동 및 보상하는 표시장치
WO2025100488A1 (ja) 表示装置及び電子機器
US12444336B2 (en) Display device and electronic apparatus
WO2025239226A1 (ja) 表示装置及び電子機器
US12451093B2 (en) Display device with pulse width modulation signal generation unit
WO2025013772A1 (ja) 表示装置
WO2025258267A1 (ja) 表示装置、ディスプレイコントローラおよび電子機器
CN121666612A (zh) 显示装置
CN110010082B (zh) 用于防止显示闪烁的设备、系统和方法
WO2026029160A1 (ja) 表示装置及び電子機器
KR20250115631A (ko) 표시 장치
WO2025013397A1 (ja) 表示装置
WO2025018102A1 (ja) 表示装置および電子機器
WO2025182707A1 (ja) 表示装置
WO2026074816A1 (ja) 制御回路、表示装置、及び表示システム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22892450

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023559474

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 202280073249.8

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 18707485

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2022892450

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022892450

Country of ref document: EP

Effective date: 20240610

WWG Wipo information: grant in national office

Ref document number: 18707485

Country of ref document: US