WO2023082872A1 - 用于配置存储器的方法, 装置和终端 - Google Patents

用于配置存储器的方法, 装置和终端 Download PDF

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Publication number
WO2023082872A1
WO2023082872A1 PCT/CN2022/121446 CN2022121446W WO2023082872A1 WO 2023082872 A1 WO2023082872 A1 WO 2023082872A1 CN 2022121446 W CN2022121446 W CN 2022121446W WO 2023082872 A1 WO2023082872 A1 WO 2023082872A1
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Prior art keywords
memory
channel condition
block
time unit
condition parameter
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PCT/CN2022/121446
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English (en)
French (fr)
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熊晓竹
郭青云
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Oppo广东移动通信有限公司
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Publication of WO2023082872A1 publication Critical patent/WO2023082872A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
    • H04W16/22—Traffic simulation tools or models
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • Embodiments of the present application relate to the field of communication technologies, and more specifically, relate to a method, device and terminal for configuring a memory.
  • the terminal During downlink reception, the terminal needs to access memory, such as double data rate synchronous dynamic random access memory (DDR). Therefore, the voltage and/or frequency of the memory needs to be set before data accesses the memory to match the throughput of the memory.
  • memory such as double data rate synchronous dynamic random access memory (DDR). Therefore, the voltage and/or frequency of the memory needs to be set before data accesses the memory to match the throughput of the memory.
  • DDR double data rate synchronous dynamic random access memory
  • the present application provides a prediction method, device and terminal.
  • a method for configuring a memory including: predicting a first channel condition parameter, wherein the first channel condition parameter is used to indicate the channel condition of the terminal in a first time unit after the current time unit; according to The first channel condition parameter, the first modulation and coding strategy configured by the terminal, and the pre-stored mapping relationship information, determine a coding block corresponding to the first channel condition parameter and the first modulation and coding strategy The first block error rate, wherein the mapping relationship information is used to indicate the mapping relationship among the channel condition parameters, modulation and coding strategies, and the block error rate of the coding block; according to the first block error rate, determine the The throughput rate of the memory of the terminal in the first time unit, where the memory is used to store the data of the coding block included in the first transmission block transmitted within the first time unit.
  • an apparatus for configuring a memory including: a prediction module configured to predict a first channel condition parameter, wherein the first channel condition parameter is used to indicate a first time after the current time unit of the terminal the channel condition of the unit; the processing module,
  • mapping relationship information is used to indicate the mapping relationship between the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block; according to the first block error rate rate, determining the throughput rate of the memory of the terminal in the first time unit, where the memory is used to store the data of the coding block included in the first transmission block transmitted in the first time unit.
  • a chip including the device for configuring a memory according to the second aspect.
  • a terminal including a memory and a processor.
  • the memory is used to store codes
  • the processor is used to execute the codes stored in the memory to perform the method as described in the first aspect.
  • a computer-readable storage medium on which codes for executing the method described in the first aspect are stored.
  • a computer program product including a plurality of instructions, and when executed by a computing device, the instructions implement the method as described in the first aspect.
  • FIG. 1 is a schematic diagram of a system architecture to which the embodiment of the present application can be applied.
  • Fig. 2 is a schematic flowchart of a method for configuring a memory provided by an embodiment of the present application.
  • FIG. 3 is an example diagram of a possible implementation of step S230 in FIG. 2 .
  • FIG. 4 is an example diagram of an implementation manner of the method shown in FIG. 2 in an initial transmission scenario.
  • FIG. 5 is an example diagram of an implementation manner of the method shown in FIG. 2 in a retransmission scenario.
  • FIG. 6 is a schematic structural diagram of an apparatus for configuring a memory provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a terminal provided by an embodiment of the present application.
  • the embodiment of the present application may be applied to the communication system 100 shown in FIG. 1 .
  • the communication system 100 is a cellular communication system.
  • the cellular communication system may be, for example, a long term evolution (long term evolution, LTE) system, a fifth generation (5th generation, 5G) system, or a new radio (new radio, NR).
  • LTE long term evolution
  • 5G fifth generation
  • NR new radio
  • the communication system 100 may include a network device 110 (such as a base station) and a terminal 120 .
  • the terminal 120 may be a mobile station, a user equipment, a mobile terminal, a mobile phone (mobile phone), a tablet computer (Pad), a notebook computer, a palmtop computer, and the like.
  • the network device 110 may send downlink data to the terminal 120 through a downlink.
  • the downlink data may be, for example, a physical downlink shared channel (physical downlink shared channel, PDSCH).
  • the terminal 120 may perform a decoding operation on the PDSCH. If the decoding is wrong, the terminal 120 may request the network device 110 to perform retransmission based on a hybrid automatic repeat request (HARQ) mechanism. Whether the decoding is correct or the decoding is wrong, the terminal 120 may need to perform data access to the memory. For example, during the initial data transmission process, the terminal 120 may need to store data that has been decoded incorrectly to the HARQ memory on the memory.
  • HARQ hybrid automatic repeat request
  • the terminal 120 may need to first read the data that fails to be decoded stored in the HARQ memory of the memory to the on-chip memory, so as to combine it with the retransmission data.
  • the memory may be an off-chip memory of the baseband chip.
  • the memory can be DDR, for example.
  • the voltage and/or frequency of the memory needs to be set before data accesses the memory to match the throughput of the memory. For example, assuming that the network device schedules the terminal to receive PDSCH in the current time slot, the terminal needs to predict the throughput rate of the memory in the current time slot before the arrival of the current time slot, so as to set the voltage and/or frequency of the memory to match the throughput. The predicted value of the rate matches.
  • the traditional technology usually configures parameters for the terminal according to the network equipment, and calculates the peak throughput rate that the terminal can achieve under the current configuration of the memory. Then, the terminal regards the peak throughput rate as a predicted value of the throughput rate of the memory, so as to set the voltage and/or frequency of the memory based on the peak throughput rate.
  • the terminal may include an on-chip memory included in the baseband chip and an off-chip memory outside the baseband chip.
  • the modem of the terminal experiences a fast fading channel or receives other interference, it will cause a large number of coding block (code block, CB) decoding errors.
  • code block, CB code block
  • the soft bits of the coded blocks that have been decoded incorrectly need to be stored in the HARQ memory of the off-chip memory, so as to perform HARQ combination during retransmission.
  • FR1 refers to the frequency range of 450MHz-6000MHz
  • FR1 refers to the frequency range of 450MHz-6000MHz
  • the soft bits of the coding blocks obtained in the initial transmission and retransmission need to be moved from the on-chip memory to the off-chip memory.
  • the off-chip memory reaches the peak throughput rate.
  • the peak throughput rate can reach twice the throughput rate of the off-chip memory at the time of initial transmission, that is, 84Gbps.
  • Table 1 lists the relationship between the data throughput rate of the carrier, the peak throughput rate of the memory, and the predicted value of the throughput rate of the memory under the carrier configurations commonly used in NR, LTE, and ENDC in traditional technologies.
  • the traditional technology regards the peak throughput rate of the memory as a predicted value of the throughput rate of the memory.
  • the throughput rate of the memory can only reach the peak throughput rate in extreme cases (retransmission scenario, and all encoded blocks of the transport block are decoded incorrectly). In other words, the throughput of the memory cannot reach its peak in most cases.
  • the prediction method of the throughput rate of the memory in the conventional technology cannot accurately reflect the actual throughput rate of the memory.
  • Traditional technology usually sets the voltage and/or frequency of the memory in units of time slots. If the voltage and/or frequency of the memory are set according to the peak throughput of the memory for each time slot, the power consumption of the memory will be very large and power saving cannot be achieved. the goal of.
  • the throughput rate of the memory can be determined by the throughput rate of soft bits in the physical layer, the throughput rate of hard bits in the media access control (MAC) layer, and the packet data convergence protocol (packet data convergence protocol) in the data plane.
  • Convergence protocol, PDCP) layer decryption data throughput decision (wherein, both the MAC layer and the PDCP layer belong to the data plane).
  • the throughput rate of hard bits in the MAC layer and the throughput rate of decrypted data in the PDCP layer determine the average throughput rate of the memory, while the throughput rate of soft bits in the physical layer determines the peak throughput rate of the memory.
  • the throughput rate of the memory is usually changed dynamically.
  • the throughput rate of the memory may vary every time slot.
  • the factors that may cause the change of the throughput rate of the memory are analyzed below.
  • the block error rate (block error rate, BLER) of the transmission block between the network device and the terminal usually needs to be kept below a certain range, for example, the BLER needs to be kept below 10%.
  • the network device usually adjusts the modulation and coding scheme (MCS) to reduce the transmission rate between the network device and the terminal.
  • MCS modulation and coding scheme
  • the network will adjust the MCS to increase the transmission rate between the network device and the terminal.
  • the size of the transport block transmitted by the network device to the terminal will become larger.
  • a change in the transport block size will cause a change in the average throughput of the memory. It can be seen that the change of the MCS will cause the change of the throughput rate of the memory.
  • the channel condition of the terminal may also change. For example, when the downlink channel experiences fast fading channel or interference, the channel condition of the terminal will deteriorate. However, the network device does not adjust the size of the transmission block in real time, but has a certain time delay. In a short period of time (for example, the time of one slot), the network device may not have time to adjust the size of the transport block. When the channel condition deteriorates sharply and before the adjustment of the transport block size is completed, the BLER of the transport block will increase rapidly. In this case, a large number of data read and write operations related to the HARQ process will occur in the memory, resulting in a sudden increase in the throughput of the memory. It can be seen that the change of the BLER of the transport block of the terminal will also cause the change of the throughput rate of the memory.
  • each time slot may be an initial transmission or a retransmission.
  • the soft bits of the coded block need to be moved from the on-chip memory to the memory for subsequent HARQ combination.
  • the soft bits of the encoded block need to be moved from the memory to the on-chip memory first. After the decoding is completed, the soft bits of the encoded block are moved from the on-chip memory to the memory. It can be seen that the change of the transmission scene (the initial transmission scene and the retransmission scene) will cause the change of the throughput rate of the memory.
  • the related art regards the peak throughput rate of the memory as the predicted value of the throughput rate of the memory, which cannot accurately reflect the actual throughput rate of the memory. If the voltage and/or frequency of the memory are set according to the peak throughput rate of the memory, the power consumption of the memory is very large, and the purpose of power saving cannot be achieved.
  • a first channel condition parameter is predicted.
  • the channel condition parameter mentioned in the embodiment of the present application may be any type of parameter that can describe the channel state.
  • the channel condition parameter may be a signal to noise ratio (signal to noise ratio, SNR).
  • the first channel condition parameter may be used to indicate the channel condition of the terminal in the first time unit after the current time unit.
  • the time unit mentioned in this embodiment of the present application may refer to one or more symbols, one or more time slots, one or more subframes, one or more milliseconds, and the like.
  • the first time unit may be a next time unit of the current time unit. Alternatively, one or more time units may also be separated between the first time unit and the current time unit. Taking a time unit as a time slot as an example, the current time unit and the first time unit may be, for example, two adjacent time slots, that is, the first time unit is a time slot next to the current time slot.
  • the first channel condition parameter may be predicted based on the channel condition parameter of the terminal at the current time unit.
  • the first channel condition parameter may be predicted based on channel condition parameters of the terminal in historical time units before the current time unit.
  • a weighted sum may be performed on the channel condition parameters of the terminal at the current time unit and the channel condition parameters of the historical time unit to predict the first channel condition parameter.
  • the channel condition parameter is SNR
  • the time unit is a time slot
  • the first time unit is the next time slot of the current time slot
  • SNR est is the predicted SNR of the next time slot.
  • SNR latest is the SNR of the current time slot, that is, the latest SNR value.
  • SNR history is the historical SNR, for example, it may be the SNR of the previous time slot of the current time slot.
  • a is the weight factor. The value of a may be a fixed value, or may be adjusted according to the prediction effect of the SNR. Exemplarily, a can be set to 0.4.
  • step S220 according to the first channel condition parameter, the first MCS configured by the terminal, and the pre-stored mapping relationship information, determine the first block error rate of the coding block corresponding to the first channel condition parameter and the first modulation and coding strategy .
  • the first MCS is the MCS currently configured by the terminal.
  • the first MCS may be configured by the network device for the terminal according to channel conditions.
  • the terminal Before performing step S220, the terminal may acquire the first MCS first. For example, the terminal may first receive downlink control information (DCI) sent by the network device. Then, the terminal may acquire the index value of the MCS from the information field corresponding to the MCS in the downlink control information, so as to obtain the first MCS.
  • DCI downlink control information
  • the terminal may store mapping relationship information in advance.
  • the mapping relationship information may be used to indicate the mapping relationship among the channel condition parameter, the MCS, and the block error rate of the coding block.
  • the form of the mapping relationship information may be a mapping relationship curve or a mapping relationship table, which is not specifically limited in this embodiment of the present application.
  • the block error rate of a coded block may refer to the probability that a coded block in a transport block has a decoding error under the condition that the transport block is transmitted incorrectly.
  • the so-called transport block transmission error refers to a decoding error of at least one coding block in the transport block. It can be seen that the block error rate of the coding block can be understood as the conditional probability under the transmission error condition of the transmission block.
  • mapping relationship information may be obtained in various ways. For example, in some embodiments, relationship curves between channel condition parameters and block error rates of coding blocks under different MCSs can be simulated. Then, according to the relationship curve obtained by simulation, the relationship between the MCS, the channel condition parameter and the block error rate is recorded in the mapping relationship table. In some other embodiments, in order to improve the accuracy of the mapping relationship information, the mapping relationship information may be an average result of recorded performance curves under various channel environments.
  • the first block error rate may be the block error rate of the coding block corresponding to the first channel condition parameter and the first MCS.
  • the first block error rate may indicate the block error rate of the coding blocks of the first time unit.
  • the terminal can obtain the first block error rate by querying the mapping relationship information according to the first channel condition parameter and the first MCS.
  • mapping relationship information is given below by taking SNR as an example of the channel condition parameter.
  • SNR min_mcsx in Table 2 indicates the minimum threshold of SNR when the MCS is MCSX. When the SNR is smaller than the minimum threshold, the block error rate of the coded block is 1.
  • SNR step indicates the progressive step of the SNR value. SNR step can be set according to actual needs. In one embodiment, in order to balance accuracy and complexity, the SNR step can be set to 0.25dB.
  • BLERi mcsx indicates the block error rate of the coded block when the MCS is MCSX and the SNR is SNR minmcsx +i*SNR step .
  • the first block error rate mentioned above may be BLER 3mcs5 .
  • the throughput rate of the memory of the terminal in the first time unit is determined (the throughput rate may refer to the predicted actual throughput rate of the external memory).
  • the number of correctly decoded coded blocks and the number of decoded wrongly coded blocks may be calculated according to the first block error rate, and then the throughput rate of the memory is determined according to the number of correctly decoded and wrongly decoded coded blocks.
  • a mapping relationship between the first block error rate, the number of coding blocks included in the transport block, and the throughput rate of the memory may be established, and then the throughput rate of the memory in the first time unit is determined based on the mapping relationship.
  • the throughput rate of the memory may be calculated according to an empirical formula.
  • the memory of the terminal may be used to store the data of the coding block included in the first transmission block transmitted within the first time unit.
  • the embodiment of the present application accurately predicts the actual throughput rate of the memory, so as to more accurately set the voltage and/or frequency of the memory in each time unit, so as to achieve the purpose of saving power consumption.
  • the embodiment of the present application predicts the channel condition parameter of the first time unit, and accurately predicts the actual throughput rate of the memory in the first time unit based on the predicted result and the pre-stored mapping relationship information. Compared with the method of setting the voltage and/or frequency of the memory based on the peak throughput of the memory, setting the voltage and/or frequency of the memory in the first time unit based on the actual throughput of the memory in the first time unit can be To achieve the purpose of saving power consumption.
  • step S230 includes step S232 and step S234.
  • the first value and the second value are determined according to the first block error rate and the number of coded blocks contained in the first transmission block transmitted within the first time unit.
  • the first value represents the number of incorrectly decoded coded blocks in the first transport block.
  • the second value represents the number of correctly decoded coded blocks in the first transport block. Whether the decoding is correct or incorrect can be judged based on cyclic redundancy check (cyclic redundancy check, CRC) information.
  • CRC cyclic redundancy check
  • the number of coding blocks included in the first transmission block may be determined according to factors such as bandwidth of the communication system, subcarrier spacing, data modulation mode, and number of transmission layers. Take the highest throughput scenario of NR FR1 as an example. In this scenario, the subcarrier spacing is 30KHz, the bandwidth is 100MHz, the modulation method is 256QAM, and the number of transmission layers is 4 layers. One transmission block corresponds to 152 coding blocks.
  • the number of coded blocks decoded incorrectly and the number of coded blocks decoded correctly can be determined.
  • the number of coded blocks that are verified to be wrong is 152*P
  • the number of coded blocks that are verified to be correct is 152*(1 -P).
  • the throughput rate of the memory in the first time unit is determined according to the first value and the second value.
  • the throughput rate of the on-chip memory may be different. Therefore, in some embodiments, the type corresponding to the first transmission block can be determined first (indicating whether the first transmission block is for initial transmission or retransmission), and then according to the type corresponding to the first transmission block, the first value and the second A value that determines the throughput rate of the memory for the first unit of time.
  • DDR memory as an example
  • DDR the following types of data need to be read and written to DDR:
  • the package traffic accelerator reads DDR (PTA reads the decrypted data from DDR and sends the data to the upper layer).
  • the data volume of data of type 1, 2, 3, 5, and 6 can be obtained by statistics at the physical layer, and the data volume of data of type 4 can be obtained by statistics of the data plane.
  • FIG. 4 is an example diagram of an implementation manner of the method shown in FIG. 2 in an initial transmission scenario.
  • Timing 0 in Figure 4 represents the decoding timing.
  • Sequence 1 in FIG. 4 represents the sequence of writing the decrypted data of the encoded block into the DDR.
  • Timing 2 in FIG. 4 represents the timing of reading the decrypted data from the DDR encoding block.
  • Timing 3 in FIG. 4 represents the timing at which the soft bits of the encoded block are written into the DDR.
  • Timing 4 in FIG. 4 represents the timing at which the hard bits of the coding block are written into the DDR.
  • t 0 in Fig. 4 represents the initial decoding time of TB0.
  • the decoding of CB2 and CB3 is correct, but because the decoding of CB1 is wrong, the decryption operation is not performed on the data plane.
  • the data plane writes the hard bits of CB2 and CB3 into DDR.
  • correctly decoded coded blocks are usually stored in the form of decrypted data or hard bit data, and wrongly decoded coded blocks are usually stored in the form of soft bits.
  • the coding blocks with decoding errors can be stored in the on-chip memory first, and when the on-chip memory is full, the remaining coding blocks with decoding errors are written into DDR. Of course, it is also possible to directly write the wrong coded block into the DDR.
  • the present application does not limit the specific storage rules of the coded blocks that are decoded incorrectly.
  • the data access volume of DDR can be obtained through the following three formulas:
  • M initial max(0, N error *nR left )+N correct *CB size
  • Minitial is the data access amount of DDR at the time of initial transmission
  • N error is the number of coding blocks with decoding errors
  • n is the number of bits corresponding to the soft bits of each coding block
  • R left is the remaining storage space of the on-chip memory
  • N correct is the number of correctly decoded coding blocks
  • CB size is the size of coding blocks.
  • n cb is the number of bits of the coding block
  • R is the code rate
  • n soft is the number of bits of each soft bit.
  • R left R total *r mov -R occupied
  • R total is the total size of the on-chip memory storage space
  • r mov represents the percentage of the on-chip memory space that can be occupied (for example, after the on-chip memory occupies 80%, the remaining data will be stored in the memory, at this time
  • the value of r mov is 80%
  • R occupied is the size of the storage space of the on-chip memory already occupied.
  • FIG. 5 is an example diagram of an implementation manner of the method shown in FIG. 2 in a retransmission scenario.
  • Timing 5 in FIG. 5 represents the decoding timing.
  • Sequence 6 in FIG. 5 represents the sequence of writing the soft bits of the encoded block into the DDR.
  • Sequence 7 in FIG. 5 represents the sequence of writing the decrypted data of the encoded block into the DDR.
  • Timing 8 in FIG. 5 represents the timing of reading the decrypted data from the DDR encoding block.
  • Timing 9 in FIG. 5 represents the timing at which the hard bits of the coding block are written into the DDR.
  • Timing 10 in FIG. 5 represents the timing at which the soft bits of the encoded block are read from the DDR to the on-chip memory.
  • Timing 11 in FIG. 5 represents the timing at which the hard bits of the coding block are read from the DDR.
  • t 1 in FIG. 5 represents the initial decoding time of TB0 during retransmission.
  • the terminal when the terminal receives the retransmitted TB0 data, it will store in the DDR ahead of the decoding time t 1 the encoding blocks (such as CB1 and CB4 ⁇ CB9) that were wrongly decoded last time. Read into on-chip memory. After the incorrectly decoded coded block is read into the on-chip memory, it is combined with the received retransmitted coded block data (for example, the decoded wrongly CB1 data is combined with the retransmitted CB1 data).
  • the encoding blocks such as CB1 and CB4 ⁇ CB9
  • CB0, CB2, and CB3 are decoded correctly during the initial transmission, so there is no need to decode CB0, CB2, and CB3 after retransmission.
  • the decoding of CB1 and CB4 is correct.
  • the terminal submits the data of CB1 and CB4 from the physical layer to the data plane.
  • the data plane receives the data of CB1 and CB4, at sequence 11, the data plane reads the data of CB2 and CB3 from the DDR.
  • the data plane decrypts the data of CB1-CB4, and writes the decrypted data into the DDR.
  • the PTA reads the decrypted data of CB1-CB4 from the DDR and sends them to the upper layer.
  • the specific time for the PTA to read the data of CB1-CB4 from the DDR is uncertain.
  • the decoding of CB7 and CB9 after retransmission is correct. However, due to the decoding error of the previous coding block, the data plane does not perform the decryption operation.
  • the data plane writes the hard bits of CB7 and CB9 into the DDR at timing 9.
  • the data access volume of DDR can be obtained by the following formula.
  • M re is the amount of DDR data access for retransmission
  • n harq is the amount of soft bit data moved from DDR to the on-chip memory
  • N hard is the number of encoded blocks stored as hard bits.
  • the throughput rate of DDR refers to the ratio of the total amount of data read and written on DDR to the time unit within a time unit (such as the duration of a time slot).
  • the throughput rate of DDR can be calculated according to the following formula:
  • C represents the DDR throughput rate
  • M total represents the total amount of data accessed to the DDR
  • T represents a time unit.
  • the amount of data accessed to DDR includes the amount of data read from DDR and the amount of data written to DDR.
  • the predicted value of the DDR throughput can be obtained according to the above formula.
  • FIG. 6 is a schematic structural diagram of an apparatus for configuring a memory provided by an embodiment of the present application.
  • the apparatus 600 in FIG. 6 includes a prediction module 610 and a processing module 620 .
  • the prediction module 610 is configured to predict a first channel condition parameter.
  • the first channel condition parameter is used to indicate the channel condition of the terminal in the first time unit after the current time unit.
  • the processing module 620 is configured to, according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information, determine the relationship between the first channel condition parameter and the first modulation The first block error rate of the coding block corresponding to the coding strategy, wherein the mapping relationship information is used to indicate the mapping relationship between the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block; according to the first A block error rate, determining the actual throughput rate of the memory of the terminal in the first time unit, the memory is used to store the data of the coding block included in the first transmission block transmitted in the first time unit .
  • the processing module 620 is configured to determine the first value and the second Values, wherein the first value represents the number of coded blocks that are decoded incorrectly in the first transport block, and the second value represents the number of coded blocks that are correctly decoded in the first transport block; according to The first value and the second value determine the throughput rate of the memory in the first time unit.
  • the processing module 620 is configured to determine a type corresponding to the first transmission block, and the type corresponding to the first transmission block indicates whether the first transmission block is to be initially transmitted or retransmitted; according to the The type corresponding to the first transmission block, the first value, and the second value determine the throughput rate of the memory in the first time unit.
  • the prediction module 610 is configured to predict the first channel condition parameter according to a second channel condition parameter, where the second channel condition parameter is a channel condition parameter of the terminal at the current time unit.
  • the processing module 620 is further configured to determine the first error block according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and the pre-stored mapping relationship information. Before the rate is determined, the first modulation and coding strategy configured by the network device for the terminal is acquired from downlink control information.
  • the memory is DDR.
  • the first channel condition parameter is SNR.
  • the current time unit and the first time unit are two adjacent time slots.
  • FIG. 7 is a schematic structural diagram of a terminal provided by an embodiment of the present application.
  • the terminal in FIG. 7 includes a memory 710 and a processor 720.
  • the memory 710 can be used to store codes
  • the processor 720 can be used to execute the codes stored in the memory 710, so as to execute the prediction method described in any of the foregoing embodiments.
  • sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be read by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital versatile disc (digital video disc, DVD)) or a semiconductor medium (for example, a solid state disk (solid state disk, SSD) )wait.
  • a magnetic medium for example, a floppy disk, a hard disk, a magnetic tape
  • an optical medium for example, a digital versatile disc (digital video disc, DVD)
  • a semiconductor medium for example, a solid state disk (solid state disk, SSD)

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Abstract

提供了一种用于配置存储器的方法, 装置和终端. 该方法包括: 预测第一信道条件参数, 其中第一信道条件参数用于指示终端在当前时间单元之后的第一时间单元的信道条件; 根据第一信道条件参数, 终端配置的第一调制与编码策略, 以及预先存储的映射关系信息, 确定与第一信道条件参数和第一调制与编码策略对应的编码块的第一误块率, 其中映射关系信息用于指示信道条件参数, 调制与编码策略以及编码块的误块率三者之间的映射关系; 根据第一误块率, 确定终端的存储器在第一时间单元的吞吐率, 存储器用于存储在第一时间单元内传输的第一传输块所包含的编码块的数据. 本申请实施例通过预测存储器的吞吐率, 达到节省功耗的目的.

Description

用于配置存储器的方法、装置和终端
本申请要求于2021年11月15日提交中国专利局、申请号为202111353277.9、申请名称为“用于配置存储器的方法、装置和终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请的实施例涉及通信技术领域，并且更为具体地，涉及一种用于配置存储器的方法、装置和终端。
背景技术
在下行接收过程中，终端需要访问存储器，如双倍速率同步动态随机访问存储器(double data rate synchronous dynamic random access memory，DDR)。因此，存储器的电压和/或频率需要在数据访问该存储器之前就设置好，以匹配该存储器的吞吐率。
传统技术通常将存储器的峰值吞吐率作为存储器的吞吐率的预测值，并基于存储器的峰值吞吐率设置存储器的电压和/或频率，这样会增加存储器的功耗，不利于实现省电的目的。
发明内容
为了解决上述问题，本申请提供一种预测方法、装置和终端。
第一方面，提供一种用于配置存储器的方法，包括：预测第一信道条件参数，其中所述第一信道条件参数用于指示终端在当前时间单元之后的第一时间单元的信道条件；根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定与所述第一信道条件参数和所述第一调制与编码策略对应的编码块的第一误块率，其中所述映射关系信息用于指示信道条件参数、调制与编码策略以及编码块的误块率三者之间的映射关系；根据所述第一误块率，确定所述终端的存储器在所述第一时间单元的吞吐率，所述存储器用于存储在所述第一时间单元内传输的第一传输块所包含的编码块的数据。
第二方面，提供一种用于配置存储器的装置，包括：预测模块，被配置为预测第一信 道条件参数，其中所述第一信道条件参数用于指示终端在当前时间单元之后的第一时间单元的信道条件；处理模块，
被配置为根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定与所述第一信道条件参数和所述第一调制与编码策略对应的编码块的第一误块率，其中所述映射关系信息用于指示信道条件参数、调制与编码策略以及编码块的误块率三者之间的映射关系；根据所述第一误块率，确定所述终端的存储器在所述第一时间单元的吞吐率，所述存储器用于存储在所述第一时间单元内传输的第一传输块所包含的编码块的数据。
第三方面，提供一种芯片，包括第二方面所述的用于配置存储器的装置。
第四方面，提供一种终端，包括存储器和处理器。所述存储器用于存储代码，所述处理器用于执行所述存储器中存储的代码，以执行如第一方面所述的方法。
第五方面，提供一种计算机可读存储介质，其上存储有用于执行第一方面所述的方法的代码。
第六方面，提供一种计算机程序产品，包括多个指令，所述指令在被计算装置执行时实现如第一方面所述的方法。
附图说明
图1是可应用本申请实施例的系统架构示意图。
图2是本申请实施例提供的用于配置存储器的方法的示意性流程图。
图3是图2中的步骤S230的一种可能的实现方式的示例图。
图4是图2所示的方法在初传场景下的实现方式的示例图。
图5是图2所示的方法在重传场景下的实现方式的示例图。
图6是本申请实施例提供的用于配置存储器的装置的结构示意图。
图7是本申请实施例提供的终端的结构示意图。
具体实施方式
本申请实施例可应用于图1所示的通信系统100。该通信系统100为蜂窝通信系统。该蜂窝通信系统例如可以是长期演进(long term evolution，LTE)系统、第五代(5th generation，5G)系统或新无线(new radio，NR)等。
通信系统100可以包括网络设备110(如基站)和终端120。终端120可以是移动台、用户设备、移动终端、手机(mobile phone)、平板电脑(Pad)、笔记本电脑、 掌上电脑等。
网络设备110可以通过下行链路向终端120发送下行数据。该下行数据例如可以是物理下行共享信道(physical downlink shared channel，PDSCH)。在接收到PDSCH之后，终端120可以对PDSCH进行译码操作。如果译码错误，则终端120可以请求网络设备110基于混合自动重传请求(hybrid automatic repeat request，HARQ)机制进行重传。无论译码正确还是译码错误，终端120均可能需要对存储器进行数据访问。例如，在数据初传过程中，终端120可能需要将译码错误的数据存储至该存储器上的HARQ存储器。又如，在数据重传过程中，终端120可能需要先将存储器的HARQ存储器中存储的译码失败的数据读取到片上存储器，以与重传数据进行合并。该存储器可以是基带芯片的片外存储器。该存储器例如可以是DDR。
存储器的电压和/或频率需要在数据访问该存储器之前就设置好，以匹配该存储器的吞吐率。例如，假设网络设备调度终端在当前时隙接收PDSCH，则终端需要在当前时隙到来之前，对存储器在当前时隙的吞吐率进行预测，从而将存储器的电压和/或频率设置成与该吞吐率的预测值相匹配。
传统技术通常根据网络设备为终端配置参数，计算终端在当前配置下该存储器所能达到的峰值吞吐率。然后，终端会将该峰值吞吐率当成该存储器所的吞吐率的预测值，从而基于该峰值吞吐率设置该存储器的电压和/或频率。
存储器的峰值吞吐率出现在高误块率(block error rate，BLER)的场景中。例如，终端可以包括基带芯片包含的片内存储器和基带芯片外部的片外存储器。终端的调制解调器在接收下行PDSCH的过程中，如果经历了快衰信道或者受到别的干扰，会造成大量的编码块(code block，CB)的译码错误。在初传情况下，译码错误的编码块的软比特需要存储在片外存储器的HARQ存储器中，以便重传时做HARQ合并。在重传情况下，需要先把存储在片外存储器的HARQ存储器中的软比特读到片上HARQ存储器。然后，终端执行HARQ合并操作，并对合并后的数据进行译码。如果重传数据的译码再次错误，则需要再次将编码块的软比特存储到片外存储器中。极端情况，如果某个传输块(transport block，TB)的所有编码块在初传和重传时均译码错误，则在重传情况下，把编码块的软比特从片外存储器读到片上HARQ存储器，再从片上HARQ存储器搬移到片外存储器的读写操作，会让片外存储器的吞吐率达到前文提到的峰值吞吐率。
以NR FR1 7Gbps(FR1指的是450MHz-6000MHz的频率范围)的数据吞吐率为例进行说明。假设编码块的每个软比特的比特数为4，码率为2/3，在初传时，如果传 输块的所有编码块均译码错误，则编码块的软比特造成的片外存储器的吞吐率为7Gbps*1.5*4＝42Gbps(式中的1.5表示的是码率的倒数)。重传时，需要先把软比特从片外存储器读到片上存储器进行HARQ合并。如果传输块的所有编码块再次全部译码错误，则需要将初传和重传得到的编码块的软比特均从片上存储器搬移到片外存储器，此时，片外存储器达到峰值吞吐率，该峰值吞吐率能够达到片外存储器在初传时的吞吐率的2倍，即84Gbps。
传统技术中，当网络设备为终端配置了LTE/NR的载波数、载波带宽以及子载波间隔之后，终端会根据这些配置参数计算存储器的峰值吞吐率，然后将该峰值吞吐率作为吞吐率的预测值，以设置存储器的电压和/或频率。例如，假设网络设备配置了3个LTE载波，每个载波带宽20MHz，最高调制方式是256QAM，最高层数是4层，则该3个载波的数据吞吐率可以达到1.2Gbps,假设编码块的每个软比特的比特数为4，码率为2/3，则存储器的峰值吞吐率为1.2Gbps*1.5*4*2＝14.4Gbps。
表1列举了传统技术中，在NR、LTE、ENDC常用的载波配置下，载波的数据吞吐率、存储器的峰值吞吐率以及存储器的吞吐率的预测值之间的关系。
表1
Figure PCTCN2022121446-appb-000001
从上文的论述可以看出，传统技术把存储器的峰值吞吐率当作存储器的吞吐率的预测值。但是，存储器的吞吐率只有在极端情况下(重传场景，且传输块的编码块全部译码错误)才会达到峰值吞吐率。换句话说，存储器的吞吐率在大多数情况下均无法达到峰值。由此可见，传统技术的存储器的吞吐率的预测方式并不能准确地反映存储器的实际吞吐率。 传统技术通常以时隙为单位设置存储器的电压和/或频率，如果每个时隙都按照存储器的峰值吞吐率设置存储器的电压和/频率，则存储器的功耗会非常大，不能达到省电的目的。
实际上，在下行接收过程中，存储器的吞吐率可以由物理层软比特的吞吐率，介质访问控制(media access control，MAC)层的硬比特的吞吐率以及数据面分组数据汇聚协议(packet data convergence protocol，PDCP)层解密数据的吞吐率决定(其中，MAC层和PDCP层均属于数据面)。MAC层硬比特的吞吐率和PDCP层解密数据的吞吐率决定了存储器的平均吞吐率，而物理层软比特的吞吐率决定了存储器的峰值吞吐率。
存储器的吞吐率通常是动态变化的。例如，存储器的吞吐率在每个时隙均可能会发生变化。下面对可能引起存储器的吞吐率变化的因素进行分析。
首先，网络设备与终端之间的传输块的误块率(block error rate，BLER)通常需要维持在一定的范围之下，例如BLER需要维持在10％以下。为了实现这一目的，当终端的信道条件变差时，网络设备通常会调整调制与编码策略(modulation and coding scheme，MCS)，以降低网络设备与终端之间的传输速率。在这种情况下，网络设备向终端传输的传输块的尺寸会变小。当终端的信道条件变好时，网络会调整MCS，以提升网络设备与终端之间的传输速率。在这种情况下，网络设备向终端传输的传输块的尺寸会变大。传输块尺寸的变化，会引起存储器的平均吞吐率的变化。由此可见，MCS的变化会引起存储器的吞吐率的变化。
其次，在相邻的两个时隙之间，终端的信道条件也可能会发生变化。例如，当下行信道经历快衰信道或者干扰时，终端的信道条件会变差。但是，网络设备对传输块的尺寸的调整并非实时的，而是具有一定的时延。在较短的时间(例如一个时隙的时间)内，网络设备可能还来不及调整传输块的尺寸。在信道条件急剧变差至传输块尺寸调整完成前的一段时间，传输块的BLER会极速上升。在这种情况下，存储器将出现大量与HARQ过程相关的数据读写操作，导致存储器的吞吐率会突然增大。由此可见，终端的传输块的BLER的变化也会引起存储器的吞吐率的变化。
再次，每个时隙有可能是初传，也可能是重传。在初传且编码块译码错误的情况下，编码块的软比特需要从片上存储器搬移至存储器，以便后续进行HARQ合并。在重传并且译码错误的情况下，编码块的软比特需要先从存储器搬移到片上存储器。待译码完成后，再将编码块的软比特从片上存储器搬移到存储器。由此可见，传输场景(初传场景和重传场景)的变化会引起存储器的吞吐率的变化。
由上述分析可以看出，MCS的变化、传输块的BLER的变化以及初传和重传场景的变化均可能会导致存储器的吞吐率发生变化。因此，相关技术把存储器的峰值吞吐率当作 存储器的吞吐率的预测值，并不能准确地反映存储器的实际吞吐率。按照存储器的峰值吞吐率去设置存储器的电压和/或频率，存储器的功耗非常大，不能达到省电的目的。
为了解决上述问题，下面结合图2，对本申请实施例进行介绍。
如图2所示，在步骤S210，预测第一信道条件参数。本申请实施例提及的信道条件参数可以是任意类型的能够描述信道状态的参数。示例性地，该信道条件参数可以是信噪比(signal to noise ratio，SNR)。
第一信道条件参数可用于指示终端在当前时间单元之后的第一时间单元的信道条件。本申请实施例提及的时间单元可以指一个或多个符号，一个或多个时隙，一个或多个子帧，一个或多个毫秒等。第一时间单元可以是当前时间单元的下一时间单元。或者，第一时间单元与当前时间单元之间也可以间隔一个或多个时间单元。以时间单元为时隙为例，当前时间单元和第一时间单元例如可以是相邻的两个时隙，即第一时间单元为当前时隙的下一时隙。
第一信道条件参数的预测方式可以有多种。例如，可以基于终端在当前时间单元的信道条件参数对第一信道条件参数进行预测。又如，可以基于终端在当前时间单元之前的历史时间单元的信道条件参数对第一信道条件参数进行预测。又如，可以对终端在当前时间单元的信道条件参数和历史时间单元的信道条件参数进行加权求和，以预测第一信道条件参数。
作为示例，假设信道条件参数为SNR，时间单元为时隙，第一时间单元为当前时隙的下一时隙，则可以采用如下公式预测该下一时隙的SNR：
SNR est＝(1-a)*SNR history+a*SNR latest
在上式中，SNR est为预测出的下一时隙的SNR。SNR latest为当前时隙的SNR，即最新的SNR值。SNR history为历史SNR，例如可以是当前时隙的前一时隙的SNR。a为权重因子。a的取值可以是固定值，也可以根据SNR的预测效果进行调整。示例性地，a可以设置为0.4。
由于相邻两个时间时隙的信道变化有限，因此，相邻两个时间时隙的信道条件参数的变化也有限，所以根据当前时隙的信道条件参数能够比较准确的得到下个时隙的信道条件参数。
在步骤S220，根据第一信道条件参数、终端配置的第一MCS，以及预先存储的映射关系信息，确定与第一信道条件参数和第一调制与编码策略对应的编码块的第一误块率。
第一MCS为终端当前配置的MCS。该第一MCS可以由网络设备根据信道条件为终端进行配置。在执行步骤S220之前，终端可以先获取该第一MCS。例如，终端可以先接 收网络设备发送的下行控制信息(downlink control information，DCI)。然后，终端可以从下行控制信息中的MCS对应的信息域获取MCS的索引值，从而得到该第一MCS。
终端可以预先存储映射关系信息。该映射关系信息可用于指示信道条件参数、MCS以及编码块的误块率三者之间的映射关系。该映射关系信息的形式可以为映射关系曲线，也可以是映射关系表，本申请实施例对此不作具体限定。
编码块的误块率可以指传输块传输错误的条件下，传输块中的编码块出现译码错误的概率。所谓传输块传输错误，指的是该传输块中的至少一个编码块译码错误。由此可见，编码块的误块率可以理解为传输块传输错误条件下的条件概率。
上述映射关系信息可以通过多种方式获得。例如，在一些实施例中，可以仿真不同MCS下，信道条件参数和编码块的误块率的关系曲线。然后根据仿真得到的关系曲线，将MCS、信道条件参数和误块率的关系记录在映射关系表中。在另一些实施例中，为了提高映射关系信息的准确性，映射关系信息可以是记录的多种信道环境下的性能曲线的平均结果。
第一误块率可以为第一信道条件参数和第一MCS对应的编码块的误块率。换句话说，第一误块率可以指示第一时间单元的编码块的误块率。终端根据第一信道条件参数和第一MCS，通过查询上述映射关系信息，即可得到该第一误块率。
下面结合表2，以信道条件参数为SNR为例，给出映射关系信息的一种可能的形式。
表2
MCS SNR 编码块的误块率
MCS0 小于SNR min_mcs0 1
MCS0 SNR min_mcs0+1*SNR step BLER1 mcs0
MCS0 SNR min_mcs0+2*SNR step BLER2 mcs0
MCS0 SNR min_mcs0+3*SNR step BLER3 mcs0
  … …
MCS1 小于SNR min_mcs1 1
MCS1 SNR min_mcs1+1*SNR step BLER1 mcs1
MCS1 SNR min_mcs1+2*SNR step BLER2 mcs1
MCS1 SNR min_mcs1+3*SNR step BLER3 mcs1
  …  
MCSmax 小于SNR min_mcsmax 1
MCSmax SNR min_mcsmax+1*SNR step BLER1 mcsmax
MCSmax SNR min_mcsmax+2*SNR step BLER2 mcsmax
MCSmax SNR min_mcsmax+3*SNR step BLER3 mcsmax
  …  
表2中的SNR min_mcsx表示MCS为MCSX时，SNR的最小阈值。当SNR小于该最小阈值时，编码块的误块率为1。SNR step表示SNR的取值的递进步长。SNR step可以根据实际需要设置。在一个实施例中，为了兼顾精度与复杂度，可以将SNR step设置为0.25dB。BLERi mcsx表示MCS为MCSX、SNR为SNR minmcsx+i*SNR step时，编码块的误块率。
以第一信道条件参数为SNR min_mcs5+3*SNR step、终端配置的第一MCS为MCS5为例，则前文提到的第一误块率可以为BLER 3mcs5。
在步骤S230，根据第一误块率，确定终端的存储器在第一时间单元的吞吐率(该吞吐率可以指预测出的外存储器的实际吞吐率)。例如，可以根据第一误块率计算出译码正确的编码块和译码错误的编码块的数量，然后根据译码正确和译码错误的编码块的数量确定存储器的吞吐率。又如，可以建立第一误块率、传输块包含的编码块的数量和存储器的吞吐率的映射关系，然后基于该映射关系确定存储器在第一时间单元的吞吐率。又如，在确定第一误块率的前提下，可以根据经验公式推算存储器的吞吐率。终端的存储器可以用于存储在第一时间单元内传输的第一传输块所包含的编码块的数据。
本申请实施例对存储器的实际吞吐率进行准确预测，从而更准确地设置存储器在各个时间单元内的电压和/或频率，以达到节省功耗电量的目的。本申请实施例对第一时间单元的信道条件参数进行预测，基于预测的结果以及预先存储的映射关系信息，准确预测存储器在该第一时间单元的实际吞吐率。与基于存储器的峰值吞吐率对存储器进行电压和/或频率设置的方式相比，基于存储器在该第一时间单元的实际吞吐率，设置存储器在第一时间单元内的电压和/或频率，能够达到节省功耗的目的。
下面结合图3，给出步骤S230的一种可能的实现方式。如图3所示，步骤S230包括步骤S232和步骤S234。
在步骤S232，根据第一误块率，以及第一时间单元内传输的第一传输块所包含的编码块的数量，确定第一数值和第二数值。第一数值表示第一传输块中的译码错误的编码块的数量。第二数值表示第一传输块中的译码正确的编码块的数量。译码正确或错误，可以基于循环冗余校验(cyclic redundancy check，CRC)信息判断。
第一传输块中包含的编码块的数量可以根据通信系统的带宽、子载波间隔、数据的调制方式、传输的层数等因素确定。以NR FR1的最高吞吐率场景为例，在该场景下，子载波间隔为30KHz，带宽为100MHz，调制方式为256QAM，传输的层数为4层，则一个传输块对应152个编码块。
在得到第一误块率之后以及第一传输块中包含的编码块的数量之后，即可确定译码错误的编码块的数量和译码正确的编码块的数量。
例如，假设第一传输块包含152个编码块，且编码块的误块率为P，则校验错误的编码块个数为152*P，校验正确的编码块个数为152*(1-P)。
在步骤S234，根据第一数值和第二数值，确定存储器在第一时间单元的吞吐率。在初传和重传场景下，片上存储器的吞吐率可能是不同的。因此，在一些实施例中，可以先确定第一传输块对应的类型(指示第一传输块进行的是初传还是重传)，再根据第一传输块对应的类型、第一数值和第二数值，确定存储器在第一时间单元的吞吐率。
以存储器为DDR为例，在下行接收过程中，以下类型的数据要对DDR进行读写操作：
1、物理层软比特的写DDR(当编码块译码错误时，把编码块对应的软比特写入DDR)；
2、物理层软比特的读DDR(重传时，需要把重传的数据对应的软比特从DDR读到片上存储器进行软比特合并)。
3、数据面解密后的数据的写DDR(数据面对物理层递交的译码正确的编码块进行解密，把解密后的数据写入DDR)。
4、包流量加速器(package traffic accelerator，PTA)的读DDR(PTA从DDR读取解密后的数据，并将该数据送入高层)。
5、数据面硬比特的写DDR(如果某个编码块译码错误，数据面把该编码块之后的、译码正确的编码块暂存到DDR)。
6、数据面硬比特的读DDR(数据面把暂存在DDR的译码正确的编码块读出来进行解密操作，并把解密后的数据写入DDR，等待PTA读取)。
上面提到的六种类型的数据中，类型为1、2、3、5、6的数据的数据量可以由物理层统计得到，类型为4的数据的数据量可以由数据面统计得到。
下面结合图4和图5，以第一传输块为TB0、存储器为DDR为例，分别介绍在初传和重传过程中，如何根据第一数值和第二数值，确定存储器在第一时间单元的实际吞吐量。
图4是图2所示的方法在初传场景下的实现方式的示例图。图4中的时序0代表的是译码时序。图4中的时序1代表的是编码块解密后的数据写入DDR的时序。图4中的时序2代表从DDR读编码块解密后的数据的时序。图4中的时序3代表的是编码块的软比特写入DDR的时序。图4中的时序4代表的是编码块的硬比特写入DDR的时序。图4中的t 0表示TB0的起始译码时间。
参见图4，TB0初传时，CB0、CB2和CB3校验正确，其余编码块校验错误。CB0译 码正确，因此，在时序1，物理层将CB0的数据递交给数据面。数据面对CB0进行解密，并将解密后的数据写入DDR。在时序2，PTA从DDR读CB0解密后的数据传给高层。由于CB1译码错误，在时序3，物理层把CB1以及CB4～CB9的软比特写入DDR,等待重传合并。
CB2和CB3译码正确，但是由于CB1译码错误，所以数据面不进行解密操作。在时序4，数据面将CB2和CB3的硬比特写入DDR。
从图4可以看出，译码正确的编码块通常以解密数据或硬比特数据的形式存储，译码错误的编码块通常以软比特的形式存储。为了方便HARQ合并，译码错误的编码块可以优先存储在片上存储器，当片上存储器存满后，再将剩下译码错误的编码块写入DDR。当然，也可以直接将译码错误的编码块写入DDR。本申请对译码错误的编码块的具体存储规则不作限定。
数据初传时，DDR的数据访问量，可以通过如下三个公式得到：
M initial＝max(0，N error*n-R left)+N correct*CB size
其中，M initial为初传时DDR的数据访问量，N error为译码错误的编码块个数，n为每个编码块的软比特对应的比特数，R left为片上存储器剩余的存储空间，N correct为译码正确的编码块个数，CB size为编码块大小。
Figure PCTCN2022121446-appb-000002
其中，n cb为编码块的比特数，R为码率，n soft为每个软比特的比特数。
R left＝R total*r mov-R occupy
其中，R total为片上存储器存储空间的总的大小，r mov表示可占用的片上存储器空间的百分比(例如，可以在片上存储器占用80％后，将剩下的数据将存入存储器中，此时r mov的值为80％)，R occupy为已经占用的片上存储器的存储空间的大小。
图5是图2所示的方法在重传场景下的实现方式的示例图。图5中的时序5代表的是译码时序。图5中的时序6代表的是编码块软比特写入DDR的时序。图5中的时序7代表的是编码块解密后的数据写入DDR的时序。图5中的时序8代表的是从DDR读编码块解密后的数据的时序。图5中的时序9代表的是编码块的硬比特写入DDR的时序。图5中的时序10代表的是编码块的软比特从DDR读到片上存储器的时序。图5中的时序11代表的是编码块的硬比特从DDR读出的时序。图5中的t 1表示重传时TB0的起始译码时刻。
参见图5，在时序10，当终端接收到重传的TB0的数据时，会提前于译码时间t 1将 DDR中存储的，上一次译码错误的编码块(例如CB1和CB4～CB9)读入片上存储器。译码错误的编码块读入片上存储器后，与接收到的重传的编码块的数据进行合并(例如，将译码错误的CB1的数据与重传的CB1的数据合并)。
CB0、CB2、CB3在初传时译码正确，因此，重传后不需要对CB0、CB2和CB3进行译码操作。
重传时，CB1、CB4译码正确。终端将CB1和CB4的数据从物理层递交给数据面。数据面接收到CB1和CB4的数据后，在时序11，数据面从DDR中读取CB2和CB3的数据。
在时序7，数据面将CB1～CB4的数据进行解密操作，并将解密后的数据写入DDR中。
在时序8，PTA从DDR读取CB1～CB4解密后的数据传给高层。其中，PTA从DDR读取CB1～CB4的数据的具体时间是不确定的。
重传后的CB5、CB6、CB8再次译码错误。在时序6，物理层把CB5、CB6、CB8的软比特写入DDR,等待重传合并。
重传后的CB7和CB9译码正确。但是，由于之前的编码块译码错误,所以数据面不进行解密操作。数据面在时序9将CB7和CB9的硬比特写入DDR。
从图5可以看出，以硬比特的数据形式存储在DDR的编码块，需要先从DDR读取到片上存储器。在片上存储器进行解密操后，再将解密的数据存储到DDR中。在这个过程中，这部分数据需要进行从DDR读取和写入DDR两次操作。
HARQ重传过程中，DDR的数据访问量可以通过如下公式得到。
M re＝n harq+N error*n+(N soft+N hard*2-N error)*CB size
其中，M re为重传的DDR数据访问量，n harq为从DDR搬到片上存储器的软比特数据量，N hard为存储为硬比特的编码块个数。
DDR的吞吐率，指在一个时间单元(例如一个时隙的时长)内，DDR上读、写的数据总量与时间单元的比值。DDR的吞吐率可以根据如下公式计算得到：
C＝M total/T
其中，C表示DDR吞吐率，M total表示访问DDR的数据总量，T表示一个时间单元。访问DDR的数据量包括从DDR读取的数据量和写入DDR的数据量。
在确定当前的传输类型后，根据上述公式，即可得到DDR吞吐率的预测值。
上文结合图1至图5，详细描述了本公开的方法实施例，下面结合图6至图7，详细描述本公开的装置实施例。应理解，方法实施例的描述与装置实施例的描述相互对应，因此，未详细描述的部分可以参见前面方法实施例。
图6是本申请实施例提供的一种用于配置存储器的装置的示意性结构图。图6的装置600包括预测模块610和处理模块620。
预测模块610被配置为预测第一信道条件参数。所述第一信道条件参数用于指示终端在当前时间单元之后的第一时间单元的信道条件。
处理模块620被配置为根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定与所述第一信道条件参数和所述第一调制与编码策略对应的编码块的第一误块率，其中所述映射关系信息用于指示信道条件参数、调制与编码策略以及编码块的误块率三者之间的映射关系；根据所述第一误块率，确定所述终端的存储器在所述第一时间单元的实际吞吐率，所述存储器用于存储在所述第一时间单元内传输的第一传输块所包含的编码块的数据。
可选地，所述处理模块620被配置为根据所述第一误块率，以及所述第一时间单元内传输的第一传输块所包含的编码块的数量，确定第一数值和第二数值，其中所述第一数值表示所述第一传输块中的译码错误的编码块的数量，所述第二数值表示所述第一传输块中的译码正确的编码块的数量；根据所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率。
可选地，所述处理模块620被配置为确定所述第一传输块对应的类型，所述第一传输块对应的类型指示所述第一传输块进行的是初传或重传；根据所述第一传输块对应的类型、所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率。
可选地，所述预测模块610被配置为根据第二信道条件参数预测所述第一信道条件参数，其中所述第二信道条件参数为所述终端在所述当前时间单元的信道条件参数。
可选地，所述处理模块620还被配置为在所述根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定第一误块率之前，从下行控制信息中获取网络设备为所述终端配置的所述第一调制与编码策略。
可选地，所述存储器为DDR。
可选地，所述第一信道条件参数为SNR。
可选地，所述当前时间单元和所述第一时间单元为相邻的两个时隙。
图7是本申请实施例提供的一种终端的示意性结构图。图7的终端包括存储器710和处理器720，所述存储器710可用于存储代码，所述处理器720用于执行所述存储器710中存储的代码，以执行前文任一实施例描述的预测方法。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程 构成任何限定。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够读取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，数字通用光盘(digital video disc，DVD))或者半导体介质(例如，固态硬盘(solid state disk，SSD))等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种用于配置存储器的方法，其特征在于，包括：
    预测第一信道条件参数，其中所述第一信道条件参数用于指示终端在当前时间单元之后的第一时间单元的信道条件；
    根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定与所述第一信道条件参数和所述第一调制与编码策略对应的编码块的第一误块率，其中所述映射关系信息用于指示信道条件参数、调制与编码策略以及编码块的误块率三者之间的映射关系；
    根据所述第一误块率，确定所述终端的存储器在所述第一时间单元的吞吐率，所述存储器用于存储在所述第一时间单元内传输的第一传输块所包含的编码块的数据。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第一误块率，确定所述终端的存储器在所述第一时间单元的吞吐率，包括：
    根据所述第一误块率，以及所述第一时间单元内传输的第一传输块所包含的编码块的数量，确定第一数值和第二数值，其中所述第一数值表示所述第一传输块中的译码错误的编码块的数量，所述第二数值表示所述第一传输块中的译码正确的编码块的数量；
    根据所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率，包括：
    确定所述第一传输块对应的类型，所述第一传输块对应的类型指示所述第一传输块进行的是初传或重传；
    根据所述第一传输块对应的类型、所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率。
  4. 根据权利要求1所述的方法，其特征在于，所述预测第一信道条件参数，包括：
    根据第二信道条件参数预测所述第一信道条件参数，其中所述第二信道条件参数为所述终端在所述当前时间单元的信道条件参数。
  5. 根据权利要求1所述的方法，其特征在于，在所述根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定第一误块率之前，所述方法还包括：
    接收下行控制信息；
    从所述下行控制信息中获取网络设备为所述终端配置的所述第一调制与编码策略。
  6. 根据权利要求1所述的方法，其特征在于，所述存储器为DDR。
  7. 根据权利要求1所述的方法，其特征在于，所述第一信道条件参数为SNR。
  8. 根据权利要求1所述的方法，其特征在于，所述当前时间单元和所述第一时间单元为相邻的两个时隙。
  9. 一种用于配置存储器的装置，其特征在于，包括：
    预测模块，被配置为预测第一信道条件参数，其中所述第一信道条件参数用于指示终端在当前时间单元之后的第一时间单元的信道条件；
    处理模块，被配置为根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定与所述第一信道条件参数和所述第一调制与编码策略对应的编码块的第一误块率，其中所述映射关系信息用于指示信道条件参数、调制与编码策略以及编码块的误块率三者之间的映射关系；根据所述第一误块率，确定所述终端的存储器在所述第一时间单元的吞吐率，所述存储器用于存储在所述第一时间单元内传输的第一传输块所包含的编码块的数据。
  10. 根据权利要求9所述的装置，其特征在于，所述处理模块被配置为根据所述第一误块率，以及所述第一时间单元内传输的第一传输块所包含的编码块的数量，确定第一数值和第二数值，其中所述第一数值表示所述第一传输块中的译码错误的编码块的数量，所述第二数值表示所述第一传输块中的译码正确的编码块的数量；根据所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率。
  11. 根据权利要求10所述的装置，其特征在于，所述处理模块被配置为确定所述第一传输块对应的类型，所述第一传输块对应的类型指示所述第一传输块进行的是初传或重传；根据所述第一传输块对应的类型、所述第一数值和所述第二数值，确定所述存储器在所述第一时间单元的吞吐率。
  12. 根据权利要求9所述的装置，其特征在于，所述预测模块被配置为根据第二信道条件参数预测所述第一信道条件参数，其中所述第二信道条件参数为所述终端在所述当前时间单元的信道条件参数。
  13. 根据权利要求9所述的装置，其特征在于，所述处理模块还被配置为在所述根据所述第一信道条件参数、所述终端配置的第一调制与编码策略，以及预先存储的映射关系信息，确定第一误块率之前，从下行控制信息中获取网络设备为所述终端配置的所述第一调制与编码策略。
  14. 根据权利要求9所述的装置，其特征在于，所述存储器为DDR。
  15. 根据权利要求9所述的装置，其特征在于，所述第一信道条件参数为SNR。
  16. 根据权利要求9所述的装置，其特征在于，所述当前时间单元和所述第一时间单元为相邻的两个时隙。
  17. 一种终端，其特征在于，包括存储器和处理器，所述存储器用于存储代码，所述处理器用于执行所述存储器中存储的代码，以执行如权利要求1-8中任一项所述的方法。
  18. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有程序代码，所述程序代码在被执行时用于实现如权利要求1-8中任一项所述的方法。
  19. 一种计算机程序产品，包括多个指令，所述指令在被计算装置执行时实现如权利要求1至8中任一项所述的方法。
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