WO2023082350A1 - Array substrate and manufacturing method therefor, and display panel - Google Patents

Array substrate and manufacturing method therefor, and display panel Download PDF

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Publication number
WO2023082350A1
WO2023082350A1 PCT/CN2021/133535 CN2021133535W WO2023082350A1 WO 2023082350 A1 WO2023082350 A1 WO 2023082350A1 CN 2021133535 W CN2021133535 W CN 2021133535W WO 2023082350 A1 WO2023082350 A1 WO 2023082350A1
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Prior art keywords
thin film
electrode
layer
array substrate
film transistor
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PCT/CN2021/133535
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French (fr)
Chinese (zh)
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沈海燕
郑辉
黄灿
鲜于文旭
张春鹏
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武汉华星光电半导体显示技术有限公司
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Priority to US17/618,463 priority Critical patent/US20240014216A1/en
Publication of WO2023082350A1 publication Critical patent/WO2023082350A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • the resolution (Pixel per inch, PPI) of the display panel is related to the pixel aperture ratio of the array substrate, and the pixel aperture ratio of the array substrate is related to the size and unit of the thin film transistor.
  • the area is related to the number of thin film transistors. The larger the area occupied by the thin film transistors, the lower the pixel aperture ratio and the lower the resolution of the display panel.
  • the development of high-resolution display devices is limited by the limitation of the process line width and wiring of thin film transistors.
  • the purpose of the present application is to provide an array substrate, a manufacturing method thereof, and a display panel, which are beneficial to improving the resolution of the display panel.
  • the first thin film transistor layer is arranged on the substrate, and the first thin film transistor layer includes:
  • a plurality of first thin film transistors arranged at intervals, the first thin film transistors include:
  • a first gate extending in the thickness direction of the array substrate, and located on a side of the first active pattern away from the first electrode and the second electrode in a direction perpendicular to the thickness direction of the array substrate side;
  • the first electrode and the second electrode of at least two of the first thin film transistors are arranged around one of the first openings, and one of the first openings includes at least two of the first thin film transistors.
  • a display panel comprising the above-mentioned array substrate and a light-emitting element, the light-emitting element is electrically connected to at least one of the first thin film transistors.
  • a method for manufacturing the aforementioned array substrate comprising the following steps:
  • the opening including a first annular sidewall of the first electrode layer and a second annular sidewall of the second electrode layer;
  • At least two first gates arranged at intervals corresponding to one of the openings are formed on the surface of the patterned semiconductor layer away from the first electrode layer and the second electrode layer, and at least two first gates arranged at intervals corresponding to one of the openings are formed. Two spaced-apart portions of the first grid are located within the opening;
  • each of the disconnected parts is located on two adjacent adjacent ones of the first openings. Between the two first gates, at least two disconnected parts communicate with the opening, and at least two disconnected parts connect the patterned semiconductor layer, the first electrode layer and the second The electrode layers are respectively disconnected into at least two of the first active patterns, at least two of the first electrodes, and at least two of the second electrodes.
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel.
  • the first thin film transistor includes a first electrode with a first sidewall, a second electrode with a second sidewall, a first active pattern, and a first gate.
  • the first active pattern extends in the thickness direction of the array substrate
  • the first grid extends in the thickness direction of the array substrate and is located on the side of the first active pattern away from the first electrode and the second electrode
  • at least two second electrodes The first side wall of the first electrode of a thin film transistor and the second side wall of the second electrode are arranged around the first opening penetrating through the first thin film transistor layer, so that the vertical type first thin film transistor array is arranged, combined with the vertical type
  • the thin film transistors occupy a small horizontal space, which is beneficial to increase the number of thin film transistors, thereby improving the resolution of the display panel.
  • FIG. 1 is a top view of an array substrate according to the first embodiment of the present application
  • Fig. 2 is a schematic cross-sectional view along the A-A tangent line of the array substrate shown in Fig. 1;
  • Fig. 3 is a three-dimensional schematic diagram along the A-A tangent line of the array substrate shown in Fig. 1;
  • FIG. 4 is a schematic cross-sectional view along the B-B tangent line of the array substrate shown in FIG. 1;
  • FIG. 5 is a schematic flow chart of manufacturing the array substrate shown in FIG. 1;
  • 6A-6J are schematic diagrams of the process of manufacturing the array substrate shown in FIG. 1;
  • FIG. 7 is a schematic cross-sectional view of an array substrate according to a second embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of an array substrate according to a third embodiment of the present application.
  • the vertical thin film transistor occupies a small space in the horizontal direction.
  • the vertical thin film transistor occupies a small horizontal space, it can The number of thin film transistors per unit area in the horizontal direction is increased.
  • there is no corresponding design in the prior art on how to arrange a plurality of vertical thin film transistors in an array on a substrate, and realizing vertical thin film transistors arranged in an array is a technical problem that needs to be solved.
  • the present application arranges the first thin film transistor layer on the substrate, at least one first opening penetrates the first thin film transistor layer, and the first thin film transistor layer includes a plurality of first thin film transistors arranged at intervals, and the first thin film transistor Including a first electrode, a second electrode, a first active pattern and a first grid, the first electrode has a first side wall, the second electrode has a second side wall, and the first active pattern is in the thickness direction of the array substrate Extending, the first gate extends in the thickness direction of the array substrate and is located on the side of the first active pattern away from the first electrode and the second electrode in the direction perpendicular to the thickness direction of the array substrate, and the at least two first thin film transistors
  • the first electrode and the second electrode are arranged around a first opening, and a first opening includes first side walls of the first electrodes of at least two first thin film transistors and first side walls of the second electrodes of at least two first thin film transistors.
  • Two side walls, at least two vertical first thin film transistors are designed around a first opening, so that a plurality of vertical first thin film transistors are arranged in an array, combined with the advantages of vertical thin film transistors occupying a small horizontal space , which is beneficial to increase the number of thin film transistors per unit area, thereby improving the resolution of the display panel including the array substrate.
  • Figure 1 is a top view of the array substrate of the first embodiment of the present application
  • Figure 2 is a schematic cross-sectional view along the A-A tangent line of the array substrate shown in Figure 1
  • Figure 3 is a schematic cross-sectional view along the array substrate A-A shown in Figure 1
  • FIG. 4 is a schematic cross-sectional view along a B-B tangent line of the array substrate shown in FIG. 1 .
  • the array substrate 100 can be applied to display panels such as a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, or a submillimeter light emitting diode display panel.
  • the array substrate 100 can also be applied to an active backlight module.
  • the array substrate 100 includes a substrate 10, a buffer layer 101, a first thin film transistor layer 20, at least one first hole 100a1, and at least one first opening 100a3.
  • the first thin film transistor layer 20 is disposed on the substrate 10, and at least one first opening 100a3 Both the at least one first hole 100a1 and the at least one first hole 100a1 pass through the first thin film transistor layer 20 , and the at least one first hole 100a1 is arranged one-to-one with the at least one first opening 100a3 .
  • the substrate 10 is a glass substrate. It can be understood that the substrate 10 can also be a flexible substrate, such as a polyimide layer.
  • the buffer layer 101 is disposed on the substrate 10 , and the buffer layer 101 is used to prevent impurities in the substrate 10 from diffusing into the first TFT layer 20 and affecting the electrical properties of the first TFT 20a.
  • the buffer layer 101 includes at least one of a silicon oxide layer or a silicon nitride layer.
  • the buffer layer 101 has a thickness of 300nm-600nm.
  • the buffer layer 101 is a silicon oxide layer.
  • the first thin film transistor layer 20 is disposed on the buffer layer 101, and the first thin film transistor layer 20 includes a plurality of first thin film transistors 20a arranged at intervals.
  • the plurality of first thin film transistors 20a includes a plurality of first thin film transistor groups 20b, the plurality of first thin film transistor groups 20b are spaced from each other and arranged in an array, and each first thin film transistor group 20b consists of at least one first hole 100a1 arranged around It consists of two first thin film transistors 20a, and each first thin film transistor 20a is a vertical thin film transistor.
  • each first thin film transistor group 20b includes four first thin film transistors 20a arranged at intervals around a first hole 100a1, and four first thin film transistors 20a arranged around a first hole 100a1.
  • the thin film transistors 20a are arranged symmetrically about the center, and the rotation angle between any two adjacent first thin film transistors 20a in each first thin film transistor group 20b is 90 degrees. It can be understood that each first thin film transistor group 20b may also include two, three, five or six first thin film transistors 20a arranged around the first hole 100a1.
  • the array substrate further includes at least two disconnection parts 20c, the at least two disconnection parts 20c penetrate the first thin film transistor layer 20, and the at least two first thin film transistors 20a arranged around a first hole 100a1
  • a disconnection portion 20c is disposed between any two adjacent first thin film transistors 20a, so that any two adjacent first thin film transistors 20a disposed around one first hole 100a1 are electrically insulated from each other.
  • the disconnection portion 20c between the plurality of first thin film transistors 20a in each first thin film transistor group 20b is disposed around a first hole 100a1 and communicated with the first hole 100a1.
  • each first thin film transistor group 20b includes four first thin film transistors 20a arranged at intervals around a first hole 100a1, the number of disconnected parts 20c is four, and the four disconnected parts 20c surround a first hole 100a1.
  • the hole 100a1 is provided and communicated with the first hole 100a1.
  • annular groove 100b that penetrates the first thin film transistor layer 20 and surrounds the first thin film transistor group 20b is provided on the periphery of any one of the first thin film transistor groups 20b, so that The two adjacent first thin film transistors 20a in the two adjacent first thin film transistor groups 20b are electrically insulated.
  • the shape of the annular groove 100b is rectangular.
  • each first thin film transistor 20 a includes a first electrode 201 , a first insulating layer 202 , a second electrode 203 , a first active pattern 204 , a second insulating layer 205 and a first gate 206 .
  • the first electrodes 201 of the plurality of first thin film transistors 20a are arranged on the same layer
  • the second electrodes 203 of the plurality of first thin film transistors 20a are arranged on the same layer
  • the first insulating layers 202 of the plurality of first thin film transistors 20a are arranged on the same layer.
  • the first active patterns 204 of the first thin film transistors 20a are arranged in the same layer, the first gates 206 of the plurality of first thin film transistors 20a are arranged in the same layer, and the second insulating layers 205 of the plurality of first thin film transistors 20a are arranged in the same layer , so that a plurality of vertical first thin film transistors 20a arranged in an array can be prepared through the same manufacturing process.
  • the first electrodes 201 of the multiple first thin film transistors 20a in the present application are set It refers to obtaining a plurality of first electrodes 201 after patterning the same metal film layer, and setting the first insulating layers 202 of the plurality of first thin film transistors 20a in the same layer refers to obtaining after patterning the same insulating layer.
  • the first electrode 201 is disposed between the second electrode 203 and the substrate 10 , and an end of the first electrode 201 close to the first hole 100a1 has a first sidewall 201a, and the first sidewall 201a is an inclined plane.
  • the first electrode 201 is one of a source or a drain.
  • the first electrode 201 is made of at least one material selected from molybdenum, aluminum, titanium and copper.
  • the thickness of the first electrode 201 is 3000-8000 angstroms. It can be understood that the first electrode 201 and the second electrode 203 can also be arranged in the same layer.
  • the first electrode 201 is disposed on the buffer layer 101 , the first electrode 201 is a source electrode, and the first electrode 201 is composed of two aluminum layers and a titanium layer between the aluminum layers.
  • the first insulating layer 202 is disposed between the first electrode 201 and the second electrode 203 , and an end of the first insulating layer 202 near the first hole 100a1 has a third sidewall 202a.
  • the first insulating layer 202 includes at least one of a silicon nitride layer or a silicon oxide layer.
  • the thickness of the first insulating layer 202 is 0.8 ⁇ m-1.2 ⁇ m.
  • the first insulating layer 202 is disposed on the first electrode 201 and exposes part of the first electrode 201, and the exposed part of the first electrode 201 extends outward relative to the end of the first insulating layer 202 having the third side wall 202a. come out.
  • the third sidewall 202a is an inclined plane, and the slope ⁇ of the third sidewall 202a is greater than 0 degrees and less than 90 degrees, so as to form a continuous first active pattern 204 on the third sidewall 202a.
  • the slope ⁇ of the third side wall 202a is 5 degrees, 10 degrees, 15 degrees, 20 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 70 degrees or 75 degrees.
  • the slope ⁇ of the third sidewall 202a is greater than or equal to 30 degrees and less than or equal to 80 degrees, ensuring that the first active pattern 204 is formed on the third sidewall 202a while forming the continuous first active pattern 204
  • the thickness of the active pattern 204 is uniform, and avoids the problem that the channel of the first active pattern 204 formed on the third sidewall 202a is doped to cause an increase in leakage current.
  • the second electrode 203 is disposed on the first insulating layer 202, and an end of the second electrode 203 near the first hole 100a1 has a second sidewall 203a, and the second sidewall 203a is an inclined plane.
  • the second electrode 203 is the other of the source or the drain.
  • the second electrode 203 is made of at least one material selected from molybdenum, aluminum, titanium and copper.
  • the thickness of the second electrode 203 is 300 ⁇ -8000 ⁇ .
  • the second electrode 203 is a drain electrode, and the second electrode 203 is composed of two aluminum layers and a titanium layer located between the aluminum layers.
  • the second sidewall 203a is coplanar with the third sidewall 202a, so as to form a continuous and uniform first active pattern 204 along the third sidewall 202a and the second sidewall 203a.
  • a first step is formed between the second electrode 203 and the exposed portion of the first electrode 201 .
  • the first active pattern 204 extends in the thickness direction of the array substrate 100, and part of the first active pattern 204 is located on the first sidewall 201a, the second sidewall 203a and the third sidewall 202a .
  • the first active pattern 204 includes a first channel 2041, a first doped portion 2042 and a second doped portion 2043, the first channel 2041 is connected between the first doped portion 2042 and the second doped portion 2043, At least part of the first doped portion 2042 extends on the first side wall 201a of the first electrode 201, the second doped portion 2043 is disposed on the surface of the second electrode 203 away from the first electrode 201, and the first channel 2041 At least a portion of 1 extends on the third sidewall 202 a of the first insulating layer 202 and the second sidewall 203 a of the second electrode 203 .
  • the preparation material of the first active pattern 204 includes any one of metal oxide, polysilicon, and amorphous silicon.
  • the first channel 2041 extends from the exposed part of the first electrode 201 along the third sidewall 202a and the second sidewall 203a to the surface of the second electrode 203 away from the first electrode 201, that is, the first channel 2041 is arranged along the coplanar second sidewall 203a and third sidewall 202a, and the other part of the first channel 2041 is respectively arranged on the surface of the first electrode 201 away from the substrate 10 and the surface of the second electrode 203 away from the substrate 10 on the surface.
  • the first doped portion 2042 extends from the buffer layer 101 along the first sidewall 201a of the first electrode 201 to the surface of the first electrode 201 away from the buffer layer 101 , that is, the first doped portion 2042 is disposed on the first electrode 201 surface, the first sidewall 201a of the first electrode 201 and the buffer layer 101.
  • the second doped part 2043 is disposed on the surface of the second electrode 203 away from the first electrode 201 .
  • the first active pattern 204 is made of metal oxide, such as InGaZnO.
  • the orthographic projection of the first active pattern 204 on the substrate 10 is a rectangle.
  • the width of the first channel 2041 of the first active pattern 204 is W
  • the length of the first channel 2041 of the first active pattern 204 is L.
  • a ratio of the width W of the first channel 2041 to the length L of the first channel 2041 is greater than or equal to 1 and less than or equal to 20.
  • the ratios of the width W of the first channel 2041 to the length L of the first channel 2041 are 2, 3, 4, 5, 6, 7, 8, 9 and 12.
  • the width W of the first trench 2041 is greater than or equal to 2 microns and less than or equal to 10 microns.
  • the second insulating layer 205 is a gate insulating layer, at least part of the second insulating layer 205 extends in the thickness direction of the array substrate 100, and at least part of the second insulating layer 205 is disposed on the first active pattern 204 and the first grid 206 .
  • the second insulating layer 205 is an inorganic insulating layer formed by chemical deposition, and the inorganic insulating layer includes at least one of a silicon oxide layer or a silicon nitride layer.
  • the thickness of the second insulating layer 205 is 1000 ⁇ -1500 ⁇ .
  • the second insulating layer 205 can also be an organic insulating layer.
  • the second insulating layer 205 extends from the first doped portion 2042 of the first active pattern 204 to the second electrode 203 along the first channel 2041 and the second doped portion 2043 , and the second insulating layer 205 Covering the second electrode 203 , that is, the second insulating layer 205 covers the first active pattern 204 and the second electrode 203 .
  • the first gate 206 extends in the thickness direction of the array substrate 100, and the first gate 206 is located on the first active pattern 204 away from the first electrode 201 and the first electrode 201 in the direction perpendicular to the thickness of the array substrate 100 One side of the second electrode 203 .
  • the preparation material of the first grid 206 is selected from at least one of molybdenum, aluminum, titanium, copper and silver.
  • the first gate 206 extends along the portion of the second insulating layer 205 located in the first hole 100a1 to the surface of the second insulating layer 205 away from the second electrode 203 .
  • the orthographic projection of the first grid 206 on the substrate 10 is a rectangle.
  • the first doped part 2042 and the second doped part 2043 are respectively located on opposite sides of the first gate 206 in the thickness direction perpendicular to the array substrate 100, and the orthographic projection of the first gate 206 on the substrate 10 is the same as the first doped part 2043.
  • the orthographic projections of the channel 2041 on the substrate 10 are completely coincident.
  • the first active pattern 204 is doped by using the first gate 206 as a mask, and the first active pattern 204 is undoped for the part covered by the first gate 206 to form the second gate.
  • a channel 2041 , the part of the first active pattern 204 not shielded by the first gate 206 is doped to form a first doped part 2042 and a second doped part 2043 .
  • the first opening 100 a 3 is formed through the film layers formed through the first electrode 201 , the first insulating layer 202 , and the second electrode 203 .
  • One first thin film crystal group 20b is set corresponding to one first opening 100a3.
  • the first electrode 201, the first insulating layer 202, and the second electrode 203 of at least two first thin film transistors 20a arranged around the same first hole 100a1 are arranged around a first opening 100a3, and a first opening 100a3 includes at least two The first sidewall 201a of the first electrode 201 of the first thin film transistor 20a, the second sidewall 203a of the second electrode 203, and the third sidewall 202a of the first insulating 202 layer.
  • At least two disconnection portions 20c disposed around one first hole 100a1 are disposed around one first opening 100a3 and communicate with one first opening 100a3.
  • the first opening 100a3 includes a first sub-opening 100a31 and a second sub-opening 100a32
  • the first sub-opening 100a31 communicates with the second sub-opening 100a32
  • the first sub-opening 100a31 is located on the side of the second sub-opening 100a32 away from the substrate 10
  • the size of the second sub-opening 100a32 is smaller than the size of the first sub-opening 100a31
  • the first sub-opening 100a31 is formed by penetrating the film layer forming the second electrode 203 and the first insulating layer 202
  • the second sub-opening 100a32 is formed by penetrating
  • the film layer forming the first electrode 201 is formed.
  • the second electrodes 203 and the first insulating layer 202 of at least two first thin film transistors 20a are arranged around the first sub-opening 100a31, and the first sub-opening 100a31 includes the second sidewall 203a of the second electrode 203 and the first insulating layer 202
  • the first electrodes 201 of at least two first thin film transistors 20a are disposed around the second sub-opening 100a32, and the second sub-opening 100a32 includes the first sidewall 201a of the first electrode 201.
  • the first sub-opening 100a31 and the second sub-opening 100a32 are both inverted prism-shaped.
  • the first hole 100a1 is formed by sequentially forming a semiconductor layer, a gate insulating layer, and a gate metal layer in the first opening 100a3, and patterning the semiconductor layer, the gate insulating layer, and the gate metal layer to respectively
  • the first active pattern 204 , the second insulating layer 205 and the first gate 206 are obtained, that is, the first hole 100a1 is formed by forming a patterned film layer in the first opening 100a3 .
  • the first holes 100a1 can also be filled with organic materials, so that the surface of the array substrate 100 becomes flat, which facilitates the arrangement of light-emitting elements and the like on the array substrate and the connection between the light-emitting elements and the first thin film transistor 20a.
  • the cross section of the first hole 100a1 is a square, and the side length of the square is greater than or equal to 2 micrometers, so as to adapt to the process precision of the array substrate.
  • This embodiment adopts the design that two or more vertical first thin film transistors surround one first hole, which is beneficial to simultaneously prepare a plurality of vertical first thin film transistors arranged in an array by using the same manufacturing process.
  • the first thin film transistor fully utilizes the space in the thickness direction of the array substrate and occupies a smaller space in the horizontal direction, which is beneficial to increasing the number of thin film transistors, thereby improving the resolution of the display panel including the array substrate.
  • FIG. 5 is a schematic flow chart of manufacturing the array substrate shown in FIG. 1 .
  • the manufacturing method comprises the steps of:
  • Step S100 sequentially forming a first electrode layer, a first insulating layer, and a second electrode layer on the substrate.
  • a substrate 10 is provided, a buffer layer 101 is formed on the substrate 10 by chemical deposition, a first electrode layer 30 is formed on the buffer layer 101 by physical deposition, and a first electrode layer 30 is formed on the first electrode layer 30 by chemical deposition.
  • the entire surface of the first insulating layer 202 is formed on the first insulating layer 202, and the entire surface of the second electrode layer 40 is formed on the first insulating layer 202, as shown in FIG. 6A.
  • Step S101 forming a plurality of first sub-openings penetrating through the second electrode layer and the first insulating layer.
  • a plurality of first sub-openings 100a31 penetrating through the second electrode layer 40 and the first insulating layer 202 are formed by adopting a traditional photolithography process and an etching process.
  • the longitudinal section of 100a31 is an inverted trapezoid, as shown in Fig. 6B.
  • the first insulating layer 202 has a third annular sidewall 202b surrounding the first sub-opening 100a31
  • the second electrode layer 40 has a second ring-shaped sidewall 202b surrounding the first sub-opening 100a31.
  • the annular side wall 40a, the third annular side wall 202b and the second annular side wall 40a are coplanar
  • the first sub-opening 100a31 is surrounded by the second annular side wall 40a and the third annular side wall 202b
  • Both the slope of the third annular sidewall 202b and the slope of the second annular sidewall 40a are greater than 0 degrees and less than 90 degrees.
  • the slope of the third annular side wall 202b and the slope of the second annular side wall 40a are both greater than or equal to 30 degrees and less than or equal to 80 degrees, which is beneficial to the third annular side wall 202b and the second annular side wall
  • a continuous first semiconductor layer is formed on the wall 40a, and the thickness of the first semiconductor layer is uniform, which is also conducive to proper doping of the first semiconductor layer to avoid excessive doping regions and large leakage current.
  • Step S102 forming a plurality of second sub-openings penetrating through the first electrode layer, each second sub-opening corresponds to a first sub-opening and communicates with the first sub-opening, and the size of each first sub-opening is larger than the corresponding first sub-opening The size of the second sub-opening.
  • the second sub-opening 100a32 penetrating through the first electrode layer 30 is formed by adopting a conventional photolithography process and an etching process.
  • the first electrode layer 30 has a first annular sidewall 30a, and the second The sub-opening 100a32 is enclosed by the first annular side wall 30a.
  • the second sub-opening 100a32 is set corresponding to the first sub-opening 100a31, and the first sub-opening 100a31 communicates with the second sub-opening 100a32.
  • the rectangular truss shape, the longitudinal section of the second sub-opening 100a32 is an inverted trapezoid, as shown in FIG. 6C .
  • the first insulating layer 202 exposes part of the first electrode layer 30, and the second electrode layer 40 A first step is formed between the portion exposed to the first electrode layer 30 .
  • Step S103 forming a stepped patterned first semiconductor layer on the second electrode layer, in the first sub-opening and in the second sub-opening.
  • the wall 30a extends to the surface of the first electrode layer 30 away from the substrate 10, and then extends along the third annular sidewall 202b and the second annular sidewall 40a to the surface of the second electrode layer away from the first insulating layer 202, as Figure 6D shows.
  • the stepped patterned first semiconductor layer 50 includes a first inclined active layer 501 disposed along the third annular sidewall 202b and the second annular sidewall 40a, and a first inclined active layer 501 disposed along the first annular sidewall 30a.
  • the third horizontal active layer 504, the first horizontal active layer 502 and the second horizontal active layer 503 are respectively connected to the opposite sides of the first inclined active layer 501, the third horizontal active layer 504 and the first horizontal
  • the active layer 502 is respectively connected to the opposite sides of the second inclined active layer 505, and the patterned first semiconductor layer 50 extends in the thickness direction of the array substrate in a step shape, which is beneficial to save the occupation of the first thin film transistor in the horizontal direction. Space.
  • Step S104 forming a second insulating layer covering the step-shaped patterned first semiconductor layer and the second electrode layer.
  • chemical vapor deposition is used to form the entire second insulating layer 205 on the stepped patterned first semiconductor layer 50 and the second electrode layer 40 , as shown in FIG. 6E .
  • the second insulating layer 205 includes a first inclined insulating layer 2051 arranged along the first inclined active layer 501, a second inclined insulating layer 2056 arranged along the second inclined active layer 505, and a second inclined insulating layer 2056 arranged on the first horizontal active layer. 502, the second horizontal insulating layer 2053 disposed on the second horizontal active layer 503, the third horizontal insulating layer 2054 disposed on the third horizontal active layer 504, and the second horizontal insulating layer 2054 disposed on the second horizontal active layer 504.
  • the fourth horizontal insulating layer 2055 on the electrode layer 40, the first horizontal insulating layer 2052 and the second horizontal insulating layer 2053 are connected to opposite sides of the first inclined insulating layer 2051, and the fourth horizontal insulating layer 2055 is connected to the second horizontal insulating layer 2053.
  • the layer 2053 is away from the side of the first inclined insulating layer 2051, the third horizontal insulating layer 2054 and the first horizontal insulating layer 2052 are respectively connected to the opposite sides of the second inclined insulating layer 2056, the second horizontal insulating layer 2053, the first inclined insulating layer
  • the insulating layer 2051 , the second inclined insulating layer 2056 , the first horizontal insulating layer 2052 , and the third horizontal insulating layer 2054 constitute a stepped portion of the second insulating layer 205 .
  • Step S105 forming a first gate layer on the second insulating layer.
  • the entire surface of the first gate layer 60 is formed on the second insulating layer 205 by physical deposition, as shown in FIG. 6F .
  • Step S106 Patterning the first gate layer, the second insulating layer, the stepped patterned first semiconductor layer, the first insulating layer, the first electrode layer, and the second electrode layer by patterning to obtain the first thin film transistor layer.
  • the first gate layer 60 is patterned by using a photolithography process and an etching process to obtain a plurality of first gates 206, at least two first gates 206 are arranged corresponding to one first sub-opening 100a31 and distributed in a ring shape Parts of at least two first gates 206 corresponding to one first sub-opening 100a31 are located in the first sub-opening 100a31, and each first gate 206 starts from the first horizontal insulating layer 2052 along the first inclined insulating layer 2051 extends to the second horizontal insulating layer 2053, as shown in FIG. 6G.
  • the orthographic projection of each first grid 206 on the substrate 10 is a rectangle.
  • the four first grids 206 are distributed in a ring and arranged symmetrically, and the number of first grids 206 between two adjacent first grids 206
  • the rotation angle is 90 degrees.
  • the second insulating layer 205 and the stepped patterned first semiconductor layer 50 are sequentially etched using a yellow light process and an etching process to obtain a plurality of first active patterns 204 and a plurality of first holes 100a1, at least two The first active pattern 204 is disposed around a first hole 100a1.
  • Each first active pattern 204 is set corresponding to a first grid 206, the orthographic projection of each first active pattern 204 on the substrate 10 is a rectangle, and the orthographic projection of the first grid 206 on the substrate 10 is located at the corresponding In the orthographic projection of the first active pattern 204 on the substrate 10 .
  • Each first hole 100a1 is set corresponding to a first sub-opening 100a31, and each first hole 100a1 is formed by forming a plurality of first active patterns 204, a plurality of first gates 206 and patterning in the first sub-opening 100a31.
  • the second insulating layer 205 is formed. Each first hole 100a1 penetrates through the first gate layer 60 , the second insulating layer 205 , the stepped patterned first semiconductor layer 50 , the second electrode layer 40 , the first insulating layer 202 and the first electrode layer 30 .
  • a first via hole 2054a penetrating the third horizontal insulating layer 2054 is formed, and a second via hole 504a penetrating the third horizontal active layer 504 is formed, the second via hole 504a communicates with the first via hole 2054a and both The size is the same, and a plurality of first holes 100a1 are obtained, as shown in FIG.
  • the semiconductor layer 50 patterned first semiconductor layer 50 as shown in the dotted line box, obtains a plurality of first active patterns 204, as shown in FIG. 6I.
  • the first electrode layer 30 and the second electrode layer 40 are etched using a yellow light process and an etching process to obtain a plurality of first electrodes 201 and a plurality of second electrodes 203, as shown in FIG. 6J .
  • the etching of the first electrode layer 30 and the second electrode layer 40 by using the yellow light process and the etching process includes: forming The annular groove 100b is annular and arranged around at least two first active patterns arranged around a first hole 100a1, and then etched between two adjacent first active patterns 204 around a first hole 100a1 Between the first electrode layer 30, the second electrode layer 40 and the first insulating layer 202, a plurality of first electrodes 201 and a plurality of second electrodes 203 arranged around a first hole 100a1 are obtained.
  • each first thin film transistor group 20b includes a surrounding At least two first thin film transistors 20a arranged in a first hole 100a1, an annular groove 100b is arranged around a first thin film transistor group 20b, each first thin film transistor 20a includes a first electrode 201, and is located on the first electrode 201 A first insulating layer 202, a second electrode 203 located on the first insulating layer 202, a side wall extending along a side wall of a first electrode 201, a side wall of the first insulating layer 202, and a side wall of the second electrode 203
  • each thin film transistor group includes at least two vertical first thin film transistors arranged around the first hole, and the vertical first thin film transistor groups
  • a thin film transistor includes a first electrode, a second electrode, a first insulating layer between the first electrode and the second electrode, a first active pattern, a second insulating layer, and a first gate, so as to prepare a plurality of The array substrate of the vertical thin film transistors arranged in an array, combined with the feature that the first vertical thin film transistor occupies less horizontal space, is beneficial to increase the number of thin film transistors, thereby improving the resolution of the display panel including the array substrate.
  • FIG. 7 is a schematic diagram of the array substrate according to the second embodiment of the present application.
  • the array substrate shown in FIG. 7 is basically similar to the array substrate shown in FIG. 2, except that the array substrate shown in FIG. 7 further includes a second thin film transistor layer 70, at least one second hole 100a2, and at least one second opening 100a4 As well as the fifth insulating layer 80, at least one second hole 100a2 and at least one second opening 100a4 both penetrate the second thin film transistor layer 70, and the second thin film transistor layer 70 is disposed on the side of the first thin film transistor layer 20 away from the substrate 10,
  • the fifth insulating layer 80 is disposed between the second TFT layer 70 and the first TFT layer 20 .
  • Each second thin film transistor layer 70 includes a plurality of second thin film transistors 70a arranged in the same layer, and the second thin film transistors 70a are also vertical thin film transistors. At least two second thin film transistors 70a are arranged around one second hole 100a2, and the at least two second thin film transistors 70a arranged around one second hole 100a2 form a second thin film transistor group.
  • the second thin film transistor 70 a includes a third electrode 701 , a fourth electrode 703 , a second active pattern 704 , a third insulating layer 702 , a fourth insulating layer 705 and a second gate 706 .
  • the end of the third electrode 701 close to the second hole 100a2 has a fourth side wall 701a, the electrode 701 is the source electrode, and the thickness and material of the third electrode 701 are the same as those of the first electrode 201, which will not be described in detail here .
  • an end of the fourth electrode 703 close to the second hole 100 a 2 has a fifth sidewall 703 a , and the fourth electrode 703 is disposed on a side of the third electrode 701 away from the substrate 10 .
  • the fourth electrode 703 is a drain electrode, and the thickness and material of the fourth electrode 703 are the same as those of the second electrode 203 , which will not be described in detail here.
  • the third insulating layer 702 has a sixth sidewall 702 a near the end of the second hole 100 a 2 , and the third insulating layer 702 is disposed between the third electrode 701 and the fourth electrode 703 .
  • the thickness and material of the third insulating layer 702 are the same as those of the first insulating layer 202 , which will not be described in detail here.
  • one end of the third electrode 701 with the sixth sidewall 702a extends outward relative to the third insulating layer 702
  • the third electrode 701 and the fourth electrode 703 extend outward relative to the end of the third insulating layer 702 with the sixth sidewall 702a.
  • a second step is formed between the outwardly extending portions.
  • the slope of the sixth side wall 702a is greater than or equal to 30 degrees and less than or equal to 80 degrees, so as to facilitate the subsequent formation of a flat one.
  • the sixth side wall 702a is coplanar with the fifth side wall 703a. Specifically, the slope of the sixth sidewall 702a is equal to the slope of the third sidewall 202a.
  • the second active pattern 704 extends in the thickness direction of the array substrate 100, and part of the second active pattern 704 is located on the fourth sidewall 701a, the fifth sidewall 703a and the sixth sidewall 702a .
  • the second active pattern 704 and the first active pattern 204 are obtained by patterning the same semiconductor layer.
  • the thickness and material of the second active pattern 704 are the same as those of the first active pattern 204 , which will not be described in detail here.
  • the second active pattern 704 extends from the fifth insulating layer 80 along the fourth side wall 701 a to the surface of the third electrode 701 away from the fifth insulating layer 80 , and extends from the third electrode 701 along the sixth
  • the sidewall 702 a and the fifth sidewall 703 a extend to the surface of the fourth electrode 703 away from the third insulating layer 702 .
  • the second active pattern 704 includes a second channel 7041, a third doped part 7042 and a fourth doped part 7043, and the third doped part 7042 and the fourth doped part 7043 are connected to the second channel 7041
  • the third doped part 7042 and the fourth doped part 7043 are respectively located on opposite sides of the second gate 706 in the direction perpendicular to the thickness of the array substrate 100 at opposite ends.
  • the second gate 706 extends in the thickness direction of the array substrate 100, and the second gate 706 is located on the second active pattern 704 away from the third electrode 701 and One side of the fourth electrode 703 .
  • the second gate 706 is obtained by patterning the same gate metal layer as the first gate 206 , and the thickness and material of the second gate 706 are the same as those of the first gate 206 , which will not be described in detail here.
  • the fourth insulating layer 705 extends in the thickness direction of the array substrate 100 , and at least part of the fourth insulating layer 705 is disposed between the second active pattern 704 and the second gate 706 .
  • the fourth insulating layer 705 and the second insulating layer 205 are obtained by patterning the same insulating layer.
  • the thickness and material of the fourth insulating layer 705 are the same as those of the second insulating layer 205 , which will not be described in detail here.
  • the fourth insulating layer 705 covers the entire second active pattern 704 and the fourth electrode 703 .
  • the fifth insulating layer 80 includes a third opening 80a, and the third opening 80a communicates with the second opening 100a4 and the first opening 100a3.
  • the fifth insulating layer 80 is made of at least one material selected from silicon nitride or silicon oxide.
  • the number of second TFTs 70 a in each second TFT layer 70 is the same as the number of first TFTs 20 a in each first TFT layer 20 .
  • the second thin film transistor 70a in the second thin film transistor layer 70 is arranged in one-to-one correspondence with the first thin film transistor 20a in the first thin film transistor layer 20 in the thickness direction of the array substrate.
  • the insulating layer 205 is connected to the fourth insulating layer 705 of the corresponding second thin film transistor 70a, and the first thin film transistor 20a is electrically insulated from the corresponding second thin film transistor 70a.
  • At least one second opening 100a4 is arranged one-to-one with at least one first opening 100a3, and each second opening 100a4 communicates with the corresponding first opening 100a3.
  • the third electrode 701, the fourth electrode 703 and the third insulating layer 702 of at least two second thin film transistors 70a are arranged around one second opening 100a4, and one second opening 100a4 includes at least two second thin film transistors 70a
  • the second opening 100a4 includes a third sub-opening 100a41 and a fourth sub-opening 100a42, the third sub-opening 100a41 is located on the side of the fourth sub-opening 100a42 away from the substrate 10, the size of the third sub-opening 100a41 is larger than the size of the fourth sub-opening 100a42 .
  • Both the third sub-opening 100a41 and the fourth sub-opening 100a42 are in the shape of an inverted quadrangular prism.
  • the second hole 100a2 is formed by forming the second active pattern 704, the fourth insulating layer 705 and the second gate 706 in the second opening 100a4, and the second opening 100a4 and the second hole 100a2 are formed in an array One to one up and down in the thickness direction of the substrate.
  • the second hole 100a2 and the first hole 100a1 are arranged one to one above the other in the thickness direction of the array substrate, and the second hole 100a2 communicates with the first hole 100a1, and the size of the second hole 100a2 is larger than that of the first hole 100a1.
  • the number of layers of the second thin film transistor layer 70 may be one or multiple, for example, 3, 4, 5 and so on.
  • An insulating layer is provided between two adjacent second thin film transistor layers 70 .
  • the first thin film transistor layer 20 and the at least one second thin film transistor layer 70 can be prepared through the same process, so as to simplify the process while preparing a plurality of vertical thin film transistors arranged in an array.
  • FIG. 8 is a schematic cross-sectional view of the array substrate according to the third embodiment of the present application.
  • the array substrate shown in FIG. 8 is basically similar to the array substrate shown in FIG. 7, the differences include: the number of the second thin film transistor layer 70 is two, at least one first thin film transistor 20a and at least one second thin film transistor 70a are in the array The thickness direction of the substrate is adjacent and correspondingly disposed, and the second electrode 203 of at least one first thin film transistor 20a is multiplexed as the third electrode 701 of the second thin film transistor 70a adjacent to and correspondingly disposed to the first thin film transistor 20a.
  • the first active pattern 204 of the first thin film transistor 20a is connected to the second active pattern 704 of the second thin film transistor 70a corresponding to the first thin film transistor 20a, and the second active pattern 704 of the first thin film transistor 20a
  • the insulating layer 205 is connected to the fourth insulating layer 705 of the second thin film transistor 70 a corresponding to the first thin film transistor 20 a.
  • the second active patterns 704 of the two second thin film transistor layers 70 and the first active pattern 204 in one first thin film transistor layer 20 are obtained by patterning the same semiconductor layer obtained, and the second gates 706 of the two second thin film transistor layers 70 and the first gate 206 in one first thin film transistor layer 20 are obtained by patterning the same gate layer, the two second thin film transistors
  • the fourth insulating layer 705 of layer 70 and the second insulating layer 205 in one first thin film transistor layer 20 are the same insulating layer, and the two second thin film transistor layers 70 and the first thin film transistor layer 20 can be prepared by the same process It is obtained that, while simplifying the manufacturing process, it is beneficial to increase the number of thin film transistors, thereby improving the resolution of the display panel including the array substrate.
  • the present application also provides a display panel.
  • the display panel includes any one of the above-mentioned array substrates and a light emitting element.
  • the light emitting element can be a liquid crystal display unit, a micro light emitting diode, a submillimeter light emitting diode or an organic light emitting diode.
  • the light emitting element is electrically connected with at least one first thin film transistor, and the at least one first thin film transistor controls the turning on of the light emitting element. It can be understood that the light emitting element can also be electrically connected with at least one second thin film transistor.

Abstract

Disclosed in the present application are an array substrate and a manufacturing method therefor, and a display panel. A first thin film transistor comprises a first electrode, a second electrode, a first active pattern, and a first gate. The first active pattern extends in the thickness direction of the array substrate. The first gate extends in the thickness direction of the array substrate. The first sidewall of the first electrode and the second sidewall of the second electrode of the at least two first thin film transistors are arranged around a first opening penetrating through the first thin film transistor layer.

Description

阵列基板及其制造方法、显示面板Array substrate, manufacturing method thereof, and display panel 技术领域technical field
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示面板。The present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
背景技术Background technique
近年来，高分辨率显示装置是显示领域的发展趋势，显示面板的分辨率(Pixel per inch，PPI)与阵列基板的像素开口率有关，而阵列基板的像素开口率与薄膜晶体管的尺寸及单位面积薄膜晶体管的数目相关，薄膜晶体管所占区域越大，像素开口率就越低，显示面板的分辨率越低。然而，受限于薄膜晶体管的工艺线宽和布线的限制，高分辨显示装置的发展受到限制。In recent years, high-resolution display devices are the development trend in the display field. The resolution (Pixel per inch, PPI) of the display panel is related to the pixel aperture ratio of the array substrate, and the pixel aperture ratio of the array substrate is related to the size and unit of the thin film transistor. The area is related to the number of thin film transistors. The larger the area occupied by the thin film transistors, the lower the pixel aperture ratio and the lower the resolution of the display panel. However, the development of high-resolution display devices is limited by the limitation of the process line width and wiring of thin film transistors.
因此，有必要提出一种技术方案以提高显示装置的分辨率。Therefore, it is necessary to propose a technical solution to improve the resolution of the display device.
技术问题technical problem
本申请的目的在于提供一种阵列基板及其制造方法、显示面板，有利于提高显示面板的分辨率。The purpose of the present application is to provide an array substrate, a manufacturing method thereof, and a display panel, which are beneficial to improving the resolution of the display panel.
技术解决方案technical solution
一种阵列基板，所述阵列基板包括：An array substrate, the array substrate comprising:
基板；以及substrate; and
第一薄膜晶体管层，设置于所述基板上，所述第一薄膜晶体管层 包括：The first thin film transistor layer is arranged on the substrate, and the first thin film transistor layer includes:
多个间隔设置的第一薄膜晶体管，所述第一薄膜晶体管包括：A plurality of first thin film transistors arranged at intervals, the first thin film transistors include:
第一电极，具有第一侧壁；a first electrode having a first sidewall;
第二电极，具有第二侧壁；a second electrode having a second sidewall;
第一有源图案，在所述阵列基板的厚度方向上延伸；以及a first active pattern extending in a thickness direction of the array substrate; and
第一栅极，在所述阵列基板的厚度方向上延伸，且在垂直于所述阵列基板的厚度方向上位于所述第一有源图案远离所述第一电极和所述第二电极的一侧；以及a first gate extending in the thickness direction of the array substrate, and located on a side of the first active pattern away from the first electrode and the second electrode in a direction perpendicular to the thickness direction of the array substrate side; and
至少一个第一开口，贯穿所述第一薄膜晶体管层；at least one first opening penetrating through the first thin film transistor layer;
其中，至少两个所述第一薄膜晶体管的所述第一电极和所述第二电极围绕一个所述第一开口设置，且一个所述第一开口包括至少两个所述第一薄膜晶体管的所述第一电极的第一侧壁以及至少两个所述第一薄膜晶体管的所述第二电极的所述第二侧壁。Wherein, the first electrode and the second electrode of at least two of the first thin film transistors are arranged around one of the first openings, and one of the first openings includes at least two of the first thin film transistors. The first sidewall of the first electrode and the second sidewalls of the second electrodes of at least two first thin film transistors.
一种显示面板，所述显示面板包括上述阵列基板及发光元件，发光元件与至少一个所述第一薄膜晶体管电性连接。A display panel, comprising the above-mentioned array substrate and a light-emitting element, the light-emitting element is electrically connected to at least one of the first thin film transistors.
一种上述阵列基板的制造方法，所述方法包括如下步骤：A method for manufacturing the aforementioned array substrate, the method comprising the following steps:
于基板上形成第一电极层和第二电极层；forming a first electrode layer and a second electrode layer on the substrate;
形成贯穿所述第一电极层和所述第二电极层的至少一个开口，所述开口包括所述第一电极层的第一环形侧壁和所述第二电极层的第二环形侧壁；forming at least one opening through the first electrode layer and the second electrode layer, the opening including a first annular sidewall of the first electrode layer and a second annular sidewall of the second electrode layer;
至少于所述第一电极层的第一环形侧壁、所述第二电极层的第二环形侧壁以及所述基板上形成图案化半导体层；forming a patterned semiconductor layer on at least the first annular sidewall of the first electrode layer, the second annular sidewall of the second electrode layer, and the substrate;
至少于所述图案化半导体层远离所述第一电极层和第二电极层的表面上形成对应一个所述开口设置的至少两个间隔设置的第一栅极，对应一个所述开口设置的至少两个间隔设置的第一栅极的部分位于所述开口内；At least two first gates arranged at intervals corresponding to one of the openings are formed on the surface of the patterned semiconductor layer away from the first electrode layer and the second electrode layer, and at least two first gates arranged at intervals corresponding to one of the openings are formed. two spaced-apart portions of the first grid are located within the opening;
形成贯穿所述图案化半导体层、所述第一电极层以及所述第二电极层的至少两个断开部，每个所述断开部位于对应一个所述第一开口设置的相邻两个所述第一栅极之间，至少两个所述断开部与所述开口连通，且至少两个断开部将所述图案化半导体层、所述第一电极层以及所述第二电极层分别断开为至少两个所述第一有源图案、至少两个所述第一电极以及至少两个所述第二电极。Forming at least two disconnected parts through the patterned semiconductor layer, the first electrode layer and the second electrode layer, each of the disconnected parts is located on two adjacent adjacent ones of the first openings. Between the two first gates, at least two disconnected parts communicate with the opening, and at least two disconnected parts connect the patterned semiconductor layer, the first electrode layer and the second The electrode layers are respectively disconnected into at least two of the first active patterns, at least two of the first electrodes, and at least two of the second electrodes.
有益效果Beneficial effect
本申请提供一种阵列基板及其制造方法、显示面板，第一薄膜晶体管包括具有第一侧壁的第一电极、具有第二侧壁的第二电极、第一有源图案以及第一栅极，第一有源图案在阵列基板的厚度方向上延伸，第一栅极在阵列基板的厚度方向上延伸且位于第一有源图案远离第一电极和第二电极的一侧，至少两个第一薄膜晶体管的第一电极的第一侧壁和第二电极的第二侧壁围绕贯穿第一薄膜晶体管层的第一开口设置，以使垂直型的第一薄膜晶体管阵列排布，结合垂直型薄膜晶体管占用水平空间小的优点，有利于增加薄膜晶体管的数目，进而提高显示面板的分辨率。The present application provides an array substrate, a manufacturing method thereof, and a display panel. The first thin film transistor includes a first electrode with a first sidewall, a second electrode with a second sidewall, a first active pattern, and a first gate. , the first active pattern extends in the thickness direction of the array substrate, the first grid extends in the thickness direction of the array substrate and is located on the side of the first active pattern away from the first electrode and the second electrode, and at least two second electrodes The first side wall of the first electrode of a thin film transistor and the second side wall of the second electrode are arranged around the first opening penetrating through the first thin film transistor layer, so that the vertical type first thin film transistor array is arranged, combined with the vertical type The thin film transistors occupy a small horizontal space, which is beneficial to increase the number of thin film transistors, thereby improving the resolution of the display panel.
附图说明Description of drawings
图1为本申请第一实施例阵列基板的俯视图；FIG. 1 is a top view of an array substrate according to the first embodiment of the present application;
图2为沿图1所示阵列基板的A-A切线的截面示意图；Fig. 2 is a schematic cross-sectional view along the A-A tangent line of the array substrate shown in Fig. 1;
图3为沿图1所示阵列基板的A-A切线的立体示意图；Fig. 3 is a three-dimensional schematic diagram along the A-A tangent line of the array substrate shown in Fig. 1;
图4为沿图1所示阵列基板的B-B切线的截面示意图；FIG. 4 is a schematic cross-sectional view along the B-B tangent line of the array substrate shown in FIG. 1;
图5为制造图1所示阵列基板的流程示意图；FIG. 5 is a schematic flow chart of manufacturing the array substrate shown in FIG. 1;
图6A-图6J为制造图1所示阵列基板的过程示意图；6A-6J are schematic diagrams of the process of manufacturing the array substrate shown in FIG. 1;
图7为本申请第二实施例阵列基板的截面示意图；7 is a schematic cross-sectional view of an array substrate according to a second embodiment of the present application;
图8为本申请第三实施例阵列基板的截面示意图。FIG. 8 is a schematic cross-sectional view of an array substrate according to a third embodiment of the present application.
本发明的实施方式Embodiments of the present invention
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.
目前，垂直型的薄膜晶体管由于有源层沿阵列基板的厚度方向延伸，使得垂直型的薄膜晶体管在水平方向上占用的空间较小，利用垂直型的薄膜晶体管占用水平空间较小的特点，可以增加在水平方向单位面积的薄膜晶体管的数目。然而，多个垂直型的薄膜晶体管如何阵列地布设于基板上在现有技术中并没有对应的设计，实现阵列排布的 垂直型薄膜晶体管是需要解决的技术问题。At present, since the active layer of the vertical thin film transistor extends along the thickness direction of the array substrate, the vertical thin film transistor occupies a small space in the horizontal direction. By utilizing the feature that the vertical thin film transistor occupies a small horizontal space, it can The number of thin film transistors per unit area in the horizontal direction is increased. However, there is no corresponding design in the prior art on how to arrange a plurality of vertical thin film transistors in an array on a substrate, and realizing vertical thin film transistors arranged in an array is a technical problem that needs to be solved.
针对此问题，本申请将第一薄膜晶体管层设置于基板上，至少一个第一开口贯穿第一薄膜晶体管层，且第一薄膜晶体管层包括多个间隔设置的第一薄膜晶体管，第一薄膜晶体管包括第一电极、第二电极、第一有源图案以及第一栅极，第一电极具有第一侧壁，第二电极具有第二侧壁，第一有源图案在阵列基板的厚度方向上延伸，第一栅极在阵列基板的厚度方向上延伸且在垂直于阵列基板的厚度方向上位于第一有源图案远离第一电极和第二电极的一侧，至少两个第一薄膜晶体管的第一电极和第二电极围绕一个第一开口设置，且一个第一开口包括至少两个第一薄膜晶体管的第一电极的第一侧壁和至少两个第一薄膜晶体管的第二电极的第二侧壁，至少两个垂直型第一薄膜晶体管的组成部分围绕一个第一开口设置的设计，使得多个垂直型的第一薄膜晶体管阵列排布，结合垂直型薄膜晶体占用水平空间小的优点，有利于增加单位面积薄膜晶体管的数目，进而提高包括阵列基板的显示面板的分辨率。To solve this problem, the present application arranges the first thin film transistor layer on the substrate, at least one first opening penetrates the first thin film transistor layer, and the first thin film transistor layer includes a plurality of first thin film transistors arranged at intervals, and the first thin film transistor Including a first electrode, a second electrode, a first active pattern and a first grid, the first electrode has a first side wall, the second electrode has a second side wall, and the first active pattern is in the thickness direction of the array substrate Extending, the first gate extends in the thickness direction of the array substrate and is located on the side of the first active pattern away from the first electrode and the second electrode in the direction perpendicular to the thickness direction of the array substrate, and the at least two first thin film transistors The first electrode and the second electrode are arranged around a first opening, and a first opening includes first side walls of the first electrodes of at least two first thin film transistors and first side walls of the second electrodes of at least two first thin film transistors. Two side walls, at least two vertical first thin film transistors are designed around a first opening, so that a plurality of vertical first thin film transistors are arranged in an array, combined with the advantages of vertical thin film transistors occupying a small horizontal space , which is beneficial to increase the number of thin film transistors per unit area, thereby improving the resolution of the display panel including the array substrate.
请参阅图1-图4，图1为本申请第一实施例阵列基板的俯视图，图2为沿图1所示阵列基板的A-A切线的截面示意图，图3为沿图1所示阵列基板A-A切线的立体示意图，图4为沿图1所示阵列基板的B-B切线的截面示意图。阵列基板100可以应用于液晶显示面板、有机发光二极管显示面板、微型发光二极管显示面板或者次毫米发光二极管显示面板等显示面板。阵列基板100也可以应用于主动式的背光模组。阵列基板100包括基板10、缓冲层101、第一薄膜晶体管层 20、至少一个第一孔100a1以及至少一个第一开口100a3，第一薄膜晶体管层20设置于基板10上，至少一个第一开口100a3和至少一个第一孔100a1均贯穿第一薄膜晶体管层20，至少一个第一孔100a1与至少一个第一开口100a3一对一设置。Please refer to Figures 1-4, Figure 1 is a top view of the array substrate of the first embodiment of the present application, Figure 2 is a schematic cross-sectional view along the A-A tangent line of the array substrate shown in Figure 1, and Figure 3 is a schematic cross-sectional view along the array substrate A-A shown in Figure 1 A schematic perspective view of a tangent line, FIG. 4 is a schematic cross-sectional view along a B-B tangent line of the array substrate shown in FIG. 1 . The array substrate 100 can be applied to display panels such as a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, or a submillimeter light emitting diode display panel. The array substrate 100 can also be applied to an active backlight module. The array substrate 100 includes a substrate 10, a buffer layer 101, a first thin film transistor layer 20, at least one first hole 100a1, and at least one first opening 100a3. The first thin film transistor layer 20 is disposed on the substrate 10, and at least one first opening 100a3 Both the at least one first hole 100a1 and the at least one first hole 100a1 pass through the first thin film transistor layer 20 , and the at least one first hole 100a1 is arranged one-to-one with the at least one first opening 100a3 .
在本实施例中，基板10为玻璃基板。可以理解的是，基板10也可以为柔性基板，例如聚酰亚胺层。In this embodiment, the substrate 10 is a glass substrate. It can be understood that the substrate 10 can also be a flexible substrate, such as a polyimide layer.
在本实施例中，缓冲层101设置于基板10上，缓冲层101用于防止基板10中的杂质扩散至第一薄膜晶体管层20中而影响第一薄膜晶体管20a的电性能。缓冲层101包括氧化硅层或氮化硅层中的至少一种。缓冲层101的厚度为300纳米-600纳米。具体地，缓冲层101为氧化硅层。In this embodiment, the buffer layer 101 is disposed on the substrate 10 , and the buffer layer 101 is used to prevent impurities in the substrate 10 from diffusing into the first TFT layer 20 and affecting the electrical properties of the first TFT 20a. The buffer layer 101 includes at least one of a silicon oxide layer or a silicon nitride layer. The buffer layer 101 has a thickness of 300nm-600nm. Specifically, the buffer layer 101 is a silicon oxide layer.
在本实施例中，第一薄膜晶体管层20设置于缓冲层101上，第一薄膜晶体管层20包括多个间隔设置的第一薄膜晶体管20a。多个第一薄膜晶体管20a包括多个第一薄膜晶体管组20b，多个第一薄膜晶体管组20b相互间隔且阵列排布，每个第一薄膜晶体管组20b由围绕一个第一孔100a1设置的至少两个第一薄膜晶体管20a组成，每个第一薄膜晶体管20a为垂直型的薄膜晶体管。In this embodiment, the first thin film transistor layer 20 is disposed on the buffer layer 101, and the first thin film transistor layer 20 includes a plurality of first thin film transistors 20a arranged at intervals. The plurality of first thin film transistors 20a includes a plurality of first thin film transistor groups 20b, the plurality of first thin film transistor groups 20b are spaced from each other and arranged in an array, and each first thin film transistor group 20b consists of at least one first hole 100a1 arranged around It consists of two first thin film transistors 20a, and each first thin film transistor 20a is a vertical thin film transistor.
具体地，如图1和图2所示，每个第一薄膜晶体管组20b包括围绕一个第一孔100a1间隔设置的四个第一薄膜晶体管20a，围绕一个第一孔100a1设置的四个第一薄膜晶体管20a中心对称设置，每个第一薄膜晶体管组20b中任意相邻两个第一薄膜晶体管20a之间的旋转角度为90度。可以理解的是，每个第一薄膜晶体管组20b也可以包 括两个、三个、五个或者六个围绕第一孔100a1设置的第一薄膜晶体管20a。Specifically, as shown in FIG. 1 and FIG. 2, each first thin film transistor group 20b includes four first thin film transistors 20a arranged at intervals around a first hole 100a1, and four first thin film transistors 20a arranged around a first hole 100a1. The thin film transistors 20a are arranged symmetrically about the center, and the rotation angle between any two adjacent first thin film transistors 20a in each first thin film transistor group 20b is 90 degrees. It can be understood that each first thin film transistor group 20b may also include two, three, five or six first thin film transistors 20a arranged around the first hole 100a1.
在本实施例中，阵列基板还包括至少两个断开部20c，至少两个断开部20c贯穿第一薄膜晶体管层20，围绕一个第一孔100a1设置的至少两个第一薄膜晶体管20a中，任意两个相邻的第一薄膜晶体管20a之间设置有断开部20c，以使得围绕一个第一孔100a1设置的任意相邻两个第一薄膜晶体管20a相互之间电性绝缘。每个第一薄膜晶体管组20b中多个第一薄膜晶体管20a之间的断开部20c围绕一个第一孔100a1设置且与第一孔100a1连通。In this embodiment, the array substrate further includes at least two disconnection parts 20c, the at least two disconnection parts 20c penetrate the first thin film transistor layer 20, and the at least two first thin film transistors 20a arranged around a first hole 100a1 A disconnection portion 20c is disposed between any two adjacent first thin film transistors 20a, so that any two adjacent first thin film transistors 20a disposed around one first hole 100a1 are electrically insulated from each other. The disconnection portion 20c between the plurality of first thin film transistors 20a in each first thin film transistor group 20b is disposed around a first hole 100a1 and communicated with the first hole 100a1.
具体地，每个第一薄膜晶体管组20b包括围绕一个第一孔100a1间隔设置的四个第一薄膜晶体管20a时，断开部20c的数目为4个，4个断开部20c围绕一个第一孔100a1设置且与第一孔100a1连通。Specifically, when each first thin film transistor group 20b includes four first thin film transistors 20a arranged at intervals around a first hole 100a1, the number of disconnected parts 20c is four, and the four disconnected parts 20c surround a first hole 100a1. The hole 100a1 is provided and communicated with the first hole 100a1.
在本实施例中，如图1和图4所示，任意一个第一薄膜晶体管组20b的外围设置有贯穿第一薄膜晶体管层20且环绕第一薄膜晶体管组20b设置的环形槽100b，以使得相邻两个第一薄膜晶体管组20b中的相邻两个第一薄膜晶体管20a之间电性绝缘。环形槽100b的形状为矩形。In this embodiment, as shown in FIG. 1 and FIG. 4 , an annular groove 100b that penetrates the first thin film transistor layer 20 and surrounds the first thin film transistor group 20b is provided on the periphery of any one of the first thin film transistor groups 20b, so that The two adjacent first thin film transistors 20a in the two adjacent first thin film transistor groups 20b are electrically insulated. The shape of the annular groove 100b is rectangular.
在本实施例中，每个第一薄膜晶体管20a包括第一电极201、第一绝缘层202、第二电极203、第一有源图案204、第二绝缘层205以及第一栅极206。多个第一薄膜晶体管20a的第一电极201同层设置，多个第一薄膜晶体管20a的第二电极203同层设置，多个第一薄膜晶体管20a的第一绝缘层202同层设置，多个第一薄膜晶体管20a 的第一有源图案204同层设置，多个第一薄膜晶体管20a的第一栅极206同层设置，多个第一薄膜晶体管20a的第二绝缘层205同层设置，以使得多个阵列排布的垂直型第一薄膜晶体管20a通过同一个制程制备得到。In this embodiment, each first thin film transistor 20 a includes a first electrode 201 , a first insulating layer 202 , a second electrode 203 , a first active pattern 204 , a second insulating layer 205 and a first gate 206 . The first electrodes 201 of the plurality of first thin film transistors 20a are arranged on the same layer, the second electrodes 203 of the plurality of first thin film transistors 20a are arranged on the same layer, and the first insulating layers 202 of the plurality of first thin film transistors 20a are arranged on the same layer. The first active patterns 204 of the first thin film transistors 20a are arranged in the same layer, the first gates 206 of the plurality of first thin film transistors 20a are arranged in the same layer, and the second insulating layers 205 of the plurality of first thin film transistors 20a are arranged in the same layer , so that a plurality of vertical first thin film transistors 20a arranged in an array can be prepared through the same manufacturing process.
需要说明的是，同层设置的多个不同构件是指通过对同一个膜层进行图案化得到的多个不同构件，例如，本申请多个第一薄膜晶体管20a的第一电极201同层设置是指通过对同一个金属膜层进行图案化后得到多个第一电极201，多个第一薄膜晶体管20a的第一绝缘层202同层设置是指对同一个绝缘层进行图案化后得到的多个第一绝缘层202。It should be noted that multiple different components arranged in the same layer refer to multiple different components obtained by patterning the same film layer, for example, the first electrodes 201 of the multiple first thin film transistors 20a in the present application are set It refers to obtaining a plurality of first electrodes 201 after patterning the same metal film layer, and setting the first insulating layers 202 of the plurality of first thin film transistors 20a in the same layer refers to obtaining after patterning the same insulating layer. A plurality of first insulating layers 202 .
在本实施例中，第一电极201设置于第二电极203与基板10之间，第一电极201靠近第一孔100a1的一端具有第一侧壁201a，第一侧壁201a为倾斜的平面。第一电极201为源极或漏极中的一者。第一电极201的制备材料选自钼、铝、钛以及铜中的至少一种。第一电极201的厚度为3000埃-8000埃。可以理解的是，第一电极201与第二电极203也可以同层设置。In this embodiment, the first electrode 201 is disposed between the second electrode 203 and the substrate 10 , and an end of the first electrode 201 close to the first hole 100a1 has a first sidewall 201a, and the first sidewall 201a is an inclined plane. The first electrode 201 is one of a source or a drain. The first electrode 201 is made of at least one material selected from molybdenum, aluminum, titanium and copper. The thickness of the first electrode 201 is 3000-8000 angstroms. It can be understood that the first electrode 201 and the second electrode 203 can also be arranged in the same layer.
具体地，第一电极201设置于缓冲层101上，第一电极201为源极，第一电极201由两个铝层以及位于铝层之间的钛层组成。Specifically, the first electrode 201 is disposed on the buffer layer 101 , the first electrode 201 is a source electrode, and the first electrode 201 is composed of two aluminum layers and a titanium layer between the aluminum layers.
在本实施例中，第一绝缘层202设置于第一电极201和第二电极203之间，第一绝缘层202靠近第一孔100a1的一端具有第三侧壁202a。第一绝缘层202包括氮化硅层或氧化硅层中的至少一种。第一绝缘层202的厚度为0.8微米-1.2微米。In this embodiment, the first insulating layer 202 is disposed between the first electrode 201 and the second electrode 203 , and an end of the first insulating layer 202 near the first hole 100a1 has a third sidewall 202a. The first insulating layer 202 includes at least one of a silicon nitride layer or a silicon oxide layer. The thickness of the first insulating layer 202 is 0.8 μm-1.2 μm.
具体地，第一绝缘层202设置于第一电极201上且使第一电极201的部分暴露，第一电极201暴露的部分相对于第一绝缘层202具有第三侧壁202a的一端向外延伸出来。Specifically, the first insulating layer 202 is disposed on the first electrode 201 and exposes part of the first electrode 201, and the exposed part of the first electrode 201 extends outward relative to the end of the first insulating layer 202 having the third side wall 202a. come out.
其中，第三侧壁202a为倾斜的平面，第三侧壁202a的坡度θ大于0度且小于90度，以便于在第三侧壁202a上形成连续的第一有源图案204。例如，第三侧壁202a的坡度θ为5度、10度、15度、20度、35度、40度、45度、50度、55度、60度、70度或75度。Wherein, the third sidewall 202a is an inclined plane, and the slope θ of the third sidewall 202a is greater than 0 degrees and less than 90 degrees, so as to form a continuous first active pattern 204 on the third sidewall 202a. For example, the slope θ of the third side wall 202a is 5 degrees, 10 degrees, 15 degrees, 20 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 70 degrees or 75 degrees.
进一步地，第三侧壁202a的坡度θ大于或等于30度且小于或等于80度，保证形成连续的第一有源图案204的同时，保证第一有源图案204在第三侧壁202a上的厚度具有均一性，且避免形成在第三侧壁202a上的第一有源图案204的沟道被掺杂而导致漏电流增大的问题。Further, the slope θ of the third sidewall 202a is greater than or equal to 30 degrees and less than or equal to 80 degrees, ensuring that the first active pattern 204 is formed on the third sidewall 202a while forming the continuous first active pattern 204 The thickness of the active pattern 204 is uniform, and avoids the problem that the channel of the first active pattern 204 formed on the third sidewall 202a is doped to cause an increase in leakage current.
在本实施例中，第二电极203设置于第一绝缘层202上，第二电极203靠近第一孔100a1的一端具有第二侧壁203a，第二侧壁203a为倾斜的平面。第二电极203为源极或漏极中的另一者。第二电极203的制备材料选自钼、铝、钛以及铜中的至少一种。第二电极203的厚度为300埃-8000埃。In this embodiment, the second electrode 203 is disposed on the first insulating layer 202, and an end of the second electrode 203 near the first hole 100a1 has a second sidewall 203a, and the second sidewall 203a is an inclined plane. The second electrode 203 is the other of the source or the drain. The second electrode 203 is made of at least one material selected from molybdenum, aluminum, titanium and copper. The thickness of the second electrode 203 is 300 Å-8000 Å.
具体地，第二电极203为漏极，第二电极203由两个铝层以及位于铝层之间的钛层组成。第二侧壁203a与第三侧壁202a共平面，以便于沿着第三侧壁202a和第二侧壁203a形成连续且厚度均匀的第一有源图案204。另外，第二电极203与第一电极201暴露的部分之间形成第一台阶。Specifically, the second electrode 203 is a drain electrode, and the second electrode 203 is composed of two aluminum layers and a titanium layer located between the aluminum layers. The second sidewall 203a is coplanar with the third sidewall 202a, so as to form a continuous and uniform first active pattern 204 along the third sidewall 202a and the second sidewall 203a. In addition, a first step is formed between the second electrode 203 and the exposed portion of the first electrode 201 .
在本实施例中，第一有源图案204在阵列基板100的厚度方向上延伸，且第一有源图案204的部分位于第一侧壁201a、第二侧壁203a以及第三侧壁202a上。第一有源图案204包括第一沟道2041、第一掺杂部2042以及第二掺杂部2043，第一沟道2041连接在第一掺杂部2042与第二掺杂部2043之间，第一掺杂部2042的至少部分在第一电极201的第一侧壁201a上延伸，第二掺杂部2043设置于第二电极203远离第一电极201的表面上，且第一沟道2041的至少部分在第一绝缘层202的第三侧壁202a和第二电极203的第二侧壁203a上延伸。第一有源图案204的制备材料包括金属氧化物、多晶硅、非晶硅中的任意一种。第一有源图案204通过化学沉积形成。In this embodiment, the first active pattern 204 extends in the thickness direction of the array substrate 100, and part of the first active pattern 204 is located on the first sidewall 201a, the second sidewall 203a and the third sidewall 202a . The first active pattern 204 includes a first channel 2041, a first doped portion 2042 and a second doped portion 2043, the first channel 2041 is connected between the first doped portion 2042 and the second doped portion 2043, At least part of the first doped portion 2042 extends on the first side wall 201a of the first electrode 201, the second doped portion 2043 is disposed on the surface of the second electrode 203 away from the first electrode 201, and the first channel 2041 At least a portion of 1 extends on the third sidewall 202 a of the first insulating layer 202 and the second sidewall 203 a of the second electrode 203 . The preparation material of the first active pattern 204 includes any one of metal oxide, polysilicon, and amorphous silicon. The first active pattern 204 is formed by chemical deposition.
具体地，第一沟道2041从第一电极201暴露的部分上沿着第三侧壁202a和第二侧壁203a延伸至第二电极203远离第一电极201的表面上，即第一沟道2041的部分沿着共平面的第二侧壁203a和第三侧壁202a设置，且第一沟道2041的另一部分分别设置于第一电极201远离基板10的表面和第二电极203远离基板10的表面上。第一掺杂部2042从缓冲层101上沿着第一电极201的第一侧壁201a延伸至第一电极201远离缓冲层101的表面上，即第一掺杂部2042设置于第一电极201的表面、第一电极201的第一侧壁201a和缓冲层101上。第二掺杂部2043设置于第二电极203远离第一电极201的表面上。第一有源图案204的制备材料为金属氧化物，例如为氧化铟镓锌。Specifically, the first channel 2041 extends from the exposed part of the first electrode 201 along the third sidewall 202a and the second sidewall 203a to the surface of the second electrode 203 away from the first electrode 201, that is, the first channel 2041 is arranged along the coplanar second sidewall 203a and third sidewall 202a, and the other part of the first channel 2041 is respectively arranged on the surface of the first electrode 201 away from the substrate 10 and the surface of the second electrode 203 away from the substrate 10 on the surface. The first doped portion 2042 extends from the buffer layer 101 along the first sidewall 201a of the first electrode 201 to the surface of the first electrode 201 away from the buffer layer 101 , that is, the first doped portion 2042 is disposed on the first electrode 201 surface, the first sidewall 201a of the first electrode 201 and the buffer layer 101. The second doped part 2043 is disposed on the surface of the second electrode 203 away from the first electrode 201 . The first active pattern 204 is made of metal oxide, such as InGaZnO.
在本实施例中，如图1及图2所示，第一有源图案204在基板10上的正投影为矩形。第一有源图案204的第一沟道2041的宽度为 W，第一有源图案204的第一沟道2041的长度为L。第一沟道2041的宽度W与第一沟道2041的长度L的比值大于或等于1且小于或等于20。例如，第一沟道2041的宽度W与第一沟道2041的长度L的比值为2、3、4、5、6、7、8、9以及12。其中，第一沟道2041的宽度W大于或等于2微米且小于或等于10微米。In this embodiment, as shown in FIGS. 1 and 2 , the orthographic projection of the first active pattern 204 on the substrate 10 is a rectangle. The width of the first channel 2041 of the first active pattern 204 is W, and the length of the first channel 2041 of the first active pattern 204 is L. A ratio of the width W of the first channel 2041 to the length L of the first channel 2041 is greater than or equal to 1 and less than or equal to 20. For example, the ratios of the width W of the first channel 2041 to the length L of the first channel 2041 are 2, 3, 4, 5, 6, 7, 8, 9 and 12. Wherein, the width W of the first trench 2041 is greater than or equal to 2 microns and less than or equal to 10 microns.
在本实施例中，第二绝缘层205为栅极绝缘层，第二绝缘层205的至少部分在阵列基板100的厚度方向上延伸，第二绝缘层205的至少部分设置于第一有源图案204与第一栅极206之间。第二绝缘层205为无机绝缘层，无机绝缘层通过化学沉积形成，无机绝缘层包括氧化硅层或氮化硅层中的至少一种。第二绝缘层205的厚度为1000埃-1500埃。第二绝缘层205也可以为有机绝缘层。In this embodiment, the second insulating layer 205 is a gate insulating layer, at least part of the second insulating layer 205 extends in the thickness direction of the array substrate 100, and at least part of the second insulating layer 205 is disposed on the first active pattern 204 and the first grid 206 . The second insulating layer 205 is an inorganic insulating layer formed by chemical deposition, and the inorganic insulating layer includes at least one of a silicon oxide layer or a silicon nitride layer. The thickness of the second insulating layer 205 is 1000 Å-1500 Å. The second insulating layer 205 can also be an organic insulating layer.
具体地，第二绝缘层205从第一有源图案204的第一掺杂部2042沿着第一沟道2041以及第二掺杂部2043延伸至第二电极203上，且第二绝缘层205覆盖第二电极203，即第二绝缘层205覆盖第一有源图案204以及第二电极203。Specifically, the second insulating layer 205 extends from the first doped portion 2042 of the first active pattern 204 to the second electrode 203 along the first channel 2041 and the second doped portion 2043 , and the second insulating layer 205 Covering the second electrode 203 , that is, the second insulating layer 205 covers the first active pattern 204 and the second electrode 203 .
在本实施例中，第一栅极206在阵列基板100的厚度方向上延伸，且第一栅极206在垂直于阵列基板100的厚度方向上位于第一有源图案204远离第一电极201和第二电极203的一侧。第一栅极206的制备材料选自钼、铝、钛、铜以及银中的至少一种。具体地，第一栅极206沿着第二绝缘层205位于第一孔100a1中的部分延伸至第二绝缘层205远离第二电极203的表面上。In this embodiment, the first gate 206 extends in the thickness direction of the array substrate 100, and the first gate 206 is located on the first active pattern 204 away from the first electrode 201 and the first electrode 201 in the direction perpendicular to the thickness of the array substrate 100 One side of the second electrode 203 . The preparation material of the first grid 206 is selected from at least one of molybdenum, aluminum, titanium, copper and silver. Specifically, the first gate 206 extends along the portion of the second insulating layer 205 located in the first hole 100a1 to the surface of the second insulating layer 205 away from the second electrode 203 .
第一栅极206在基板10上的正投影为矩形。在垂直于阵列基板 100的厚度方向上第一掺杂部2042与第二掺杂部2043分别位于第一栅极206的相对两侧，第一栅极206在基板10上的正投影与第一沟道2041在基板10上的正投影完全重合。The orthographic projection of the first grid 206 on the substrate 10 is a rectangle. The first doped part 2042 and the second doped part 2043 are respectively located on opposite sides of the first gate 206 in the thickness direction perpendicular to the array substrate 100, and the orthographic projection of the first gate 206 on the substrate 10 is the same as the first doped part 2043. The orthographic projections of the channel 2041 on the substrate 10 are completely coincident.
需要说明的是，本实施例以第一栅极206作为掩膜以对第一有源图案204进行掺杂，第一有源图案204为第一栅极206遮挡的部分未掺杂而形成第一沟道2041，第一有源图案204没有被第一栅极206遮挡的部分经过掺杂形成第一掺杂部2042和第二掺杂部2043。It should be noted that, in this embodiment, the first active pattern 204 is doped by using the first gate 206 as a mask, and the first active pattern 204 is undoped for the part covered by the first gate 206 to form the second gate. A channel 2041 , the part of the first active pattern 204 not shielded by the first gate 206 is doped to form a first doped part 2042 and a second doped part 2043 .
在本实施例中，第一开口100a3是通过贯穿形成第一电极201、第一绝缘层202、第二电极203的膜层形成。一个第一薄膜晶体组20b对应一个第一开口100a3设置。围绕同一个第一孔100a1设置的至少两个第一薄膜晶体管20a的第一电极201、第一绝缘层202、第二电极203围绕一个第一开口100a3设置，且一个第一开口100a3包括至少两个第一薄膜晶体管20a的第一电极201的第一侧壁201a、第二电极203的第二侧壁203a以及第一绝缘202层的第三侧壁202a。围绕一个第一孔100a1设置的至少两个断开部20c围绕一个第一开口100a3设置且与一个第一开口100a3连通。In this embodiment, the first opening 100 a 3 is formed through the film layers formed through the first electrode 201 , the first insulating layer 202 , and the second electrode 203 . One first thin film crystal group 20b is set corresponding to one first opening 100a3. The first electrode 201, the first insulating layer 202, and the second electrode 203 of at least two first thin film transistors 20a arranged around the same first hole 100a1 are arranged around a first opening 100a3, and a first opening 100a3 includes at least two The first sidewall 201a of the first electrode 201 of the first thin film transistor 20a, the second sidewall 203a of the second electrode 203, and the third sidewall 202a of the first insulating 202 layer. At least two disconnection portions 20c disposed around one first hole 100a1 are disposed around one first opening 100a3 and communicate with one first opening 100a3.
具体地，第一开口100a3包括第一子开口100a31和第二子开口100a32，第一子开口100a31与第二子开口100a32连通，第一子开口100a31位于第二子开口100a32远离基板10的一侧，且第二子开口100a32的尺寸小于第一子开口100a31的尺寸，第一子开口100a31是通过贯穿形成第二电极203和第一绝缘层202的膜层形成，第二子开口100a32是通过贯穿形成第一电极201的膜层形成。至少两个第 一薄膜晶体管20a的第二电极203和第一绝缘层202围绕第一子开口100a31设置，且第一子开口100a31包括第二电极203的第二侧壁203a和第一绝缘层202的第三侧壁202a；至少两个第一薄膜晶体管20a的第一电极201围绕第二子开口100a32设置，且第二子开口100a32包括第一电极201的第一侧壁201a。其中，第一子开口100a31和第二子开口100a32均为倒正棱台型。Specifically, the first opening 100a3 includes a first sub-opening 100a31 and a second sub-opening 100a32, the first sub-opening 100a31 communicates with the second sub-opening 100a32, the first sub-opening 100a31 is located on the side of the second sub-opening 100a32 away from the substrate 10 , and the size of the second sub-opening 100a32 is smaller than the size of the first sub-opening 100a31, the first sub-opening 100a31 is formed by penetrating the film layer forming the second electrode 203 and the first insulating layer 202, and the second sub-opening 100a32 is formed by penetrating The film layer forming the first electrode 201 is formed. The second electrodes 203 and the first insulating layer 202 of at least two first thin film transistors 20a are arranged around the first sub-opening 100a31, and the first sub-opening 100a31 includes the second sidewall 203a of the second electrode 203 and the first insulating layer 202 The first electrodes 201 of at least two first thin film transistors 20a are disposed around the second sub-opening 100a32, and the second sub-opening 100a32 includes the first sidewall 201a of the first electrode 201. Wherein, the first sub-opening 100a31 and the second sub-opening 100a32 are both inverted prism-shaped.
需要说明的是，第一孔100a1是通过在第一开口100a3中依次形成半导体层、栅极绝缘层以及栅极金属层，对半导体层、栅极绝缘层以及栅极金属层进行图案化以分别得到第一有源图案204、第二绝缘层205以及第一栅极206后形成，即第一孔100a1是通过在第一开口100a3中形成图案化膜层形成。It should be noted that, the first hole 100a1 is formed by sequentially forming a semiconductor layer, a gate insulating layer, and a gate metal layer in the first opening 100a3, and patterning the semiconductor layer, the gate insulating layer, and the gate metal layer to respectively The first active pattern 204 , the second insulating layer 205 and the first gate 206 are obtained, that is, the first hole 100a1 is formed by forming a patterned film layer in the first opening 100a3 .
在本实施例中，第一孔100a1中还可以填充有机材料，以使得阵列基板100的表面变得平坦，有利于发光元件等设置于阵列基板上且将发光元件与第一薄膜晶体管20a之间实现电性连接。其中，第一孔100a1的横截面为正方形，正方形的边长大于或等于2微米，以适应阵列基板的制程精度。In this embodiment, the first holes 100a1 can also be filled with organic materials, so that the surface of the array substrate 100 becomes flat, which facilitates the arrangement of light-emitting elements and the like on the array substrate and the connection between the light-emitting elements and the first thin film transistor 20a. To achieve electrical connection. Wherein, the cross section of the first hole 100a1 is a square, and the side length of the square is greater than or equal to 2 micrometers, so as to adapt to the process precision of the array substrate.
本实施例采用两个或两个以上垂直型的第一薄膜晶体管围绕一个第一孔的设计，有利于采用相同的制程工艺同时制备多个阵列排布的垂直型第一薄膜晶体管，结合垂直型的第一薄膜晶体管充分利用阵列基板厚度方向的空间而占用较小的水平方向的空间，有利于增加薄膜晶体管的数目，进而提高包括阵列基板的显示面板的分辨率。This embodiment adopts the design that two or more vertical first thin film transistors surround one first hole, which is beneficial to simultaneously prepare a plurality of vertical first thin film transistors arranged in an array by using the same manufacturing process. The first thin film transistor fully utilizes the space in the thickness direction of the array substrate and occupies a smaller space in the horizontal direction, which is beneficial to increasing the number of thin film transistors, thereby improving the resolution of the display panel including the array substrate.
请参阅图5，其为制造图1所示阵列基板的流程示意图。制造方 法包括如下步骤：Please refer to FIG. 5 , which is a schematic flow chart of manufacturing the array substrate shown in FIG. 1 . The manufacturing method comprises the steps of:
步骤S100：依次于基板上形成第一电极层、第一绝缘层、第二电极层。Step S100: sequentially forming a first electrode layer, a first insulating layer, and a second electrode layer on the substrate.
具体地，提供一个基板10，采用化学沉积于基板10上形成整面的缓冲层101，采用物理沉积于缓冲层101上形成整面的第一电极层30，采用化学沉积于第一电极层30上形成整面的第一绝缘层202，采用物理沉积于第一绝缘层202上形成整面的第二电极层40，如图6A所示。Specifically, a substrate 10 is provided, a buffer layer 101 is formed on the substrate 10 by chemical deposition, a first electrode layer 30 is formed on the buffer layer 101 by physical deposition, and a first electrode layer 30 is formed on the first electrode layer 30 by chemical deposition. The entire surface of the first insulating layer 202 is formed on the first insulating layer 202, and the entire surface of the second electrode layer 40 is formed on the first insulating layer 202, as shown in FIG. 6A.
步骤S101：形成贯穿第二电极层和第一绝缘层的多个第一子开口。Step S101 : forming a plurality of first sub-openings penetrating through the second electrode layer and the first insulating layer.
具体地，采用传统的黄光制程以及蚀刻工艺形成贯穿第二电极层40和第一绝缘层202的多个第一子开口100a31，第一子开口100a31呈倒四棱台型，第一子开口100a31的纵截面为倒梯形，如图6B所示。Specifically, a plurality of first sub-openings 100a31 penetrating through the second electrode layer 40 and the first insulating layer 202 are formed by adopting a traditional photolithography process and an etching process. The longitudinal section of 100a31 is an inverted trapezoid, as shown in Fig. 6B.
在此步骤中，通过形成第一子开口100a31，使得第一绝缘层202具有围绕第一子开口100a31的第三环型侧壁202b，第二电极层40具有围绕第一子开口100a31的第二环型侧壁40a，第三环型侧壁202b与第二环型侧壁40a共平面，第一子开口100a31由第二环型侧壁40a和第三环型侧壁202b围合而成，第三环型侧壁202b的坡度和第二环型侧壁40a的坡度均大于0度且小于90度。其中，第三环型侧壁202b的坡度和第二环型侧壁40a的坡度均大于或等于30度且小于或等于80度，有利于在第三环型侧壁202b和第二环型侧壁40a上形成连续的第一半导体层，且第一半导体层的厚度具有均一性，还有利于对第 一半导体层进行合适的掺杂以避免掺杂区域过多而漏电流大。In this step, by forming the first sub-opening 100a31, the first insulating layer 202 has a third annular sidewall 202b surrounding the first sub-opening 100a31, and the second electrode layer 40 has a second ring-shaped sidewall 202b surrounding the first sub-opening 100a31. The annular side wall 40a, the third annular side wall 202b and the second annular side wall 40a are coplanar, the first sub-opening 100a31 is surrounded by the second annular side wall 40a and the third annular side wall 202b, Both the slope of the third annular sidewall 202b and the slope of the second annular sidewall 40a are greater than 0 degrees and less than 90 degrees. Wherein, the slope of the third annular side wall 202b and the slope of the second annular side wall 40a are both greater than or equal to 30 degrees and less than or equal to 80 degrees, which is beneficial to the third annular side wall 202b and the second annular side wall A continuous first semiconductor layer is formed on the wall 40a, and the thickness of the first semiconductor layer is uniform, which is also conducive to proper doping of the first semiconductor layer to avoid excessive doping regions and large leakage current.
步骤S102：形成贯穿第一电极层的多个第二子开口，每个第二子开口对应一个第一子开口设置且与第一子开口连通，每个第一子开口的尺寸大于对应的第二子开口的尺寸。Step S102: forming a plurality of second sub-openings penetrating through the first electrode layer, each second sub-opening corresponds to a first sub-opening and communicates with the first sub-opening, and the size of each first sub-opening is larger than the corresponding first sub-opening The size of the second sub-opening.
具体地，采用传统的黄光制程以及蚀刻工艺形成贯穿第一电极层30的第二子开口100a32，通过形成第二子开口100a32，使得第一电极层30具有第一环形侧壁30a，第二子开口100a32由第一环形侧壁30a围合而成。第二子开口100a32对应第一子开口100a31设置，且第一子开口100a31与第二子开口100a32连通，第一子开口100a31的尺寸大于第二子开口100a32的尺寸，第二子开口100a32呈倒四棱台型，第二子开口100a32的纵截面呈倒梯形，如图6C所示。Specifically, the second sub-opening 100a32 penetrating through the first electrode layer 30 is formed by adopting a conventional photolithography process and an etching process. By forming the second sub-opening 100a32, the first electrode layer 30 has a first annular sidewall 30a, and the second The sub-opening 100a32 is enclosed by the first annular side wall 30a. The second sub-opening 100a32 is set corresponding to the first sub-opening 100a31, and the first sub-opening 100a31 communicates with the second sub-opening 100a32. The rectangular truss shape, the longitudinal section of the second sub-opening 100a32 is an inverted trapezoid, as shown in FIG. 6C .
在此步骤中，通过形成第二子开口100a32，且第二子开口100a32的尺寸小于第一子开口100a31的尺寸，第一绝缘层202使第一电极层30的部分暴露，第二电极层40与第一电极层30暴露的部分之间形成第一台阶。In this step, by forming the second sub-opening 100a32, and the size of the second sub-opening 100a32 is smaller than the size of the first sub-opening 100a31, the first insulating layer 202 exposes part of the first electrode layer 30, and the second electrode layer 40 A first step is formed between the portion exposed to the first electrode layer 30 .
步骤S103：于第二电极层上、第一子开口中以及第二子开口中形成台阶型的图案化第一半导体层。Step S103 : forming a stepped patterned first semiconductor layer on the second electrode layer, in the first sub-opening and in the second sub-opening.
具体地，采用化学沉积于第二电极层40远离第一绝缘层202的表面、第二电极层40的第二环型侧壁40a、第一绝缘层202的第三环型侧壁202b、第一电极层30暴露的部分以及缓冲层101上形成整面的第一半导体层，采用黄光制程以及蚀刻工艺对整面的第一半导体层进行图案化，去除第二电极层40上部分的第一半导体层，得到台 阶型的图案化第一半导体层50，台阶型的图案化第一半导体层50从位于第二子开口中的缓冲层101上沿着第一电极层30的第一环形侧壁30a延伸至第一电极层30远离基板10的表面上，再沿着第三环型侧壁202b和第二环型侧壁40a延伸至第二电极层远离第一绝缘层202的表面，如图6D所示。Specifically, using chemical deposition on the surface of the second electrode layer 40 away from the first insulating layer 202, the second annular sidewall 40a of the second electrode layer 40, the third annular sidewall 202b of the first insulating layer 202, the second An entire surface of the first semiconductor layer is formed on the exposed part of the electrode layer 30 and the buffer layer 101, and the entire surface of the first semiconductor layer is patterned by using a photolithography process and an etching process, and the first semiconductor layer on the upper part of the second electrode layer 40 is removed. A semiconductor layer, obtaining a step-type patterned first semiconductor layer 50, the step-type patterned first semiconductor layer 50 starts from the buffer layer 101 located in the second sub-opening along the first annular side of the first electrode layer 30 The wall 30a extends to the surface of the first electrode layer 30 away from the substrate 10, and then extends along the third annular sidewall 202b and the second annular sidewall 40a to the surface of the second electrode layer away from the first insulating layer 202, as Figure 6D shows.
在此步骤中，台阶型的图案化第一半导体层50包括沿第三环型侧壁202b以及第二环形侧壁40a设置的第一倾斜有源层501、沿第一环型侧壁30a设置的第二倾斜有源层505、设置于第一电极层30表面上的第一水平有源层502、设置于第二电极40表面上的第二水平有源层503以及设置于缓冲层101上的第三水平有源层504，第一水平有源层502和第二水平有源层503分别连接于第一倾斜有源层501的相对两侧，第三水平有源层504与第一水平有源层502分别连接于第二倾斜有源层505的相对两侧，图案化第一半导体层50呈台阶型在阵列基板的厚度方向上延伸，有利于节省第一薄膜晶体管在水平方向上占用的空间。In this step, the stepped patterned first semiconductor layer 50 includes a first inclined active layer 501 disposed along the third annular sidewall 202b and the second annular sidewall 40a, and a first inclined active layer 501 disposed along the first annular sidewall 30a. The second inclined active layer 505, the first horizontal active layer 502 disposed on the surface of the first electrode layer 30, the second horizontal active layer 503 disposed on the surface of the second electrode 40, and the buffer layer 101 The third horizontal active layer 504, the first horizontal active layer 502 and the second horizontal active layer 503 are respectively connected to the opposite sides of the first inclined active layer 501, the third horizontal active layer 504 and the first horizontal The active layer 502 is respectively connected to the opposite sides of the second inclined active layer 505, and the patterned first semiconductor layer 50 extends in the thickness direction of the array substrate in a step shape, which is beneficial to save the occupation of the first thin film transistor in the horizontal direction. Space.
步骤S104：形成覆盖台阶型的图案化第一半导体层和第二电极层的第二绝缘层。Step S104: forming a second insulating layer covering the step-shaped patterned first semiconductor layer and the second electrode layer.
具体地，采用化学气相沉积于台阶型的图案化第一半导体层50以及第二电极层40上形成整面的第二绝缘层205，如图6E所示。Specifically, chemical vapor deposition is used to form the entire second insulating layer 205 on the stepped patterned first semiconductor layer 50 and the second electrode layer 40 , as shown in FIG. 6E .
在此步骤中，第二绝缘层205覆盖台阶型的图案化第一半导体层50的部分也呈台阶型。第二绝缘层205包括沿着第一倾斜有源层501设置的第一倾斜绝缘层2051、沿着第二倾斜有源层505设置的第二 倾斜绝缘层2056、设置于第一水平有源层502上的第一水平绝缘层2052、设置于第二水平有源层503上的第二水平绝缘层2053、设置于第三水平有源层504上的第三水平绝缘层2054以及设置于第二电极层40上的第四水平绝缘层2055，第一水平绝缘层2052和第二水平绝缘层2053连接于第一倾斜绝缘层2051的相对两侧，第四水平绝缘层2055连接于第二水平绝缘层2053远离第一倾斜绝缘层2051的一侧，第三水平绝缘层2054和第一水平绝缘层2052分别连接于第二倾斜绝缘层2056的相对两侧，第二水平绝缘层2053、第一倾斜绝缘层2051、第二倾斜绝缘层2056、第一水平绝缘层2052以及第三水平绝缘层2054构成第二绝缘层205的台阶部分。In this step, the portion of the second insulating layer 205 covering the stepped first semiconductor layer 50 is also stepped. The second insulating layer 205 includes a first inclined insulating layer 2051 arranged along the first inclined active layer 501, a second inclined insulating layer 2056 arranged along the second inclined active layer 505, and a second inclined insulating layer 2056 arranged on the first horizontal active layer. 502, the second horizontal insulating layer 2053 disposed on the second horizontal active layer 503, the third horizontal insulating layer 2054 disposed on the third horizontal active layer 504, and the second horizontal insulating layer 2054 disposed on the second horizontal active layer 504. The fourth horizontal insulating layer 2055 on the electrode layer 40, the first horizontal insulating layer 2052 and the second horizontal insulating layer 2053 are connected to opposite sides of the first inclined insulating layer 2051, and the fourth horizontal insulating layer 2055 is connected to the second horizontal insulating layer 2053. The layer 2053 is away from the side of the first inclined insulating layer 2051, the third horizontal insulating layer 2054 and the first horizontal insulating layer 2052 are respectively connected to the opposite sides of the second inclined insulating layer 2056, the second horizontal insulating layer 2053, the first inclined insulating layer The insulating layer 2051 , the second inclined insulating layer 2056 , the first horizontal insulating layer 2052 , and the third horizontal insulating layer 2054 constitute a stepped portion of the second insulating layer 205 .
步骤S105：于第二绝缘层上形成第一栅极层。Step S105: forming a first gate layer on the second insulating layer.
具体地，采用物理沉积于第二绝缘层205上形成整面的第一栅极层60，如图6F所示。Specifically, the entire surface of the first gate layer 60 is formed on the second insulating layer 205 by physical deposition, as shown in FIG. 6F .
步骤S106：采用构图工艺对第一栅极层、第二绝缘层、台阶型的图案化第一半导体层、第一绝缘层、第一电极层以及第二电极层进行图案化处理，得到第一薄膜晶体管层。Step S106: Patterning the first gate layer, the second insulating layer, the stepped patterned first semiconductor layer, the first insulating layer, the first electrode layer, and the second electrode layer by patterning to obtain the first thin film transistor layer.
首先，采用黄光制程以及刻蚀工艺对第一栅极层60进行图案化，得到多个第一栅极206，至少两个第一栅极206对应一个第一子开口100a31设置且呈环形分布，对应一个第一子开口100a31设置的至少两个第一栅极206的部分位于第一子开口100a31内，每个第一栅极206从第一水平绝缘层2052上沿着第一倾斜绝缘层2051延伸至第二水平绝缘层2053上，如图6G所示。其中，每个第一栅极206在基 板10上的正投影为矩形。例如，对应一个第一子开口100a31设置的第一栅极206的数目为4个时，4个第一栅极206呈环形分布且对称地设置，相邻两个第一栅极206之间的旋转角度为90度。Firstly, the first gate layer 60 is patterned by using a photolithography process and an etching process to obtain a plurality of first gates 206, at least two first gates 206 are arranged corresponding to one first sub-opening 100a31 and distributed in a ring shape Parts of at least two first gates 206 corresponding to one first sub-opening 100a31 are located in the first sub-opening 100a31, and each first gate 206 starts from the first horizontal insulating layer 2052 along the first inclined insulating layer 2051 extends to the second horizontal insulating layer 2053, as shown in FIG. 6G. Wherein, the orthographic projection of each first grid 206 on the substrate 10 is a rectangle. For example, when the number of first grids 206 provided corresponding to one first sub-opening 100a31 is four, the four first grids 206 are distributed in a ring and arranged symmetrically, and the number of first grids 206 between two adjacent first grids 206 The rotation angle is 90 degrees.
其次，采用黄光制程以及蚀刻工艺依次对第二绝缘层205以及台阶型的图案化第一半导体层50进行蚀刻，得到多个第一有源图案204和多个第一孔100a1，至少两个第一有源图案204环绕一个第一孔100a1设置。每个第一有源图案204对应一个第一栅极206设置，每个第一有源图案204在基板10上的正投影为矩形，且第一栅极206在基板10上的正投影位于对应的第一有源图案204在基板10上的正投影内。每个第一孔100a1对应一个第一子开口100a31设置，每个第一孔100a1是通过在第一子开口100a31中形成多个第一有源图案204、多个第一栅极206以及图案化第二绝缘层205形成。每个第一孔100a1贯穿第一栅极层60、第二绝缘层205、台阶型的图案化第一半导体层50、第二电极层40、第一绝缘层202以及第一电极层30。Secondly, the second insulating layer 205 and the stepped patterned first semiconductor layer 50 are sequentially etched using a yellow light process and an etching process to obtain a plurality of first active patterns 204 and a plurality of first holes 100a1, at least two The first active pattern 204 is disposed around a first hole 100a1. Each first active pattern 204 is set corresponding to a first grid 206, the orthographic projection of each first active pattern 204 on the substrate 10 is a rectangle, and the orthographic projection of the first grid 206 on the substrate 10 is located at the corresponding In the orthographic projection of the first active pattern 204 on the substrate 10 . Each first hole 100a1 is set corresponding to a first sub-opening 100a31, and each first hole 100a1 is formed by forming a plurality of first active patterns 204, a plurality of first gates 206 and patterning in the first sub-opening 100a31. The second insulating layer 205 is formed. Each first hole 100a1 penetrates through the first gate layer 60 , the second insulating layer 205 , the stepped patterned first semiconductor layer 50 , the second electrode layer 40 , the first insulating layer 202 and the first electrode layer 30 .
具体地，形成贯穿第三水平绝缘层2054的第一通孔2054a，且形成贯穿第三水平有源层504的第二通孔504a，第二通孔504a与第一通孔2054a连通且两者尺寸相同，得到多个第一孔100a1，如图6H所示；蚀刻对应第一开口100a3设置的相邻两个第一栅极206之间的第二绝缘层205和台阶型的图案化第一半导体层50(如虚线框中的图案化第一半导体层50)，得到多个第一有源图案204，如图6I所示。Specifically, a first via hole 2054a penetrating the third horizontal insulating layer 2054 is formed, and a second via hole 504a penetrating the third horizontal active layer 504 is formed, the second via hole 504a communicates with the first via hole 2054a and both The size is the same, and a plurality of first holes 100a1 are obtained, as shown in FIG. The semiconductor layer 50 (patterned first semiconductor layer 50 as shown in the dotted line box), obtains a plurality of first active patterns 204, as shown in FIG. 6I.
接着，采用黄光制程以及蚀刻工艺对第一电极层30和第二电极层40进行蚀刻，得到多个第一电极201和多个第二电极203，如图 6J所示。其中，采用黄光制程以及蚀刻工艺对第一电极层30和第二电极层40进行蚀刻包括：形成贯穿第二绝缘层205、第二电极层40、第一绝缘层202以及第一电极层30的环形槽100b，环形槽100b为环形且围绕环绕一个第一孔100a1设置的至少两个第一有源图案设置，再蚀刻围绕一个第一孔100a1的相邻两个第一有源图案204之间的第一电极层30、第二电极层40以及第一绝缘层202，得到围绕一个第一孔100a1设置的多个第一电极201和多个第二电极203。Next, the first electrode layer 30 and the second electrode layer 40 are etched using a yellow light process and an etching process to obtain a plurality of first electrodes 201 and a plurality of second electrodes 203, as shown in FIG. 6J . Wherein, the etching of the first electrode layer 30 and the second electrode layer 40 by using the yellow light process and the etching process includes: forming The annular groove 100b is annular and arranged around at least two first active patterns arranged around a first hole 100a1, and then etched between two adjacent first active patterns 204 around a first hole 100a1 Between the first electrode layer 30, the second electrode layer 40 and the first insulating layer 202, a plurality of first electrodes 201 and a plurality of second electrodes 203 arranged around a first hole 100a1 are obtained.
最后，如图6J所示，以第一栅极206作为掩膜对多个第一有源图案204进行掺杂，得到多个第一薄膜晶体管组20b，每个第一薄膜晶体管组20b包括围绕一个第一孔100a1设置的至少两个第一薄膜晶体管20a，一个环形槽100b围绕一个第一薄膜晶体管组20b设置，每个第一薄膜晶体管20a包括一个第一电极201、位于第一电极201上的第一绝缘层202、位于第一绝缘层202上的一个第二电极203、沿着一个第一电极201的侧壁、第一绝缘层202的侧壁以及第二电极203的侧壁延伸的第一有源图案204、与第一有源图案204对应的第一栅极206以及第一栅极206与第一有源图案204之间的第二绝缘层205。Finally, as shown in FIG. 6J, a plurality of first active patterns 204 are doped with the first gate 206 as a mask to obtain a plurality of first thin film transistor groups 20b, each first thin film transistor group 20b includes a surrounding At least two first thin film transistors 20a arranged in a first hole 100a1, an annular groove 100b is arranged around a first thin film transistor group 20b, each first thin film transistor 20a includes a first electrode 201, and is located on the first electrode 201 A first insulating layer 202, a second electrode 203 located on the first insulating layer 202, a side wall extending along a side wall of a first electrode 201, a side wall of the first insulating layer 202, and a side wall of the second electrode 203 The first active pattern 204 , the first gate 206 corresponding to the first active pattern 204 , and the second insulating layer 205 between the first gate 206 and the first active pattern 204 .
本实施例阵列基板的制造方法，采用相同的制程制备得到多个第一薄膜晶体管组，每个薄膜晶体管组包括至少两个围绕第一孔设置的垂直型的第一薄膜晶体管，垂直型的第一薄膜晶体管包括第一电极、第二电极、位于第一电极和第二电极之间的第一绝缘层、第一有源图案、第二绝缘层以及第一栅极，以制备得到具有多个阵列排布垂直型 薄膜晶体管的阵列基板，结合垂直型的第一薄膜晶体管占用的水平空间较小的特点，有利于增加薄膜晶体管的数目，进而提高包括阵列基板的显示面板的分辨率。In the manufacturing method of the array substrate in this embodiment, a plurality of first thin film transistor groups are prepared by using the same manufacturing process, each thin film transistor group includes at least two vertical first thin film transistors arranged around the first hole, and the vertical first thin film transistor groups A thin film transistor includes a first electrode, a second electrode, a first insulating layer between the first electrode and the second electrode, a first active pattern, a second insulating layer, and a first gate, so as to prepare a plurality of The array substrate of the vertical thin film transistors arranged in an array, combined with the feature that the first vertical thin film transistor occupies less horizontal space, is beneficial to increase the number of thin film transistors, thereby improving the resolution of the display panel including the array substrate.
请参阅图7，其为本申请第二实施例阵列基板的示意图。图7所示阵列基板与图2所示阵列基板基本相似，不同之处包括：图7所示阵列基板还包括一个第二薄膜晶体管层70、至少一个第二孔100a2、至少一个第二开口100a4以及第五绝缘层80，至少一个第二孔100a2和至少一个第二开口100a4均贯穿第二薄膜晶体管层70，第二薄膜晶体管层70设置于第一薄膜晶体管层20远离基板10的一侧，第五绝缘层80设置于第二薄膜晶体管层70与第一薄膜晶体管层20之间。Please refer to FIG. 7 , which is a schematic diagram of the array substrate according to the second embodiment of the present application. The array substrate shown in FIG. 7 is basically similar to the array substrate shown in FIG. 2, except that the array substrate shown in FIG. 7 further includes a second thin film transistor layer 70, at least one second hole 100a2, and at least one second opening 100a4 As well as the fifth insulating layer 80, at least one second hole 100a2 and at least one second opening 100a4 both penetrate the second thin film transistor layer 70, and the second thin film transistor layer 70 is disposed on the side of the first thin film transistor layer 20 away from the substrate 10, The fifth insulating layer 80 is disposed between the second TFT layer 70 and the first TFT layer 20 .
每个第二薄膜晶体管层70包括多个同层设置的第二薄膜晶体70a，第二薄膜晶体管70a也为垂直型的薄膜晶体管。至少两个第二薄膜晶体管70a围绕一个第二孔100a2设置，围绕一个第二孔100a2设置的至少两个第二薄膜晶体管70a组成第二薄膜晶体管组。Each second thin film transistor layer 70 includes a plurality of second thin film transistors 70a arranged in the same layer, and the second thin film transistors 70a are also vertical thin film transistors. At least two second thin film transistors 70a are arranged around one second hole 100a2, and the at least two second thin film transistors 70a arranged around one second hole 100a2 form a second thin film transistor group.
其中，第二薄膜晶体管70a包括第三电极701、第四电极703、第二有源图案704、第三绝缘层702、第四绝缘层705以及第二栅极706。Wherein, the second thin film transistor 70 a includes a third electrode 701 , a fourth electrode 703 , a second active pattern 704 , a third insulating layer 702 , a fourth insulating layer 705 and a second gate 706 .
在本实施例中，第三电极701靠近第二孔100a2的一端具有第四侧壁701a，电极701为源极，第三电极701的厚度和材料与第一电极201相同，此处不作详述。In this embodiment, the end of the third electrode 701 close to the second hole 100a2 has a fourth side wall 701a, the electrode 701 is the source electrode, and the thickness and material of the third electrode 701 are the same as those of the first electrode 201, which will not be described in detail here .
在本实施例中，第四电极703靠近第二孔100a2的一端具有第五侧壁703a，第四电极703设置于第三电极701远离基板10的一侧。 第四电极703为漏极，第四电极703的厚度和材料与第二电极203相同，此处不作详述。In this embodiment, an end of the fourth electrode 703 close to the second hole 100 a 2 has a fifth sidewall 703 a , and the fourth electrode 703 is disposed on a side of the third electrode 701 away from the substrate 10 . The fourth electrode 703 is a drain electrode, and the thickness and material of the fourth electrode 703 are the same as those of the second electrode 203 , which will not be described in detail here.
在本实施例中，第三绝缘层702靠近第二孔100a2的一端具有第六侧壁702a，第三绝缘层702设置于第三电极701与第四电极703之间。第三绝缘层702的厚度和材料与第一绝缘层202相同，此处不作详述。另外，第三电极701相对于第三绝缘层702具有第六侧壁702a的一端向外延伸，第三电极701与第四电极703相对于第三绝缘层702具有第六侧壁702a的一端向外延伸的部分之间形成第二台阶。In this embodiment, the third insulating layer 702 has a sixth sidewall 702 a near the end of the second hole 100 a 2 , and the third insulating layer 702 is disposed between the third electrode 701 and the fourth electrode 703 . The thickness and material of the third insulating layer 702 are the same as those of the first insulating layer 202 , which will not be described in detail here. In addition, one end of the third electrode 701 with the sixth sidewall 702a extends outward relative to the third insulating layer 702 , and the third electrode 701 and the fourth electrode 703 extend outward relative to the end of the third insulating layer 702 with the sixth sidewall 702a. A second step is formed between the outwardly extending portions.
其中，第六侧壁702a的坡度均大于或等于30度且小于或等于80度，以便于后续形成平整的。第六侧壁702a与第五侧壁703a共平面。具体地，第六侧壁702a的坡度等于第三侧壁202a的坡度。Wherein, the slope of the sixth side wall 702a is greater than or equal to 30 degrees and less than or equal to 80 degrees, so as to facilitate the subsequent formation of a flat one. The sixth side wall 702a is coplanar with the fifth side wall 703a. Specifically, the slope of the sixth sidewall 702a is equal to the slope of the third sidewall 202a.
在本实施例中，第二有源图案704在阵列基板100的厚度方向上延伸，且第二有源图案704的部分位于第四侧壁701a、第五侧壁703a以及第六侧壁702a上。第二有源图案704与第一有源图案204通过图案化同一个半导体层得到。第二有源图案704的厚度和材料与第一有源图案204相同，此处不作详述。In this embodiment, the second active pattern 704 extends in the thickness direction of the array substrate 100, and part of the second active pattern 704 is located on the fourth sidewall 701a, the fifth sidewall 703a and the sixth sidewall 702a . The second active pattern 704 and the first active pattern 204 are obtained by patterning the same semiconductor layer. The thickness and material of the second active pattern 704 are the same as those of the first active pattern 204 , which will not be described in detail here.
具体地，第二有源图案704由第五绝缘层80上沿着第四侧壁701a延伸至第三电极701远离第五绝缘层80的表面上，且从第三电极701上沿着第六侧壁702a以及第五侧壁703a延伸至第四电极703远离第三绝缘层702的表面上。Specifically, the second active pattern 704 extends from the fifth insulating layer 80 along the fourth side wall 701 a to the surface of the third electrode 701 away from the fifth insulating layer 80 , and extends from the third electrode 701 along the sixth The sidewall 702 a and the fifth sidewall 703 a extend to the surface of the fourth electrode 703 away from the third insulating layer 702 .
其中，第二有源图案704包括第二沟道7041、第三掺杂部7042 和第四掺杂部7043，第三掺杂部7042和第四掺杂部7043连接于第二沟道7041的相对两端，在垂直于阵列基板100厚度的方向上第三掺杂部7042和第四掺杂部7043分别位于第二栅极706的相对两侧。Wherein, the second active pattern 704 includes a second channel 7041, a third doped part 7042 and a fourth doped part 7043, and the third doped part 7042 and the fourth doped part 7043 are connected to the second channel 7041 The third doped part 7042 and the fourth doped part 7043 are respectively located on opposite sides of the second gate 706 in the direction perpendicular to the thickness of the array substrate 100 at opposite ends.
在本实施例中，第二栅极706在阵列基板100的厚度方向上延伸，且在垂直于阵列基板100的厚度方向上第二栅极706位于第二有源图案704远离第三电极701和第四电极703的一侧。第二栅极706与第一栅极206通过图案化同一个栅极金属层得到，第二栅极706的厚度和材料与第一栅极206相同，此处不做详述。In this embodiment, the second gate 706 extends in the thickness direction of the array substrate 100, and the second gate 706 is located on the second active pattern 704 away from the third electrode 701 and One side of the fourth electrode 703 . The second gate 706 is obtained by patterning the same gate metal layer as the first gate 206 , and the thickness and material of the second gate 706 are the same as those of the first gate 206 , which will not be described in detail here.
在本实施例中，第四绝缘层705的至少部分在阵列基板100的厚度方向上延伸，且第四绝缘层705的至少部分设置于第二有源图案704与第二栅极706之间。第四绝缘层705与第二绝缘层205通过图案化同一个绝缘层得到，第四绝缘层705的厚度和材料与第二绝缘层205与相同，此处不做详述。具体地，第四绝缘层705覆盖整个第二有源图案704和第四电极703。In this embodiment, at least part of the fourth insulating layer 705 extends in the thickness direction of the array substrate 100 , and at least part of the fourth insulating layer 705 is disposed between the second active pattern 704 and the second gate 706 . The fourth insulating layer 705 and the second insulating layer 205 are obtained by patterning the same insulating layer. The thickness and material of the fourth insulating layer 705 are the same as those of the second insulating layer 205 , which will not be described in detail here. Specifically, the fourth insulating layer 705 covers the entire second active pattern 704 and the fourth electrode 703 .
在本实施例中，第五绝缘层80包括第三开口80a，第三开口80a连通第二开口100a4和第一开口100a3。第五绝缘层80的制备材料选自氮化硅或氧化硅中的至少一种。In this embodiment, the fifth insulating layer 80 includes a third opening 80a, and the third opening 80a communicates with the second opening 100a4 and the first opening 100a3. The fifth insulating layer 80 is made of at least one material selected from silicon nitride or silicon oxide.
在本实施例中，每个第二薄膜晶体管层70中的第二薄膜晶体管70a的数目与每个第一薄膜晶体管层20中的第一薄膜晶体管20a的数目相同。另外，一个第二薄膜晶体管层70中的第二薄膜晶体管70a与第一薄膜晶体管层20中的第一薄膜晶体管20a在阵列基板的厚度方向上一一对应设置，第一薄膜晶体管20a的第二绝缘层205与对应 设置的第二薄膜晶体管70a的第四绝缘层705连接，第一薄膜晶体管20a与对应的第二薄膜晶体管70a之间电性绝缘。In this embodiment, the number of second TFTs 70 a in each second TFT layer 70 is the same as the number of first TFTs 20 a in each first TFT layer 20 . In addition, the second thin film transistor 70a in the second thin film transistor layer 70 is arranged in one-to-one correspondence with the first thin film transistor 20a in the first thin film transistor layer 20 in the thickness direction of the array substrate. The insulating layer 205 is connected to the fourth insulating layer 705 of the corresponding second thin film transistor 70a, and the first thin film transistor 20a is electrically insulated from the corresponding second thin film transistor 70a.
在本实施例中，至少一个第二开口100a4与至少一个第一开口100a3一对一设置，且每个第二开口100a4与对应的第一开口100a3连通。其中，至少两个第二薄膜晶体管70a的第三电极701、第四电极703以及第三绝缘层702围绕一个第二开口100a4设置，且一个第二开口100a4包括至少两个第二薄膜晶体管70a的第三电极701的第四侧壁701a、至少两个第二薄膜晶体管70a的第四电极703的第五侧壁703a以及至少两个第二薄膜晶体管70a的第三绝缘层702的第六侧壁702a。第二开口100a4包括第三子开口100a41和第四子开口100a42，第三子开口100a41位于第四子开口100a42远离基板10的一侧，第三子开口100a41的尺寸大于第四子开口100a42的尺寸。第三子开口100a41和第四子开口100a42均为倒四棱台型。In this embodiment, at least one second opening 100a4 is arranged one-to-one with at least one first opening 100a3, and each second opening 100a4 communicates with the corresponding first opening 100a3. Wherein, the third electrode 701, the fourth electrode 703 and the third insulating layer 702 of at least two second thin film transistors 70a are arranged around one second opening 100a4, and one second opening 100a4 includes at least two second thin film transistors 70a The fourth side wall 701a of the third electrode 701, the fifth side wall 703a of the fourth electrode 703 of the at least two second thin film transistors 70a, and the sixth side wall of the third insulating layer 702 of the at least two second thin film transistors 70a 702a. The second opening 100a4 includes a third sub-opening 100a41 and a fourth sub-opening 100a42, the third sub-opening 100a41 is located on the side of the fourth sub-opening 100a42 away from the substrate 10, the size of the third sub-opening 100a41 is larger than the size of the fourth sub-opening 100a42 . Both the third sub-opening 100a41 and the fourth sub-opening 100a42 are in the shape of an inverted quadrangular prism.
在本实施例中，第二孔100a2是通过在第二开口100a4中形成第二有源图案704、第四绝缘层705以及第二栅极706形成，第二开口100a4与第二孔100a2在阵列基板的厚度方向上一对一上下设置。第二孔100a2与第一孔100a1在阵列基板的厚度方向上一对一上下设置，且第二孔100a2与第一孔100a1连通，第二孔100a2的尺寸大于第一孔100a1的尺寸。In this embodiment, the second hole 100a2 is formed by forming the second active pattern 704, the fourth insulating layer 705 and the second gate 706 in the second opening 100a4, and the second opening 100a4 and the second hole 100a2 are formed in an array One to one up and down in the thickness direction of the substrate. The second hole 100a2 and the first hole 100a1 are arranged one to one above the other in the thickness direction of the array substrate, and the second hole 100a2 communicates with the first hole 100a1, and the size of the second hole 100a2 is larger than that of the first hole 100a1.
需要说明的是，第二薄膜晶体管层70的层数可以为一个，也可以为多个，例如3个、4个、5个等。相邻两个第二薄膜晶体管层70之间设置绝缘层。另外，第一薄膜晶体管层20与至少一个第二薄膜 晶体管层70可以通过同一个制程制备得到，以制备多个阵列排布的垂直型薄膜晶体管的同时，简化制程。It should be noted that the number of layers of the second thin film transistor layer 70 may be one or multiple, for example, 3, 4, 5 and so on. An insulating layer is provided between two adjacent second thin film transistor layers 70 . In addition, the first thin film transistor layer 20 and the at least one second thin film transistor layer 70 can be prepared through the same process, so as to simplify the process while preparing a plurality of vertical thin film transistors arranged in an array.
请参阅图8，其为本申请第三实施例阵列基板的截面示意图。图8所示阵列基板与图7所示阵列基板基本相似，不同之处包括：第二薄膜晶体管层70的数目为两个，至少一个第一薄膜晶体管20a与至少一个第二薄膜晶体管70a在阵列基板的厚度方向上相邻且对应设置，且至少一个第一薄膜晶体管20a的第二电极203复用为与第一薄膜晶体管20a相邻且对应设置的第二薄膜晶体管70a的第三电极701。Please refer to FIG. 8 , which is a schematic cross-sectional view of the array substrate according to the third embodiment of the present application. The array substrate shown in FIG. 8 is basically similar to the array substrate shown in FIG. 7, the differences include: the number of the second thin film transistor layer 70 is two, at least one first thin film transistor 20a and at least one second thin film transistor 70a are in the array The thickness direction of the substrate is adjacent and correspondingly disposed, and the second electrode 203 of at least one first thin film transistor 20a is multiplexed as the third electrode 701 of the second thin film transistor 70a adjacent to and correspondingly disposed to the first thin film transistor 20a.
在本实施例中，第一薄膜晶体管20a的第一有源图案204和与第一薄膜晶体管20a对应设置的第二薄膜晶体管70a的第二有源图案704连接，第一薄膜晶体管20a的第二绝缘层205和与第一薄膜晶体管20a对应设置的第二薄膜晶体管70a的第四绝缘层705连接。In this embodiment, the first active pattern 204 of the first thin film transistor 20a is connected to the second active pattern 704 of the second thin film transistor 70a corresponding to the first thin film transistor 20a, and the second active pattern 704 of the first thin film transistor 20a The insulating layer 205 is connected to the fourth insulating layer 705 of the second thin film transistor 70 a corresponding to the first thin film transistor 20 a.
需要说明的是，本实施例中的两个第二薄膜晶体管层70的第二有源图案704和一个第一薄膜晶体管层20中的第一有源图案204通过对同一个半导体层进行图案化得到，且两个第二薄膜晶体管层70的第二栅极706和一个第一薄膜晶体管层20中的第一栅极206通过对同一个栅极层进行图案化得到，两个第二薄膜晶体管层70的第四绝缘层705和一个第一薄膜晶体管层20中的第二绝缘层205为同一个绝缘层，两个第二薄膜晶体管层70和第一薄膜晶体管层20可以采用同一个制程制备得到，简化制程的同时，有利于增加薄膜晶体管的数目，进而提高包括阵列基板的显示面板的分辨率。It should be noted that, in this embodiment, the second active patterns 704 of the two second thin film transistor layers 70 and the first active pattern 204 in one first thin film transistor layer 20 are obtained by patterning the same semiconductor layer obtained, and the second gates 706 of the two second thin film transistor layers 70 and the first gate 206 in one first thin film transistor layer 20 are obtained by patterning the same gate layer, the two second thin film transistors The fourth insulating layer 705 of layer 70 and the second insulating layer 205 in one first thin film transistor layer 20 are the same insulating layer, and the two second thin film transistor layers 70 and the first thin film transistor layer 20 can be prepared by the same process It is obtained that, while simplifying the manufacturing process, it is beneficial to increase the number of thin film transistors, thereby improving the resolution of the display panel including the array substrate.
本申请还提供一种显示面板，显示面板包括上述任意一种阵列基 板和发光元件，发光元件可以为液晶显示单元、微型发光二极管、次毫米发光二极管或者有机发光二极管。发光元件与至少一个第一薄膜晶体管电性连接，至少一个第一薄膜晶体管控制发光元件的开启。可以理解的是，发光元件也可以与至少一个第二薄膜晶体管电性连接。The present application also provides a display panel. The display panel includes any one of the above-mentioned array substrates and a light emitting element. The light emitting element can be a liquid crystal display unit, a micro light emitting diode, a submillimeter light emitting diode or an organic light emitting diode. The light emitting element is electrically connected with at least one first thin film transistor, and the at least one first thin film transistor controls the turning on of the light emitting element. It can be understood that the light emitting element can also be electrically connected with at least one second thin film transistor.
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。The descriptions of the above embodiments are only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or modify some of the technical solutions. Features are replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (17)

  1. 一种阵列基板，其中，所述阵列基板包括：An array substrate, wherein the array substrate comprises:
    基板；以及substrate; and
    第一薄膜晶体管层，设置于所述基板上，所述第一薄膜晶体管层包括：The first thin film transistor layer is disposed on the substrate, and the first thin film transistor layer includes:
    多个间隔设置的第一薄膜晶体管，所述第一薄膜晶体管包括：A plurality of first thin film transistors arranged at intervals, the first thin film transistors include:
    第一电极，具有第一侧壁；a first electrode having a first sidewall;
    第二电极，具有第二侧壁；a second electrode having a second sidewall;
    第一有源图案，在所述阵列基板的厚度方向上延伸；以及a first active pattern extending in a thickness direction of the array substrate; and
    第一栅极，在所述阵列基板的厚度方向上延伸，且在垂直于所述阵列基板的厚度方向上位于所述第一有源图案远离所述第一电极和所述第二电极的一侧；以及a first gate extending in the thickness direction of the array substrate, and located on a side of the first active pattern away from the first electrode and the second electrode in a direction perpendicular to the thickness direction of the array substrate side; and
    至少一个第一开口，贯穿所述第一薄膜晶体管层；at least one first opening penetrating through the first thin film transistor layer;
    其中，至少两个所述第一薄膜晶体管的所述第一电极和所述第二电极围绕一个所述第一开口设置，且一个所述第一开口包括至少两个所述第一薄膜晶体管的所述第一电极的第一侧壁以及至少两个所述第一薄膜晶体管的所述第二电极的所述第二侧壁。Wherein, the first electrode and the second electrode of at least two of the first thin film transistors are arranged around one of the first openings, and one of the first openings includes at least two of the first thin film transistors. The first sidewall of the first electrode and the second sidewalls of the second electrodes of at least two first thin film transistors.
  2. 根据权利要求1所述的阵列基板，其中，所述第一电极设置于所述第二电极与所述基板之间，且所述第一薄膜晶体管还包括：The array substrate according to claim 1, wherein the first electrode is disposed between the second electrode and the substrate, and the first thin film transistor further comprises:
    第一绝缘层，设置于所述第一电极与所述第二电极之间，所述第一绝缘层具有第三侧壁；以及a first insulating layer disposed between the first electrode and the second electrode, the first insulating layer having a third sidewall; and
    第二绝缘层，所述第二绝缘层的至少部分在所述阵列基板的厚度方向上延伸，且所述第二绝缘层的至少部分设置于所述第一有源图案与所述第一栅极之间；A second insulating layer, at least part of the second insulating layer extends in the thickness direction of the array substrate, and at least part of the second insulating layer is disposed between the first active pattern and the first gate Between poles;
    其中，至少两个所述第一薄膜晶体管的所述第一绝缘层围绕一个所述第一开口设置，一个所述第一开口还包括至少两个所述第一薄膜晶体管的所述第一绝缘层的所述第三侧壁，且所述第一有源图案的部分位于所述第一绝缘层的所述第三侧壁上。Wherein, the first insulating layers of at least two of the first thin film transistors are arranged around one of the first openings, and one of the first openings further includes the first insulating layers of at least two of the first thin film transistors. layer, and a portion of the first active pattern is located on the third sidewall of the first insulating layer.
  3. 根据权利要求2所述的阵列基板，其中，所述第一开口包括：The array substrate according to claim 2, wherein the first opening comprises:
    第一子开口，至少两个所述第一薄膜晶体管的所述第二电极和所述第一绝缘层围绕所述第一子开口设置，且所述第一子开口包括所述第二电极的所述第二侧壁和所述第一绝缘层的所述第三侧壁，所述第二侧壁与所述第三侧壁共平面；以及The first sub-opening, the second electrodes of at least two first thin film transistors and the first insulating layer are arranged around the first sub-opening, and the first sub-opening includes the second electrodes. the second sidewall and the third sidewall of the first insulating layer, the second sidewall being coplanar with the third sidewall; and
    第二子开口，至少两个所述第一薄膜晶体管的所述第一电极围绕所述第二子开口设置，且所述第二子开口包括所述第一电极的所述第一侧壁，所述第二子开口与所述第一子开口连通，且所述第二子开口的尺寸小于所述第一子开口的尺寸。a second sub-opening, the first electrodes of at least two first thin film transistors are disposed around the second sub-opening, and the second sub-opening includes the first sidewall of the first electrode, The second sub-opening communicates with the first sub-opening, and the size of the second sub-opening is smaller than that of the first sub-opening.
  4. 根据权利要求2所述的阵列基板，其中，所述第三侧壁的坡度大于或等于30度且小于或等于80度。The array substrate according to claim 2, wherein the slope of the third side wall is greater than or equal to 30 degrees and less than or equal to 80 degrees.
  5. 根据权利要求2所述的阵列基板，其中，所述第一有源图案包括：The array substrate according to claim 2, wherein the first active pattern comprises:
    第一掺杂部，所述第一掺杂部的至少部分在所述第一电极的所述第一侧壁上延伸；a first doped portion, at least part of which extends on the first sidewall of the first electrode;
    第二掺杂部，设置于所述第二电极远离所述第一电极的表面上；以及a second doped portion disposed on a surface of the second electrode away from the first electrode; and
    第一沟道，连接在所述第一掺杂部与所述第二掺杂部之间，且所述第一沟道的至少部分在所述第一绝缘层的所述第三侧壁和所述第二电极的所述第二侧壁上延伸。a first channel connected between the first doped portion and the second doped portion, and at least part of the first channel is between the third sidewall and the first insulating layer extending on the second sidewall of the second electrode.
  6. 根据权利要求5所述的阵列基板，其中，在垂直于所述阵列基板厚度的方向上所述第一掺杂部与所述第二掺杂部分别位于所述第一栅极的相对两侧，且所述第一沟道在所述基板上的正投影与所述第一栅极在所述基板上的正投影完全重合。The array substrate according to claim 5, wherein in a direction perpendicular to the thickness of the array substrate, the first doped part and the second doped part are respectively located on opposite sides of the first gate , and the orthographic projection of the first channel on the substrate completely coincides with the orthographic projection of the first grid on the substrate.
  7. 根据权利要求1所述的阵列基板，其中，所述第一有源图案在所述基板上的正投影对应的图形为矩形，所述第一栅极在所述基板上的正投影对应的图形为矩形。The array substrate according to claim 1, wherein the figure corresponding to the orthographic projection of the first active pattern on the substrate is a rectangle, and the figure corresponding to the orthographic projection of the first gate on the substrate is a rectangle.
  8. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：The array substrate according to claim 1, wherein the array substrate further comprises:
    至少两个断开部，至少两个所述断开部贯穿所述第一薄膜晶体管层，至少两个所述断开部围绕一个所述第一开口设置且与一个所述第一开口连通，且每个所述断开部位于对应一个所述第一开口设置的相邻两个所述第一薄膜晶体管之间，对应一个所述第一开口设置的相邻两个所述第一薄膜晶体管的所述第一电极和所述第二电极围绕一个所述第一开口设置。At least two disconnection parts, at least two disconnection parts penetrate the first thin film transistor layer, at least two disconnection parts are arranged around one of the first openings and communicate with one of the first openings, And each of the disconnecting parts is located between two adjacent first thin film transistors arranged corresponding to one of the first openings, and two adjacent first thin film transistors arranged corresponding to one of the first openings The first electrode and the second electrode are arranged around one of the first openings.
  9. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：The array substrate according to claim 1, wherein the array substrate further comprises:
    环形槽，贯穿所述第一薄膜晶体管层，且环绕一个第一薄膜晶体管组设置，一个所述第一薄膜晶体组由对应一个所述第一开口设置的 至少两个所述第一薄膜晶体管组成，对应一个所述第一开口设置的至少两个所述第一薄膜晶体管的所述第一电极和所述第二电极围绕一个所述第一开口设置。An annular groove that runs through the first thin film transistor layer and is arranged around a first thin film transistor group, where one first thin film transistor group is composed of at least two first thin film transistors arranged corresponding to one first opening The first electrodes and the second electrodes of the at least two first thin film transistors corresponding to one of the first openings are arranged around one of the first openings.
  10. 根据权利要求2所述的阵列基板，其中，多个所述第一薄膜晶体管的所述第一电极同层设置，多个所述第一薄膜晶体管的所述第二电极同层设置，多个所述第一薄膜晶体管的所述第一绝缘层同层设置，多个所述第一薄膜晶体管的所述第一有源图案同层设置，多个所述第一薄膜晶体管的所述第一栅极同层设置，多个所述第一薄膜晶体管的所述第二绝缘层同层设置。The array substrate according to claim 2, wherein the first electrodes of the plurality of first thin film transistors are arranged on the same layer, the second electrodes of the plurality of first thin film transistors are arranged on the same layer, and the plurality of first electrodes of the first thin film transistors are arranged on the same layer. The first insulating layers of the first thin film transistors are arranged in the same layer, the first active patterns of the plurality of first thin film transistors are arranged in the same layer, and the first of the plurality of first thin film transistors The gates are arranged in the same layer, and the second insulating layers of the plurality of first thin film transistors are arranged in the same layer.
  11. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：The array substrate according to claim 2, wherein the array substrate further comprises:
    第二薄膜晶体管层，设置于所述第一薄膜晶体管层远离所述基板的一侧，且包括多个间隔设置的第二薄膜晶体管，所述第二薄膜晶体管包括：The second thin film transistor layer is disposed on a side of the first thin film transistor layer away from the substrate, and includes a plurality of second thin film transistors arranged at intervals, and the second thin film transistors include:
    第三电极，具有第四侧壁；a third electrode having a fourth sidewall;
    第四电极，具有第五侧壁，且设置于所述第三电极远离所述基板的一侧；The fourth electrode has a fifth sidewall and is disposed on a side of the third electrode away from the substrate;
    第三绝缘层，具有第六侧壁，且设置于所述第三电极与所述第四电极之间；a third insulating layer having a sixth sidewall and disposed between the third electrode and the fourth electrode;
    第二有源图案，在所述阵列基板的厚度方向上延伸，且所述第二有源图案的部分位于所述第四侧壁、所述第五侧壁以及所述第六侧壁上；a second active pattern extending in the thickness direction of the array substrate, and part of the second active pattern is located on the fourth sidewall, the fifth sidewall, and the sixth sidewall;
    第二栅极，在所述阵列基板的厚度方向上延伸，且在垂直于所述阵列基板的厚度方向上位于所述第二有源图案远离所述第三电极和所述第四电极的一侧；以及a second gate extending in the thickness direction of the array substrate, and located on a side of the second active pattern away from the third electrode and the fourth electrode in a direction perpendicular to the thickness direction of the array substrate side; and
    第四绝缘层，所述第四绝缘层的至少部分在所述阵列基板的厚度方向上延伸，且所述第四绝缘层的至少部分设置于所述第二有源图案与所述第二栅极之间；以及a fourth insulating layer, at least part of the fourth insulating layer extends in the thickness direction of the array substrate, and at least part of the fourth insulating layer is disposed between the second active pattern and the second gate between poles; and
    至少一个第二开口，贯穿所述第二薄膜晶体管层，与至少一个所述第一开口一对一设置，且每个所述第二开口与对应的所述第一开口连通；At least one second opening runs through the second thin film transistor layer and is arranged one-to-one with at least one of the first openings, and each of the second openings communicates with the corresponding first opening;
    其中，至少两个所述第二薄膜晶体管的所述第三电极、所述第四电极以及所述第三绝缘层围绕一个所述第二开口设置，且一个所述第二开口包括至少两个所述第二薄膜晶体管的所述第三电极的第四侧壁、至少两个所述第二薄膜晶体管的所述第四电极的所述第五侧壁以及至少两个所述第二薄膜晶体管的所述第三绝缘层的所述第六侧壁。Wherein, the third electrode, the fourth electrode and the third insulating layer of at least two of the second thin film transistors are arranged around one of the second openings, and one of the second openings includes at least two The fourth sidewall of the third electrode of the second thin film transistor, the fifth sidewall of the fourth electrode of at least two of the second thin film transistors, and at least two of the second thin film transistors The sixth sidewall of the third insulating layer.
  12. 根据权利要求11所述的阵列基板，其中，所述第一薄膜晶体管层中的多个所述第一薄膜晶体管与一个所述第二薄膜晶体管层中的多个所述第二薄膜晶体管在所述阵列基板的厚度方向上一对一设置。The array substrate according to claim 11, wherein the plurality of first thin film transistors in the first thin film transistor layer and the plurality of second thin film transistors in one second thin film transistor layer are in the same The array substrates are arranged one-to-one in the thickness direction of the array substrate.
  13. 根据权利要求12所述的阵列基板，其中，所述第一薄膜晶体管层与所述第二薄膜晶体管层相邻设置，所述第一薄膜晶体管的所述第二电极复用为与所述第一薄膜晶体管相邻且对应设置的所述第二薄膜晶体管的所述第三电极。The array substrate according to claim 12, wherein the first thin film transistor layer is adjacent to the second thin film transistor layer, and the second electrode of the first thin film transistor is multiplexed with the first thin film transistor layer. A thin film transistor is adjacent to and corresponding to the third electrode of the second thin film transistor.
  14. 根据权利要求12所述的阵列基板，其中，所述第一薄膜晶体管的所述第一有源图案和与所述第一薄膜晶体管对应设置的所述第二薄膜晶体管的所述第二有源图案连接，所述第一薄膜晶体管的所述第二绝缘层和与所述第一薄膜晶体管对应设置的所述第二薄膜晶体管的所述第四绝缘层连接。The array substrate according to claim 12, wherein the first active pattern of the first thin film transistor and the second active pattern of the second thin film transistor corresponding to the first thin film transistor are The second insulating layer of the first thin film transistor is connected to the fourth insulating layer of the second thin film transistor corresponding to the first thin film transistor.
  15. 根据权利要求11所述的阵列基板，其中，所述第二开口的尺寸大于对应的所述第一开口的尺寸。The array substrate according to claim 11, wherein a size of the second opening is larger than a corresponding size of the first opening.
  16. 一种显示面板，其中，所述显示面板包括如权利要求1所述阵列基板及发光元件，所述发光元件与至少一个所述第一薄膜晶体管电性连接。A display panel, wherein the display panel comprises the array substrate according to claim 1 and a light emitting element, the light emitting element is electrically connected to at least one of the first thin film transistors.
  17. 一种如权利要求1所述阵列基板的制造方法，其中，所述方法包括如下步骤：A method for manufacturing an array substrate as claimed in claim 1, wherein said method comprises the following steps:
    于基板上形成第一电极层和第二电极层；forming a first electrode layer and a second electrode layer on the substrate;
    形成贯穿所述第一电极层和所述第二电极层的至少一个开口，所述开口包括所述第一电极层的第一环形侧壁和所述第二电极层的第二环形侧壁；forming at least one opening through the first electrode layer and the second electrode layer, the opening including a first annular sidewall of the first electrode layer and a second annular sidewall of the second electrode layer;
    至少于所述第一电极层的第一环形侧壁、所述第二电极层的第二环形侧壁以及所述基板上形成图案化半导体层；forming a patterned semiconductor layer on at least the first annular sidewall of the first electrode layer, the second annular sidewall of the second electrode layer, and the substrate;
    至少于所述图案化半导体层远离所述第一电极层和第二电极层的表面上形成对应一个所述开口设置的至少两个间隔设置的第一栅极，对应一个所述开口设置的至少两个间隔设置的第一栅极的部分位于所述开口内；At least two first gates arranged at intervals corresponding to one of the openings are formed on the surface of the patterned semiconductor layer away from the first electrode layer and the second electrode layer, and at least two first gates arranged at intervals corresponding to one of the openings are formed. two spaced-apart portions of the first grid are located within the opening;
    形成贯穿所述图案化半导体层、所述第一电极层以及所述第二电极层的至少两个断开部，每个所述断开部位于对应一个所述第一开口设置的相邻两个所述第一栅极之间，至少两个所述断开部与所述开口连通，且至少两个断开部将所述图案化半导体层、所述第一电极层以及所述第二电极层分别断开为至少两个所述第一有源图案、至少两个所述第一电极以及至少两个所述第二电极。Forming at least two disconnected parts through the patterned semiconductor layer, the first electrode layer and the second electrode layer, each of the disconnected parts is located on two adjacent adjacent ones of the first openings. Between the two first gates, at least two disconnected parts communicate with the opening, and at least two disconnected parts connect the patterned semiconductor layer, the first electrode layer and the second The electrode layers are respectively disconnected into at least two of the first active patterns, at least two of the first electrodes, and at least two of the second electrodes.
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