CN117253799A - Manufacturing method of transistor device - Google Patents

Manufacturing method of transistor device Download PDF

Info

Publication number
CN117253799A
CN117253799A CN202210657082.1A CN202210657082A CN117253799A CN 117253799 A CN117253799 A CN 117253799A CN 202210657082 A CN202210657082 A CN 202210657082A CN 117253799 A CN117253799 A CN 117253799A
Authority
CN
China
Prior art keywords
layer
forming
electrode layer
electrode
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210657082.1A
Other languages
Chinese (zh)
Inventor
李泠
刘明
耿玓
段新绿
陆丛研
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN202210657082.1A priority Critical patent/CN117253799A/en
Priority to PCT/CN2022/114594 priority patent/WO2023236358A1/en
Publication of CN117253799A publication Critical patent/CN117253799A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a manufacturing method of a transistor device, which comprises the following steps: providing a substrate; sequentially forming a first electrode layer, a first insulating layer and a second electrode layer on one side of a substrate; forming a via penetrating the first electrode layer and the first insulating layer, the bottom of the via extending to the second electrode layer; and forming a semiconductor layer, a gate insulating layer and a gate electrode on the side surface of the via hole in sequence. The invention is beneficial to manufacturing the transistor device with good gate control capability, and the manufactured device can better realize miniaturization and is beneficial to large-scale array.

Description

Manufacturing method of transistor device
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a transistor device.
Background
At present, integrated circuits are continuously developed to finer dimensions, and advanced processes are one of the most top nodes in integrated circuit manufacturing. The transistor structure with a planar structure gradually shows higher leakage current and other defects while the transistor volume is continuously reduced. Therefore, in order to meet the better gate control performance and avoid the leakage current, the current main development direction is to manufacture the fin field effect transistor (Fin Field effect transistor, finFET) with three-dimensional structure. However, the current process has difficulty in continuously shrinking the channel area on the structure, and the whole device structure is difficult to further shrink.
Therefore, how to manufacture a transistor device with good gate control capability becomes a current urgent problem to be solved.
Disclosure of Invention
In view of the above problems, the present invention provides a method for manufacturing a transistor device, which is advantageous for manufacturing a transistor device with good gate control capability, and the manufactured device can be better miniaturized, and is advantageous for large-scale array.
The application provides the following technical scheme through an embodiment:
a method of manufacturing a transistor device, comprising:
providing a substrate; sequentially forming a first electrode layer, a first insulating layer and a second electrode layer on one side of the substrate; forming a via penetrating the first electrode layer and the first insulating layer, the bottom of the via extending to the second electrode layer; and forming a semiconductor layer, a gate insulating layer and a gate electrode on the side surface of the via hole in sequence.
Optionally, the forming a via penetrating the first electrode layer and the first insulating layer includes:
and forming a via hole penetrating the first electrode layer, the first insulating layer and the second electrode layer.
Optionally, the forming a via penetrating the first electrode layer and the first insulating layer includes:
and forming a via hole penetrating the first electrode layer and the first insulating layer, and enabling the length of the via hole extending to the second electrode layer to be not less than 10nm.
Optionally, the peripheral diameter of the semiconductor layer formed to extend into the second electrode layer and the length of the gate electrode extending into the second electrode layer satisfy the relationship: h is more than or equal to 0.5× (120 nm-D), wherein H is the length of the gate electrode extending into the second electrode layer, and D is the peripheral diameter of the end of the semiconductor layer extending into the second electrode layer.
Optionally, the material of the semiconductor layer includes indium oxide, gallium oxide and zinc oxide; forming the semiconductor layer on the side surface of the via hole, including:
forming an indium oxide film layer, a gallium oxide film layer and a zinc oxide film layer on the side surface of the via hole in a circulating way; the deposition sequence of each cycle is sequentially an indium oxide film layer, a gallium oxide film layer and a zinc oxide film layer.
Optionally, after the indium oxide thin film layer, the gallium oxide thin film layer and the zinc oxide thin film layer are formed on the side surface of the via hole in a circulating manner, the method further includes:
forming an indium oxide thin film layer on the surface of the zinc oxide thin film layer; wherein the gate insulating layer forms the surface of the indium oxide thin film layer.
Optionally, the material of the semiconductor layer includes indium oxide, gallium oxide and zinc oxide; forming the semiconductor layer on the side surface of the via hole, including:
forming indium oxide with a ratio ofIs provided.
Optionally, the material of the semiconductor layer includes indium oxide, gallium oxide and zinc oxide; forming the semiconductor layer on the side surface of the via hole, including:
the semiconductor layer having the same ratio of gallium oxide to zinc oxide is formed.
Optionally, before the first electrode layer, the first insulating layer and the second electrode layer are sequentially formed on one side of the substrate, the method further includes:
forming a second insulating layer on one side of the substrate; wherein the first electrode layer is formed on a surface of the second insulating layer away from the substrate.
Optionally, forming the semiconductor layer includes:
forming a semiconductor layer having a thickness of 3nm to 5 nm.
According to the manufacturing method of the transistor device, the grid electrode and the Channel are manufactured to be of a vertical structure in the manufacturing process, and the semiconductor layer is manufactured to surround the grid electrode, so that a CAA (Channel-All-Around) structure is formed. The area of the semiconductor layer can be effectively increased, the carrier quantity of the semiconductor layer is improved, and the current conduction efficiency is improved; meanwhile, the semiconductor layer is fully surrounded on the outer side of the grid electrode, so that the area of the semiconductor layer corresponding to the grid electrode is effectively increased, and the control capability of the grid electrode to the semiconductor layer is improved.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 to 16 are schematic views of a transistor device structure formed at different manufacturing stages using a method for manufacturing a transistor device according to an embodiment of the present invention;
fig. 17 and 18 are schematic diagrams illustrating the direction of the electric field formed at the gate end in the embodiment of the invention;
FIG. 19 is a schematic view showing the length of the gate electrode extending into the second electrode layer and the diameter of the semiconductor layer periphery in an embodiment of the present invention;
fig. 20 is a schematic structural diagram of a semiconductor layer according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
The current manufacturing process of the transistor device comprises a manufacturing process aiming at a transistor with a planar structure and a manufacturing process aiming at a transistor with a three-dimensional structure; for example, a manufacturing process for fin field effect transistors. But it is currently difficult for these fabrication processes to further reduce the area of the device and improve the gate control performance. In view of this, the embodiment of the invention provides a manufacturing method of a transistor device, which is characterized in that a gate and a Channel are manufactured to be vertical structures in a manufacturing process, and a semiconductor layer is manufactured to surround the gate, so as to form a CAA (Channel-All-Around) structure. The area of the semiconductor layer can be effectively increased, the carrier quantity of the semiconductor layer is improved, and the current conduction efficiency is improved; meanwhile, the semiconductor layer is fully surrounded on the outer side of the grid electrode, so that the area of the semiconductor layer corresponding to the grid electrode is effectively increased, and the control capability of the grid electrode to the semiconductor layer is improved. The manufacturing process increases the control area of the gate electrode to the semiconductor layer and the area of the semiconductor layer under a limited volume, and can be used for manufacturing transistor devices with smaller sizes. The general inventive concept will now be described with reference to a specific example.
Referring to fig. 1, a substrate 31 is provided first; the substrate 31 may be made of a conventional substrate material such as Si, siO 2 SiC, etc., and even other flexible substrate materials, without limitation. Then, a deposition process may be used to sequentially form the first electrode layer 32, the first insulating layer 33, and the second electrode layer 34 on one side of the substrate 31. It is to be understood that the second insulating layer 35 may also be formed on the substrate 31 side before the first electrode layer 32 is formed, and the first electrode layer 32 is formed on the second insulating layer 35.
For example:
an oxide layer of 350nm thickness may be pre-deposited on the silicon substrate as the second insulating layer 35, followed by pre-cleaning, and then a metal tungsten material layer (first tungsten material layer 32 a) of 56nm thickness is deposited on the oxide layer for fabricating the first electrode layer 32; then, the first protective layer 41 and the second protective layer 42 are sequentially deposited, and the two protective layers may be sequentially SiN and SiO, and the total thickness may be controlled to be 200nm, as shown in fig. 2.
Further, the protective layer is covered with a photoresist 43, and then is subjected to photolithography, development and cleaning, as shown in fig. 3, so that the first tungsten material layer 32a is manufactured into a first electrode layer 32, as shown in fig. 4; next, the first electrode layer 32 is covered with the first planarization layer 51 to fill up the patterned first electrode layer 32, as shown in fig. 5, the thickness of the deposited first planarization layer 51 may be controlled to be about 100nm, and then, chemical mechanical polishing is performed to the surface of the first electrode layer 32, and cleaning is performed, as shown in fig. 6.
Further, an oxide layer of 50nm thickness is deposited as the first insulating layer 33, as shown in fig. 7, to isolate the first electrode layer 32 and the second electrode layer 34.
Further, a pre-cleaning is performed and a metal tungsten material (second tungsten material layer 34 a) of 56nm thickness is deposited on the first insulating layer 33 for fabricating the second electrode layer 34; then, sequentially depositing a first protective layer 61 and a second protective layer 62 on the tungsten material layer for manufacturing the second electrode layer 34, wherein the two protective layers can be sequentially SiN and SiO, and the total thickness can be controlled at 230nm; then, a photoresist 63 is covered on the protective layer, and then photo-etching development and cleaning are performed, as shown in fig. 9, so that a second tungsten material layer 34a is formed as a second electrode layer 34, as shown in fig. 1; then, the second electrode layer 34 is covered with the second planarization layer 65 to fill up the patterned second electrode layer 34, the thickness of the deposited planarization layer can be controlled to be about 100nm, and then, the second planarization layer 65 is subjected to chemical mechanical polishing and cleaning, as shown in fig. 10.
Further, the second flat layer 65 may be etched through a patterned mask to form a first wiring hole 321 reaching the first electrode layer 32 and a second wiring hole 341 reaching the second electrode layer 34, as shown in fig. 11; next, a metal material is deposited in the first wiring hole 321 and the second wiring hole 341 to draw out the first electrode layer 32 and the second electrode layer 34 from the wiring, as shown in fig. 12; and (5) carrying out chemical mechanical polishing after the metal material deposition is finished.
Next, a via hole 71 penetrating the first electrode layer 32 and the first insulating layer 33 is formed, and the bottom of the via hole 71 extends to the second electrode layer 34, as shown in fig. 13. Referring to fig. 13 to 16, a semiconductor layer 72, a gate insulating layer 73 and a gate 74 are sequentially formed on the side of the via hole 71. The semiconductor layer 72 serves as a semiconductor channel.
For example:
the first protective layer 81 and the second protective layer 82 are sequentially deposited on the second planarization layer 65, and similarly, the two protective layers may be sequentially SiN and SiO, and the total thickness may be controlled to 760nm, which may be 200nm. Then, the photoresist 83 is covered, and the etching position is aligned to the metal superposition position of the first electrode layer 32 and the second electrode layer 34, as shown in fig. 14; etching is performed to form a via hole 71 such that the via hole 71 connects the first electrode layer 32 and the second electrode layer 34, as shown in fig. 13. Referring to FIGS. 15-16, an IGZO semiconductor layer with a thickness of 5nm is deposited in the via hole 71, and AlO with a thickness of 5nm is deposited on the surface of the semiconductor layer 72 x Gate insulating layer 73, mostThen, a gate material such as ITO, IZO or TiN is deposited in the remaining space of the via hole 71 until the via hole 71 is completely filled, as shown in FIG. 15, or the thickness is controlled to be 10nm. When the gate material completely fills the via hole 71 at the end, the diameter of the opening can be controlled in advance, so that the diameter of the final gate 74 meets the requirement; in this example, the diameter of the controllable via 71 may be 50nm or less, may be 40nm, and the final thickness of the gate 74 may be 20nm. Finally, the excess gate material is removed, as shown in fig. 16.
Note that, the gate 74 is made of ITO, IZO, tiN, etc., which can have a better conductivity, and can be made of metal or other oxide with strong conductivity that is advantageous for the ALD (Atomic layer deposition ) process. The first insulating layer 33 may employ HfO, hfAlO, al 2 O 3 The first insulating layer 33 may be formed by combining a plurality of thin films of different materials. The semiconductor layer 72 may be formed using IGZO (indium gallium zinc oxide), or low-leakage and high-mobility derivatives such as IZTO (indium zinc tin oxide) and IGZTO (indium gallium zinc tin oxide). The first electrode layer 32 and the second electrode layer 34 may be formed of TiN, W, mo, etc., which have work functions well suited to IGZO materials and have good oxidation resistance.
In forming the via hole 71, the via hole 71 penetrating the first electrode layer 32, the first insulating layer 33, and the second electrode layer 34 may be controlled to be formed. Of course, the via hole 71 extending into the first electrode layer 32 may be formed, but the via hole 71 does not penetrate through the first electrode layer 32, so that the first electrode layer 32 may be wrapped around the subsequently formed semiconductor layer 72 to achieve good electrical contact.
In some implementations, referring to fig. 17-18, the via 71 is formed to extend to a length of not less than 10nm into the first electrode layer 32. This ensures that after the gate 74 is formed in the via 71, the gate 74 may also extend into the first electrode layer 32; the gate 74 may generate a first electric field 91 parallel or substantially parallel to the length direction of the gate 74 in the semiconductor layer 72 and the first electrode layer 32 near the bottom of the via 71; a second electric field 92 may also be generated in semiconductor layer 72 and first electrode layer 32 near the bottom of via 71 that is perpendicular or substantially perpendicular to the length of gate 74. The ability of the gate 74 to control the location of contact with the first electrode layer 32 on the semiconductor layer 72 can be further enhanced, thereby enhancing the performance of the gate 74 of the fabricated device and avoiding the generation of leakage current.
Referring to fig. 19, after depositing the gate 74 in the via hole 71 during forming the via hole 71, the peripheral diameter of the semiconductor layer 72 extending into the first electrode layer 32 and the length of the gate 74 extending into the first electrode layer 32 satisfy the relationship: h.gtoreq.0.5× (120 nm-D), where H is the length of the gate 74 extending into the first electrode layer 32 and D is the peripheral diameter of the semiconductor layer 72 extending into the first electrode layer 32. Further, D is controlled to be less than or equal to 100nm. Thus, the balance between the first electric field 91 and the second electric field 92 is realized, the control performance of the grid electrode 74 on the position of the semiconductor layer 72 close to the bottom of the via hole 71 is ensured, and further miniaturization and miniaturization of the device are facilitated. Moreover, the first electrode layer 32 can be prevented from being etched through the via hole 71 during manufacturing, and at the moment, the end face and the side face of the deposited semiconductor layer 72 can form good contact with the first electrode layer 32, so that the contact resistance is effectively reduced; in addition, when the diameter of the via hole 71 is designed to be larger, the contact area between the first electrode layer 32 and the semiconductor layer 72 can be further increased, and the contact resistance can be reduced.
In fabricating the semiconductor layer 72, the deposition may be cycled on the side of the via hole 71, and each of the cycled structures 720 may be sequentially deposited to form an indium oxide thin film layer 721, a gallium oxide thin film layer 722, and a zinc oxide thin film layer 723, each cycle being as shown in fig. 20. The deposition order of each cycle is sequentially an indium oxide thin film layer 721, a gallium oxide thin film layer 722, and a zinc oxide thin film layer 723. The high-indium-ratio semiconductor layer 72 can achieve larger on-state current under the same gate voltage, but the threshold voltage of the device is more negative, that is, the threshold voltage of the device is less than 0V and is far away from 0V; the threshold voltage related pair of devices of semiconductor layer 72 with a low indium fraction is more positive, that is, the threshold voltage of the device is greater than 0V, or less than 0V but closer to 0V, but the device on-current will be less. It should be noted that, according to the different requirements on the expected performance of the device, the reference close to the positive or close to the negative is judged to be possibly changed; for example, a voltage of-1V may be used as a reference, a voltage greater than-1V may be positive, and a voltage less than-1V may be negative. Therefore, the proportion of each element of indium, gallium, and zinc can be accurately controlled in the manufacturing process by the layered structure design in the present embodiment, thereby achieving adjustment and balance of the turn-off control capability of the semiconductor layer 72 and the mobility of the semiconductor layer 72.
In fabricating semiconductor layer 72, the order of each cyclic stack may also be: a zinc oxide thin film layer 723, an indium oxide thin film layer 721, and a gallium oxide thin film layer 722; alternatively, a gallium oxide thin film layer 722, an indium oxide thin film layer 721, and a zinc oxide thin film layer 723; alternatively, a gallium oxide thin film layer 722, a zinc oxide thin film layer 723, and an indium oxide thin film layer 721. Such a stacked structure can ensure that the indium oxide thin film layer 721 and the gallium oxide thin film layer 722 are adjacent, thereby effectively suppressing the formation of oxygen vacancies and improving the controllability of the fabricated device.
Further, after the cyclic stack is completed, an indium oxide film layer 721 may be formed on the surface of the zinc oxide film layer 723 to complete all the fabrication of the semiconductor layer 72, and the gate insulating layer 73 may be formed on the surface of the indium oxide film layer 721. Thus, better interface characteristics are obtained, and subthreshold characteristics and working current of the device are improved.
In manufacturing the circularly stacked film layers, the thickness of each indium oxide film layer 721, each gallium oxide film layer 722, and each zinc oxide film layer 723 is controlled to be less than 1 angstrom. Thus, even if the compounds of different layers are deposited alternately, the finally formed multi-element semiconductor film cannot see the layered structure, and can be equivalently considered as a complete mixture of the elements, so that other characteristics of the IGZO material are ensured.
Further, the ratio of deposited film materials can be controlled in fabricating circularly stacked film layers. For example, the ratio of indium oxide material in each cycle or in the entire semiconductor layer 72 may be controlled toThe indium oxide material in the proportion can reach larger on-state current under the condition of the same grid voltage of the device; further, oxygen in each cycle or in the entire semiconductor layer 72 may also be controlledThe gallium oxide material and the zinc oxide material have the same duty ratio, so that the grid electrode 74 has better turn-off performance on the semiconductor layer 72 while ensuring that a larger on-state current is achieved, and the balance between high current and easy turn-off of the semiconductor layer 72 is realized. That is, the material ratio in each cycle or in the entire semiconductor layer 72 can be controlled to be: inO (Ino) x ：GaO x ：ZnO x The ratio range of (2) is 3:1:1-6:1:1; for example 5:1:1.
In some implementations, the thickness of the semiconductor layer formed may be controlled to be 3nm to 5nm, thereby ensuring good mobility of the semiconductor layer 72, while also facilitating further miniaturization of the device, as well as high density, large scale array fabrication.
In summary, in the method for manufacturing a transistor device according to the embodiments of the present invention, the gate and the Channel are manufactured to have a vertical structure in the manufacturing process, and the semiconductor layer is manufactured to surround the gate, so as to form a CAA (Channel-All-Around) structure. The area of the semiconductor layer can be effectively increased, the carrier quantity of the semiconductor layer is improved, and the current conduction efficiency is improved; meanwhile, the semiconductor layer is fully surrounded on the outer side of the grid electrode, so that the area of the semiconductor layer corresponding to the grid electrode is effectively increased, and the control capability of the grid electrode to the semiconductor layer is improved.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A method of manufacturing a transistor device, comprising:
providing a substrate;
sequentially forming a first electrode layer, a first insulating layer and a second electrode layer on one side of the substrate;
forming a via penetrating the first electrode layer and the first insulating layer, the bottom of the via extending to the second electrode layer;
and forming a semiconductor layer, a gate insulating layer and a gate electrode on the side surface of the via hole in sequence.
2. The method of manufacturing of claim 1, wherein forming a via penetrating the first electrode layer and first insulating layer comprises:
and forming a via hole penetrating the first electrode layer, the first insulating layer and the second electrode layer.
3. The method of manufacturing of claim 1, wherein forming a via penetrating the first electrode layer and first insulating layer comprises:
and forming a via hole penetrating the first electrode layer and the first insulating layer, and enabling the length of the via hole extending to the second electrode layer to be not less than 10nm.
4. The method of manufacturing according to claim 1, wherein a peripheral diameter of the semiconductor layer formed to protrude into the second electrode layer and a length of the gate electrode to protrude into the second electrode layer satisfy a relationship: h is more than or equal to 0.5× (120 nm-D), wherein H is the length of the gate electrode extending into the second electrode layer, and D is the peripheral diameter of the end of the semiconductor layer extending into the second electrode layer.
5. The method of manufacturing according to claim 1, wherein the material of the semiconductor layer includes indium oxide, gallium oxide, and zinc oxide; forming the semiconductor layer on the side surface of the via hole, including:
forming an indium oxide film layer, a gallium oxide film layer and a zinc oxide film layer on the side surface of the via hole in a circulating way; the deposition sequence of each cycle is sequentially an indium oxide film layer, a gallium oxide film layer and a zinc oxide film layer.
6. The method of manufacturing of claim 5, wherein after cyclically forming the indium oxide thin film layer, the gallium oxide thin film layer, and the zinc oxide thin film layer on the side surfaces of the via hole, further comprising:
forming an indium oxide thin film layer on the surface of the zinc oxide thin film layer; wherein the gate insulating layer forms the surface of the indium oxide thin film layer.
7. The method of manufacturing according to claim 1, wherein the material of the semiconductor layer includes indium oxide, gallium oxide, and zinc oxide; forming the semiconductor layer on the side surface of the via hole, including:
forming indium oxide with a ratio ofIs provided.
8. The method of manufacturing according to claim 1, wherein the material of the semiconductor layer includes indium oxide, gallium oxide, and zinc oxide; forming the semiconductor layer on the side surface of the via hole, including:
the semiconductor layer having the same ratio of gallium oxide to zinc oxide is formed.
9. The method of manufacturing of claim 1, wherein before sequentially forming the first electrode layer, the first insulating layer, and the second electrode layer on one side of the substrate, further comprising:
forming a second insulating layer on one side of the substrate; wherein the first electrode layer is formed on a surface of the second insulating layer away from the substrate.
10. The method of manufacturing according to claim 1, wherein forming the semiconductor layer comprises:
forming a semiconductor layer having a thickness of 3nm to 5 nm.
CN202210657082.1A 2022-06-10 2022-06-10 Manufacturing method of transistor device Pending CN117253799A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202210657082.1A CN117253799A (en) 2022-06-10 2022-06-10 Manufacturing method of transistor device
PCT/CN2022/114594 WO2023236358A1 (en) 2022-06-10 2022-08-24 Manufacturing method for transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210657082.1A CN117253799A (en) 2022-06-10 2022-06-10 Manufacturing method of transistor device

Publications (1)

Publication Number Publication Date
CN117253799A true CN117253799A (en) 2023-12-19

Family

ID=89117455

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210657082.1A Pending CN117253799A (en) 2022-06-10 2022-06-10 Manufacturing method of transistor device

Country Status (2)

Country Link
CN (1) CN117253799A (en)
WO (1) WO2023236358A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100574317B1 (en) * 2004-02-19 2006-04-26 삼성전자주식회사 Gate structure, semiconductor device having the same and methods of forming the gate structure and semiconductor device
CN103730508B (en) * 2012-10-16 2016-08-03 瀚宇彩晶股份有限公司 Rectilinear thin-film transistor structure of display floater and preparation method thereof
CN106910778B (en) * 2017-03-29 2020-02-18 京东方科技集团股份有限公司 Thin film transistor, preparation method thereof and array substrate
CN114122015B (en) * 2021-11-15 2023-08-22 武汉华星光电半导体显示技术有限公司 Array substrate, manufacturing method thereof and display panel
CN114156285B (en) * 2021-11-30 2023-08-22 武汉华星光电半导体显示技术有限公司 Array substrate, preparation method thereof and display panel

Also Published As

Publication number Publication date
WO2023236358A1 (en) 2023-12-14

Similar Documents

Publication Publication Date Title
KR102301251B1 (en) A gate all around semiconductor device and a mehtod for fabricating the same
US10242990B2 (en) Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors
US9356027B1 (en) Dual work function integration for stacked FinFET
JP4930056B2 (en) Field effect transistor and manufacturing method thereof
TW201829293A (en) Semiconductor device
Kaneko et al. Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension
US20120205751A1 (en) Semiconductor device
TW202133451A (en) Semiconductor device
US11557652B2 (en) Metal source/drain-based MOSFET and method for fabricating the same
CN111243958A (en) Method for forming dielectric layer, semiconductor structure and forming method thereof
TW201721838A (en) 3D fin tunneling field effect transistor
US20210305376A1 (en) Semiconductor device structure
CN111755512A (en) Semiconductor device and preparation method thereof
CN111106177A (en) Semiconductor device, method of manufacturing the same, and electronic apparatus including the same
CN109801960B (en) Semiconductor device, method of manufacturing the same, and electronic apparatus including the same
CN109326650B (en) Semiconductor device, method of manufacturing the same, and electronic apparatus including the same
CN112652664B (en) Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
CN111435643A (en) Preparation method of three-dimensional stacked gate-all-around transistor
US11757045B2 (en) Semiconductor device and method of manufacturing the same
CN117253799A (en) Manufacturing method of transistor device
TWI781489B (en) Transistors and method of forming the same
CN117276326A (en) Transistor device and memory
CN106531795B (en) Semiconductor device and manufacturing method of grid stack of semiconductor device
CN117276321A (en) Transistor device and memory
CN113193047B (en) Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination