CN106910778B - Thin film transistor, preparation method thereof and array substrate - Google Patents
Thin film transistor, preparation method thereof and array substrate Download PDFInfo
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- CN106910778B CN106910778B CN201710198484.9A CN201710198484A CN106910778B CN 106910778 B CN106910778 B CN 106910778B CN 201710198484 A CN201710198484 A CN 201710198484A CN 106910778 B CN106910778 B CN 106910778B
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- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 43
- 239000010408 film Substances 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 27
- 238000001312 dry etching Methods 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 238000004380 ashing Methods 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000583 Nd alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- UBSJOWMHLJZVDJ-UHFFFAOYSA-N aluminum neodymium Chemical compound [Al].[Nd] UBSJOWMHLJZVDJ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
The embodiment of the invention provides a thin film transistor, a preparation method thereof and an array substrate, relates to the technical field of display, and can increase the channel length of the thin film transistor without changing the size and the thickness of the thin film transistor with a vertical structure. The thin film transistor comprises a substrate, a first conducting layer, an insulating layer, a second conducting layer, an active layer, a gate insulating layer and a gate, wherein the first conducting layer, the insulating layer and the second conducting layer are sequentially arranged on the substrate; the active layer, the gate insulating layer and the gate electrode are arranged on one sides of the first conducting layer, the insulating layer and the second conducting layer; the size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer; the channel length of the thin film transistor is longer than the distance from the edge of the intersecting surface of the upper surface of the insulating layer and the first side surface to the edge of the intersecting surface of the lower surface of the insulating layer and the first side surface on the first side surface of the insulating layer, which is in contact with the active layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a preparation method thereof and an array substrate.
Background
With the development of display technology, the development of ultra-high resolution (PPI) technology is becoming one of the mainstream development directions, however, the aperture ratio of ultra-high resolution products is often low.
As shown in fig. 1(a) and 1(b), since the TFT (Thin Film Transistor for short) of the conventional BCE (back channel etch) structure and the Self-Aligned structure has a large size, the aperture ratio of the array substrate is reduced, and thus it is not suitable for the development of the ultra-high resolution product. As shown in fig. 1(c), in order to secure the aperture ratio of the ultra-high resolution product, there is a literature that a Vertical TFT having a greatly reduced size and good TFT characteristics is reported, compared to the BCE structure and the Self-Aligned structure, and thus the Vertical TFT has a great application prospect in the ultra-high resolution product.
As shown in fig. 1(c), the source electrode 02 and the drain electrode 01 of the TFT of Vertical structure are separated by an insulating layer 30, and the channel length is approximately equal to the thickness of the insulating layer (about 0.5 μm), which is very easy to induce short channel effect and is not good for stabilizing the TFT characteristics.
Disclosure of Invention
Embodiments of the present invention provide a thin film transistor, a method for manufacturing the same, and an array substrate, which can increase a channel length of a Vertical TFT without changing the size and thickness of the Vertical TFT, thereby improving the unstable TFT characteristics caused by a short channel effect.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, a thin film transistor is provided, which includes a substrate, a first conductive layer, an insulating layer, a second conductive layer, an active layer, a gate insulating layer, and a gate electrode, which are sequentially disposed on the substrate; the active layer is arranged on one side of the first conducting layer, the insulating layer and the second conducting layer, the gate insulating layer is arranged on one side of the active layer far away from the first conducting layer, the insulating layer and the second conducting layer, and the gate electrode is arranged on one side of the gate insulating layer far away from the active layer.
The size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer; the channel length of the thin film transistor is longer than the distance from the edge of the upper surface of the insulating layer, which is intersected with the first side surface, to the edge of the lower surface of the insulating layer, which is intersected with the first side surface, on the first side surface of the insulating layer, which is contacted with the active layer.
Optionally, the first side surface is stepped.
Optionally, the size of the upper surface of the insulating layer is larger than the size of the lower surface of the second conductive layer in contact with the insulating layer; the first side surface is planar.
Preferably, the material of the insulating layer is SiOx.
In a second aspect, an array substrate is provided, which includes the thin film transistor of the first aspect.
In a third aspect, a method for manufacturing a thin film transistor is provided, including forming a first conductive layer, an insulating layer, a second conductive layer, an active layer, a gate insulating layer, and a gate electrode on a substrate in sequence; the active layer is located on one side of the first conducting layer, the insulating layer and the second conducting layer, the gate insulating layer is located on one side of the active layer far away from the first conducting layer, the insulating layer and the second conducting layer, and the gate electrode is located on one side of the gate insulating layer far away from the active layer.
The size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer; the channel length of the thin film transistor is longer than the distance from the edge of the upper surface of the insulating layer, which is intersected with the first side surface, to the edge of the lower surface of the insulating layer, which is intersected with the first side surface, on the first side surface of the insulating layer, which is contacted with the active layer.
Optionally, the size of the upper surface of the insulating layer is larger than the size of the lower surface of the second conductive layer in contact with the insulating layer; the first side surface is planar. Forming the second conductive layer, the insulating layer, including:
and sequentially forming an insulating layer film and a second conductive layer film on the first conductive layer, and forming a first photoresist pattern through a mask exposure process.
And carrying out over-etching on the second conducting layer film by adopting wet etching to form the second conducting layer with the size smaller than that of the first photoresist pattern.
And etching the insulating layer film by adopting dry etching to form the insulating layer with the planar first side surface.
Optionally, the first side surface is stepped. Forming the second conductive layer, the insulating layer, including:
sequentially forming an insulating layer film and a second conductive layer film on the first conductive layer, and forming a first photoresist pattern through a mask exposure process; performing over-etching on the second conducting layer film by adopting wet etching to form the second conducting layer with the size smaller than that of the first photoresist pattern; and etching the insulating layer film for the first time by adopting dry etching to form the insulating layer with the planar first side surface.
And reducing the size of the first photoresist pattern by adopting an ashing process to form a second photoresist pattern, wherein the size of the second photoresist pattern is larger than or equal to that of the second conductive layer.
And performing secondary etching on the insulating layer with the planar first side surface by adopting dry etching to form the insulating layer with the primary step-shaped first side surface.
Further preferably, in a case that the size of the second conductive layer is smaller than the size of the second photoresist pattern, after the insulating layer with the first side surface being one-step-shaped is formed, the method further includes: and ashing the second photoresist pattern and etching the insulating layer with the first side in the shape of the one-step for the third time at least once to ensure that the first side is in the shape of the multi-step. Ashing the second photoresist pattern and etching the insulating layer with the first side in the first step shape for the third time, wherein the ashing step comprises:
and reducing the size of the second photoresist pattern by adopting an ashing process to form a third photoresist pattern, wherein the size of the third photoresist pattern is larger than or equal to that of the second conductive layer.
And performing third etching on the insulating layer with the first side surface in the first step shape by adopting dry etching so as to increase the number of steps of the first side surface by one step.
Preferably, the active layer, the gate insulating layer and the gate electrode are formed by a single patterning process.
The embodiment of the invention provides a thin film transistor, a preparation method thereof and an array substrate.A TFT with a Vertical structure is formed by sequentially arranging a first conductive layer, an insulating layer, a second conductive layer, an active layer, a gate insulating layer and a grid electrode on a substrate, and the channel length of the TFT with the Vertical structure is larger than that of a first side surface of the insulating layer, which is in contact with the active layer, and the distance from the intersected edge of the upper surface of the insulating layer and the first side surface to the intersected edge of the lower surface of the insulating layer and the first side surface, so that the channel length of the TFT is increased on the basis of not changing the size and the thickness of the TFT with the Vertical structure, and the phenomenon of unstable TFT characteristics caused by a short channel effect is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1(a) is a schematic structural diagram of a TFT with a BCE structure provided in the prior art;
FIG. 1(b) is a schematic structural diagram of a TFT with a Self-Aligned structure provided in the prior art;
FIG. 1(c) is a schematic structural diagram of a Vertical TFT provided in the prior art;
FIG. 2 is a schematic structural diagram of a TFT according to an embodiment of the present invention;
FIG. 3(a) is a schematic side view of a TFT according to an embodiment of the present invention;
FIG. 3(b) is a schematic side view of a TFT according to an embodiment of the present invention;
FIG. 3(c) is a schematic side view of a TFT according to an embodiment of the present invention;
FIG. 3(d) is a schematic side view of a TFT according to an embodiment of the present invention;
FIG. 4 is a schematic side view of a TFT according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a side view of a TFT according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a side view of a TFT according to an embodiment of the present invention;
FIG. 7 is a schematic diagram eight illustrating a side view of a TFT according to an embodiment of the present invention;
FIG. 8 is a schematic diagram nine illustrating a side view of a TFT according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a TFT in a side view according to one embodiment of the present invention;
FIG. 10 is an eleventh schematic side view of a TFT according to an embodiment of the present invention;
FIG. 11 is a side view of a TFT according to an embodiment of the present invention;
FIG. 12 is a thirteen schematic side views of a TFT according to an embodiment of the present invention;
FIG. 13 is a schematic flow chart of a process for fabricating a TFT with a planar first side according to an embodiment of the present invention;
fig. 14(a) is a schematic view of a first process for manufacturing a TFT having a planar first side according to an embodiment of the present invention;
fig. 14(b) is a schematic diagram of a second process for manufacturing a TFT with a planar first side according to an embodiment of the present invention;
fig. 14(c) is a schematic diagram of a third process of manufacturing a TFT with a planar first side according to an embodiment of the present invention;
fig. 15 is a schematic flow chart of a process for preparing a TFT with a first side surface having a one-step shape according to an embodiment of the present invention;
fig. 16(a) is a schematic view of a first process for preparing a TFT with a first side surface having one step shape according to an embodiment of the present invention;
fig. 16(b) is a schematic diagram of a second process for preparing a TFT with a first side surface being one-step-shaped according to an embodiment of the present invention;
fig. 16(c) is a schematic diagram of a third process for preparing a TFT with a first side surface being one-step-shaped according to an embodiment of the present invention;
fig. 16(d) is a schematic diagram of a process of manufacturing a TFT with a first side surface having a one-step shape according to an embodiment of the present invention;
fig. 16(e) is a schematic diagram of a process of preparing a TFT with a first side surface being one-step-shaped according to an embodiment of the present invention;
fig. 17 is a schematic flow chart of a process for preparing a TFT with a two-step first side according to an embodiment of the present invention;
fig. 18(a) is a schematic view of a first process for preparing a TFT with a two-step-shaped first side according to an embodiment of the present invention;
fig. 18(b) is a schematic diagram of a second process for preparing a TFT with a two-step first side according to an embodiment of the present invention.
Reference numerals:
01-a drain electrode; 02-source electrode; 10-a substrate; 20-a first conductive layer; 30-an insulating layer; 31-an insulating layer film; 32-a first side; 33-third side; 40-a second conductive layer; 41-a second conductive layer film; 42-a second side; 50-an active layer; 60-a gate insulating layer; 70-a gate; 81-a first photoresist pattern; 82-a second photoresist pattern; 83-third photoresist pattern.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a TFT, as shown in fig. 2 to 12, including a substrate 10, a first conductive layer 20, an insulating layer 30, a second conductive layer 40, an active layer 50, a gate insulating layer 60, and a gate electrode 70, which are sequentially disposed on the substrate 10; the active layer 50 is disposed on one side of the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, the gate insulating layer 60 is disposed on one side of the active layer 50 away from the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, and the gate electrode 70 is disposed on one side of the gate insulating layer 60 away from the active layer 50.
The size of the upper surface of the first conductive layer 20 is larger than or equal to the size of the lower surface of the insulating layer 30, and the size of the upper surface of the insulating layer 30 is larger than or equal to the size of the lower surface of the second conductive layer 40; the channel length of the TFT is longer than the distance from the edge of the insulating layer 30 where the upper surface meets the first side 32 to the edge of the insulating layer 30 where the lower surface meets the first side 32 on the first side 32 where the insulating layer 30 contacts the active layer 50.
Here, as shown in fig. 2, a side of the insulating layer 30 contacting the active layer 50 is a first side 32, a side of the second conductive layer 40 contacting the active layer 50 is a second side 42, and a side adjacent to the first side 32 among the plurality of sides of the insulating layer 30 is a third side 33. The channel length of the TFT is: the sum of the distance a from the edge of the second side surface 42 intersecting the lower surface of the second conductive layer 40 to the edge of the first side surface 32 intersecting the upper surface of the insulating layer 30 and the length B of the edge intersecting the first side surface 32 and the third side surface 33 (fig. 2 shows a perspective view in which only the first side surface is planar).
For example, as shown in fig. 3(B), the distance from the edge where the second side surface 42 intersects with the lower surface of the second conductive layer 40 to the edge where the first side surface 32 intersects with the upper surface of the insulating layer 30 is a equal to L1, the length of the edge where the first side surface 32 intersects with the third side surface 33 is B equal to L2, and the channel length of the TFT is L1+ L2, the channel length of the TFT of the present invention is increased by L1 compared with the prior art; as shown in fig. 8, a distance a from a side where the second side surface 42 intersects with the lower surface of the second conductive layer 40 to a side where the first side surface 32 intersects with the upper surface of the insulating layer 30 is L3, a length B of a side where the first side surface 32 intersects with the third side surface 33 is L4+ L5+ L6, and a channel length of the TFT is L3+ L4+ L5+ L6, which is increased by L3+ L4 in comparison with the prior art; as shown in fig. 9, a distance a from a side where the second side surface 42 intersects with the lower surface of the second conductive layer 40 to a side where the first side surface 32 intersects with the upper surface of the insulating layer 30 is 0, a length B of a side where the first side surface 32 intersects with the third side surface 33 is L7+ L8+ L9+ L10+ L11, and a channel length of the TFT is L7+ L8+ L9+ L10+ L11, which increases a channel length of the TFT by L7+ L8 in comparison with the prior art.
First, in the TFT, if the first conductive layer 20 is a source electrode, the second conductive layer 40 is a drain electrode; alternatively, the first conductive layer 20 is a drain and the second conductive layer 40 is a source.
Here, the material of the first conductive layer 20 and the second conductive layer 40 may be a metal material such as Mo (molybdenum), Cu (copper), Al (aluminum), AlNd (aluminum neodymium alloy), or a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide).
Second, the type of TFT is not limited, and may be amorphous silicon, metal oxide, polysilicon, organic, or the like.
Third, the material of the insulating layer 30 is not limited, and may be, for example, SiOx(silicon oxide), SiNx(silicon nitride), SiON (silicon oxynitride), and organic resins.
Fourth, as shown in fig. 3(a), the active layer 50, the gate insulating layer 60, and the gate electrode 70 may be disposed only on one side of the first conductive layer 20, the insulating layer 30, and the second conductive layer 40 and extend over the substrate 10, or may be disposed on one side of the first conductive layer 20, the insulating layer 30, and the second conductive layer 40 and extend from a side surface of the second conductive layer 40 to an upper surface thereof in partial contact (as shown in fig. 3 (b)) or complete contact (as shown in fig. 3 (c)) with the upper surface of the second conductive layer 40, as shown in fig. 3(d), or may be disposed only on one side of the first conductive layer 20, the insulating layer 30, and the second conductive layer 40, without increasing the size of the TFT.
Fifthly, a surface of the first conductive layer 20 away from the substrate 10 is an upper surface, a surface opposite to the upper surface is a lower surface of the first conductive layer 20, and a plurality of surfaces adjacent to between the upper surface and the lower surface are a plurality of side surfaces of the first conductive layer 20; a surface of the insulating layer 30 away from the substrate 10 is an upper surface, a surface opposite to the upper surface is a lower surface of the insulating layer 30, and a plurality of surfaces adjacent between the upper surface and the lower surface are a plurality of side surfaces of the insulating layer 30, wherein a side surface of the plurality of side surfaces contacting the active layer 50 is a first side surface 32; a surface of the second conductive layer 40 away from the substrate 10 is an upper surface, a surface opposite to the upper surface is a lower surface of the second conductive layer 40, and a plurality of surfaces adjacent between the upper surface and the lower surface are a plurality of side surfaces of the second conductive layer 40, wherein a side surface of the plurality of side surfaces contacting the active layer 50 is a second side surface 42.
Sixth, the shape of the first side surface 32 is not limited, and may be planar, curved, stepped, or the like.
Seventh, since the entire TFT is processed in the process of forming the first side surface 32, the other sides of the insulating layer 30 except the first side surface 32 are formed in the same shape as the first side surface 32.
The embodiment of the invention provides a TFT, which is formed by sequentially arranging a first conducting layer 20, an insulating layer 30, a second conducting layer 40, an active layer 50, a gate insulating layer 60 and a gate electrode 70 on a substrate 10, wherein the channel length of the TFT with a Vertical structure is larger than that of a first side surface 32, which is in contact with the active layer 50, of the insulating layer 30, and the distance from the edge, which is intersected with the first side surface 32, of the upper surface of the insulating layer 30 to the edge, which is intersected with the first side surface 32, of the lower surface of the insulating layer 30, so that the channel length of the TFT is increased on the basis of not changing the size and the thickness of the TFT with the Vertical structure, and the phenomenon that the characteristics of the TFT are unstable due to a short channel effect is further improved.
Alternatively, as shown in FIGS. 5-12, the first side 32 is stepped.
It should be noted that the number of steps of the first side surface 32 is determined by the thickness of the insulating layer 30, and is limited by the process, when the thickness of the insulating layer 30 is fixed, the number of steps of the first side surface 32 increases to a certain extent, and the process cannot be realized.
In the embodiment of the present invention, the first side surface 32 is set to be step-shaped, on one hand, the channel length of the TFT can be increased; on the other hand, since the thickness of the insulating layer 30 is large (not less than)
) In addition, the slope of the insulating layer 30 formed by etching is larger than the angle, and the active layer 50, the gate insulating layer 60, and the gate electrode 70 are easily broken in the subsequent process of providing the active layer 50, the gate insulating layer 60, and the gate electrode 70, in order to avoid this situation, the first side surface 32 is provided in a step shape, and a plane parallel to the substrate 10 in the step-shaped first side surface 32 can play a role of buffering, so that the risk of breaking the active layer 50, the gate insulating layer 60, and the gate electrode 70 is greatly reduced.
Alternatively, as shown in fig. 2-4, the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact therewith; the first side 32 is planar.
In the embodiment of the present invention, in the case where the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact therewith, the first side surface 32 is set to be planar, and on the one hand, the channel length of the TFT can be increased; on the other hand, the preparation method has the advantage of simple preparation process.
Preferably, the material of the insulating layer 30 is SiOx.
In the embodiment of the invention, SiOx is adopted as an insulating layer material, compared with SiNxSiOx is not a conductor, and SiON and an organic resin are not a material which can prevent the first conductive layer 20 and the second conductive layer 40 from being electrically connected through the insulating layer 30.
An embodiment of the present invention further provides an array substrate, including the TFT according to any one of the foregoing embodiments of the present invention.
The embodiment of the invention provides an array substrate, which comprises a TFT with a Vertical structure, wherein a first conducting layer 20, an insulating layer 30, a second conducting layer 40, an active layer 50, a gate insulating layer 60 and a gate electrode 70 are sequentially arranged on a substrate 10 of the TFT, the channel length of the TFT is larger than the distance from the edge of the upper surface of the insulating layer 30, which is intersected with the first side surface 32, to the edge of the lower surface of the insulating layer 30, which is intersected with the first side surface 32, on the first side surface 32, which is contacted with the active layer 50, and the channel length of the TFT is increased on the basis of not changing the size and the thickness of the TFT with the Vertical structure, so that the phenomenon of unstable characteristics of the TFT caused by a short channel effect is improved.
An embodiment of the present invention provides a method for manufacturing a TFT, as shown in fig. 13 to 18, including forming a first conductive layer 20, an insulating layer 30, a second conductive layer 40, an active layer 50, a gate insulating layer 60, and a gate electrode 70 in sequence on a substrate 10; the active layer 50 is located on one side of the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, the gate insulating layer 60 is located on one side of the active layer 50 away from the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, and the gate electrode 70 is located on one side of the gate insulating layer 60 away from the active layer 50.
The size of the upper surface of the first conductive layer 20 is larger than or equal to the size of the lower surface of the insulating layer 30, and the size of the upper surface of the insulating layer 30 is larger than or equal to the size of the lower surface of the second conductive layer 40; the channel length of the TFT is longer than the distance from the edge of the insulating layer 30 where the upper surface meets the first side 32 to the edge of the insulating layer 30 where the lower surface meets the first side 32 on the first side 32 where the insulating layer 30 contacts the active layer 50.
Embodiments of the present invention provide a method for manufacturing a TFT, which has the same technical effects as the array substrate, and will not be described herein again.
Alternatively, as shown in fig. 13-14(c), the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact therewith; the first side 32 is planar.
Based on this, as shown in fig. 13, the second conductive layer 40 and the insulating layer 30 are formed, which can be specifically realized by the following steps:
s101, as shown in fig. 14(a), the insulating layer thin film 31 and the second conductive layer thin film 41 are sequentially formed on the first conductive layer 20, and the first photoresist pattern 81 is formed through a mask exposure process.
S102, as shown in fig. 14(b), the second conductive layer film 41 is over-etched by wet etching, and the second conductive layer 40 having a size smaller than that of the first photoresist pattern 81 is formed.
S103, as shown in fig. 14(c), the insulating layer film 31 is etched by dry etching, and the insulating layer 30 having the planar first side surface 32 is formed.
Here, the overetching of the second conductive layer film 41 by wet etching and the etching of the insulating layer film 31 by dry etching are both related to specific CD Bias (Critical Dimension Bias, abbreviated as etching amount), and the time required for different CD biases is different.
On this basis, the first photoresist pattern 81 may be removed through a lift-off process to facilitate the subsequent formation of the active layer 50, the gate insulating layer 60, and the gate electrode 70.
It should be noted that, as will be understood by those skilled in the art, after the insulating layer film 31 is etched by dry etching, the size of the upper surface of the insulating layer 30, in which the first side surface 32 is formed in a planar shape, is substantially equal to the size of the first photoresist pattern 81.
In the embodiment of the present invention, in the case that the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact therewith, the insulating layer 30 having the planar first side surface 32 is formed by performing dry etching on the insulating layer film 31, so that on one hand, the channel length of the TFT can be increased; on the other hand, the preparation method has the advantage of simple preparation process.
Of course, the insulating layer 30 having the planar first side surface 32 may be formed by other methods, which are not limited herein.
Alternatively, as shown in fig. 15-16(e), the first side 32 is stepped.
Based on this, as shown in fig. 15, the second conductive layer 40 and the insulating layer 30 are formed, which can be specifically realized by the following steps:
s201, as shown in fig. 16(a), an insulating layer film 31 and a second conductive layer film 41 are sequentially formed on the first conductive layer 20, and a first photoresist pattern 81 is formed through a mask exposure process.
S202, as shown in fig. 16(b), the second conductive layer film 41 is over-etched by wet etching, and the second conductive layer 40 having a size smaller than that of the first photoresist pattern 81 is formed.
S203, as shown in fig. 16(c), the insulating layer film 31 is first etched by dry etching, and the insulating layer 30 having the planar first side surface 32 is formed.
It should be noted that, as will be understood by those skilled in the art, after the insulating layer film 31 is etched by dry etching, the size of the upper surface of the insulating layer 30, in which the first side surface 32 is formed in a planar shape, is substantially equal to the size of the first photoresist pattern 81.
S204, as shown in fig. 16(d), the ashing process is used to reduce the size of the first photoresist pattern 81 to form a second photoresist pattern 82, and the size of the second photoresist pattern 82 is greater than or equal to the size of the second conductive layer 40.
S205, as shown in fig. 16(e), performing a second etching on the insulating layer 30 with the planar first side surface 32 by using dry etching, so as to form the insulating layer 30 with the first side surface 32 in a one-step shape (fig. 16(e) only shows one case where the first side surface 32 is in the one-step shape, and fig. 5-8 can be referred to for other cases).
Here, the wet etching is used to perform the over-etching on the second conductive layer thin film 41, the dry etching is used to perform the first etching on the insulating layer thin film 31, and the dry etching is used to perform the second etching on the insulating layer 30 having the first side surface 32 in a planar shape, which are all related to specific CD Bias, and the time required for different CD biases is different.
On this basis, the second photoresist pattern 82 may be removed through a lift-off process to facilitate the subsequent formation of the active layer 50, the gate insulating layer 60, and the gate electrode 70.
It should be noted that, as will be understood by those skilled in the art, after the insulating layer 30 with the planar first side surface 32 is etched by dry etching, the size of the upper surface of the insulating layer 30 with the stepped first side surface 32 is substantially equal to the size of the second photoresist pattern 82.
In the embodiment of the invention, the insulating layer 30 with the planar first side surface 32 is formed by performing the first dry etching on the insulating layer film 31, the size of the first photoresist pattern 81 is reduced by adopting an ashing process, and finally the insulating layer 30 with the planar first side surface 32 is subjected to the second dry etching to form the insulating layer 30 with the first side surface 32 in the shape of the primary step, so that on one hand, the channel length of the TFT can be increased; on the other hand, the plane parallel to the substrate 10 in the stepped first side 32 may serve as a buffer, greatly reducing the risk of breaking the active layer 50, the gate insulating layer 60, and the gate electrode 70.
Of course, the insulating layer 30 with the first side 32 being one-step stepped may be formed by other methods, which are not limited herein.
Further preferably, as shown in fig. 17 to 18(b), after forming the insulating layer 30 having the first side 32 in a one-step shape in a case where the size of the second conductive layer 40 is smaller than the size of the second photoresist pattern 82, the method further includes: the ashing of the second photoresist pattern 82 and the third etching of the insulating layer 30 having the first side 32 with the one-step shape are repeated at least once to form the first side 32 with the multi-step shape.
As shown in fig. 17, ashing the second photoresist pattern 82 and etching the insulating layer 30 having the first side surface 32 in the one-step shape for the third time may specifically be implemented by the following steps:
s301, as shown in fig. 18(a), the ashing process is used to reduce the size of the second photoresist pattern 82 and form a third photoresist pattern 83, wherein the size of the third photoresist pattern 83 is equal to or greater than the size of the second conductive layer 40.
S302, as shown in fig. 18(b), performing a third etching on the insulating layer 30 with the first side surface 32 being in the step shape by using dry etching, so as to increase the number of steps of the first side surface 32 by one step (fig. 18(b) only shows one case where the number of steps of the side surface of the insulating layer is increased by one step, and in other cases, refer to fig. 9-12).
Here, the third etching is performed on the insulating layer 30 having the first side surface 32 in the first step shape by dry etching, and the time required for different CD Bias is different depending on the specific CD Bias.
On this basis, the third photoresist pattern 83 may be removed by a lift-off process to facilitate the subsequent formation of the active layer 50, the gate insulating layer 60, and the gate electrode 70.
First, it should be noted that, after the insulating layer 30 with the first side surface 32 being one-step-shaped is etched by dry etching, the size of the upper surface of the insulating layer 30 with the first side surface 32 being two-step-shaped is formed to be substantially equal to the size of the third photoresist pattern 83.
Second, the number of steps of the first side surface 32 and the number of times of dry etching the insulating layer 30 in which the second photoresist pattern 82 is ashed and the first side surface 32 is stepped in one step are determined by the thickness of the insulating layer 30.
In the embodiment of the present invention, by increasing the number of steps of the first side surface 32, increasing the number of planes parallel to the substrate 10 in the step-shaped first side surface 32, and shortening the distance of each step, compared with the first side surface 32 of one step, the first side surface 32 of multiple steps can play a better role in buffering, so as to better avoid the phenomenon of breaking the active layer 50, the gate insulating layer 60, and the gate electrode 70.
Of course, the insulating layer 30 having the first side 32 in a multi-step shape may be formed by other methods, which are not limited herein.
Preferably, as shown in fig. 3(b) and 3(c), the active layer 50, the gate insulating layer 60, and the gate electrode 70 are formed through a single patterning process.
In the embodiment of the present invention, the active layer 50, the gate insulating layer 60, and the gate electrode 70 are formed by a single patterning process, which has an advantage of simplifying a manufacturing process.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A thin film transistor comprises a substrate, a first conducting layer, an insulating layer, a second conducting layer, an active layer, a gate insulating layer and a gate, wherein the first conducting layer, the insulating layer and the second conducting layer are sequentially arranged on the substrate from bottom to top; the active layer is arranged on one side of the first conducting layer, the insulating layer and the second conducting layer, the gate insulating layer is arranged on one side of the active layer far away from the first conducting layer, the insulating layer and the second conducting layer, the gate electrode is arranged on one side of the gate insulating layer far away from the active layer,
the size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer;
the channel length of the thin film transistor is longer than the distance from the edge of the upper surface of the insulating layer, which is intersected with the first side surface, to the edge of the lower surface of the insulating layer, which is intersected with the first side surface, on the first side surface of the insulating layer, which is contacted with the active layer.
2. The thin film transistor of claim 1, wherein the first side surface is stepped.
3. The thin film transistor according to claim 1, wherein a size of an upper surface of the insulating layer is larger than a size of a lower surface of the second conductive layer in contact therewith;
the first side surface is planar.
4. The thin film transistor according to any one of claims 1 to 3, wherein a material of the insulating layer is SiOx.
5. An array substrate comprising the thin film transistor according to any one of claims 1 to 4.
6. A preparation method of a thin film transistor comprises the steps of sequentially forming a first conducting layer, an insulating layer, a second conducting layer, an active layer, a gate insulating layer and a gate electrode on a substrate from bottom to top; the active layer is located on one side of the first conductive layer, the insulating layer and the second conductive layer, the gate insulating layer is located on one side of the active layer away from the first conductive layer, the insulating layer and the second conductive layer, and the gate electrode is located on one side of the gate insulating layer away from the active layer,
the size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer;
the channel length of the thin film transistor is longer than the distance from the edge of the upper surface of the insulating layer, which is intersected with the first side surface, to the edge of the lower surface of the insulating layer, which is intersected with the first side surface, on the first side surface of the insulating layer, which is contacted with the active layer.
7. The manufacturing method according to claim 6, wherein a size of an upper surface of the insulating layer is larger than a size of a lower surface of the second conductive layer in contact therewith; the first side surface is planar;
forming the second conductive layer, the insulating layer, including:
sequentially forming an insulating layer film and a second conductive layer film on the first conductive layer, and forming a first photoresist pattern through a mask exposure process;
performing over-etching on the second conducting layer film by adopting wet etching to form the second conducting layer with the size smaller than that of the first photoresist pattern;
and etching the insulating layer film by adopting dry etching to form the insulating layer with the planar first side surface.
8. The method of claim 6, wherein the first side is stepped;
forming the second conductive layer, the insulating layer, including:
sequentially forming an insulating layer film and a second conductive layer film on the first conductive layer, and forming a first photoresist pattern through a mask exposure process;
performing over-etching on the second conducting layer film by adopting wet etching to form the second conducting layer with the size smaller than that of the first photoresist pattern;
performing first etching on the insulating layer film by adopting dry etching to form the insulating layer with the planar first side surface;
reducing the size of the first photoresist pattern by adopting an ashing process to form a second photoresist pattern, wherein the size of the second photoresist pattern is larger than or equal to that of the second conductive layer;
and performing secondary etching on the insulating layer with the planar first side surface by adopting dry etching to form the insulating layer with the primary step-shaped first side surface.
9. The method according to claim 8, wherein after the insulating layer with the first side surface stepped one step is formed in a case where the size of the second conductive layer is smaller than the size of the second photoresist pattern, the method further comprises: ashing the second photoresist pattern and etching the insulating layer with the first side in the shape of the one-step for the third time at least once to enable the first side to be in the shape of the multi-step;
ashing the second photoresist pattern and etching the insulating layer with the first side in the first step shape for the third time, wherein the ashing step comprises:
reducing the size of the second photoresist pattern by adopting an ashing process to form a third photoresist pattern, wherein the size of the third photoresist pattern is larger than or equal to that of the second conductive layer;
and performing third etching on the insulating layer with the first side surface in the first step shape by adopting dry etching so as to increase the number of steps of the first side surface by one step.
10. The method according to claim 6, wherein the active layer, the gate insulating layer and the gate electrode are formed by a single patterning process.
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| CN110707181B (en) * | 2019-11-06 | 2020-12-22 | 武汉敏芯半导体股份有限公司 | Method for manufacturing mesa type photoelectric detector |
| CN114122015B (en) * | 2021-11-15 | 2023-08-22 | 武汉华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display panel |
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| CN104157693A (en) * | 2013-05-14 | 2014-11-19 | 乐金显示有限公司 | Oxide thin film transistor and method of fabricating the same |
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