WO2023081289A1 - Convertisseur numérique-analogique d'entrée à réponse impulsionnelle finie - Google Patents

Convertisseur numérique-analogique d'entrée à réponse impulsionnelle finie Download PDF

Info

Publication number
WO2023081289A1
WO2023081289A1 PCT/US2022/048836 US2022048836W WO2023081289A1 WO 2023081289 A1 WO2023081289 A1 WO 2023081289A1 US 2022048836 W US2022048836 W US 2022048836W WO 2023081289 A1 WO2023081289 A1 WO 2023081289A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital
analog converter
taps
input
group
Prior art date
Application number
PCT/US2022/048836
Other languages
English (en)
Inventor
Paul M. Astrachan
Lingli Zhang
John L. Melanson
James Kelton
Original Assignee
Cirrus Logic International Semiconductor Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic International Semiconductor Ltd. filed Critical Cirrus Logic International Semiconductor Ltd.
Priority to GBGB2403544.6A priority Critical patent/GB202403544D0/en
Priority claimed from US17/980,105 external-priority patent/US20230139547A1/en
Publication of WO2023081289A1 publication Critical patent/WO2023081289A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/808—Simultaneous conversion using weighted impedances using resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
    • H03M3/504—Details of the final digital/analogue conversion following the digital delta-sigma modulation the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Definitions

  • the present disclosure relates in general to circuits for electronic devices, including without limitation personal audio devices such as wireless telephones and media players, and more specifically, to a digital-to-analog converter (DAC) with embedded minimal error adaptive slope compensation for a digital peak current controlled switched mode power supply.
  • DAC digital-to-analog converter
  • Personal audio devices including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use.
  • Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers.
  • Such circuitry often includes a speaker driver including a power amplifier for driving an audio output signal to headphones or speakers.
  • Such circuitry often includes a digital-to- analog converter (DAC) for converting a digital audio signal into a corresponding analog audio signal, which may be amplified and driven to a loudspeaker or other audio transducer.
  • DAC digital-to- analog converter
  • a digital signal may comprise a pulse-width modulated (PWM) signal to which an analog gain is applied using a serial string of resistors having appropriate tap points in order to provide a desired input resistance.
  • PWM pulse-width modulated
  • no filtering of the digital input signal may occur because it is a binary signal and such approach does not support a multi-level signal that is typically required for filtered data.
  • one or more disadvantages and problems associated with existing approaches to converting a digital PWM signal to an analog signal may be reduced or eliminated.
  • a digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.
  • a method may be provided for use in a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance.
  • the method may include selectively enabling and selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.
  • a digital- to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.
  • a method may be provided for a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator.
  • the method may include selectively enabling and disabling particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such an even number of members are enabled at a time, with half of such enabled members in a first group and half of such enabled members in a second group.
  • FIGURE 1 illustrates an example personal audio device, in accordance with embodiments of the present disclosure
  • FIGURE 2 illustrates a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure
  • FIGURE 3 illustrates an example circuit diagram of selected components of a digital-to- analog converter, in accordance with embodiments of the present disclosure
  • FIGURE 4 illustrates an example of generation of analog gain by delaying and summing the various delayed PWM signals through each of parallel gain taps of a digital- to-analog converter, in accordance with embodiments of the present disclosure
  • FIGURES 5A and 5B illustrate examples of a filter that may be implemented by enabling two pairs of parallel gain taps of a digital-to-analog converter, in accordance with embodiments of the present disclosure
  • FIGURES 6A and 6B illustrate examples of a filter that may be implemented by enabling six pairs of parallel gain taps of a digital-to-analog converter, in accordance with embodiments of the present disclosure
  • FIGURE 7 illustrates an example graph depicting example tap delays used when two tap pairs are enabled, in accordance with embodiments of the present disclosure
  • FIGURE 8 illustrates an example graph depicting example tap delays used when four tap pairs are enabled, in accordance with embodiments of the present disclosure.
  • FIGURE 9 illustrates an example graph depicting example tap delays used when six tap pairs are enabled, in accordance with embodiments of the present disclosure.
  • FIGURE 1 illustrates an example personal audio device 1, in accordance with embodiments of the present disclosure.
  • FIGURE 1 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8 A and 8B.
  • Headset 3 depicted in FIGURE 1 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers.
  • a plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1.
  • Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1.
  • personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer.
  • IC audio integrated circuit
  • FIGURE 2 illustrates a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure.
  • a microcontroller core 18 may supply a digital input signal DIG_IN to a digital gain element 12 which may apply a digital gain GAIND to digital input signal DIG_IN in order to generate modified digital input signal DIG_IN' to digital-to- analog converter (DAC) 14.
  • DAC 14 may convert modified digital input signal DIG_IN' to an analog differential output signal VOUT.
  • DAC 14 may be configured to apply an analog gain GAINA to amplify or attenuate modified digital input signal DIG_IN' to provide differential output signal VOUT, which may operate a speaker, a headphone transducer, a line level signal output, other transducer, and/or other suitable output.
  • digital gain GAIND and analog gain GAINA may apply a desired overall gain (e.g., GAIND- GAINA) to digital input signal DIG_IN in order to generate differential output signal VOUT.
  • a power supply 10 may provide the power supply rail inputs of DAC 14.
  • audio IC 9 may include control circuitry 20 configured to control digital gain GAIND and analog gain GAINA, as described in greater detail below.
  • FIGURES 1 and 2 contemplate that audio IC 9 resides in a personal audio device, systems and methods described herein may also be applied to electrical and electronic systems and devices other than a personal audio device, including audio systems for use in a computing device larger than a personal audio device, including without limitation an automobile, a building, or other structure.
  • a DAC such as DAC 14 may be used in other applications besides audio processing and generating audio signals, including without limitation generating analog signals for other transducers, including without limitation haptic transducers.
  • FIGURE 3 illustrates an example circuit diagram of selected components of DAC 14, in accordance with embodiments of the present disclosure.
  • each of positive polarity signal DIG_IN ' ,+) and negative polarity signal DIG_IN' ( ) may comprise PWM signals.
  • DAC 14 may include a plurality of parallel taps arranged in pairs such that one input of each tap pair receives positive polarity signal DIG_IN' ,+) and the other input of such tap pair receives negative polarity signal DIG_IN' ( ) .
  • Each tap may include a delay element 30 that adds a signal delay of a defined duration, a buffer 32 for buffering the delayed signal, and an input resistor 34, with a terminal of each input resistor 34 of taps receiving positive polarity signal DIG_IN ' ,+) coupled together at an inverting input of an integrator 38 and a terminal of each input resistor 34 of taps receiving negative polarity signal DIG_IN' ( ) coupled together at a non-inverting input of integrator 38.
  • a feedback resistor 36 may be coupled between an inverting output of and a non- inverting input of integrator 38 and another feedback resistor 36 may be coupled between a non-inverting output of and an inverting input of integrator 38.
  • integrator 38 may generate an analog integrator output signal VINT that may be further processed by other components of DAC 14 (not explicitly shown, but may include one or more loop filters, modulators, driving output stages, etc.) to generate analog output voltage VOUT.
  • each gain tap may be selectively enabled or disabled (e.g., by control circuitry 20), such that input resistance, and accordingly analog gain of DAC 14, may be programmed by enabling between 1 and N parallel taps, wherein N is the number of taps available.
  • an analog gain GAINA in decibels for DAC 14 may be given by: n ⁇ R F
  • GAIN A 201og— — —
  • n the number of the N taps that are enabled.
  • n the number of the N taps that are enabled.
  • a desired gain may be provided by tuning feedback resistors 36 and/or the combination of enabled parallel gain taps to result in an appropriate gain for a given application.
  • gains may further be manipulated by tuning (e.g., by control circuitry 20) digital gain GAIND as appropriate to achieve a desired overall gain. For example, if a gain of 10 dB were desired, four taps of DAC 14 may be enabled to provide analog GAINA of 12.04 dB and digital gain GAIND may be tuned to apply an attenuation of 2.04 dB to result in an overall path gain of 10 dB.
  • selectively enabling and disabling the various parallel taps of DAC 14 may in effect implement a hybrid analog/digital finite impulse response (FIR) filter with desired filter characteristics (e.g., desired filter nulls) by taking advantage of the summing nodes present at the inputs of integrator 38.
  • FIR finite impulse response
  • FIGURE 4 illustrates an example of generation of analog gain GAINA by delaying and summing the various delayed PWM signals through each of the taps of DAC 14, in accordance with embodiments of the present disclosure.
  • FIGURE 4 depicts a modified digital analog signal DIG_IN' with delays of durations A, B, C, and D applied by delay elements 30 of different gain taps.
  • FIGURE 4 further shows the summation of two of the delayed signals and summation of all four of the delayed signals. As seen in FIGURE 4, the group delay between the two summed PWM signals are the same, and the gain is increased by two for the sum of the four delayed signals as compared to the sum of two delayed signals.
  • both control of gain and filter characteristics of DAC 14 may be achieved by selectively enabling and disabling parallel gain taps of DAC 14.
  • a filter represented in the time-domain by the impulse response function of FIGURE 5A and with a frequency-domain representation represented by FIGURE 5B may be implemented.
  • a filter represented in the time-domain by the impulse response function of FIGURE 6A and with a frequency-domain representation represented by FIGURE 6B may be implemented.
  • control circuitry 20 for enabling and disabling taps of DAC 14 may be configured to enable and disable taps at points of time in which signal artifacts may be avoided. For example, assume a tap pair delays a data symbol by a period of time t. By delaying a control signal for enabling or disabling the tap pair by time t from the start of the symbol (which may always be zero), the tap pair may too be enabled or disabled when the data associated with such tap is also zero. In an alternative implementation, a tap pair may be enabled or disabled when its input data is “1” if desired.
  • control circuitry 20 may be configured to sequence control signals for enabling and disabling each tap pair of DAC 14 based on a delay added to modified digital input signal DIG_IN' by such tap pair, so as to enable only when both polarities of the delayed signal as delayed by delay elements 30 are zero or “1”, as desired.
  • Choices for the hybrid analog/digital FIR structure described above with respect to FIGURE 3 may play a role in both filtering and matching of the input waveform and output of a multiple level output stage (or other component downstream of DAC 14), as well as minimize integrated crosstalk noise, integrator dynamic range, and total harmonic distortion noise.
  • control circuitry 20 may enable an even number of tap pairs at a time, with half of such enabled tap pairs in a first group and half of such enabled tap pairs in a second group, wherein the first group and the second group are separated temporally from each other in order to facilitate matching of input and output waveforms. Accordingly, when enabling additional tap pairs, control circuitry 20 may enable a tap pair for each of the first group and the second group, and when disabling tap pairs, may disable a tap pair from each of the first group and the second group. Furthermore, when enabling (or disabling) additional tap pairs, control circuitry 20 may enable (or disable) tap pairs at tap locations by alternating between tap locations that decrease duration between the centers of each tap group and tap locations that increase duration between the centers of each tap group.
  • control circuitry 20 may enable two tap pairs: one tap pair in the first group having a delay of ti and another tap pair in the second group having a delay of t2.
  • control circuitry 20 may enable an additional two tap pairs: one tap pair having the lowest delay greater than ti and another tap pair having the highest delay less than t2, such that the difference between the centers of the two groups slightly decreases, and the centers of the first group and the second group remain at approximately delays ti and t2 (e.g., each center remains within the difference between delays ti and t2 and the delays of their respective adjacent tap pairs).
  • control circuitry 20 may enable an additional two tap pairs: one tap pair having the highest delay lower than ti and another tap pair having the lowest delay greater than t2, such that the difference between the centers of the two groups slightly increases, and the centers of the first group and the second group approximately return to delays ti and t2, respectively.
  • control circuitry 20 may alternatingly enable tap pairs in the opposite order - to first increase duration between centers of the first group and second group and then to decrease duration between centers of the first group and second group.
  • control circuitry 20 may set delays ti and t2 at 25% and 75%, respectively, of the pulse width of modified digital input signal DIG_IN'.
  • FIGURES 4 through 9 contemplate the use of a differential input signal and pairs of differential gain taps
  • the systems and methods exemplified by FIGURES 4 through 9 and the description thereof may also be applied to an input network of a plurality of single-ended taps each having a delay, including each of the single-ended taps having a different delay.
  • references in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated.
  • each refers to each member of a set or each member of a subset of a set.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un convertisseur numérique-analogique qui peut comprendre un intégrateur, un réseau d'entrée comprenant une pluralité de prises parallèles, chaque élément de la pluralité de prises parallèles comprenant une résistance d'entrée respective, et un ensemble de circuits de régulation configurés pour activer sélectivement et désactiver sélectivement des éléments particuliers de la pluralité de prises parallèles afin de programmer une résistance d'entrée efficace du réseau d'entrée pour réguler un gain analogique du convertisseur numérique-analogique.
PCT/US2022/048836 2021-11-03 2022-11-03 Convertisseur numérique-analogique d'entrée à réponse impulsionnelle finie WO2023081289A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GBGB2403544.6A GB202403544D0 (en) 2021-11-03 2022-11-03 Finite impulse response input digital-to-analog convertor

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US202163275161P 2021-11-03 2021-11-03
US63/275,161 2021-11-03
US202163277812P 2021-11-10 2021-11-10
US63/277,812 2021-11-10
US17/980,105 2022-11-03
US17/980,105 US20230139547A1 (en) 2021-11-03 2022-11-03 Finite impulse response input digital-to-analog converter

Publications (1)

Publication Number Publication Date
WO2023081289A1 true WO2023081289A1 (fr) 2023-05-11

Family

ID=84519475

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/048836 WO2023081289A1 (fr) 2021-11-03 2022-11-03 Convertisseur numérique-analogique d'entrée à réponse impulsionnelle finie

Country Status (2)

Country Link
GB (1) GB202403544D0 (fr)
WO (1) WO2023081289A1 (fr)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140062745A1 (en) * 2012-08-29 2014-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for a high resolution digital input class d amplifier with feedback

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140062745A1 (en) * 2012-08-29 2014-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for a high resolution digital input class d amplifier with feedback

Also Published As

Publication number Publication date
GB202403544D0 (en) 2024-04-24

Similar Documents

Publication Publication Date Title
CN110417414B (zh) 可切换次级回放路径
US11271583B2 (en) Current digital-to-analog converter with high-impedance output
US20170294888A1 (en) Audio amplifier system
US10873811B1 (en) Low-latency audio output with variable group delay
CN110731050B (zh) 控制信号路径的噪声传递函数以减少电荷泵噪声
US10404248B2 (en) Calibration of a dual-path pulse width modulation system
WO2013149020A1 (fr) Agencement à faible bruit et faible consommation pour la lecture de signaux audio
KR102225018B1 (ko) 펄스 폭 변조 증폭기를 위한 구성 가능한 제어 루프 토폴로지
WO2018194979A1 (fr) Convertisseur numérique-analogique à courant entièrement différentiel
US20230139547A1 (en) Finite impulse response input digital-to-analog converter
WO2023081289A1 (fr) Convertisseur numérique-analogique d'entrée à réponse impulsionnelle finie
WO2023081296A1 (fr) Convertisseur numérique-analogique d'entrée à réponse impulsionnelle finie
CN110603731B (zh) 具有可配置最终输出级的放大器中的切换
WO2022256180A1 (fr) Minimisation de la distorsion harmonique totale et de la distorsion d'intermodulation induite par l'alimentation électrique dans un amplificateur à modulation d'impulsions en largeur de classe d asymétrique
WO2017184458A1 (fr) Alimentation électrique à variation de signal unique pour une pluralité d'amplificateurs
US10476444B1 (en) Cross-fading in dual-path pulse width modulation system
CN209897012U (zh) D类放大器电路和音频系统
US11438697B2 (en) Low-latency audio output with variable group delay
US10594310B2 (en) Full-scale range enhancement in a dual-path pulse width modulation playback system
US20170048614A1 (en) Corrections for Transducer Deficiencies
WO2018004610A1 (fr) Réduction à un minimum des transitoires de démarrage dans un chemin de lecture audio
WO2021138060A1 (fr) Réduction au minimum du bruit de canal libre dans un amplificateur de modulation de largeur d'impulsion de classe d
CN118104129A (zh) 多电平脉宽调制系统中的共模补偿

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22823179

Country of ref document: EP

Kind code of ref document: A1