WO2023080085A1 - Semiconductor device production method - Google Patents

Abstract

A semiconductor device production method comprising: a step for preparing a wafer having a main surface on which a device region and predetermined cutting lines defining the device region are set; an electrode forming step for forming a dummy electrode on the predetermined cutting lines; a step for forming a sealing insulator covering the periphery of the dummy electrode on the main surface so as to expose a part of the dummy electrode; a step for removing the dummy electrode and forming an opening extending along the predetermined cutting lines on the sealing insulator; and a step for cutting the wafer along the opening.

Description

Semiconductor device manufacturing method

This application claims priority based on Japanese Patent Application No. 2021-181315 filed with the Japan Patent Office on November 5, 2021, and the entire disclosure of this application is incorporated herein by reference. The present disclosure relates to a method of manufacturing a semiconductor device.

Patent Document 1 discloses a semiconductor device including a semiconductor substrate, electrodes and a protective layer. The electrode is arranged on the semiconductor substrate. The protective layer has a laminate structure including an inorganic protective layer and an organic protective layer, and covers the electrodes.

U.S. Patent Application Publication No. 2019/0080976

One embodiment provides a method of manufacturing a semiconductor device that can improve reliability.

One embodiment comprises the steps of: preparing a wafer having a main surface on which a device region and a line to cut for partitioning the device region is set; an electrode forming step of forming a dummy electrode on the line to cut; forming a sealing insulator covering the periphery of the dummy electrode on the main surface so as to expose the dummy electrode; removing the dummy electrode and sealing the opening extending along the line to cut; A method for manufacturing a semiconductor device is provided, comprising the steps of: forming a non-insulating insulator; and cutting the wafer along the opening.

The above or further objects, features and advantages will be made clear by the embodiments described with reference to the accompanying drawings.

FIG. 1 is a plan view showing the semiconductor device according to the first embodiment. FIG. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is an enlarged plan view showing the main part of the inner part of the chip. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is an enlarged cross-sectional view showing the main part of the periphery of the chip. FIG. 6 is a plan view showing a layout example of gate electrodes and source electrodes. FIG. 7 is a plan view showing a layout example of the upper insulating film. FIG. 8 is a plan view showing the wafer structure used during fabrication. 9 is a cross-sectional view showing the device region shown in FIG. 8. FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 1. FIG. FIG. 10B is a cross-sectional view showing a step after FIG. 10A. FIG. 10C is a cross-sectional view showing a step after FIG. 10B. FIG. 10D is a cross-sectional view showing a step after FIG. 10C. FIG. 10E is a cross-sectional view showing a step after FIG. 10D. FIG. 10F is a cross-sectional view showing a step after FIG. 10E. FIG. 10G is a cross-sectional view showing a step after FIG. 10F. FIG. 10H is a cross-sectional view showing a step after FIG. 10G. FIG. 10I is a cross-sectional view showing a step after FIG. 10H. FIG. 10J is a cross-sectional view showing a step after FIG. 10I. FIG. 10K is a cross-sectional view showing a step after FIG. 10J. FIG. 10L is a cross-sectional view showing a step after FIG. 10K. FIG. 10M is a cross-sectional view showing a step after FIG. 10L. FIG. 10N is a cross-sectional view showing a step after FIG. 10M. FIG. 11 is a cross-sectional view showing the semiconductor device according to the second embodiment. 12A to 12C are cross-sectional views showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 13 is a cross-sectional view showing the semiconductor device according to the third embodiment. 14A and 14B are cross-sectional views showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 15 is a plan view showing the semiconductor device according to the fourth embodiment. FIG. 16 is a plan view showing the semiconductor device according to the fifth embodiment. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 16. FIG. 18 is a circuit diagram showing an electrical configuration of the semiconductor device shown in FIG. 16. FIG. FIG. 19 is a plan view showing the semiconductor device according to the sixth embodiment. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 19. FIG. FIG. 21 is a plan view showing the semiconductor device according to the seventh embodiment. FIG. 22 is a plan view showing the semiconductor device according to the eighth embodiment. FIG. 23 is a plan view showing the semiconductor device according to the ninth embodiment. FIG. 24 is a plan view showing the semiconductor device according to the tenth embodiment. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 24. FIG. FIG. 26 is a cross-sectional view showing the semiconductor device according to the eleventh embodiment. FIG. 27 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment. FIG. 28 is a cross-sectional view showing a modification of the chip applied to each embodiment. FIG. 29 is a cross-sectional view showing a modification of the sealing insulator applied to each embodiment. FIG. 30 is a plan view showing a package in which the semiconductor devices according to the first to ninth embodiments are mounted. FIG. 31 is a plan view showing a package on which semiconductor devices according to tenth to twelfth embodiments are mounted. FIG. 32 is a perspective view showing a package in which the semiconductor devices according to the first to ninth embodiments and the semiconductor devices according to the tenth to twelfth embodiments are mounted. 33 is an exploded perspective view of the package shown in FIG. 32; FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 32. FIG.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The attached drawings are schematic diagrams and are not strictly illustrated, and the scales and the like do not necessarily match. In addition, the same reference numerals are given to structures corresponding to each other in the accompanying drawings, and duplicate descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omissions or simplifications apply.

FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is an enlarged plan view showing the main part of the inner part of the chip 2. FIG. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is an enlarged cross-sectional view showing the main part of the periphery of the chip 2. As shown in FIG. FIG. 6 is a plan view showing a layout example of the gate electrode 30 and the source electrode 32. As shown in FIG. FIG. 7 is a plan view showing a layout example of the upper insulating film 38. As shown in FIG.

1 to 7, a semiconductor device 1A in this embodiment includes a chip 2 that includes a wide bandgap semiconductor single crystal and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). include. That is, the semiconductor device 1A is a "wide bandgap semiconductor device". Chip 2 may also be referred to as a "semiconductor chip" or a "wide bandgap semiconductor chip". A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). GaN (gallium nitride), SiC (silicon carbide) and C (diamond) are exemplified as wide bandgap semiconductors.

The chip 2 is, in this embodiment, a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. That is, the semiconductor device 1A is a "SiC semiconductor device". Hexagonal SiC single crystals have a plurality of polytypes including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals and the like. In this form an example is shown in which the chip 2 comprises a 4H—SiC single crystal, but this does not exclude the choice of other polytypes.

The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. ing. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2 . The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of SiC single crystal.

In this case, it is preferable that the first main surface 3 is formed by the silicon surface of the SiC single crystal, and the second main surface 4 is formed by the carbon surface of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may exceed 0° and be 10° or less. The off angle is preferably 5° or less. The second main surface 4 may be a ground surface having grinding marks, or may be a smooth surface having no grinding marks.

The first side surface 5A and the second side surface 5B extend in the first direction X along the first main surface 3 and face the second direction Y intersecting (specifically, perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. As shown in FIG. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. The first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks, or may be smooth surfaces having no grinding marks.

The chip 2 may have a thickness of 5 μm or more and 250 μm or less with respect to the normal direction Z. The thickness of the chip 2 may be 100 μm or less. The thickness of the chip 2 is preferably 50 μm or less. It is particularly preferable that the thickness of the chip 2 is 40 μm or less. The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 10 mm or less in plan view.

The length of the first to fourth side surfaces 5A to 5D is preferably 1 mm or more. It is particularly preferable that the lengths of the first to fourth side surfaces 5A to 5D are 2 mm or more. That is, it is preferable that the chip 2 has a plane area of 1 mm square or more (preferably 2 mm square or more) and a thickness of 100 μm or less (preferably 50 μm or less) in a cross-sectional view. The lengths of the first to fourth side surfaces 5A to 5D are set in the range of 4 mm or more and 6 mm or less in this embodiment.

The semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side within the chip 2 . The first semiconductor region 6 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 consists of an epitaxial layer (specifically, a SiC epitaxial layer) in this embodiment. The first semiconductor region 6 may have a thickness in the normal direction Z of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 3 μm or more and 30 μm or less. It is particularly preferable that the thickness of the first semiconductor region 6 is 5 μm or more and 25 μm or less.

The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a region (surface layer portion) on the second main surface 4 side within the chip 2 . The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 . The second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate) in this embodiment. That is, the chip 2 has a laminated structure including a semiconductor substrate and an epitaxial layer.

The second semiconductor region 7 may have a thickness of 1 μm or more and 200 μm or less with respect to the normal direction Z. The thickness of the second semiconductor region 7 is preferably 5 μm or more and 50 μm or less. It is particularly preferable that the thickness of the second semiconductor region 7 is 5 μm or more and 20 μm or less. Considering the error that occurs in the first semiconductor region 6, the thickness of the second semiconductor region 7 is preferably 10 μm or more. Most preferably, the thickness of the second semiconductor region 7 is less than the thickness of the first semiconductor region 6 . With the second semiconductor region 7 having a relatively small thickness, the resistance value (for example, on-resistance) caused by the second semiconductor region 7 can be reduced. Of course, the thickness of the second semiconductor region 7 may exceed the thickness of the first semiconductor region 6 .

The semiconductor device 1A includes an active surface 8 formed on the first main surface 3, an outer surface 9, and first to fourth connection surfaces 10A to 10D (connecting surfaces). The active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A to 10D define a mesa portion 11 (plateau) on the first main surface 3. As shown in FIG. The active surface 8 may be called "first surface", the outer surface 9 may be called "second surface", and the first to fourth connection surfaces 10A to 10D may be called "connection surfaces". The active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A-10D (that is, the mesa portion 11) may be regarded as components of the chip 2 (first main surface 3).

The active surface 8 is formed spaced inwardly from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). The active surface 8 has a flat surface extending in the first direction X and the second direction Y. As shown in FIG. In this form, the active surface 8 is formed in a square shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.

The outer surface 9 is located outside the active surface 8 and recessed from the active surface 8 in the thickness direction of the chip 2 (the second main surface 4 side). Specifically, the outer surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6 . The outer side surface 9 extends in a belt shape along the active surface 8 in a plan view and is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active surface 8 . The outer side surface 9 has flat surfaces extending in the first direction X and the second direction Y and formed substantially parallel to the active surface 8 . The outer side surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

The first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer surface 9. The first connection surface 10A is positioned on the first side surface 5A side, the second connection surface 10B is positioned on the second side surface 5B side, the third connection surface 10C is positioned on the third side surface 5C side, and the fourth connection surface 10D. is located on the side of the fourth side surface 5D. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y. As shown in FIG. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X. As shown in FIG.

The first to fourth connection surfaces 10A to 10D may extend substantially vertically between the active surface 8 and the outer surface 9 so as to define a quadrangular prism-shaped mesa portion 11. The first to fourth connection surfaces 10A to 10D may be inclined downward from the active surface 8 toward the outer surface 9 so that the mesa portion 11 in the shape of a truncated square pyramid is defined. Thus, semiconductor device 1A includes mesa portion 11 formed in first semiconductor region 6 on first main surface 3 . The mesa portion 11 is formed only in the first semiconductor region 6 and not formed in the second semiconductor region 7 .

A semiconductor device 1A includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure 12 formed on an active surface 8 (first main surface 3). In FIG. 2, the MISFET structure 12 is shown simplified by dashed lines. A specific structure of the MISFET structure 12 will be described below with reference to FIGS. 3 and 4. FIG.

The MISFET structure 12 includes a p-type (second conductivity type) body region 13 formed on the surface layer of the active surface 8 . The body region 13 is formed spaced from the bottom of the first semiconductor region 6 toward the active surface 8 side. Body region 13 is formed in a layered shape extending along active surface 8 . The body region 13 may be partially exposed from the first to fourth connection surfaces 10A to 10D.

The MISFET structure 12 includes an n-type source region 14 formed on the surface layer of the body region 13 . The source region 14 has an n-type impurity concentration higher than that of the first semiconductor region 6 . The source region 14 is formed spaced from the bottom of the body region 13 toward the active surface 8 side. The source region 14 is formed in layers extending along the active surface 8 . Source region 14 may be exposed from the entire active surface 8 . The source region 14 may be exposed from part of the first to fourth connection surfaces 10A to 10D. Source region 14 forms a channel in body region 13 with first semiconductor region 6 .

The MISFET structure 12 includes multiple gate structures 15 formed on the active surface 8 . The plurality of gate structures 15 are arranged in the first direction X at intervals in plan view, and are formed in strips extending in the second direction Y, respectively. A plurality of gate structures 15 extend through the body region 13 and the source region 14 to reach the first semiconductor region 6 . A plurality of gate structures 15 control channel inversion and non-inversion within the body region 13 .

Each gate structure 15, in this form, includes a gate trench 15a, a gate insulating film 15b and a gate buried electrode 15c. A gate trench 15 a is formed in the active surface 8 and defines the walls of the gate structure 15 . The gate insulating film 15b covers the walls of the gate trench 15a. The gate buried electrode 15c is buried in the gate trench 15a with the gate insulating film 15b interposed therebetween and faces the channel with the gate insulating film 15b interposed therebetween.

The MISFET structure 12 includes multiple source structures 16 formed on the active surface 8 . A plurality of source structures 16 are arranged in regions between a pair of adjacent gate structures 15 on the active surface 8 . The plurality of source structures 16 are each formed in a strip shape extending in the second direction Y in plan view. A plurality of source structures 16 extend through the body region 13 and the source region 14 to reach the first semiconductor region 6 . A plurality of source structures 16 have a depth that exceeds the depth of gate structures 15 . The plurality of source structures 16 specifically has a depth approximately equal to the depth of the outer surface 9 .

Each source structure 16 includes a source trench 16a, a source insulating film 16b and a source buried electrode 16c. A source trench 16 a is formed in the active surface 8 and defines the walls of the source structure 16 . The source insulating film 16b covers the walls of the source trench 16a. The source buried electrode 16c is buried in the source trench 16a with the source insulating film 16b interposed therebetween.

The MISFET structure 12 includes a plurality of p-type contact regions 17 respectively formed in regions along the plurality of source structures 16 within the chip 2 . A plurality of contact regions 17 have a higher p-type impurity concentration than body region 13 . Each contact region 17 covers the sidewalls and bottom walls of each source structure 16 and is electrically connected to body region 13 .

The MISFET structure 12 includes a plurality of p-type well regions 18 respectively formed in regions along the plurality of source structures 16 within the chip 2 . Each well region 18 may have a p-type impurity concentration higher than body region 13 and lower than contact region 17 . Each well region 18 covers the corresponding source structure 16 with the corresponding contact region 17 interposed therebetween. Each well region 18 covers the sidewalls and bottom walls of corresponding source structure 16 and is electrically connected to body region 13 and contact region 17 .

Referring to FIG. 5, semiconductor device 1A includes p-type outer contact region 19 formed in the surface layer of outer side surface 9 . Outer contact region 19 has a p-type impurity concentration higher than that of body region 13 . The outer contact region 19 is formed in a band-like shape extending along the active surface 8 and spaced apart from the peripheral edge of the active surface 8 and the peripheral edge of the outer side surface 9 in plan view.

In this form, the outer contact region 19 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view. The outer contact region 19 is formed spaced apart from the bottom of the first semiconductor region 6 to the outer side surface 9 . The outer contact region 19 is located on the bottom side of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (source structures 16).

The semiconductor device 1A includes a p-type outer well region 20 formed in the surface layer portion of the outer side surface 9 . The outer well region 20 has a p-type impurity concentration lower than that of the outer contact region 19 . The p-type impurity concentration of the outer well region 20 is preferably approximately equal to the p-type impurity concentration of the well region 18 . The outer well region 20 is formed in a region between the peripheral edge of the active surface 8 and the outer contact region 19 in plan view, and is formed in a strip shape extending along the active surface 8 .

In this form, the outer well region 20 is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active surface 8 in plan view. The outer well region 20 is formed spaced apart from the bottom of the first semiconductor region 6 to the outer side surface 9 . The outer well region 20 may be formed deeper than the outer contact region 19 . The outer well region 20 is located on the bottom side of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (source structures 16).

The outer well region 20 is electrically connected to the outer contact region 19. In this embodiment, the outer well region 20 extends from the outer contact region 19 side toward the first to fourth connection surfaces 10A to 10D and covers the first to fourth connection surfaces 10A to 10D. Outer well region 20 is electrically connected to body region 13 at the surface layer of active surface 8 .

The semiconductor device 1A has at least one (preferably two or more and twenty or less) p-type field regions 21 formed in a region between the peripheral edge of the outer side surface 9 and the outer contact region 19 in the surface layer portion of the outer side surface 9. including. The semiconductor device 1A includes five field regions 21 in this form. A plurality of field regions 21 relax the electric field within the chip 2 at the outer surface 9 . The number, width, depth, p-type impurity concentration, etc. of the field regions 21 are arbitrary and can take various values according to the electric field to be relaxed.

The plurality of field regions 21 are arranged at intervals from the outer contact region 19 side to the peripheral edge side of the outer surface 9 . The plurality of field regions 21 are formed in strips extending along the active surface 8 in plan view. In this embodiment, the plurality of field regions 21 are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view. Thereby, the plurality of field regions 21 are each formed as an FLR (Field Limiting Ring) region.

A plurality of field regions 21 are formed at intervals from the bottom of the first semiconductor region 6 to the outer surface 9 . The plurality of field regions 21 are located on the bottom side of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (source structures 16). A plurality of field regions 21 may be formed deeper than the outer contact region 19 . The innermost field region 21 may be connected to the outer contact region 19 .

The semiconductor device 1A includes a main surface insulating film 25 covering the first main surface 3. Main surface insulating film 25 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 25 has a single layer structure made of a silicon oxide film in this embodiment. Main surface insulating film 25 particularly preferably includes a silicon oxide film made of oxide of chip 2 .

The main surface insulating film 25 covers the active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A to 10D. The main surface insulating film 25 continues to the gate insulating film 15b and the source insulating film 16b, and covers the active surface 8 so as to expose the gate buried electrode 15c and the source buried electrode 16c. The main surface insulating film 25 covers the outer surface 9 and the first to fourth connection surfaces 10A to 10D so as to cover the outer contact region 19, the outer well region 20 and the plurality of field regions 21. As shown in FIG.

The main surface insulating film 25 may be continuous with the first to fourth side surfaces 5A to 5D. In this case, the outer wall of the main surface insulating film 25 may be a ground surface having grinding marks. The outer wall of the main surface insulating film 25 may form one ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the main surface insulating film 25 may be formed with a space inwardly from the peripheral edge of the outer surface 9 to expose the first semiconductor region 6 from the peripheral edge of the outer surface 9 .

The semiconductor device 1A includes a sidewall structure 26 formed on the main surface insulating film 25 so as to cover at least one of the first to fourth connection surfaces 10A to 10D on the outer surface 9. In this form, the sidewall structure 26 is formed in an annular shape (square annular shape) surrounding the active surface 8 in plan view. The sidewall structure 26 may have a portion overlying the active surface 8 . Sidewall structure 26 may comprise an inorganic insulator or polysilicon. Sidewall structure 26 may be a sidewall interconnect electrically connected to source structure 16 .

The semiconductor device 1A includes an interlayer insulating film 27 formed on the main surface insulating film 25 . Interlayer insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 27 has a single-layer structure made of a silicon oxide film in this embodiment.

The interlayer insulating film 27 covers the active surface 8, the outer side surface 9 and the first to fourth connection surfaces 10A to 10D with the main surface insulating film 25 interposed therebetween. Specifically, the interlayer insulating film 27 covers the active surface 8, the outer side surface 9 and the first to fourth connection surfaces 10A to 10D with the sidewall structure 26 interposed therebetween. The interlayer insulating film 27 covers the MISFET structure 12 on the active surface 8 side, and covers the outer contact region 19, the outer well region 20 and the plurality of field regions 21 on the outer side surface 9 side.

The interlayer insulating film 27 continues to the first to fourth side surfaces 5A to 5D in this form. The outer wall of the interlayer insulating film 27 may be a ground surface having grinding marks. The outer wall of the interlayer insulating film 27 may form one ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the interlayer insulating film 27 may be formed spaced inwardly from the peripheral edge of the outer side surface 9 to expose the first semiconductor region 6 from the peripheral edge portion of the outer side surface 9 .

The semiconductor device 1A includes a gate electrode 30 arranged on the first main surface 3 (interlayer insulating film 27). Gate electrode 30 may be referred to as a “gate main surface electrode”. The gate electrode 30 is arranged in the inner part of the first main surface 3 with a space from the peripheral edge of the first main surface 3 . A gate electrode 30 is arranged above the active surface 8 in this embodiment. Specifically, the gate electrode 30 is arranged in a region on the periphery of the active surface 8 and close to the central portion of the third connection surface 10C (third side surface 5C). In this form, the gate electrode 30 is formed in a square shape in plan view. Of course, the gate electrode 30 may be formed in a polygonal shape other than a square shape, a circular shape, or an elliptical shape in plan view.

The gate electrode 30 preferably has a plane area of 25% or less of the first main surface 3. The planar area of gate electrode 30 may be 10% or less of first main surface 3 . The gate electrode 30 may have a thickness of 0.5 μm or more and 15 μm or less. The gate electrode 30 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film and a conductive polysilicon film.

The gate electrode 30 is made of at least one of a pure Cu film (a Cu film with a purity of 99% or higher), a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. may contain one. In this embodiment, the gate electrode 30 has a laminated structure including a Ti film and an Al alloy film (AlSiCu alloy film in this embodiment) laminated in this order from the chip 2 side.

The semiconductor device 1A includes a source electrode 32 spaced from the gate electrode 30 and arranged on the first main surface 3 (interlayer insulating film 27). The source electrode 32 may be referred to as a "source main surface electrode". The source electrode 32 is arranged in the inner part of the first main surface 3 with a space from the periphery of the first main surface 3 . A source electrode 32 is arranged on the active surface 8 in this embodiment. In this embodiment, the source electrode 32 has a body electrode portion 33 and at least one (in this embodiment, a plurality of) extraction electrode portions 34A and 34B.

The body electrode portion 33 is arranged in a region on the side of the fourth side surface 5D (fourth connection surface 10D) with a gap from the gate electrode 30 in plan view, and faces the gate electrode 30 in the first direction X. In this form, the body electrode portion 33 is formed in a polygonal shape (specifically, a rectangular shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.

The multiple lead electrode portions 34A and 34B include a first lead electrode portion 34A on one side (first side surface 5A side) and a second lead electrode portion 34B on the other side (second side surface 5B side). The first extraction electrode portion 34A is extracted from the body electrode portion 33 to a region located on one side (first side surface 5A side) in the second direction Y with respect to the gate electrode 30 in plan view, and extends in the second direction Y to the gate electrode portion 34A. It faces the electrode 30 .

The second extraction electrode portion 34B is extracted from the body electrode portion 33 to a region located on the other side (the second side surface 5B side) in the second direction Y with respect to the gate electrode 30 in plan view, and extends in the second direction Y to the gate electrode portion 34B. It faces the electrode 30 . That is, the plurality of extraction electrode portions 34A and 34B sandwich the gate electrode 30 from both sides in the second direction Y in plan view.

The source electrode 32 (body electrode portion 33 and lead-out electrode portions 34A and 34B) penetrates the interlayer insulating film 27 and the main surface insulating film 25 and electrically connects the plurality of source structures 16, the source regions 14 and the plurality of well regions 18. It is connected to the. Of course, the source electrode 32 may be composed of only the body electrode portion 33 without the lead electrode portions 34A and 34B.

The source electrode 32 has a planar area exceeding that of the gate electrode 30 . The plane area of the source electrode 32 is preferably 50% or more of the first main surface 3 . It is particularly preferable that the plane area of the source electrode 32 is 75% or more of the first main surface 3 . The source electrode 32 may have a thickness of 0.5 μm or more and 15 μm or less. The source electrode 32 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film and a conductive polysilicon film.

The source electrode 32 is composed of at least one of a pure Cu film (a Cu film with a purity of 99% or higher), a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. It is preferred to include one. In this embodiment, the source electrode 32 has a laminated structure including a Ti film and an Al alloy film (AlSiCu alloy film in this embodiment) laminated in this order from the chip 2 side. Source electrode 32 preferably comprises the same conductive material as gate electrode 30 .

The semiconductor device 1A includes at least one (a plurality in this embodiment) gate wirings 36A and 36B drawn from the gate electrode 30 onto the first main surface 3 (interlayer insulating film 27). The plurality of gate wirings 36A, 36B preferably contain the same conductive material as the gate electrode 30 . A plurality of gate lines 36A, 36B cover the active surface 8 and do not cover the outer surface 9 in this configuration. A plurality of gate wirings 36A and 36B are led out to a region between the peripheral edge of the active surface 8 and the source electrode 32 in a plan view, and extend along the source electrode 32 in a strip shape.

The plurality of gate wirings 36A, 36B specifically includes a first gate wiring 36A and a second gate wiring 36B. The first gate wiring 36A is drawn from the gate electrode 30 to a region on the first side surface 5A side in plan view. The first gate line 36A has a strip-like portion extending in the second direction Y along the third side surface 5C and a strip-like portion extending in the first direction X along the first side surface 5A. The second gate wiring 36B is drawn from the gate electrode 30 to a region on the second side surface 5B side in plan view. The second gate line 36B has a strip-like portion extending in the second direction Y along the third side surface 5C and a strip-like portion extending in the first direction X along the second side surface 5B.

The plurality of gate wirings 36A and 36B intersect (specifically, perpendicularly) both ends of the plurality of gate structures 15 at the periphery of the active surface 8 (first main surface 3). The multiple gate wirings 36A and 36B are electrically connected to the multiple gate structures 15 through the interlayer insulating film 27 . The plurality of gate wirings 36A and 36B may be directly connected to the plurality of gate structures 15, or may be electrically connected to the plurality of gate structures 15 via a conductor film.

The semiconductor device 1A includes a source wiring 37 drawn from the source electrode 32 onto the first main surface 3 (interlayer insulating film 27). Source line 37 preferably contains the same conductive material as source electrode 32 . The source wiring 37 is formed in a strip shape extending along the periphery of the active surface 8 in a region closer to the outer surface 9 than the plurality of gate wirings 36A and 36B. In this embodiment, the source wiring 37 is formed in a ring shape (specifically, a square ring shape) surrounding the gate electrode 30, the source electrode 32 and the plurality of gate wirings 36A and 36B in plan view.

The source wiring 37 covers the sidewall structure 26 with the interlayer insulating film 27 interposed therebetween, and is drawn out from the active surface 8 side to the outer surface 9 side. The source wiring 37 preferably covers the entire sidewall structure 26 over the entire circumference. Source line 37 has a portion that penetrates interlayer insulating film 27 and main surface insulating film 25 on the side of outer surface 9 and is connected to outer surface 9 (specifically, outer contact region 19). The source wiring 37 may be electrically connected to the sidewall structure 26 through the interlayer insulating film 27 .

The semiconductor device 1A includes an upper insulating film 38 that selectively covers the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A and 36B, and the source wiring 37. The upper insulating film 38 has a gate opening 39 that exposes the inner portion of the gate electrode 30 and covers the peripheral portion of the gate electrode 30 over the entire circumference. In this form, the gate opening 39 is formed in a square shape in plan view.

The upper insulating film 38 has a source opening 40 that exposes the inner part of the source electrode 32 in plan view, and covers the peripheral edge of the source electrode 32 over the entire circumference. In this form, the source opening 40 is formed in a polygonal shape along the source electrode 32 in plan view. The upper insulating film 38 covers the entire area of the plurality of gate wirings 36A and 36B and the entire area of the source wiring 37 .

The upper insulating film 38 covers the sidewall structure 26 with the interlayer insulating film 27 interposed therebetween, and extends from the active surface 8 side to the outer surface 9 side. The upper insulating film 38 is formed spaced inwardly from the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) and covers the outer contact region 19, the outer well region 20 and the plurality of field regions 21. are doing. The upper insulating film 38 partitions the dicing streets 41 with the periphery of the outer side surface 9 .

The dicing street 41 is formed in a strip shape extending along the peripheral edges (first to fourth side surfaces 5A to 5D) of the outer side surface 9 in plan view. In this embodiment, the dicing street 41 is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the inner portion (active surface 8) of the first main surface 3 in plan view. The dicing street 41 exposes the interlayer insulating film 27 in this form.

Of course, when the main surface insulating film 25 and the interlayer insulating film 27 expose the outer surface 9 , the dicing streets 41 may expose the outer surface 9 . The dicing street 41 may have a width of 1 μm or more and 200 μm or less. The width of the dicing street 41 is the width in the direction perpendicular to the extending direction of the dicing street 41 . The width of the dicing street 41 is preferably 5 μm or more and 50 μm or less.

The upper insulating film 38 preferably has a thickness exceeding the thickness of the gate electrode 30 and the thickness of the source electrode 32 . The thickness of the upper insulating film 38 is preferably less than the thickness of the chip 2 . The thickness of the upper insulating film 38 may be 3 μm or more and 35 μm or less. The thickness of the upper insulating film 38 is preferably 25 μm or less.

In this embodiment, the upper insulating film 38 has a laminated structure including an inorganic insulating film 42 and an organic insulating film 43 laminated in this order from the chip 2 side. The upper insulating film 38 may include at least one of the inorganic insulating film 42 and the organic insulating film 43, and does not necessarily include the inorganic insulating film 42 and the organic insulating film 43 at the same time. The inorganic insulating film 42 selectively covers the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A and 36B, and the source wiring 37, and partially covers the gate opening 39, the source opening 40, and the dicing street 41. Some are partitioned.

The inorganic insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film. The inorganic insulating film 42 preferably contains an insulating material different from that of the interlayer insulating film 27 . The inorganic insulating film 42 preferably contains a silicon nitride film. The inorganic insulating film 42 preferably has a thickness less than the thickness of the interlayer insulating film 27 . The inorganic insulating film 42 may have a thickness of 0.1 μm or more and 5 μm or less.

The organic insulating film 43 selectively covers the inorganic insulating film 42 and partitions part of the gate opening 39 , part of the source opening 40 and part of the dicing street 41 . Specifically, the organic insulating film 43 partially exposes the inorganic insulating film 42 on the wall surface of the gate opening 39 . Also, the organic insulating film 43 partially exposes the inorganic insulating film 42 on the wall surface of the source opening 40 . Further, the organic insulating film 43 partially exposes the inorganic insulating film 42 on the wall surface of the dicing street 41 .

Of course, the organic insulating film 43 may cover the inorganic insulating film 42 so that the inorganic insulating film 42 is not exposed from the wall surface of the gate opening 39 . The organic insulating film 43 may cover the inorganic insulating film 42 so that the inorganic insulating film 42 is not exposed from the wall surface of the source opening 40 . The organic insulating film 43 may cover the inorganic insulating film 42 so that the inorganic insulating film 42 is not exposed from the wall surfaces of the dicing streets 41 . In these cases, the organic insulating film 43 may cover the entire inorganic insulating film 42 .

The organic insulating film 43 is preferably made of a resin film other than thermosetting resin. The organic insulating film 43 may be made of translucent resin or transparent resin. The organic insulating film 43 may be made of a negative type or positive type photosensitive resin film. The organic insulating film 43 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. The organic insulating film 43 includes a polybenzoxazole film in this form.

The organic insulating film 43 preferably has a thickness exceeding the thickness of the inorganic insulating film 42 . The thickness of the organic insulating film 43 preferably exceeds the thickness of the interlayer insulating film 27 . It is particularly preferable that the thickness of the organic insulating film 43 exceeds the thickness of the gate electrode 30 and the thickness of the source electrode 32 . The thickness of the organic insulating film 43 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 43 is preferably 20 μm or less.

The semiconductor device 1A includes a gate terminal electrode 50 arranged on the gate electrode 30 . The gate terminal electrode 50 is erected in a pillar shape on a portion of the gate electrode 30 exposed from the gate opening 39 . The gate terminal electrode 50 has an area smaller than that of the gate electrode 30 in a plan view, and is arranged above the inner portion of the gate electrode 30 with a gap from the periphery of the gate electrode 30 .

The gate terminal electrode 50 has a gate terminal surface 51 and gate terminal sidewalls 52 . Gate terminal surface 51 extends flat along first main surface 3 . The gate terminal surface 51 may be a ground surface having grinding marks. The gate terminal side wall 52 is located on the upper insulating film 38 (more specifically, the organic insulating film 43) in this embodiment.

That is, the gate terminal electrode 50 includes portions in contact with the inorganic insulating film 42 and the organic insulating film 43 . The gate terminal sidewall 52 extends substantially vertically in the normal direction Z. As shown in FIG. "Substantially vertical" also includes a form extending in the stacking direction while curving (meandering). Gate terminal sidewall 52 includes a portion facing gate electrode 30 with upper insulating film 38 interposed therebetween. The gate terminal side walls 52 are preferably smooth surfaces without grinding marks.

In this embodiment, the gate terminal electrode 50 has a first projecting portion 53 projecting outward from the lower end portion of the gate terminal side wall 52 . The first projecting portion 53 is formed in a region closer to the upper insulating film 38 (organic insulating film 43 ) than the intermediate portion of the gate terminal side wall 52 . The first projecting portion 53 extends along the outer surface of the upper insulating film 38 in a cross-sectional view, and is formed in a tapered shape in which the thickness gradually decreases from the gate terminal side wall 52 toward the tip portion. As a result, the first projecting portion 53 has a sharp tip that forms an acute angle. Of course, the gate terminal electrode 50 without the first projecting portion 53 may be formed.

The gate terminal electrode 50 preferably has a thickness exceeding the thickness of the gate electrode 30 . The thickness of gate terminal electrode 50 is defined by the distance between gate electrode 30 and gate terminal surface 51 . It is particularly preferable that the thickness of the gate terminal electrode 50 exceeds the thickness of the upper insulating film 38 . The thickness of the gate terminal electrode 50 exceeds the thickness of the chip 2 in this embodiment. Of course, the thickness of the gate terminal electrode 50 may be less than the thickness of the chip 2 . The thickness of the gate terminal electrode 50 may be 10 μm or more and 300 μm or less. The thickness of the gate terminal electrode 50 is preferably 30 μm or more. It is particularly preferable that the thickness of the gate terminal electrode 50 is 80 μm or more and 200 μm or less.

The planar area of the gate terminal electrode 50 is adjusted according to the planar area of the first main surface 3 . The planar area of the gate terminal electrode 50 is defined by the planar area of the gate terminal surface 51 . The planar area of gate terminal electrode 50 is preferably 25% or less of first main surface 3 . The planar area of the gate terminal electrode 50 may be 10% or less of the first main surface 3 .

When the first main surface 3 has a plane area of 1 mm square or more, the plane area of the gate terminal electrode 50 may be 0.4 mm square or more. Gate terminal electrode 50 may be formed in a polygonal shape (for example, rectangular shape) having a plane area of 0.4 mm×0.7 mm or more. In this embodiment, the gate terminal electrode 50 is formed in a polygonal shape (quadrangular shape with four rectangular notched corners) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view. . Of course, the gate terminal electrode 50 may be formed in a rectangular shape, a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape in plan view.

In this form, the gate terminal electrode 50 has a laminated structure including a first gate conductor film 55 and a second gate conductor film 56 laminated in this order from the gate electrode 30 side. The first gate conductor film 55 may contain a Ti-based metal film. The first gate conductor film 55 may have a single layer structure made of a Ti film or a TiN film. The first gate conductor film 55 may have a laminated structure including a Ti film and a TiN film laminated in any order.

The first gate conductor film 55 has a thickness less than the thickness of the gate electrode 30 . The first gate conductor film 55 covers the gate electrode 30 in the form of a film in the gate opening 39 and is pulled out on the upper insulating film 38 in the form of a film. The first gate conductor film 55 forms part of the first projecting portion 53 . The first gate conductor film 55 is not necessarily formed and may be removed.

The second gate conductor film 56 forms the main body of the gate terminal electrode 50 . The second gate conductor film 56 may contain a Cu-based metal film. The Cu-based metal film may be a pure Cu film (a Cu film with a purity of 99% or more) or a Cu alloy film. The second gate conductor film 56 includes a pure Cu plating film in this embodiment. The second gate conductor film 56 preferably has a thickness exceeding the thickness of the gate electrode 30 . It is particularly preferable that the thickness of the second gate conductor film 56 exceeds the thickness of the upper insulating film 38 . The thickness of the second gate conductor film 56 exceeds the thickness of the chip 2 in this embodiment.

The second gate conductor film 56 covers the gate electrode 30 in the gate opening 39 with the first gate conductor film 55 interposed therebetween, and is pulled out in the form of a film onto the upper insulating film 38 with the first gate conductor film 55 interposed therebetween. ing. The second gate conductor film 56 forms part of the first projecting portion 53 . That is, the first projecting portion 53 has a laminated structure including the first gate conductor film 55 and the second gate conductor film 56 . The second gate conductor film 56 preferably has a thickness exceeding the thickness of the first gate conductor film 55 within the first projecting portion 53 .

The semiconductor device 1A includes a source terminal electrode 60 arranged on the source electrode 32 . The source terminal electrode 60 is erected in a columnar shape on a portion of the source electrode 32 exposed from the source opening 40 . The source terminal electrode 60 has an area smaller than the area of the source electrode 32 in a plan view, and is arranged above the inner portion of the source electrode 32 with a gap from the periphery of the source electrode 32 .

In this embodiment, the source terminal electrode 60 is arranged on the body electrode portion 33 of the source electrode 32 and is not arranged on the extraction electrode portions 34A and 34B of the source electrode 32. Thereby, the facing area between the gate terminal electrode 50 and the source terminal electrode 60 is reduced. Such a structure reduces the risk of a short circuit between the gate terminal electrode 50 and the source terminal electrode 60 when a conductive adhesive such as solder or metal paste is attached to the gate terminal electrode 50 and the source terminal electrode 60. is valid. Of course, a conductive joining member such as a conductive plate or a conductive wire (eg, bonding wire) may be connected to the gate terminal electrode 50 and the source terminal electrode 60 . In this case, the risk of a short circuit between the conductive joint member on the gate terminal electrode 50 side and the conductive joint member on the source terminal electrode 60 side can be reduced.

The source terminal electrode 60 has a source terminal surface 61 and source terminal sidewalls 62 . The source terminal surface 61 extends flat along the first main surface 3 . The source terminal surface 61 may be a ground surface having grinding marks. The source terminal sidewall 62 is located on the upper insulating film 38 (specifically, the organic insulating film 43) in this embodiment.

That is, the source terminal electrode 60 includes portions in contact with the inorganic insulating film 42 and the organic insulating film 43 . The source terminal sidewall 62 extends substantially vertically in the normal direction Z. As shown in FIG. "Substantially vertical" also includes a form extending in the stacking direction while curving (meandering). Source terminal sidewall 62 includes a portion facing source electrode 32 with upper insulating film 38 interposed therebetween. The source terminal sidewall 62 preferably has a smooth surface without grinding marks.

The source terminal electrode 60 has a second projecting portion 63 projecting outward from the lower end portion of the source terminal side wall 62 in this embodiment. The second projecting portion 63 is formed in a region closer to the upper insulating film 38 (organic insulating film 43 ) than the intermediate portion of the source terminal side wall 62 . The second projecting portion 63 extends along the outer surface of the upper insulating film 38 in a cross-sectional view, and is formed in a tapered shape in which the thickness gradually decreases from the source terminal side wall 62 toward the tip portion. As a result, the second projecting portion 63 has a sharp tip that forms an acute angle. Of course, the source terminal electrode 60 without the second projecting portion 63 may be formed.

The source terminal electrode 60 preferably has a thickness exceeding the thickness of the source electrode 32 . The thickness of source terminal electrode 60 is defined by the distance between source electrode 32 and source terminal surface 61 . It is particularly preferable that the thickness of the source terminal electrode 60 exceeds the thickness of the upper insulating film 38 . The thickness of the source terminal electrode 60 exceeds the thickness of the chip 2 in this embodiment.

Of course, the thickness of the source terminal electrode 60 may be less than the thickness of the chip 2. The thickness of the source terminal electrode 60 may be 10 μm or more and 300 μm or less. The thickness of the source terminal electrode 60 is preferably 30 μm or more. It is particularly preferable that the thickness of the source terminal electrode 60 is 80 μm or more and 200 μm or less. The thickness of the source terminal electrode 60 is approximately equal to the thickness of the gate terminal electrode 50 .

The planar area of the source terminal electrode 60 is adjusted according to the planar area of the first main surface 3 . The planar area of the source terminal electrode 60 is defined by the planar area of the source terminal surface 61 . The planar area of the source terminal electrode 60 preferably exceeds the planar area of the gate terminal electrode 50 . The plane area of the source terminal electrode 60 is preferably 50% or more of the first main surface 3 . It is particularly preferable that the plane area of the source terminal electrode 60 is 75% or more of the first main surface 3 .

When the first main surface 3 has a plane area of 1 mm square or more, the plane area of the source terminal electrode 60 is preferably 0.8 mm square or more. In this case, it is particularly preferable that the plane area of the source terminal electrode 60 is 1 mm square or more. The source terminal electrode 60 may be formed in a polygonal shape having a plane area of 1 mm×1.4 mm or more. In this form, the source terminal electrode 60 is formed in a square shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view. Of course, the source terminal electrode 60 may be formed in a polygonal shape other than a square shape, a circular shape, or an elliptical shape in plan view.

In this form, the source terminal electrode 60 has a laminated structure including a first source conductor film 67 and a second source conductor film 68 laminated in this order from the source electrode 32 side. The first source conductor film 67 may contain a Ti-based metal film. The first source conductor film 67 may have a single layer structure made of a Ti film or a TiN film. The first source conductor film 67 may have a laminated structure including a Ti film and a TiN film laminated in any order. The first source conductor film 67 is preferably made of the same conductive material as the first gate conductor film 55 .

The first source conductor film 67 has a thickness less than the thickness of the source electrode 32 . The first source conductor film 67 covers the source electrode 32 in the form of a film in the source opening 40 and is pulled out on the upper insulating film 38 in the form of a film. The first source conductor film 67 forms part of the second projecting portion 63 . The thickness of the first source conductor film 67 is approximately equal to the thickness of the first gate conductor film 55 . The first source conductor film 67 does not necessarily have to be formed and may be removed.

The second source conductor film 68 forms the main body of the source terminal electrode 60 . The second source conductor film 68 may contain a Cu-based metal film. The Cu-based metal film may be a pure Cu film (a Cu film with a purity of 99% or more) or a Cu alloy film. The second source conductor film 68 includes a pure Cu plating film in this embodiment. The second source conductor film 68 is preferably made of the same conductive material as the second gate conductor film 56 .

The second source conductor film 68 preferably has a thickness exceeding the thickness of the source electrode 32 . It is particularly preferable that the thickness of the second source conductor film 68 exceeds the thickness of the upper insulating film 38 . The thickness of the second source conductor film 68 exceeds the thickness of the chip 2 in this embodiment. The thickness of the second source conductor film 68 is approximately equal to the thickness of the second gate conductor film 56 .

The second source conductor film 68 covers the source electrode 32 in the source opening 40 with the first source conductor film 67 interposed therebetween, and is pulled out in the form of a film onto the upper insulating film 38 with the first source conductor film 67 interposed therebetween. ing. The second source conductor film 68 forms part of the second projecting portion 63 . That is, the second projecting portion 63 has a laminated structure including the first source conductor film 67 and the second source conductor film 68 . The second source conductor film 68 preferably has a thickness exceeding the thickness of the first source conductor film 67 within the second protruding portion 63 .

The semiconductor device 1A includes a sealing insulator 71 that covers the first main surface 3. The sealing insulator 71 covers the periphery of the gate terminal electrode 50 and the periphery of the source terminal electrode 60 so as to expose a portion of the gate terminal electrode 50 and a portion of the source terminal electrode 60 on the first main surface 3 . are doing. Specifically, the encapsulating insulator 71 covers the active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A to 10D so as to expose the gate terminal electrode 50 and the source terminal electrode 60. As shown in FIG.

The encapsulation insulator 71 exposes the gate terminal surface 51 and the source terminal surface 61 and covers the gate terminal sidewalls 52 and the source terminal sidewalls 62 . In this embodiment, the sealing insulator 71 covers the first projecting portion 53 of the gate terminal electrode 50 and faces the upper insulating film 38 with the first projecting portion 53 interposed therebetween. The sealing insulator 71 prevents the gate terminal electrode 50 from coming off. Also, the sealing insulator 71 covers the second projecting portion 63 of the source terminal electrode 60 and faces the upper insulating film 38 with the second projecting portion 63 interposed therebetween. The sealing insulator 71 prevents the source terminal electrode 60 from coming off.

The sealing insulator 71 covers the dicing street 41 at the periphery of the outer surface 9 . The sealing insulator 71 directly covers the interlayer insulating film 27 at the dicing street 41 in this embodiment. Of course, when the chip 2 (the outer surface 9) and the main surface insulating film 25 are exposed from the dicing street 41, the sealing insulator 71 directly covers the chip 2 and the main surface insulating film 25 on the dicing street 41. may

The sealing insulator 71 has an insulating main surface 72 and insulating side walls 73 . The insulating main surface 72 extends flat along the first main surface 3 . Insulating main surface 72 forms one flat surface with gate terminal surface 51 and source terminal surface 61 . The insulating main surface 72 may be a ground surface having grinding marks. In this case, the insulating main surface 72 preferably forms one ground surface together with the gate terminal surface 51 and the source terminal surface 61 .

The insulating side wall 73 extends from the periphery of the insulating main surface 72 toward the chip 2 and forms one flat surface together with the first to fourth side surfaces 5A to 5D. The insulating side wall 73 is formed substantially perpendicular to the insulating main surface 72 . The angle formed between insulating side wall 73 and insulating main surface 72 may be 88° or more and 92° or less. The insulating side wall 73 may consist of a ground surface with grinding marks. The insulating sidewall 73 may form one grinding surface with the first to fourth side surfaces 5A to 5D.

The encapsulating insulator 71 preferably has a thickness exceeding the thickness of the gate electrode 30 and the thickness of the source electrode 32 . It is particularly preferable that the thickness of the sealing insulator 71 exceeds the thickness of the upper insulating film 38 . The thickness of the encapsulation insulator 71 exceeds the thickness of the chip 2 in this embodiment. Of course, the thickness of the encapsulating insulator 71 may be less than the thickness of the chip 2 . The thickness of the sealing insulator 71 may be 10 μm or more and 300 μm or less. The thickness of the sealing insulator 71 is preferably 30 μm or more. It is particularly preferable that the thickness of the sealing insulator 71 is 80 μm or more and 200 μm or less. The thickness of encapsulating insulator 71 is approximately equal to the thickness of gate terminal electrode 50 and the thickness of source terminal electrode 60 .

The sealing insulator 71 contains a matrix resin, multiple fillers, and multiple flexible particles (flexible agents). The sealing insulator 71 is configured such that its mechanical strength is adjusted by the matrix resin, multiple fillers, and multiple flexible particles. The sealing insulator 71 only needs to contain a matrix resin, and the presence or absence of fillers and flexible particles is optional.

The sealing insulator 71 may contain a coloring material such as carbon black for coloring the matrix resin. The matrix resin is preferably made of a thermosetting resin. The matrix resin may contain at least one of epoxy resin, phenolic resin, and polyimide resin, which are examples of thermosetting resins. The matrix resin, in this form, contains an epoxy resin.

The plurality of fillers are composed of one or both of spherical objects made of insulators and amorphous objects made of insulators, and are added to the matrix resin. Amorphous objects have random shapes other than spheres, such as grains, fragments, and crushed pieces. The amorphous object may have corners. In this embodiment, the plurality of fillers are each composed of a spherical object from the viewpoint of suppressing damage due to filler attack.

The plurality of fillers may contain at least one of ceramics, oxides and nitrides. The plurality of fillers, in this form, are each composed of silicon oxide particles (silica particles). A plurality of fillers may each have a particle size of 1 nm or more and 100 μm or less. The particle size of the plurality of fillers is preferably 50 μm or less.

The sealing insulator 71 preferably contains a plurality of fillers with different particle sizes. The plurality of fillers may include a plurality of small-diameter fillers, a plurality of medium-diameter fillers, and a plurality of large-diameter fillers. The plurality of fillers are preferably added to the matrix resin at a content rate (density) in the order of small-diameter filler, medium-diameter filler, and large-diameter filler.

The small-diameter filler may have a thickness less than the thickness of the source electrode 32 (the thickness of the gate electrode 30). The particle size of the small-diameter filler may be 1 nm or more and 1 μm or less. The medium-diameter filler may have a thickness exceeding the thickness of the source electrode 32 and equal to or less than the thickness of the upper insulating film 38 . The particle diameter of the medium-diameter filler may be 1 μm or more and 20 μm or less.

The large-diameter filler may have a thickness exceeding the thickness of the upper insulating film 38 . The plurality of fillers includes at least one large diameter filler that exceeds any one of the thickness of the first semiconductor region 6 (epitaxial layer), the thickness of the second semiconductor region 7 (substrate) and the thickness of the chip 2. good too. The particle size of the large-diameter filler may be 20 μm or more and 100 μm or less. The particle size of the large-diameter filler is preferably 50 μm or less.

The average particle size of the plurality of fillers may be 1 μm or more and 10 μm or less. The average particle size of the plurality of fillers is preferably 4 μm or more and 8 μm or less. Of course, the plurality of fillers need not contain all of the small-diameter fillers, medium-diameter fillers and large-diameter fillers at the same time, and may be composed of either one or both of the small-diameter fillers and the medium-diameter fillers. For example, in this case, the maximum particle size of the plurality of fillers (medium-sized fillers) may be 10 μm or less.

The encapsulation insulator 71 may include a plurality of filler fragments having broken particle shapes at the surface of the insulating main surface 72 and the surface of the insulating sidewalls 73 . . The plurality of filler pieces may each be formed of a portion of the small-diameter filler, a portion of the medium-diameter filler, and a portion of the large-diameter filler.

The plurality of filler pieces located on the insulating main surface 72 side have broken portions formed along the insulating main surface 72 so as to face the insulating main surface 72 . A plurality of filler pieces located on the side of the insulating sidewall 73 have broken portions formed along the insulating sidewall 73 so as to face the insulating sidewall 73 . The broken portions of the plurality of filler pieces may be exposed from the insulating main surface 72 and the insulating sidewalls 73, or may be partially or wholly covered with the matrix resin. Since the plurality of filler pieces are located on the surface layers of the insulating main surface 72 and the insulating side walls 73, they do not affect the structures on the chip 2 side.

A plurality of flexible particles are added to the matrix resin. The plurality of flexible particles may include at least one of silicon-based flexible particles, acrylic-based flexible particles, and butadiene-based flexible particles. The encapsulating insulator 71 preferably contains silicon-based flexing particles. Preferably, the plurality of flexing particles have an average particle size less than the average particle size of the plurality of fillers. The average particle size of the plurality of flexible particles is preferably 1 nm or more and 1 μm or less. The maximum particle size of the plurality of flexible particles is preferably 1 μm or less.

In this form, the plurality of flexible particles are added to the matrix resin so that the ratio of the total cross-sectional area per unit cross-sectional area is 0.1% or more and 10% or less. In other words, the plurality of flexible particles are added to the matrix resin at a content in the range of 0.1% by weight to 10% by weight. The average particle size and content of the plurality of flexible particles are appropriately adjusted according to the elastic modulus to be imparted to the sealing insulator 71 during and/or after manufacturing. For example, a plurality of flexible particles having an average particle size of submicron order (=1 μm or less) can contribute to the low elastic modulus and low cure shrinkage of the sealing insulator 71 .

The semiconductor device 1A includes a drain electrode 77 (second main surface electrode) that covers the second main surface 4 . Drain electrode 77 is electrically connected to second main surface 4 . Drain electrode 77 forms ohmic contact with second semiconductor region 7 exposed from second main surface 4 . The drain electrode 77 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).

The drain electrode 77 may cover the second main surface 4 with a space inward from the periphery of the chip 2 . The drain electrode 77 is configured such that a drain-source voltage of 500 V or more and 3000 V or less is applied between the drain electrode 77 and the source terminal electrode 60 . That is, the chip 2 is formed so that a voltage of 500 V or more and 3000 V or less is applied between the first principal surface 3 and the second principal surface 4 .

As described above, the semiconductor device 1A includes the chip 2, the gate electrode 30 (source electrode 32: main surface electrode), the gate terminal electrode 50 (source terminal electrode 60), and the sealing insulator 71. Chip 2 has a first main surface 3 . Gate electrode 30 (source electrode 32 ) is arranged on first main surface 3 . The gate terminal electrode 50 (source terminal electrode 60) is arranged on the gate electrode 30 (source electrode 32). The sealing insulator 71 covers the periphery of the gate terminal electrode 50 (source terminal electrode 60) on the first main surface 3 so as to partially expose the gate terminal electrode 50 (source terminal electrode 60). .

According to this structure, the sealing insulator 71 can protect the object to be sealed from external forces and moisture (moisture). In other words, the object to be sealed can be protected from damage (including peeling) caused by external force and deterioration (including corrosion) caused by humidity. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1A with improved reliability.

The semiconductor device 1A preferably includes an upper insulating film 38 that partially covers the gate electrode 30 (source electrode 32). According to this structure, the object to be covered can be protected from external force and moisture by the upper insulating film 38 . In other words, according to this structure, the object to be sealed can be protected by both the upper insulating film 38 and the sealing insulator 71 .

In such a structure, the sealing insulator 71 preferably has a portion that directly covers the upper insulating film 38 . The sealing insulator 71 preferably has a portion covering the gate electrode 30 (source electrode 32) with the upper insulating film 38 interposed therebetween. The gate terminal electrode 50 (source terminal electrode 60 ) preferably has a portion directly covering the upper insulating film 38 . The upper insulating film 38 preferably includes one or both of the inorganic insulating film 42 and the organic insulating film 43 . The organic insulating film 43 is preferably made of a photosensitive resin film.

The upper insulating film 38 is preferably thicker than the gate electrode 30 (source electrode 32). Upper insulating film 38 is preferably thinner than chip 2 . The encapsulating insulator 71 is preferably thicker than the gate electrode 30 (source electrode 32). The sealing insulator 71 is preferably thicker than the upper insulating film 38 . It is particularly preferred that the encapsulating insulator 71 is thicker than the chip 2 .

The sealing insulator 71 preferably contains a thermosetting resin (matrix resin). Encapsulating insulator 71 preferably includes a plurality of fillers added to a thermosetting resin. According to this structure, the strength of the sealing insulator 71 can be adjusted with a plurality of fillers. The encapsulating insulator 71 preferably includes a plurality of flexibilizing particles (flexibilizers) added to a thermosetting resin. This structure allows the elastic modulus of the sealing insulator 71 to be adjusted by the plurality of flexing particles.

The sealing insulator 71 preferably exposes the gate terminal surface 51 (source terminal surface 61) of the gate terminal electrode 50 (source terminal electrode 60) and covers the gate terminal sidewall 52 (source terminal sidewall 62). . That is, the sealing insulator 71 preferably protects the gate terminal electrode 50 (source terminal electrode 60) from the side of the gate terminal sidewall 52 (source terminal sidewall 62).

In this case, the sealing insulator 71 preferably has an insulating main surface 72 forming one flat surface with the gate terminal surface 51 (source terminal surface 61). The encapsulating insulator 71 preferably has insulating sidewalls 73 forming one flat surface with the first to fourth side surfaces 5A to 5D (side surfaces) of the chip 2 . According to this structure, the object to be sealed located on the first main surface 3 side can be appropriately protected by the sealing insulator 71 .

The above configuration provides a gate terminal electrode 50 (source terminal electrode 60) having a relatively large plane area and/or a relatively large thickness for a chip 2 having a relatively large plane area and/or a relatively small thickness. is effective when applying The gate terminal electrode 50 (source terminal electrode 60) having a relatively large plane area and/or a relatively large thickness is also effective in absorbing heat generated on the chip 2 side and dissipating it to the outside.

For example, the gate terminal electrode 50 (source terminal electrode 60) is preferably thicker than the gate electrode 30 (source electrode 32). The gate terminal electrode 50 (source terminal electrode 60 ) is preferably thicker than the upper insulating film 38 . It is particularly preferable that the gate terminal electrode 50 (source terminal electrode 60 ) be thicker than the chip 2 . For example, the gate terminal electrode 50 may cover 25% or less of the first main surface 3 in plan view, and the source terminal electrode 60 may cover 50% or more of the first main surface 3 in plan view. good.

For example, the chip 2 may have a first main surface 3 having an area of 1 mm square or more in plan view. The chip 2 may have a thickness of 100 μm or less when viewed in cross section. The chip 2 preferably has a thickness of 50 μm or less when viewed in cross section. Chip 2 may have a laminated structure including a semiconductor substrate and an epitaxial layer. In this case, the epitaxial layer is preferably thicker than the semiconductor substrate.

In the above configuration, the chip 2 preferably contains a wide bandgap semiconductor single crystal. Single crystals of wide bandgap semiconductors are effective in improving electrical characteristics. Moreover, according to the single crystal of the wide bandgap semiconductor, it is possible to reduce the thickness of the tip 2 and increase the planar area of the tip 2 while suppressing deformation of the tip 2 due to its relatively high hardness. Thinning the chip 2 and expanding the planar area of the chip 2 are also effective in improving electrical characteristics.

The structure having the sealing insulator 71 is also effective in the structure including the drain electrode 77 covering the second main surface 4 of the chip 2 . Drain electrode 77 forms a potential difference (for example, 500 V or more and 3000 V or less) across chip 2 with source electrode 32 . In the case of a relatively thin chip 2, the distance between the source electrode 32 and the drain electrode 77 is reduced, increasing the risk of discharge phenomena between the rim of the first main surface 3 and the source electrode 32. FIG. In this regard, the structure having the sealing insulator 71 can improve the insulation between the peripheral edge of the first main surface 3 and the source electrode 32 and suppress the discharge phenomenon.

FIG. 8 is a plan view showing a wafer structure 80 used when manufacturing the semiconductor device 1A shown in FIG. FIG. 9 is a cross-sectional view showing device region 86 shown in FIG. 8 and 9, wafer structure 80 includes wafer 81 formed in a disk shape. Wafer 81 serves as the base of chip 2 . The wafer 81 has a first wafer main surface 82 on one side, a second wafer main surface 83 on the other side, and a wafer side surface 84 connecting the first wafer main surface 82 and the second wafer main surface 83 . .

The wafer 81 has marks 85 indicating the crystal orientation of the SiC single crystal on the wafer side surface 84 . In this form, the mark 85 includes an orientation flat cut linearly in plan view. The orientation flat extends in the second direction Y in this configuration. The orientation flat does not necessarily have to extend in the second direction Y and may extend in the first direction X as well.

Of course, the mark 85 may include a first orientation flat extending in the first direction X and a first orientation flat extending in the second direction Y. Also, the mark 85 may have an orientation notch cut toward the central portion of the wafer 81 instead of the orientation flat. The orientation notch may be a cut-out portion cut in a polygonal shape such as a triangular shape or a square shape in a plan view.

The wafer 81 may have a diameter of 50 mm or more and 300 mm or less (that is, 2 inches or more and 12 inches or less) in plan view. The diameter of wafer structure 80 is defined by the length of a chord passing through the center of wafer structure 80 outside of mark 85 . Wafer structure 80 may have a thickness between 100 μm and 1100 μm.

The wafer structure 80 includes a first semiconductor region 6 formed in a region on the first wafer main surface 82 side inside a wafer 81 and a second semiconductor region 7 formed in a region on the second wafer main surface 83 side. include. The first semiconductor region 6 is formed by an epitaxial layer and the second semiconductor region 7 is formed by a semiconductor substrate. That is, the first semiconductor region 6 is formed by epitaxially growing a semiconductor single crystal from the second semiconductor region 7 by an epitaxial growth method. The second semiconductor region 7 preferably has a thickness exceeding the thickness of the first semiconductor region 6 .

The wafer structure 80 includes a plurality of device regions 86 and a plurality of scheduled cutting lines 87 provided on the first wafer main surface 82 . A plurality of device regions 86 are regions respectively corresponding to the semiconductor devices 1A. The plurality of device regions 86 are each set to have a rectangular shape in plan view. In this form, the plurality of device regions 86 are arranged in a matrix along the first direction X and the second direction Y in plan view.

The plurality of planned cutting lines 87 are lines (regions extending in a belt shape) that define locations to be the first to fourth side surfaces 5A to 5D of the chip 2 . The plurality of planned cutting lines 87 are set in a grid pattern extending along the first direction X and the second direction Y so as to partition the plurality of device regions 86 . The plurality of planned cutting lines 87 may be defined by, for example, alignment marks or the like provided inside and/or outside the wafer 81 .

In this embodiment, the wafer structure 80 includes a mesa portion 11 formed in a plurality of device regions 86, a MISFET structure 12, an outer contact region 19, an outer well region 20, a field region 21, a main surface insulating film 25, and sidewall structures. 26, an interlayer insulating film 27, a gate electrode 30, a source electrode 32, a plurality of gate wirings 36A, 36B and a source wiring 37. FIG.

10A to 10N are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1A shown in FIG. Descriptions of specific features of each structure formed in each process shown in FIGS. 10A to 10N are omitted or simplified since they are as described above.

Referring to FIG. 10A, a wafer structure 80 is prepared (see FIGS. 8 and 9). Next, an inorganic insulating film 42 is formed on the first wafer major surface 82 . The inorganic insulating film 42 covers the interlayer insulating film 27 , the gate electrode 30 , the source electrode 32 , the plurality of gate wirings 36A and 36B and the source wiring 37 . The inorganic insulating film 42 may be formed by a CVD (Chemical Vapor Deposition) method.

Next, referring to FIG. 10B, a resist mask 96 having a predetermined pattern is formed on the inorganic insulating film 42. Then, as shown in FIG. The resist mask 96 exposes the regions where the gate opening 39, the source opening 40 and the dicing street 41 are to be formed in the inorganic insulating film 42 and covers the other regions.

Next, unnecessary portions of the inorganic insulating film 42 are removed by etching through the resist mask 96 . The etching method may be a wet etching method and/or a dry etching method. As a result, an inorganic insulating film 42 that partitions the gate opening 39, the source opening 40 and the dicing streets 41 is formed. After that, the resist mask 96 is removed.

Next, referring to FIG. 10C, organic insulating film 43 is formed on inorganic insulating film 42 . In this step, first, a photosensitive resin is applied onto the inorganic insulating film 42 . The photosensitive resin is then exposed and developed with a pattern corresponding to gate openings 39 , source openings 40 and dicing streets 41 . As a result, the upper insulating film 38 is formed together with the inorganic insulating film 42, and the organic insulating film 43 that partitions the gate opening 39, the source opening 40 and the dicing street 41 is formed.

The dicing street 41 crosses the planned cutting line 87 and straddles a plurality of device regions 86 so as to expose the planned cutting line 87 . The dicing streets 41 are formed in a lattice shape extending along a plurality of planned cutting lines 87 . The dicing street 41 exposes the interlayer insulating film 27 in this form. The resist mask 96 described above may be the organic insulating film 43 . That is, the unnecessary portion of the inorganic insulating film 42 may be removed by etching through the organic insulating film 43 .

Next, referring to FIG. 10D, the wafer structure is formed such that a first base conductor film 88 serving as the base of the first gate conductor film 55 and the first source conductor film 67 covers the device region 86 and the lines to be cut 87 . formed on 80; The first base conductor film 88 is formed in a film shape along the interlayer insulating film 27 , the gate electrode 30 , the source electrode 32 , the plurality of gate wirings 36A and 36B, the source wiring 37 and the upper insulating film 38 . The first base conductor film 88 includes a Ti-based metal film. The first base conductor film 88 may be formed by sputtering and/or vapor deposition.

Next, a second base conductor film 89 serving as the base of the second gate conductor film 56 and the second source conductor film 68 is formed on the first base conductor film 88 so as to cover the device region 86 and the line to be cut 87 . It is formed. The second base conductor film 89 consists of the interlayer insulating film 27, the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A and 36B, the source wiring 37, and the upper insulating film 38 with the first base conductor film 88 interposed therebetween. cover. The second base conductor film 89 contains a Cu-based metal film. The second base conductor film 89 may be formed by sputtering and/or vapor deposition.

Next, referring to FIG. 10E, a resist mask 90 (open mask) having a predetermined pattern is formed on the second base conductor film 89. Then, referring to FIG. The resist mask 90 includes a first opening 91 exposing the gate electrode 30, a second opening 92 exposing the source electrode 32, and a third opening 93 exposing the line 87 to be cut. In FIG. 10E, half regions of the third opening 93 are illustrated on both sides of the paper surface (the same applies hereinafter). The first opening 91 exposes the region where the gate terminal electrode 50 is to be formed in the region above the gate electrode 30 . The second opening 92 exposes the region where the source terminal electrode 60 is to be formed in the region above the source electrode 32 .

A third opening 93 is formed in a region above the dicing street 41 with a space from the upper insulating film 38 . The third opening 93 extends across a plurality of device regions 86 across the line to cut 87 so as to expose the line to cut 87 . The third opening 93 exposes the interlayer insulating film 27 in this embodiment. The third openings 93 are formed in a lattice shape extending along the plurality of scheduled cutting lines 87 in plan view, and surround the device region 86 .

This step includes a step of reducing the adhesion of the resist mask 90 to the second base conductor film 89 . The adhesion of the resist mask 90 is adjusted by adjusting exposure conditions for the resist mask 90 and post-exposure baking conditions (baking temperature, time, etc.). As a result, the growth starting point of the first protrusion 53 is formed at the lower end of the first opening 91 , and the growth starting point of the second protrusion 63 is formed at the lower end of the second opening 92 . In this form, a similar growth starting point is also formed at the lower end of the third opening 93 .

Next, referring to FIG. 10F, a third base conductor film 95 serving as the base of the second gate conductor film 56 and the second source conductor film 68 is formed on the second base conductor film 89 . In this embodiment, the third base conductor film 95 is formed by depositing a conductor (Cu-based metal in this embodiment) in the first opening 91 and the second opening 92 by plating (eg, electroplating). . The third base conductor film 95 is integrated with the second base conductor film 89 inside the first opening 91 and the second opening 92 . Thereby, the gate terminal electrode 50 covering the gate electrode 30 is formed. A source terminal electrode 60 covering the source electrode 32 is also formed.

In this step, the third base conductor film 95 (conductor) is also deposited inside the third opening 93 . The third base conductor film 95 is integrated with the second base conductor film 89 inside the third opening 93 . Thereby, a dummy terminal electrode 97 (dummy electrode) covering the line to be cut 87 is formed. In FIG. 10F, half areas of the dummy terminal electrodes 97 are illustrated in the areas on both sides of the paper surface (the same applies hereinafter). The dummy terminal electrode 97 is formed spaced apart from the gate terminal electrode 50 and the source terminal electrode 60 on the line to be cut 87 side.

Specifically, the dummy terminal electrode 97 is formed spaced apart from the gate electrode 30 and the source electrode 32 on the line to be cut 87 side. More specifically, the dummy terminal electrode 97 is formed in the dicing street 41 at a distance from the upper insulating film 38 toward the line to be cut 87 . The dummy terminal electrode 97 crosses the line to be cut 87 and straddles a plurality of device regions 86 . The dummy terminal electrode 97 is formed in a ring shape that collectively surrounds the gate terminal electrode 50 and the source terminal electrode 60 in plan view. In this form, the dummy terminal electrodes 97 are formed in a lattice shape extending along the plurality of planned cutting lines 87 in plan view, and surround the plurality of device regions 86 .

This step includes a step of allowing the plating solution to enter between the second base conductor film 89 and the resist mask 90 at the lower end of the first opening 91 . This step also includes a step of allowing the plating solution to enter between the second base conductor film 89 and the resist mask 90 at the lower end of the second opening 92 . This step also includes a step of allowing the plating solution to enter between the second base conductor film 89 and the resist mask 90 at the lower end of the third opening 93 .

As a result, a portion of the third base conductor film 95 (the gate terminal electrode 50) grows like a protrusion at the lower end of the first opening 91, forming the first protrusion 53. As shown in FIG. A portion of the third base conductor film 95 (the source terminal electrode 60 ) is grown in a projection shape at the lower end of the second opening 92 to form a second projection 63 . Also, a portion of the third base conductor film 95 (dummy terminal electrode 97) is grown in a projecting shape at the lower end of the third opening 93 to form a dummy projecting portion 97a.

Next, referring to FIG. 10G, resist mask 90 is removed. Thereby, the gate terminal electrode 50, the source terminal electrode 60 and the dummy terminal electrode 97 are exposed to the outside.

Next, referring to FIG. 10H, portions of the second base conductor film 89 exposed from the gate terminal electrode 50, the source terminal electrode 60 and the dummy terminal electrode 97 are removed. An unnecessary portion of the second base conductor film 89 may be removed by an etching method. The etching method may be a wet etching method and/or a dry etching method. Next, portions of the first base conductor film 88 exposed from the gate terminal electrode 50, the source terminal electrode 60 and the dummy terminal electrode 97 are removed. An unnecessary portion of the first base conductor film 88 may be removed by an etching method. The etching method may be a wet etching method and/or a dry etching method.

Next, referring to FIG. 10I, a sealant 94 is supplied onto the first wafer main surface 82 so as to cover the gate terminal electrode 50 , the source terminal electrode 60 and the dummy terminal electrode 97 . Encapsulant 94 provides the base for encapsulation insulator 71 . The sealant 94 fills the periphery of the gate terminal electrode 50, the periphery of the source terminal electrode 60, and the periphery of the dummy terminal electrode 97, and covers the entire area of the upper insulating film 38, the entire area of the gate terminal electrode 50, and the entire area of the source terminal electrode 60. and the entire area of the dummy terminal electrode 97 . The encapsulant 94, in this form, includes a thermosetting resin, a plurality of fillers and a plurality of flexible particles (flexibilizers) and is cured by heating. Thereby, a sealing insulator 71 is formed. Sealing insulator 71 has an insulating main surface 72 covering gate terminal electrode 50 , source terminal electrode 60 and dummy terminal electrode 97 .

Next, referring to FIG. 10J, the sealing insulator 71 is partially removed. In this embodiment, the sealing insulator 71 is ground from the insulating main surface 72 side by a grinding method. The grinding method may be a mechanical polishing method or a chemical mechanical polishing method. The insulating main surface 72 is ground until the gate terminal electrode 50, the source terminal electrode 60 and the dummy terminal electrode 97 are exposed. This step includes grinding the gate terminal electrode 50 , the source terminal electrode 60 and the dummy terminal electrode 97 .

As a result, the insulating main surface 72 forming one ground surface between the gate terminal electrode 50 (gate terminal surface 51), the source terminal electrode 60 (source terminal surface 61) and the dummy terminal electrode 97 is formed. The volume of the sealing insulator 71 remaining on the first wafer main surface 82 after the step of removing the sealing insulator 71 is reduced by the dummy terminal electrode 97 . That is, the dummy terminal electrode 97 can reduce the volume of the sealing insulator 71 that covers the first wafer main surface 82 .

The sealing insulator 71 may be formed in a semi-cured state (not completely cured) by adjusting the heating conditions in the process of FIG. 10I described above. In this case, the sealing insulator 71 is ground again in the process of FIG. 10J and then heated again to be fully cured (completely cured). In this case, the sealing insulator 71 can be easily removed.

Next, referring to FIG. 10K, a resist mask 98 (shielding mask) having a predetermined pattern is formed over the encapsulation insulator 71 . A resist mask 98 covers the gate terminal electrode 50 and the source terminal electrode 60 and exposes the dummy terminal electrode 97 . Next, the dummy terminal electrode 97 is removed by an etching method through a resist mask 98. Next, as shown in FIG. The etching method may be a wet etching method and/or a dry etching method.

As a result, the dummy terminal electrode 97 is removed so that the gate terminal electrode 50 and the source terminal electrode 60 remain, and a dicing opening 99 extending along the planned cutting line 87 is defined in the sealing insulator 71 . In FIG. 10K, a half area of the dicing opening 99 is illustrated (same below). The dicing opening 99 has a cross-sectional shape and a planar shape that match the cross-sectional shape and planar shape of the dummy terminal electrode 97 .

The dicing opening 99 exposes the interlayer insulating film 27 in this form. The dicing openings 99 partition the encapsulation insulator 71 at positions spaced apart from the plurality of planned cutting lines 87 in each of the plurality of device regions 86 . That is, the plurality of sealing insulators 71 are intermittently formed along the first wafer main surface 82 through the dicing openings 99 and do not continuously cover the first wafer main surface 82 .

The dicing opening 99 has a recessed portion 99a recessed toward the inner portion of the device region 86 at the lower end of the wall surface. The recessed portion 99 a is defined by the removed portion of the dummy projecting portion 97 a of the dummy terminal electrode 97 . The recessed portion 99a extends along the first wafer main surface 82 (interlayer insulating film 27), and is formed in a tapered shape in which the width of the recess gradually decreases from the wall surface of the dicing opening 99 toward the tip when viewed in cross section. .

Accordingly, the recessed portion 99a has a sharp tip end forming an acute angle. Resist mask 98 is then removed. Of course, the gate terminal electrode 50 without the first protrusion 53, the source terminal electrode 60 without the second protrusion 63, and the dummy terminal electrode 97 without the dummy protrusion 97a may be formed. . In this case, a dicing opening 99 having no recess portion 99a is formed.

Next, referring to FIG. 10L, the wafer 81 is partially removed from the second wafer main surface 83 side and thinned to a desired thickness. The thinning process of the wafer 81 may be performed by an etching method or a grinding method. The etching method may be a wet etching method or a dry etching method. The grinding method may be a mechanical polishing method or a chemical mechanical polishing method.

This process includes thinning the wafer 81 using the sealing insulator 71 as a support member for supporting the wafer 81 . Thereby, the wafer 81 can be handled appropriately. Moreover, since the deformation of the wafer 81 (warping due to thinning) can be suppressed by the sealing insulator 71, the wafer 81 can be thinned appropriately.

As an example, if the thickness of wafer 81 is less than the thickness of encapsulation insulator 71, wafer 81 is further thinned. As another example, if the thickness of wafer 81 is greater than or equal to the thickness of encapsulation insulator 71 , wafer 81 is thinned to a thickness less than the thickness of encapsulation insulator 71 . In these cases, the wafer 81 is preferably thinned until the thickness of the second semiconductor region 7 (semiconductor substrate) is less than the thickness of the first semiconductor region 6 (epitaxial layer).

Of course, the thickness of the second semiconductor region 7 (semiconductor substrate) may be greater than or equal to the thickness of the first semiconductor region 6 (epitaxial layer). Also, the wafer 81 may be thinned until the first semiconductor region 6 is exposed from the second wafer main surface 83 . That is, the entire second semiconductor region 7 may be removed.

The wafer 81 thinning process (FIG. 10L) can be performed at any timing after the sealing insulator 71 forming process. For example, the step of thinning the wafer 81 (FIG. 10L) may be performed before the step of removing the dummy terminal electrodes 97 (FIG. 10K).

Next, referring to FIG. 10M, a drain electrode 77 covering the second wafer main surface 83 is formed. The drain electrode 77 may be formed by sputtering and/or vapor deposition.

Next, referring to FIG. 10N, the wafer structure 80 (wafer 81) is cut along the dicing openings 99. Specifically, the wafer structure 80 is cut along the planned cutting lines 87 using the dicing openings 99 as marks. This step includes cutting the wafer 81 with a dicing blade BL. The wafer 81 may be cut from the first wafer main surface 82 side toward the second wafer main surface 83 side so as to pass through the dicing opening 99 . Of course, the wafer 81 may be cut from the second wafer main surface 83 side toward the first wafer main surface 82 side so as to pass through the dicing opening 99 .

In this step, the portion of the sealing insulator 71 that defines the wall surface of the dicing opening 99 is removed at the same time as the wafer 81 is cut. As a result, a sealing insulator 71 that continues to the cut portion of the wafer 81 is formed. That is, a sealing insulator 71 is formed having insulating sidewalls 73 forming one ground surface with the first to fourth side surfaces 5A to 5D of the chip 2 . The encapsulating insulator 71 may be removed such that all of the recessed portion 99a of the dicing opening 99 disappears.

Of course, the sealing insulator 71 may be removed so that at least part of the recessed portion 99a remains. In this case, a sealing insulator 71 having a recess 99a at the lower end of the insulating sidewall 73 is formed. A plurality of semiconductor devices 1A are manufactured from one wafer structure 80 through the steps including the above.

As described above, the method of manufacturing the semiconductor device 1A includes the steps of preparing the wafer 81, forming the dummy terminal electrode 97 (dummy electrode) (electrode forming step), forming the sealing insulator 71, removing the dummy terminal electrode 97, and A wafer 81 cutting process is included. In the step of preparing the wafer 81, the wafer 81 is prepared which has a first wafer main surface 82 (main surface) on which a device region 86 and cutting lines 87 defining the device region 86 are set. In the electrode forming step, dummy terminal electrodes 97 are formed on the lines 87 to be cut.

In the step of forming the sealing insulator 71 , the sealing insulator 71 covering the periphery of the dummy terminal electrode 97 is formed on the first wafer main surface 82 so as to partially expose the dummy terminal electrode 97 . In the step of removing the dummy terminal electrodes 97 , the dummy terminal electrodes 97 are removed and dicing openings 99 extending along the planned cutting lines 87 are formed in the sealing insulator 71 . In the step of cutting the wafer 81 , the wafer 81 is cut along the dicing openings 99 .

According to this manufacturing method, the volume of the sealing insulator 71 covering the first wafer main surface 82 is reduced by the dummy terminal electrode 97, and the stress caused by the sealing insulator 71 is reduced. The dicing openings 99 are also effective in interrupting the continuous stress along the first wafer main surface 82 due to the encapsulation insulator 71 . As a result, fluctuations in the electrical characteristics of the wafer 81 and defective shapes (for example, warpage of the wafer 81) caused by the stress of the sealing insulator 71 can be suppressed.

Also, according to this manufacturing method, the amount of removal of the sealing insulator 71 during cutting can be reduced by the dicing openings 99 . Thereby, the cutting process of the wafer 81 can be performed smoothly. Therefore, the manufacturing efficiency of the semiconductor device 1A can be improved. In addition, according to this manufacturing method, the sealing insulator 71 can protect the object to be sealed from external forces and moisture. In other words, the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. Therefore, it is possible to manufacture a highly reliable semiconductor device 1A in which variations in electrical characteristics and shape defects are suppressed.

The manufacturing method described above is preferably applied to a relatively thick sealing insulator 71 . Also, the manufacturing method described above is preferably applied to a wafer 81 having a relatively large planar area and/or a relatively small thickness. For example, the method of manufacturing the semiconductor device 1A may include a step of thinning the wafer 81 after the step of forming the sealing insulator 71 and before the step of cutting the wafer 81 . According to this manufacturing method, since the stress caused by the sealing insulator 71 is reduced, it is possible to suppress variations in electrical characteristics and shape defects of the thinned wafer 81 .

In this case, the step of thinning the wafer 81 may include thinning the wafer 81 to a thickness less than the thickness of the sealing insulator 71 . According to this manufacturing method, since the stress caused by the sealing insulator 71 is reduced, fluctuations in electrical characteristics and shape defects of the wafer 81 having a thickness less than the thickness of the sealing insulator 71 can be suppressed. .

The step of preparing the wafer 81 preferably includes a step of preparing the wafer 81 having the first wafer main surface 82 on which the planned cutting line 87 surrounding the device region 86 in plan view is set. In this case, the electrode forming step preferably includes a step of forming a dummy terminal electrode 97 covering the line to be cut 87 so as to surround the inner part of the device region 86 in plan view.

Also, the step of removing the dummy terminal electrode 97 preferably includes a step of forming a dicing opening 99 surrounding the device region 86 . According to this manufacturing method, the stress in the sealing insulator 71 along the circumferential direction of the device region 86 can be reduced. Therefore, fluctuations in electrical characteristics and shape defects in the device region 86 can be suppressed.

The electrode forming step includes a step of forming a second base conductor film 89 (conductor film) covering the line to be cut 87, and a third opening 93 exposing a portion of the second base conductor film 89 covering the line to be cut 87. on the first wafer main surface 82, depositing a conductor by plating on the portion of the second base conductor film 89 exposed from the third opening 93, and A step of removing the resist mask 98 may be included after the conductor deposition step.

The step of forming the sealing insulator 71 includes a step of forming the sealing insulator 71 covering the dummy terminal electrode 97 and a step of partially removing the sealing insulator 71 until the dummy terminal electrode 97 is exposed. may contain. The step of removing the sealing insulator 71 may include a step of partially removing the sealing insulator 71 by a grinding method. The step of removing the sealing insulator 71 may include a step of partially removing the dummy terminal electrode 97 by a grinding method.

The method of manufacturing the semiconductor device 1A may include a step of preparing a wafer structure 80 having a wafer 81 and a gate electrode 30 (source electrode 32) arranged on the device region 86 of the wafer 81. In this case, the electrode forming step includes a step of forming the gate terminal electrode 50 (source terminal electrode 60) on the gate electrode 30 (source electrode 32) and forming the dummy terminal electrode 97 on the line to be cut 87. You can stay.

In addition, in the step of forming the sealing insulator 71, the gate terminal electrode 50 (source terminal electrode 60) is formed on the main surface 82 of the first wafer so as to partially expose the gate terminal electrode 50 (source terminal electrode 60). A step of forming a sealing insulator 71 covering the periphery may be included. Further, the step of removing the dummy terminal electrode 97 may include a step of removing the dummy terminal electrode 97 so as to leave the gate terminal electrode 50 (source terminal electrode 60).

The step of preparing the wafer structure 80 may include a step of preparing the wafer structure 80 having the gate electrode 30 (source electrode 32) arranged above the device region 86 with a gap from the planned cutting line 87. In this case, the electrode forming step may include a step of forming the dummy terminal electrode 97 spaced apart from the gate electrode 30 (source electrode 32).

The electrode forming step may include a step of forming a dummy terminal electrode 97 surrounding the gate terminal electrode 50 (source terminal electrode 60). The step of removing the dummy terminal electrode 97 includes a step of exposing the dummy terminal electrode 97 and forming a resist mask 98 (shielding mask) covering the gate terminal electrode 50 (source terminal electrode 60), and etching through the resist mask 98. A step of removing the dummy terminal electrode 97 by a method may be included.

The method of manufacturing the semiconductor device 1A may include a step of forming the upper insulating film 38 covering the gate electrode 30 (source electrode 32) before the electrode forming step. In this case, the electrode forming step may include a step of forming a dummy terminal electrode 97 on the line to be cut 87 with a gap from the upper insulating film 38 .

The step of forming the sealing insulator 71 may include a step of forming the sealing insulator 71 having a portion covering the gate electrode 30 (source electrode 32) with the upper insulating film 38 interposed therebetween. The electrode forming step may include a step of forming the gate terminal electrode 50 (source terminal electrode 60) having a portion covering the gate electrode 30 (source electrode 32) with the upper insulating film 38 interposed therebetween. The step of forming the upper insulating film 38 may include a step of forming the upper insulating film 38 including at least one of the inorganic insulating film 42 and the organic insulating film 43 .

As long as the wafer 81 is cut along the scheduled cutting line 87, the cutting position of the wafer 81 is arbitrary. For example, the step of cutting wafer 81 may include removing portions of encapsulation insulator 71 that define the walls of dicing openings 99 simultaneously with cutting wafer 81 .

FIG. 11 is a cross-sectional view showing a semiconductor device 1B according to the second embodiment. Referring to FIG. 11, semiconductor device 1B has a modified form of semiconductor device 1A. Specifically, the semiconductor device 1B includes a sealing insulator 71 extending from the peripheral edge of the insulating main surface 72 toward the chip 2 and having insulating sidewalls 73 located inside the peripheral edge of the first main surface 3 . .

That is, the insulating sidewall 73 is spaced inwardly from the peripheral edge of the chip 2 so as to define a stepped portion with the first main surface 3 . The insulating sidewall 73 exposes the interlayer insulating film 27 in this form. Of course, when main surface insulating film 25 and interlayer insulating film 27 expose outer surface 9 , insulating side wall 73 may expose outer surface 9 . The insulating side wall 73 preferably has a smooth surface without grinding marks.

The encapsulating insulator 71 may have a recessed portion 99a recessed toward the inner portion of the first main surface 3 (that is, the active surface 8 side) at the lower end portion of the insulating side wall 73 . The recessed portion 99a extends along the first main surface 3 and may be formed in a tapered shape in which the width of the recess gradually decreases from the insulating side wall 73 toward the distal end in a cross-sectional view. As a result, the recessed portion 99a may have a sharp tip that forms an acute angle. Of course, the sealing insulator 71 may be formed without the recessed portion 99a.

As described above, the semiconductor device 1B includes the chip 2, the gate electrode 30 (source electrode 32: main surface electrode), the gate terminal electrode 50 (source terminal electrode 60), and the sealing insulator 71. Chip 2 has a first main surface 3 and first to fourth side surfaces 5A to 5D. The gate electrode 30 (source electrode 32) is arranged on the first main surface 3 apart from at least one (all in this embodiment) of the first to fourth side surfaces 5A to 5D. The gate terminal electrode 50 (source terminal electrode 60) is arranged on the gate electrode 30 (source electrode 32).

The sealing insulator 71 covers the periphery of the gate terminal electrode 50 (source terminal electrode 60) on the first main surface 3. The sealing insulator 71 is spaced inwardly from at least one (in this embodiment, all) of the first to fourth side surfaces 5A to 5D so as to define a stepped portion with the first main surface 3. It has insulating sidewalls 73 . According to this structure, it is possible to provide the semiconductor device 1B having the same effect as that of the semiconductor device 1A.

12A and 12B are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1B shown in FIG. Referring to FIG. 12, in the method of manufacturing semiconductor device 1B, wafer structure 80 is prepared after formation of drain electrode 77 covering second wafer main surface 83 through the steps of FIGS. 10A to 10M. . The wafer 81 is then cut along the dicing openings 99 . Specifically, the wafer 81 is cut along the planned cutting lines 87 using the dicing openings 99 as marks.

This step includes cutting the wafer 81 with a dicing blade BL. In this step, the wafer 81 is cut so as to pass through the dicing opening 99 at a position spaced apart from the wall surface of the dicing opening 99 . That is, this step does not include the step of removing the sealing insulator 71 . The wafer 81 may be cut from the first wafer main surface 82 side toward the second wafer main surface 83 side so as to pass through the dicing opening 99 . Of course, the wafer 81 may be cut from the second wafer main surface 83 side toward the first wafer main surface 82 side so as to pass through the dicing opening 99 .

As a result, the sealing insulator 71 is formed, which is located inside the device region 86 with a gap from the cut portion of the wafer 81 . That is, a sealing insulator 71 having insulating sidewalls 73 is formed at positions spaced inwardly from the first to fourth side surfaces 5A to 5D of the chip 2 . The insulating side wall 73 is formed of a smooth surface without grinding traces in this form. A plurality of semiconductor devices 1B are manufactured from one wafer structure 80 through the steps including the above. As described above, the method for manufacturing the semiconductor device 1B also produces the same effect as the method for manufacturing the semiconductor device 1A.

FIG. 13 is a cross-sectional view showing a semiconductor device 1C according to the third embodiment. Referring to FIG. 13, semiconductor device 1C has a configuration obtained by modifying semiconductor device 1A. Specifically, the semiconductor device 1</b>C has an insulating side wall 73 extending from the peripheral edge of the insulating main surface 72 toward the chip 2 in the region outside the first main surface 3 and located in the region outside the first main surface 3 . It includes a stop insulator 71 .

That is, the insulating side wall 73 protrudes outward from the periphery of the chip 2 so as to define a step portion with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The insulating side wall 73 preferably has a smooth surface without grinding marks. The sealing insulator 71 may have an inclined portion 99b at the lower end portion of the insulating side wall 73, which is inclined from the insulating side wall 73 side toward the chip 2 (first main surface 3) side. The sloped portion 99b is the remainder of the recessed portion 99a described above. Of course, the sealing insulator 71 may have a lower end extending along the first main surface 3 so as to be connected to the insulating side wall 73 at a substantially right angle without the inclined portion 99b.

As described above, the semiconductor device 1</b>C includes the chip 2 , the gate electrode 30 (source electrode 32 : main surface electrode), the gate terminal electrode 50 (source terminal electrode 60 ), and the sealing insulator 71 . Chip 2 has a first main surface 3 and first to fourth side surfaces 5A to 5D. The gate electrode 30 (source electrode 32) is arranged on the first main surface 3 apart from at least one (all in this embodiment) of the first to fourth side surfaces 5A to 5D. The gate terminal electrode 50 (source terminal electrode 60) is arranged on the gate electrode 30 (source electrode 32).

The sealing insulator 71 covers the periphery of the gate terminal electrode 50 (source terminal electrode 60) on the first main surface 3. The encapsulating insulator 71 is formed on the first to fourth side surfaces 5A to 5D so as to define a step portion with at least one (in this embodiment, all) of the first to fourth side surfaces 5A to 5D of the chip 2. It has insulating sidewalls 73 projecting outwardly from at least one (all in this embodiment) of 5D. According to this structure, it is possible to provide the semiconductor device 1C having the same effects as those of the semiconductor device 1A.

14A and 14B are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1C shown in FIG. Referring to FIG. 14, in the method of manufacturing semiconductor device 1C, wafer structure 80 is prepared after formation of drain electrode 77 covering second wafer main surface 83 through the steps of FIGS. 10A to 10M. . The wafer 81 is then cut along the dicing openings 99 . Specifically, the wafer 81 is cut along the planned cutting lines 87 using the dicing openings 99 as marks.

This step includes cutting the wafer 81 with a dicing blade BL. In this step, the wafer 81 is cut from the second wafer main surface 83 side toward the first wafer main surface 82 side so that the cut portion communicates with the dicing opening 99 . That is, in this step, unnecessary portions of the wafer 81 are removed so that portions of the sealing insulator 71 defining the wall surfaces of the dicing openings 99 are exposed. This step may include removing a portion of the encapsulation insulator 71 .

As a result, the sealing insulator 71 projecting outward from the cut portion of the wafer 81 is formed. That is, a sealing insulator 71 having insulating side walls 73 projecting outward from the first to fourth side surfaces 5A to 5D of the chip 2 is formed. The insulating side wall 73 is formed of a smooth surface without grinding traces in this form. A plurality of semiconductor devices 1C are manufactured from one wafer structure 80 through the steps including the above. As described above, the method for manufacturing the semiconductor device 1C also produces the same effect as the method for manufacturing the semiconductor device 1A.

FIG. 15 is a plan view showing a semiconductor device 1D according to the fourth embodiment. Referring to FIG. 15, a semiconductor device 1D has a modified form of semiconductor device 1A. The semiconductor device 1D specifically includes a source terminal electrode 60 having at least one (in this embodiment, a plurality of) lead terminal portions 100 . Specifically, the plurality of lead terminal portions 100 are led out above the plurality of lead electrode portions 34A and 34B of the source electrode 32 so as to face the gate terminal electrode 50 in the second direction Y, respectively. That is, the plurality of lead terminal portions 100 sandwich the gate terminal electrode 50 from both sides in the second direction Y in plan view.

As described above, the semiconductor device 1D has the same effect as the semiconductor device 1A. Also, the semiconductor device 1D is manufactured through a manufacturing method similar to the manufacturing method of the semiconductor device 1A. Therefore, the method for manufacturing the semiconductor device 1D also has the same effect as the method for manufacturing the semiconductor device 1A. This form shows an example in which the lead terminal portion 100 is applied to the semiconductor device 1A. Of course, the lead terminal portion 100 may be applied to the second and third embodiments.

FIG. 16 is a plan view showing a semiconductor device 1E according to the fifth embodiment. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 16. FIG. FIG. 18 is a circuit diagram showing an electrical configuration of semiconductor device 1E shown in FIG. 16 to 18, semiconductor device 1E has a modified form of semiconductor device 1A.

The semiconductor device 1E specifically includes a plurality of source terminal electrodes 60 spaced apart from each other on the source electrode 32 . In this embodiment, the semiconductor device 1E includes at least one (one in this embodiment) source terminal electrode 60 arranged on the body electrode portion 33 of the source electrode 32, a lead-out electrode portion 34A of the source electrode 32, It includes at least one (in this form a plurality) source terminal electrode 60 disposed over 34B.

The source terminal electrode 60 on the body electrode portion 33 side is formed as a main terminal electrode 102 that conducts the drain-source current IDS in this embodiment. The plurality of source terminal electrodes 60 on the side of the plurality of lead-out electrode portions 34A and 34B are formed as sense terminal electrodes 103 in this embodiment for conducting a monitor current IM for monitoring the drain-source current IDS. Each sense terminal electrode 103 has an area smaller than that of the main terminal electrode 102 in plan view.

One sense terminal electrode 103 is arranged on the first extraction electrode portion 34A and faces the gate terminal electrode 50 in the second direction Y in plan view. The other sense terminal electrode 103 is arranged on the second extraction electrode portion 34B and faces the gate terminal electrode 50 in the second direction Y in plan view. Thus, the plurality of sense terminal electrodes 103 sandwich the gate terminal electrode 50 from both sides in the second direction Y in plan view.

Referring to FIG. 18, in semiconductor device 1E, gate drive circuit 106 is electrically connected to gate terminal electrode 50, at least one first resistor R1 is electrically connected to main terminal electrode 102, and a plurality of sense resistors are connected. At least one second resistor R2 is connected to the terminal electrode 103 . The first resistor R1 is configured to conduct the drain-source current IDS generated in the semiconductor device 1E. The second resistor R2 is configured to conduct a monitor current IM having a value less than the drain-source current IDS.

The first resistor R1 may be a resistor or a conductive joint member having a first resistance value. The second resistor R2 may be a resistor or a conductive joint member having a second resistance value greater than the first resistance value. The conductive joining member may be a conductive plate or a conductive wire (eg, bonding wire). That is, at least one first bonding wire having a first resistance value may be connected to the main terminal electrode 102 .

Also, at least one second bonding wire having a second resistance value exceeding the first resistance value may be connected to at least one sense terminal electrode 103 . The second bonding wire may have a line thickness less than the line thickness of the first bonding wire. In this case, the bonding area of the second bonding wire to the sense terminal electrode 103 may be less than the bonding area of the first bonding wire to the main terminal electrode 102 .

As described above, the semiconductor device 1E has the same effect as the semiconductor device 1A. In the method for manufacturing the semiconductor device 1E, a resist mask 90 having a plurality of second openings 92 for exposing regions where the source terminal electrode 60 and the sense terminal electrode 103 are to be formed is formed in the method for manufacturing the semiconductor device 1A. The same steps as in the manufacturing method of 1A are carried out. Therefore, the method for manufacturing the semiconductor device 1E also produces the same effect as the method for manufacturing the semiconductor device 1A.

In this embodiment, an example in which the sense terminal electrodes 103 are arranged on the lead electrode portions 34A and 34B is shown, but the arrangement location of the sense terminal electrodes 103 is arbitrary. Therefore, the sense terminal electrode 103 may be arranged on the body electrode portion 33 . This form shows an example in which the sense terminal electrode 103 is applied to the semiconductor device 1A. Of course, the sense terminal electrode 103 may be applied to the second to fourth embodiments.

FIG. 19 is a plan view showing a semiconductor device 1F according to the sixth embodiment. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 19. FIG. 19 and 20, semiconductor device 1F has a modified form of semiconductor device 1A. The semiconductor device 1</b>F specifically includes a gap 107 formed in the source electrode 32 .

The gap portion 107 is formed in the body electrode portion 33 of the source electrode 32 . The gap 107 penetrates the source electrode 32 and exposes a portion of the interlayer insulating film 27 in a cross-sectional view. In this embodiment, the gap portion 107 extends in a strip shape from a portion of the wall portion of the source electrode 32 facing the gate electrode 30 in the first direction X toward the inner portion of the source electrode 32 .

The gap part 107 is formed in a strip shape extending in the first direction X in this embodiment. In this form, the gap portion 107 crosses the central portion of the source electrode 32 in the first direction X in plan view. The gap portion 107 has an end portion at a position spaced inward (gate electrode 30 side) from the wall portion of the source electrode 32 on the fourth side surface 5D side in plan view. Of course, the gap 107 may divide the source electrode 32 in the second direction Y.

The semiconductor device 1F includes a gate intermediate wiring 109 pulled out into the gap 107 from the gate electrode 30. As shown in FIG. The gate intermediate wiring 109 has a laminated structure including the first gate conductor film 55 and the second gate conductor film 56, like the gate electrode 30 (the plurality of gate wirings 36A and 36B). The gate intermediate wiring 109 is formed spaced apart from the source electrode 32 in a plan view and extends along the gap 107 in a strip shape.

The gate intermediate wiring 109 is electrically connected to the plurality of gate structures 15 through the interlayer insulating film 27 in the inner portion of the active surface 8 (first main surface 3). The gate intermediate wiring 109 may be directly connected to the plurality of gate structures 15, or may be electrically connected to the plurality of gate structures 15 via a conductor film.

The above-described upper insulating film 38 includes a gap covering portion 110 covering the gap portion 107 in this embodiment. The gap covering portion 110 covers the entire area of the gate intermediate wiring 109 in the gap portion 107 . Gap covering portion 110 may be pulled out from inside gap portion 107 onto source electrode 32 so as to cover the peripheral portion of source electrode 32 .

The semiconductor device 1F includes a plurality of source terminal electrodes 60 spaced apart from each other on the source electrode 32 in this embodiment. The plurality of source terminal electrodes 60 are arranged on the source electrode 32 with a gap from the gap 107 in plan view, and are opposed to each other in the second direction Y. As shown in FIG. The plurality of source terminal electrodes 60 are arranged so as to expose the gap covering portion 110 in this embodiment.

In this embodiment, each of the plurality of source terminal electrodes 60 is formed in a quadrangular shape (specifically, a rectangular shape extending in the first direction X) in plan view. The planar shape of the plurality of source terminal electrodes 60 is arbitrary, and may be formed in a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape. The plurality of source terminal electrodes 60 may include second projecting portions 63 formed on the gap covering portion 110 of the upper insulating film 38 .

The aforementioned sealing insulator 71 covers the gap 107 in the region between the plurality of source terminal electrodes 60 in this embodiment. The sealing insulator 71 covers the gap covering portion 110 of the upper insulating film 38 in the region between the plurality of source terminal electrodes 60 . That is, the sealing insulator 71 covers the gate intermediate wiring 109 with the upper insulating film 38 interposed therebetween.

In this embodiment, an example in which the upper insulating film 38 has the gap covering portion 110 is shown. However, the presence or absence of the gap covering portion 110 is arbitrary, and the upper insulating film 38 without the gap covering portion 110 may be formed. In this case, the plurality of source terminal electrodes 60 are arranged on the source electrode 32 so as to expose the gate intermediate wiring 109 . The encapsulation insulator 71 directly covers the gate intermediate wire 109 and electrically isolates the gate intermediate wire 109 from the source electrode 32 . Sealing insulator 71 directly covers part of interlayer insulating film 27 exposed from the region between source electrode 32 and gate intermediate wiring 109 in gap 107 .

As described above, the semiconductor device 1F has the same effect as the semiconductor device 1A. In the manufacturing method of the semiconductor device 1F, a wafer structure 80 in which a structure corresponding to the semiconductor device 1F is formed in each device region 86 is prepared, and the same steps as in the manufacturing method of the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1F also produces the same effect as the method for manufacturing the semiconductor device 1A.

In this form, an example is shown in which the gap portion 107, the gate intermediate wiring 109, the gap covering portion 110, etc. are applied to the semiconductor device 1A. Of course, the gap portion 107, the gate intermediate wiring 109, the gap covering portion 110, etc. may be applied to the second to fifth embodiments.

FIG. 21 is a plan view showing a semiconductor device 1G according to the seventh embodiment. Referring to FIG. 21, semiconductor device 1G has the feature (structure having gate intermediate wiring 109) of semiconductor device 1F according to the sixth embodiment, and the feature (sense terminal electrode 103) of semiconductor device 1E according to the fifth embodiment. It has a form combined with a structure having The semiconductor device 1G having such a form also provides the same effects as those of the semiconductor device 1A.

FIG. 22 is a plan view showing a semiconductor device 1H according to the eighth embodiment. Referring to FIG. 22, semiconductor device 1H has a configuration obtained by modifying semiconductor device 1A. The semiconductor device 1</b>H specifically has a gate electrode 30 arranged in a region along an arbitrary corner of the chip 2 .

That is, the gate electrode 30 has a first straight line L1 (see two-dot chain line) that crosses the central portion of the first main surface 3 in the first direction X, and a straight line L1 that crosses the central portion of the first main surface 3 in the second direction Y. When the crossing second straight line L2 (see the two-dot chain line portion) is set, it is arranged at a position shifted from both the first straight line L1 and the second straight line L2. In this embodiment, gate electrode 30 is arranged in a region along a corner connecting second side surface 5B and third side surface 5C in plan view.

The plurality of extraction electrode portions 34A and 34B related to the source electrode 32 described above sandwich the gate electrode 30 from both sides in the second direction Y in plan view, as in the first embodiment. The first extraction electrode portion 34A is extracted from the body electrode portion 33 with a first plane area. The second extraction electrode portion 34B is extracted from the body electrode portion 33 with a second plane area smaller than the first plane area. Of course, the source electrode 32 may include only the body electrode portion 33 and the first lead electrode portion 34A without the second lead electrode portion 34B.

The gate terminal electrode 50 described above is arranged on the gate electrode 30 as in the case of the first embodiment. The gate terminal electrode 50 is arranged in a region along an arbitrary corner of the chip 2 in this embodiment. That is, the gate terminal electrode 50 is arranged at a position shifted from both the first straight line L1 and the second straight line L2 in plan view. In this embodiment, the gate terminal electrode 50 is arranged in a region along the corner connecting the second side surface 5B and the third side surface 5C in plan view.

The aforementioned source terminal electrode 60, in this form, has a lead terminal portion 100 that is led out above the first lead electrode portion 34A. In this form, the source terminal electrode 60 does not have the extraction terminal portion 100 extracted above the second extraction electrode portion 34B. Therefore, the lead terminal portion 100 faces the gate terminal electrode 50 from one side in the second direction Y. As shown in FIG. The source terminal electrode 60 has a portion facing the gate terminal electrode 50 from two directions, the first direction X and the second direction Y, by having the lead terminal portion 100 .

As described above, the semiconductor device 1H has the same effect as the semiconductor device 1A. In the method for manufacturing the semiconductor device 1H, a wafer structure 80 in which structures corresponding to the semiconductor device 1H are formed in the device regions 86 is prepared, and the same steps as in the method for manufacturing the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1H also produces the same effect as the method for manufacturing the semiconductor device 1A. The structure in which the gate electrode 30 and the gate terminal electrode 50 are arranged along the corners of the chip 2 may be applied to the second to seventh embodiments.

FIG. 23 is a plan view showing a semiconductor device 1I according to the ninth embodiment. Referring to FIG. 23, semiconductor device 1I has a configuration obtained by modifying semiconductor device 1A. Specifically, the semiconductor device 1I has a gate electrode 30 arranged in the central portion of the first main surface 3 (active surface 8) in plan view.

That is, the gate electrode 30 has a first straight line L1 (see two-dot chain line) that crosses the central portion of the first main surface 3 in the first direction X, and a straight line L1 that crosses the central portion of the first main surface 3 in the second direction Y. When the crossing second straight line L2 (see two-dot chain line) is set, it is arranged so as to cover the intersection Cr of the first straight line L1 and the second straight line L2. In this embodiment, the source electrode 32 described above is formed in a ring shape (specifically, a square ring shape) surrounding the gate electrode 30 in plan view.

The semiconductor device 1I includes a plurality of gaps 107A and 107B formed in the source electrode 32. The plurality of gaps 107A, 107B includes a first gap 107A and a second gap 107B. The first gap portion 107A crosses in the second direction Y a portion extending in the first direction X in the region on one side (first side surface 5A side) of the source electrode 32 . The first gap portion 107A faces the gate electrode 30 in the second direction Y in plan view.

The second gap portion 107B crosses in the second direction Y the portion extending in the first direction X in the region on the other side (second side surface 5B side) of the source electrode 32 . The second gap portion 107B faces the gate electrode 30 in the second direction Y in plan view. In this form, the second gap 107B faces the first gap 107A across the gate electrode 30 in plan view.

The aforementioned first gate wiring 36A is drawn from the gate electrode 30 into the first gap 107A. Specifically, the first gate line 36A has a portion extending in the second direction Y in a band shape in the first gap portion 107A, and a portion extending in the first direction X along the first side surface 5A (first connection surface 10A). It has a strip-like portion. The aforementioned second gate wiring 36B is led out from the gate electrode 30 into the second gap portion 107B. Specifically, the second gate wiring 36B has a portion extending in the second direction Y in a strip shape in the second gap 107B and a portion extending in the first direction X along the second side surface 5B (second connection surface 10B). It has a strip-like portion.

The plurality of gate wirings 36A and 36B intersect (specifically, orthogonally) the both ends of the plurality of gate structures 15, as in the first embodiment. The multiple gate wirings 36A and 36B are electrically connected to the multiple gate structures 15 through the interlayer insulating film 27 . The plurality of gate wirings 36A and 36B may be directly connected to the plurality of gate structures 15, or may be electrically connected to the plurality of gate structures 15 via a conductor film.

The source wiring 37 described above, in this embodiment, is drawn out from the source electrode 32 at multiple locations and surrounds the gate electrode 30, the source electrode 32, and the gate wirings 36A and 36B. Of course, the source wiring 37 may be led out from a single portion of the source electrode 32 as in the first embodiment.

The aforementioned upper insulating film 38 includes a plurality of gap covering portions 110A and 110B covering the plurality of gap portions 107A and 107B respectively in this embodiment. The plurality of gap covering portions 110A, 110B includes a first gap covering portion 110A and a second gap covering portion 110B. The first gap covering portion 110A covers the entire first gate wiring 36A within the first gap portion 107A. The second gap covering portion 110B covers the entire area of the second gate wiring 36B within the second gap portion 107B. The plurality of gap covering portions 110A and 110B are pulled out from the plurality of gap portions 107A and 107B onto the source electrode 32 so as to cover the peripheral portion of the source electrode 32 .

The gate terminal electrode 50 described above is arranged on the gate electrode 30 as in the case of the first embodiment. The gate terminal electrode 50 is arranged in the central portion of the first main surface 3 (active surface 8) in this embodiment. That is, the gate terminal electrode 50 has a first straight line L1 (see two-dot chain line) crossing the central portion of the first main surface 3 in the first direction X, and a central portion of the first main surface 3 extending in the second direction Y. When a second straight line L2 (see the two-dot chain line) is set to cross the two straight lines L1 and L2, it is arranged so as to cover the intersection Cr of the first straight line L1 and the second straight line L2.

The semiconductor device 1I includes, in this embodiment, a plurality of source terminal electrodes 60 spaced apart from each other on the source electrode 32 . The plurality of source terminal electrodes 60 are arranged on the source electrode 32 at intervals from the plurality of gaps 107A and 107B in plan view, and face each other in the first direction X. As shown in FIG. The plurality of source terminal electrodes 60 are arranged in this form so as to expose the plurality of gaps 107A and 107B.

In this embodiment, each of the plurality of source terminal electrodes 60 is formed in a strip shape extending along the source electrode 32 in plan view (specifically, in a C shape curved along the gate terminal electrode 50). The planar shape of the plurality of source terminal electrodes 60 is arbitrary, and may be rectangular, polygonal other than rectangular, circular, or elliptical. The plurality of source terminal electrodes 60 may include second projecting portions 63 formed on the gap covering portions 110A and 110B of the upper insulating film 38 .

The aforementioned sealing insulator 71 covers the plurality of gaps 107A and 107B in the region between the plurality of source terminal electrodes 60 in this embodiment. The encapsulating insulator 71 covers the plurality of gap covering portions 110A, 110B in the regions between the plurality of source terminal electrodes 60 in this embodiment. That is, the sealing insulator 71 covers the plurality of gate wirings 36A and 36B with the plurality of gap covering portions 110A and 110B interposed therebetween.

This embodiment shows an example in which the upper insulating film 38 has the gap covering portions 110A and 110B. However, the presence or absence of the plurality of gap covering portions 110A and 110B is optional, and the upper insulating film 38 may be formed without the plurality of gap covering portions 110A and 110B. In this case, the plurality of source terminal electrodes 60 are arranged on the source electrode 32 so as to expose the gate wirings 36A and 36B.

The encapsulating insulator 71 directly covers the gate wirings 36A, 36B and electrically insulates the gate wirings 36A, 36B from the source electrode 32 . Sealing insulator 71 directly covers portions of interlayer insulating film 27 exposed from regions between source electrode 32 and gate wirings 36A and 36B within a plurality of gaps 107A and 107B.

As described above, the semiconductor device 1I has the same effect as the semiconductor device 1A. In the method of manufacturing the semiconductor device 1I, a wafer structure 80 in which structures corresponding to the semiconductor device 1I are formed in the device regions 86 is prepared, and steps similar to those of the method of manufacturing the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1I also produces the same effect as the method for manufacturing the semiconductor device 1A. The structure in which the gate electrode 30 and the gate terminal electrode 50 are arranged in the central portion of the chip 2 may be applied to the second to eighth embodiments.

FIG. 24 is a plan view showing a semiconductor device 1J according to the tenth embodiment. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 24. FIG. The semiconductor device 1J includes the chip 2 described above. The chip 2 does not have a mesa portion 11 in this form and includes a flat first principal surface 3 . The semiconductor device 1J includes an SBD (Schottky Barrier Diode) structure 120 as an example of a diode formed on the chip 2 .

The semiconductor device 1J includes an n-type diode region 121 formed in the inner part of the first main surface 3. The diode region 121 is formed using part of the first semiconductor region 6 in this embodiment.

The semiconductor device 1J includes a p-type guard region 122 that partitions the diode region 121 from other regions on the first main surface 3 . The guard region 122 is formed in the surface layer portion of the first semiconductor region 6 with an inward space from the peripheral edge of the first main surface 3 . In this form, the guard region 122 is formed in a ring shape (in this form, a square ring shape) surrounding the diode region 121 in plan view. Guard region 122 has an inner edge portion on the diode region 121 side and an outer edge portion on the peripheral edge side of first main surface 3 .

The semiconductor device 1J includes the main surface insulating film 25 that selectively covers the first main surface 3 . Main surface insulating film 25 has diode opening 123 exposing the inner edge of diode region 121 and guard region 122 . The main surface insulating film 25 is formed spaced inward from the peripheral edge of the first main surface 3 , exposing the first main surface 3 (first semiconductor region 6 ) from the peripheral edge of the first main surface 3 . there is Of course, the main surface insulating film 25 may cover the peripheral portion of the first main surface 3 . In this case, the peripheral portion of the main surface insulating film 25 may continue to the first to fourth side surfaces 5A to 5D.

The semiconductor device 1J includes a first polarity electrode 124 (main surface electrode) arranged on the first main surface 3 . The first polarity electrode 124 is the "anode electrode" in this form. The first polar electrode 124 is spaced inwardly from the periphery of the first major surface 3 . In this form, the first polar electrode 124 is formed in a square shape along the periphery of the first main surface 3 in plan view. The first polar electrode 124 enters the diode opening 123 from above the main surface insulating film 25 and is electrically connected to the first main surface 3 and the inner edge of the guard region 122 .

The first polar electrode 124 forms a Schottky junction with the diode region 121 (first semiconductor region 6). Thus, an SBD structure 120 is formed. The plane area of the first polar electrode 124 is preferably 50% or more of the first major surface 3 . It is particularly preferable that the plane area of the first polar electrode 124 is 75% or more of the first major surface 3 . The first polar electrode 124 may have a thickness of 0.5 μm to 15 μm.

The first polar electrode 124 may have a laminated structure including a Ti-based metal film and an Al-based metal film. The Ti-based metal film may have a single layer structure consisting of a Ti film or a TiN film. The Ti-based metal film may have a laminated structure including a Ti film and a TiN film in any order. The Al-based metal film is preferably thicker than the Ti-based metal film. The Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

The semiconductor device 1J includes the aforementioned upper insulating film 38 that selectively covers the main surface insulating film 25 and the first polarity electrode 124 . The upper insulating film 38 has a laminated structure including an inorganic insulating film 42 and an organic insulating film 43 laminated in this order from the chip 2 side, as in the case of the first embodiment. In this form, the upper insulating film 38 has a contact opening 125 that exposes the inner portion of the first polarity electrode 124 in plan view, and covers the peripheral edge portion of the first polarity electrode 124 over the entire circumference. . In this form, the contact opening 125 is formed in a square shape in plan view.

The upper insulating film 38 is formed spaced inwardly from the peripheral edge of the first main surface 3 (first to fourth side surfaces 5A to 5D), and forms a dicing street 41 between the peripheral edge of the first main surface 3 and the upper insulating film 38 . are partitioned. The dicing street 41 is formed in a strip shape extending along the periphery of the first main surface 3 in plan view. In this embodiment, the dicing street 41 is formed in a ring shape (specifically, a square ring shape) surrounding the inner portion of the first main surface 3 in plan view.

The dicing street 41 exposes the first main surface 3 (first semiconductor region 6) in this form. Of course, when the main surface insulating film 25 covers the peripheral portion of the first main surface 3 , the dicing streets 41 may expose the main surface insulating film 25 . The upper insulating film 38 preferably has a thickness exceeding the thickness of the first polarity electrode 124 . The thickness of the upper insulating film 38 may be less than the thickness of the chip 2 .

The semiconductor device 1J includes a terminal electrode 126 arranged on the first polarity electrode 124 . The terminal electrode 126 is erected in a columnar shape on a portion of the first polarity electrode 124 exposed from the contact opening 125 . The terminal electrode 126 has an area less than the area of the first polar electrode 124 in plan view, and is spaced apart from the periphery of the first polar electrode 124 and disposed above the inner portion of the first polar electrode 124 . good too. In this form, the terminal electrode 126 is formed in a polygonal shape (quadrangular shape in this form) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.

The terminal electrode 126 has a terminal surface 127 and terminal sidewalls 128 . Terminal surface 127 extends flat along first main surface 3 . The terminal surface 127 may consist of a ground surface with grinding marks. The terminal sidewall 128 is located on the upper insulating film 38 (specifically, the organic insulating film 43) in this embodiment.

That is, the terminal electrode 126 includes portions in contact with the inorganic insulating film 42 and the organic insulating film 43 . The terminal side wall 128 extends substantially vertically in the normal direction Z. As shown in FIG. "Substantially vertical" also includes a form extending in the stacking direction while curving (meandering). Terminal sidewall 128 includes a portion facing first polarity electrode 124 with upper insulating film 38 interposed therebetween. The terminal side wall 128 preferably has a smooth surface without grinding marks.

The terminal electrode 126 has a projecting portion 129 projecting outward from the lower end portion of the terminal side wall 128 in this embodiment. The projecting portion 129 is formed in a region closer to the upper insulating film 38 (organic insulating film 43 ) than the intermediate portion of the terminal side wall 128 . The protruding portion 129 extends along the outer surface of the upper insulating film 38 and is formed in a tapered shape in which the thickness gradually decreases from the terminal side wall 128 toward the distal end in a cross-sectional view. As a result, the protruding portion 129 has a sharp tip that forms an acute angle. Of course, the terminal electrode 126 without the projecting portion 129 may be formed.

The terminal electrode 126 preferably has a thickness exceeding the thickness of the first polarity electrode 124 . It is particularly preferable that the thickness of the terminal electrode 126 exceeds the thickness of the upper insulating film 38 . The thickness of the terminal electrode 126 exceeds the thickness of the chip 2 in this embodiment. Of course, the thickness of the terminal electrode 126 may be less than the thickness of the chip 2 .

The thickness of the terminal electrode 126 may be 10 μm or more and 300 μm or less. The thickness of the terminal electrode 126 is preferably 30 μm or more. It is particularly preferable that the thickness of the terminal electrode 126 is 80 μm or more and 200 μm or less. The terminal electrode 126 preferably has a planar area of 50% or more of the first main surface 3 . It is particularly preferable that the plane area of the terminal electrode 126 is 75% or more of the first main surface 3 .

In this form, the terminal electrode 126 has a laminated structure including a first conductor film 133 and a second conductor film 134 laminated in this order from the first polarity electrode 124 side. The first conductor film 133 may contain a Ti-based metal film. The first conductor film 133 may have a single layer structure made of a Ti film or a TiN film.

The first conductor film 133 may have a laminated structure including a Ti film and a TiN film laminated in any order. The first conductor film 133 has a thickness less than the thickness of the first polarity electrode 124 . The first conductor film 133 covers the first polarity electrode 124 in the form of a film in the contact opening 125 and is pulled out on the upper insulating film 38 in the form of a film. The first conductor film 133 forms part of the projecting portion 129 . The first conductor film 133 does not necessarily have to be formed, and may be removed.

The second conductor film 134 forms the main body of the terminal electrode 126 . The second conductor film 134 may contain a Cu-based metal film. The Cu-based metal film may be a pure Cu film (a Cu film with a purity of 99% or more) or a Cu alloy film. The second conductor film 134 includes a pure Cu plating film in this embodiment. The second conductor film 134 preferably has a thickness exceeding the thickness of the first polar electrode 124 . It is particularly preferable that the thickness of the second conductor film 134 exceeds the thickness of the upper insulating film 38 . The thickness of the second conductor film 134 exceeds the thickness of the chip 2 in this embodiment.

The second conductor film 134 covers the first polarity electrode 124 in the contact opening 125 with the first conductor film 133 interposed therebetween, and is pulled out in the form of a film onto the upper insulating film 38 with the first conductor film 133 interposed therebetween. there is The second conductor film 134 forms part of the projecting portion 129 . That is, the projecting portion 129 has a laminated structure including the first conductor film 133 and the second conductor film 134 . The second conductor film 134 has a thickness exceeding the thickness of the first conductor film 133 within the projecting portion 129 .

The semiconductor device 1J includes the aforementioned sealing insulator 71 covering the first main surface 3 . In this form, the sealing insulator 71 covers the periphery of the terminal electrode 126 so as to partially expose the terminal electrode 126 on the first main surface 3 . Specifically, the sealing insulator 71 exposes the terminal surface 127 and covers the terminal side walls 128 . In this embodiment, the sealing insulator 71 covers the projecting portion 129 and faces the upper insulating film 38 with the projecting portion 129 interposed therebetween. The sealing insulator 71 prevents the terminal electrode 126 from coming off.

The sealing insulator 71 has a portion that directly covers the upper insulating film 38 . The sealing insulator 71 covers the first polarity electrode 124 with the upper insulating film 38 interposed therebetween. The encapsulating insulator 71 covers the dicing streets 41 defined by the upper insulating film 38 at the periphery of the first main surface 3 . The encapsulating insulator 71 directly covers the first major surface 3 (first semiconductor region 6 ) at the dicing street 41 in this embodiment. Of course, when the main surface insulating film 25 is exposed from the dicing streets 41 , the sealing insulator 71 may directly cover the main surface insulating film 25 at the dicing streets 41 .

The sealing insulator 71 preferably has a thickness exceeding the thickness of the first polar electrode 124 . It is particularly preferable that the thickness of the sealing insulator 71 exceeds the thickness of the upper insulating film 38 . The thickness of the encapsulation insulator 71 exceeds the thickness of the chip 2 in this embodiment. Of course, the thickness of the encapsulating insulator 71 may be less than the thickness of the chip 2 . The thickness of the sealing insulator 71 may be 10 μm or more and 300 μm or less. The thickness of the sealing insulator 71 is preferably 30 μm or more. It is particularly preferable that the thickness of the sealing insulator 71 is 80 μm or more and 200 μm or less.

The sealing insulator 71 has an insulating main surface 72 and insulating side walls 73 . The insulating main surface 72 extends flat along the first main surface 3 . The insulating main surface 72 forms one flat surface with the terminal surface 127 . The insulating main surface 72 may be a ground surface having grinding marks. In this case, the insulating main surface 72 preferably forms one ground surface with the terminal surface 127 .

The insulating side wall 73 extends from the peripheral edge of the insulating main surface 72 toward the chip 2 and continues to the first to fourth side surfaces 5A to 5D. The insulating side wall 73 is formed substantially perpendicular to the insulating main surface 72 . The angle formed between insulating side wall 73 and insulating main surface 72 may be 88° or more and 92° or less. The insulating side wall 73 may consist of a ground surface with grinding marks. The insulating sidewall 73 may form one grinding surface with the first to fourth side surfaces 5A to 5D.

The semiconductor device 1J includes a second polarity electrode 136 (second main surface electrode) covering the second main surface 4. The second polar electrode 136 is the "cathode electrode" in this form. The second polar electrode 136 is electrically connected to the second major surface 4 . The second polar electrode 136 forms an ohmic contact with the second semiconductor region 7 exposed from the second major surface 4 . The second polar electrode 136 may cover the entire second main surface 4 so as to be connected to the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).

The second polar electrode 136 may cover the second main surface 4 with a space inward from the periphery of the chip 2 . The second polarity electrode 136 is configured such that a voltage of 500 V or more and 3000 V or less is applied between the terminal electrode 126 and the terminal electrode 126 . That is, the chip 2 is formed so that a voltage of 500 V or more and 3000 V or less is applied between the first principal surface 3 and the second principal surface 4 .

As described above, the semiconductor device 1J includes the chip 2, the first polarity electrode 124 (main surface electrode), the terminal electrode 126, and the sealing insulator 71. Chip 2 has a first main surface 3 . The first polar electrode 124 is arranged on the first main surface 3 at a distance from the periphery of the first main surface 3 . A terminal electrode 126 is disposed on the first polarity electrode 124 . The sealing insulator 71 covers the periphery of the terminal electrode 126 on the first main surface 3 .

According to this structure, the sealing insulator 71 can protect the object to be sealed from external force and moisture. In other words, the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide a semiconductor device 1J with improved reliability.

Thus, according to the semiconductor device 1J, the same effects as those of the semiconductor device 1A can be obtained. In the manufacturing method of the semiconductor device 1J, a wafer structure 80 in which a structure corresponding to the semiconductor device 1J is formed in each device region 86 is prepared, and the same steps as in the manufacturing method of the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1J also produces the same effect as the method for manufacturing the semiconductor device 1A.

FIG. 26 is a cross-sectional view showing a semiconductor device 1K according to the eleventh embodiment. Referring to FIG. 26, a semiconductor device 1K is obtained by combining the technical idea of a semiconductor device 1B (see FIGS. 11 and 12) according to the second embodiment with a semiconductor device 1J (see FIGS. 24 and 25). have. That is, the semiconductor device 1K includes a sealing insulator 71 extending from the peripheral edge of the insulating main surface 72 toward the chip 2 and having the insulating side wall 73 located inside the peripheral edge of the first main surface 3 .

That is, the insulating sidewall 73 is spaced inwardly from the peripheral edge of the chip 2 so as to define a stepped portion with the first main surface 3 . The insulating sidewall 73 exposes the first main surface 3 in this form. Of course, when the main surface insulating film 25 covers the peripheral portion of the first main surface 3 , the insulating sidewall 73 may cover the main surface insulating film 25 . The insulating side wall 73 preferably has a smooth surface without grinding marks.

The sealing insulator 71 may have a recessed portion 99 a recessed toward the inner portion of the first main surface 3 at the lower end portion of the insulating side wall 73 . The recessed portion 99a extends along the first main surface 3 and may be formed in a tapered shape in which the width of the recess gradually decreases from the insulating side wall 73 toward the distal end in a cross-sectional view. As a result, the recessed portion 99a may have a sharp tip that forms an acute angle. Of course, the sealing insulator 71 may be formed without the recessed portion 99a.

As described above, the semiconductor device 1K includes the chip 2, the first polarity electrode 124 (main surface electrode), the terminal electrode 126, and the sealing insulator 71. Chip 2 has a first main surface 3 and first to fourth side surfaces 5A to 5D. The first polar electrode 124 is arranged on the first main surface 3, spaced apart from at least one (in this embodiment, all) of the first to fourth side surfaces 5A to 5D. A terminal electrode 126 is disposed on the first polarity electrode 124 .

The sealing insulator 71 covers the periphery of the terminal electrode 126 on the first main surface 3 . The sealing insulator 71 is spaced inwardly from at least one (in this embodiment, all) of the first to fourth side surfaces 5A to 5D so as to define a stepped portion with the first main surface 3. It has insulating sidewalls 73 . According to this structure, it is possible to provide the semiconductor device 1K having the same effects as those of the semiconductor device 1J.

FIG. 27 is a cross-sectional view showing a semiconductor device 1L according to the twelfth embodiment. Referring to FIG. 27, semiconductor device 1L has a configuration in which the technical idea of semiconductor device 1C (see FIGS. 13 and 14) according to the third embodiment is combined with semiconductor device 1J (see FIGS. 24 and 25). have. That is, the semiconductor device 1L is a sealing insulator extending from the peripheral edge of the insulating main surface 72 toward the chip 2 in the region outside the first main surface 3 and having the insulating sidewall 73 located in the region outside the first main surface 3. 71 included.

That is, the insulating side wall 73 protrudes outward from the periphery of the chip 2 so as to define a step portion with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The insulating side wall 73 preferably has a smooth surface without grinding marks. The sealing insulator 71 may have an inclined portion 99b at the lower end portion of the insulating side wall 73 that is inclined from the insulating side wall 73 side toward the first main surface 3 side. The sloped portion 99b is the remainder of the recessed portion 99a described above. Of course, the sealing insulator 71 may have a lower end extending along the first main surface 3 so as to be connected to the insulating side wall 73 at a substantially right angle without the inclined portion 99b.

As described above, the semiconductor device 1L includes the chip 2, the first polarity electrode 124 (main surface electrode), the terminal electrode 126, and the sealing insulator 71. Chip 2 has a first main surface 3 and first to fourth side surfaces 5A to 5D. The first polar electrode 124 is arranged on the first main surface 3, spaced apart from at least one (in this embodiment, all) of the first to fourth side surfaces 5A to 5D. A terminal electrode 126 is disposed on the first polarity electrode 124 .

The sealing insulator 71 covers the periphery of the terminal electrode 126 on the first main surface 3 . The encapsulating insulator 71 is formed on the first to fourth side surfaces 5A to 5D so as to define a step portion with at least one (in this embodiment, all) of the first to fourth side surfaces 5A to 5D of the chip 2. It has insulating sidewalls 73 projecting outwardly from at least one (all in this embodiment) of 5D. According to this structure, it is possible to provide the semiconductor device 1L having the same effect as that of the semiconductor device 1J.

Modifications applied to each embodiment are shown below. FIG. 28 is a cross-sectional view showing a modification of the chip 2 applied to each embodiment. FIG. 28 shows, as an example, a mode in which a chip 2 according to a modification is applied to a semiconductor device 1A. However, the chip 2 according to the modification may be applied to the second to twelfth embodiments.

Referring to FIG. 28, semiconductor device 1A may include only first semiconductor region 6 without second semiconductor region 7 inside chip 2 . In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4 and the first to fourth side surfaces 5A to 5D of the chip 2. FIG. In other words, the chip 2 in this form does not have a semiconductor substrate and has a single-layer structure consisting of an epitaxial layer. Such a chip 2 is formed by completely removing the second semiconductor region 7 (semiconductor substrate) in the process of FIG. 10L.

FIG. 29 is a cross-sectional view showing a modification of the sealing insulator 71 applied to each embodiment. FIG. 29 shows, as an example, a mode in which a sealing insulator 71 according to a modification is applied to a semiconductor device 1A. However, the sealing insulator 71 according to the modification may be applied to the second to twelfth embodiments. Referring to FIG. 29, semiconductor device 1A may include a sealing insulator 71 covering the entire upper insulating film 38 .

In this case, in the first to ninth embodiments, the gate terminal electrode 50 not in contact with the upper insulating film 38 and the source terminal electrode 60 not in contact with the upper insulating film 38 are formed. In this case, encapsulating insulator 71 may have portions that directly cover gate electrode 30 and source electrode 32 . On the other hand, in the tenth to twelfth embodiments, the terminal electrode 126 that is not in contact with the upper insulating film 38 is formed. In this case, the encapsulating insulator 71 may have a portion that directly covers the first polarity electrode 124 .

Examples of the form of packages in which the semiconductor devices 1A to 1L according to the first to twelfth embodiments are mounted are shown below. FIG. 30 is a plan view showing a package 201A on which semiconductor devices 1A to 1I according to the first to ninth embodiments are mounted. Package 201A may also be referred to as a "semiconductor package" or "semiconductor module."

Referring to FIG. 30, package 201A includes a rectangular parallelepiped package main body 202 . The package body 202 is made of mold resin, and contains a matrix resin (for example, epoxy resin), a plurality of fillers, and a plurality of flexible particles (flexifying agent), similar to the sealing insulator 71 . The package body 202 has a first surface 203 on one side, a second surface 204 on the other side, and first to fourth side walls 205A to 205D connecting the first surface 203 and the second surface 204. As shown in FIG.

The first surface 203 and the second surface 204 are formed in a quadrangular shape when viewed from the normal direction Z thereof. The first side wall 205A and the second side wall 205B extend in the first direction X and face the second direction Y orthogonal to the first direction X. As shown in FIG. The third sidewall 205C and the fourth sidewall 205D extend in the second direction Y and face the first direction X. As shown in FIG.

The package 201A includes a metal plate 206 (conductor plate) arranged inside the package body 202 . Metal plate 206 may be referred to as a "die pad." The metal plate 206 is formed in a square shape (specifically, a rectangular shape) in plan view. The metal plate 206 includes a drawer plate portion 207 drawn out of the package body 202 from the first side wall 205A. The drawer plate portion 207 has a circular through hole 208 . Metal plate 206 may be exposed from second surface 204 .

The package 201A includes a plurality of (three in this embodiment) lead terminals 209 drawn out from the inside of the package body 202 to the outside. A plurality of lead terminals 209 are arranged on the second side wall 205B side. The plurality of lead terminals 209 are each formed in a strip shape extending in the direction perpendicular to the second side wall 205B (that is, the second direction Y). The lead terminals 209 on both sides of the plurality of lead terminals 209 are spaced apart from the metal plate 206 , and the central lead terminal 209 is integrally formed with the metal plate 206 . Arrangement of the lead terminal 209 connected to the metal plate 206 is arbitrary.

The package 201A includes a semiconductor device 210 arranged on a metal plate 206 within the package body 202 . The semiconductor device 210 is composed of any one of the semiconductor devices 1A to 1I according to the first to ninth embodiments. The semiconductor device 210 is arranged on the metal plate 206 with the drain electrode 77 facing the metal plate 206 and is electrically connected to the metal plate 206 .

The package 201A includes a conductive adhesive 211 interposed between the drain electrode 77 and the metal plate 206 to bond the semiconductor device 210 to the metal plate 206. Conductive adhesive 211 may include solder or metal paste. The solder may be lead-free solder. The metal paste may contain at least one of Au, Ag and Cu. The Ag paste may consist of Ag sintered paste. The Ag sintering paste consists of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.

The package 201A includes at least one (a plurality of in this embodiment) conducting wires 212 (conductive connection members) electrically connected to the lead terminals 209 and the semiconductor device 210 within the package body 202 . Conductor 212 consists of a metal wire (that is, a bonding wire) in this form. Conductors 212 may include at least one of gold wire, copper wire and aluminum wire. Of course, the conducting wire 212 may be made of a metal plate such as a metal clip instead of the metal wire.

At least one (one in this embodiment) conducting wire 212 is electrically connected to the gate terminal electrode 50 and the lead terminal 209 . At least one (four in this embodiment) conducting wire 212 is electrically connected to the source terminal electrode 60 and the lead terminal 209 . When source terminal electrode 60 includes sense terminal electrode 103 (see FIG. 15), lead terminal 209 corresponding to sense terminal electrode 103 and conducting wire 212 connected to sense terminal electrode 103 and lead terminal 209 are further provided.

FIG. 31 is a plan view showing a package 201B on which semiconductor devices 1J to 1L according to tenth to twelfth embodiments are mounted. Package 201B may also be referred to as a "semiconductor package" or "semiconductor module." Referring to FIG. 31, package 201B includes package body 202, metal plate 206, a plurality (two in this embodiment) of lead terminals 209, semiconductor device 213, conductive adhesive 211 and a plurality of conducting wires 212. FIG. Differences from the package 201A will be described below.

One lead terminal 209 of the plurality of lead terminals 209 is spaced apart from the metal plate 206 , and the other lead terminal 209 is integrally formed with the metal plate 206 . The semiconductor device 213 is arranged on the metal plate 206 inside the package body 202 . The semiconductor device 213 is composed of any one of the semiconductor devices 1J to 1L according to the tenth to twelfth embodiments. The semiconductor device 213 is placed on the metal plate 206 with the second polarity electrode 136 facing the metal plate 206 and electrically connected to the metal plate 206 .

A conductive adhesive 211 is interposed between the second polar electrode 136 and the metal plate 206 to bond the semiconductor device 213 to the metal plate 206 . At least one (four in this embodiment) conducting wire 212 is electrically connected to the terminal electrode 126 and the lead terminal 209 .

FIG. 32 is a perspective view showing a package 201C on which the semiconductor devices 1A to 1I according to the first to ninth embodiments and the semiconductor devices 1J to 1L according to the tenth to twelfth embodiments are mounted. 33 is an exploded perspective view of the package 201C shown in FIG. 32. FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 32. FIG. Package 201C may also be referred to as a "semiconductor package" or "semiconductor module."

32 to 34, the package 201C includes a rectangular parallelepiped package main body 222. As shown in FIG. The package body 222 is made of mold resin, and contains a matrix resin (for example, epoxy resin), a plurality of fillers, and a plurality of flexible particles (flexifying agent), similar to the sealing insulator 71 . The package body 222 has a first surface 223 on one side, a second surface 224 on the other side, and first to fourth side walls 225A to 225D connecting the first surface 223 and the second surface 224. As shown in FIG.

The first surface 223 and the second surface 224 are formed in a quadrangular shape (rectangular shape in this embodiment) when viewed from the normal direction Z thereof. The first side wall 225A and the second side wall 225B extend in the first direction X along the first surface 223 and face the second direction Y. As shown in FIG. The first side wall 225A and the second side wall 225B form the long sides of the package body 222 . The third sidewall 225C and the fourth sidewall 225D extend in the second direction Y and face the first direction X. As shown in FIG. The third side wall 225C and the fourth side wall 225D form short sides of the package body 222 .

The package 201C includes first metal plates 226 arranged inside and outside the package body 222 . The first metal plate 226 is arranged on the side of the first surface 223 of the package body 222 and includes first pad portions 227 and first lead terminals 228 . The first pad portion 227 is formed in a rectangular shape extending in the first direction X inside the package body 222 and exposed from the first surface 223 .

The first lead terminal 228 is pulled out from the first pad portion 227 toward the first side wall 225A in a strip shape extending in the second direction Y, penetrates the first side wall 225A and is exposed from the package body 222 . The first lead terminal 228 is arranged on the side of the fourth side wall 225D in plan view. The first lead terminal 228 is spaced apart from the first surface 223 and the second surface 224 and exposed from the first side wall 225A.

The package 201C includes second metal plates 230 arranged inside and outside the package body 222 . The second metal plate 230 is arranged on the second surface 224 side of the package body 222 with a gap in the normal direction Z from the first metal plate 226 , and includes a second pad section 231 and a second lead terminal 232 . The second pad portion 231 is formed in a rectangular shape extending in the first direction X inside the package body 222 and is exposed from the second surface 224 .

The second lead terminal 232 is pulled out from the second pad portion 231 toward the first side wall 225A in a strip shape extending in the second direction Y, penetrates the first side wall 225A and is exposed from the package main body 222 . The second lead terminal 232 is arranged on the side of the third side wall 225C in plan view. The second lead terminal 232 is spaced apart from the first surface 223 and the second surface 224 and exposed from the first side wall 225A.

The second lead terminal 232 is pulled out from a thickness position different from that of the first lead terminal 228 with respect to the normal direction Z. In this embodiment, the second lead terminal 232 is spaced from the first lead terminal 228 toward the second surface 224 and does not face the first lead terminal 228 in the first direction X. As shown in FIG. The second lead terminal 232 has a different length in the second direction Y than the first lead terminal 228 .

The package 201C includes a plurality of (five in this embodiment) third lead terminals 234 drawn out from the inside of the package body 222 to the outside. The plurality of third lead terminals 234 are arranged in a thickness range between the first pad portion 227 and the second pad portion 231 in this embodiment. The plurality of third lead terminals 234 are pulled out from inside the package main body 222 toward the second side wall 225B in a strip shape extending in the second direction Y, and are exposed from the package main body 222 through the second side wall 225B.

The arrangement of the plurality of third lead terminals 234 is arbitrary. In this embodiment, the plurality of third lead terminals 234 are arranged on the side of the third side wall 225C so as to be positioned on the same straight line as the second lead terminals 232 in plan view. The plurality of third lead terminals 234 may have curved portions recessed toward the first surface 223 and/or the second surface 224 at portions located outside the package body 222 .

The package 201C includes a first semiconductor device 235 arranged within the package body 222 . The first semiconductor device 235 is composed of any one of the semiconductor devices 1A to 1I according to the first to ninth embodiments. The first semiconductor device 235 is arranged between the first pad portion 227 and the second pad portion 231 . The first semiconductor device 235 is arranged on the side of the third side wall 225C in plan view. The first semiconductor device 235 is arranged on the second metal plate 230 with the drain electrode 77 facing the second metal plate 230 (the second pad portion 231 ), and is electrically connected to the second metal plate 230 . It is

The package 201C includes a second semiconductor device 236 spaced from the first semiconductor device 235 and arranged within the package body 222 . The second semiconductor device 236 is composed of any one of the semiconductor devices 1J to 1L according to the tenth to twelfth embodiments. The second semiconductor device 236 is arranged between the first pad portion 227 and the second pad portion 231 . The second semiconductor device 236 is arranged on the side of the fourth side wall 225D in plan view. The second semiconductor device 236 is arranged on the second metal plate 230 with the second polar electrode 136 facing the second metal plate 230 (the second pad portion 231). It is connected to the.

The package 201C includes a first conductor spacer 237 (first conductive connection member) and a second conductor spacer 238 (second conductive connection member) respectively arranged within the package body 222 . The first conductor spacer 237 is interposed between the first semiconductor device 235 and the first pad portion 227 and electrically connected to the first semiconductor device 235 and the first pad portion 227 . The second conductor spacer 238 is interposed between the second semiconductor device 236 and the first pad section 227 and electrically connected to the second semiconductor device 236 and the first pad section 227 .

The first conductor spacer 237 and the second conductor spacer 238 may each contain a metal plate (for example, a Cu-based metal plate). The second conductor spacer 238 is separate from the first conductor spacer 237 in this embodiment, but may be formed integrally with the first conductor spacer 237 .

The package 201C includes first to sixth conductive adhesives 239A-239F. The first through sixth conductive adhesives 239A-239F may include solder or metal paste. The solder may be lead-free solder. The metal paste may contain at least one of Au, Ag and Cu. The Ag paste may consist of Ag sintered paste. The Ag sintering paste consists of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.

The first conductive adhesive 239 A is interposed between the drain electrode 77 and the second pad portion 231 to connect the first semiconductor device 235 to the second pad portion 231 . A second conductive adhesive 239 B is interposed between the second polarity electrode 136 and the second pad portion 231 to connect the second semiconductor device 236 to the second pad portion 231 .

A third conductive adhesive 239</b>C is interposed between the source terminal electrode 60 and the first conductor spacer 237 to connect the first conductor spacer 237 to the source terminal electrode 60 . A fourth conductive adhesive 239 D is interposed between the terminal electrode 126 and the second conductor spacer 238 to connect the second conductor spacer 238 to the terminal electrode 126 .

The fifth conductive adhesive 239E is interposed between the first pad portion 227 and the first conductor spacer 237 to connect the first conductor spacer 237 to the first pad portion 227. A sixth conductive adhesive 239</b>F is interposed between the first pad portion 227 and the second conductor spacer 238 to connect the second conductor spacer 238 to the first pad portion 227 .

The package 201C includes at least one (in this embodiment, a plurality of) electrically connected to the gate terminal electrode 50 of the first semiconductor device 235 and at least one (in this embodiment, a plurality of) third lead terminals 234 in the package body 222. ) conductors 240 (conductive connecting members). Conductor 240 consists of a metal wire (that is, a bonding wire) in this form.

The conductor 240 may include at least one of gold wire, copper wire and aluminum wire. Of course, the conducting wire 240 may be made of a metal plate such as a metal clip instead of the metal wire. When the source terminal electrode 60 includes the sense terminal electrode 103 (see FIG. 15), a conductor 240 connected to the sense terminal electrode 103 and the third lead terminal 234 is further provided.

In this form, an example is shown in which the source terminal electrode 60 is connected to the first pad portion 227 via the first conductor spacer 237 . However, the source terminal electrode 60 may be connected to the first pad portion 227 by the third conductive adhesive 239C without the first conductor spacer 237 interposed therebetween. Also, in this embodiment, an example is shown in which the terminal electrode 126 is connected to the first pad portion 227 via the second conductor spacer 238 . However, the terminal electrode 126 may be connected to the first pad portion 227 by the fourth conductive adhesive 239D without the second conductor spacer 238 interposed.

Each of the above-described embodiments can be implemented in other forms. For example, the features disclosed in the first to twelfth embodiments described above can be appropriately combined among them. That is, a form including at least two of the features disclosed in the first to twelfth embodiments may be employed.

In each of the above-described embodiments, the chip 2 having the mesa portion 11 was shown. However, a chip 2 that does not have the mesa portion 11 and has the flatly extending first main surface 3 may be employed. In this case the sidewall structure 26 is removed.

In each of the above-described embodiments, the form having the source wiring 37 was shown. However, a form without the source wiring 37 may be employed. In each of the above-described embodiments, the trench gate type gate structure 15 controlling the channel inside the chip 2 was shown. However, a planar gate type gate structure 15 that controls the channel from above the first main surface 3 may be employed.

In each of the above-described embodiments, the MISFET structure 12 and the SBD structure 120 were formed on different chips 2 . However, the MISFET structure 12 and the SBD structure 120 may be formed in different regions of the first main surface 3 in the same chip 2 . In this case, SBD structure 120 may be formed as a freewheeling diode of MISFET structure 12 .

In each of the above-described embodiments, the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type". However, in each of the above-described embodiments, a form in which the "first conductivity type" is the "p-type" and the "second conductivity type" is the "n-type" may be adopted. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

In each of the above-described embodiments, the "n-type" second semiconductor region 7 was shown. However, the second semiconductor region 7 may be "p-type". In this case, instead of the MISFET structure 12, an IGBT (Insulated Gate Bipolar Transistor) structure is formed. In this case, the "source" of the MISFET structure 12 is replaced with the "emitter" of the IGBT structure and the "drain" of the MISFET structure 12 is replaced with the "collector" of the IGBT structure in the preceding description. Of course, when the chip 2 has a single-layer structure consisting of an epitaxial layer, the "p-type" second semiconductor region 7 is formed on the surface layer of the second main surface 4 of the chip 2 (epitaxial layer) by ion implantation. It may have p-type impurities introduced.

In each of the embodiments described above, the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be arbitrary directions as long as they maintain a relationship of crossing each other (specifically, orthogonally). For example, the first direction X may be a direction intersecting the first to fourth side surfaces 5A-5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A-5D.

Examples of features extracted from this specification and drawings are shown below. Hereinafter, alphanumeric characters in parentheses represent components corresponding to the above-described embodiments, but the scope of each item is not limited to the embodiments. "Semiconductor device" in the following items may be replaced with "wide bandgap semiconductor device", "SiC semiconductor device", "semiconductor switching device", or "semiconductor rectifier" as necessary. [A1] to [A20] shown below provide a method of manufacturing a semiconductor device capable of improving reliability. [B1] to [B20] shown below provide a semiconductor device having a novel structure.

[A1] A step of preparing a wafer (81) having a main surface (82) on which a device region (86) and a planned cutting line (87) defining the device region (86) are set; ), and covering the periphery of the dummy electrode (97) on the main surface (82) so as to partially expose the dummy electrode (97). and removing the dummy electrode (97) to form an opening (99) in the sealing insulator (71) extending along the line to cut (87). and cutting the wafer (81) along the opening (99).

[A2] The semiconductor device according to A1, further comprising a step of thinning the wafer (81) after the step of forming the sealing insulator (71) and before the step of cutting the wafer (81) ( 1A to 1L) manufacturing method.

[A3] The semiconductor of A2, wherein thinning the wafer (81) comprises thinning the wafer (81) to a thickness less than the thickness of the encapsulation insulator (71). Manufacturing method of the device (1A-1L).

[A4] The wafer (81) has the main surface (82) on which the line to cut (87) surrounding the device region (86) is set, and the electrode forming step includes ), and removing the dummy electrode (97) includes forming the opening (99) surrounding the device region (86). A method for manufacturing a semiconductor device (1A to 1L) according to any one of .

[A5] The electrode forming step includes: forming a conductor film (89) covering the line to cut (87); a step of forming an exposed open mask (90) on the conductor film (89); ), and removing the release mask (90) after the step of depositing the conductor (95). ) manufacturing method.

[A6] The step of forming the sealing insulator (71) includes forming the sealing insulator (71) covering the entire area of the dummy electrode (97) and exposing the dummy electrode (97). The method of manufacturing a semiconductor device (1A-1L) according to any one of A1-A5, including the step of partially removing the encapsulation insulator (71) until the semiconductor device (1A-1L) is formed.

[A7] Manufacture of the semiconductor device (1A to 1L) according to A6, wherein the step of removing the sealing insulator (71) includes a step of partially removing the sealing insulator (71) by a grinding method. Method.

[A8] preparing a wafer structure (80) having said wafer (81) and main surface electrodes (30, 32, 124) disposed over said device region (86) of said wafer (81); and the electrode forming step includes forming terminal electrodes (50, 60, 126) on the main surface electrodes (30, 32, 124), and forming the dummy electrodes on the line to cut (87). (97), the step of forming the encapsulation insulator (71) on the major surface (82) to expose portions of the terminal electrodes (50, 60, 126). The step of forming the sealing insulator (71) covering the periphery of the terminal electrodes (50, 60, 126) is included, and the step of removing the dummy electrode (97) includes ).

[A9] The main surface electrodes (30, 32, 124) are arranged on the device region (86) with a gap from the line to cut (87), and the electrode forming step A method for manufacturing a semiconductor device (1A to 1L) according to A8, including the step of forming the dummy electrode (97) spaced apart from the surface electrodes (30, 32, 124).

[A10] The method for manufacturing a semiconductor device (1A to 1L) according to A8 or A9, wherein the electrode forming step includes forming the dummy electrode (97) surrounding the terminal electrode (50, 60, 126). .

[A11] The step of removing the dummy electrode (97) includes exposing the dummy electrode (97) and forming a shielding mask (98) covering the terminal electrodes (50, 60, 126); A method for manufacturing a semiconductor device (1A-1L) according to any one of A8-A10, comprising a step of removing said dummy electrode (97) by an etching method through a shielding mask (98).

[A12] The semiconductor according to any one of A8 to A11, further comprising the step of forming an insulating film (38) covering the main surface electrodes (30, 32, 124) before the electrode forming step. Manufacturing method of the device (1A-1L).

[A13] The semiconductor device according to A12 ( 1A to 1L) manufacturing method.

[A14] The step of forming the sealing insulator (71) includes: A method for manufacturing a semiconductor device (1A to 1L) according to A12 or A13, comprising the step of forming

[A15] The electrode forming step includes forming the terminal electrodes (50, 60, 126) having portions covering the main surface electrodes (30, 32, 124) with the insulating film (38) interposed therebetween. A method for manufacturing a semiconductor device (1A to 1L) according to any one of A12 to A14, including

[A16] A12 to A15, wherein the step of forming the insulating film (38) includes forming the insulating film (38) including at least one of an inorganic insulating film (42) and an organic insulating film (43). A method for manufacturing a semiconductor device (1A to 1L) according to any one of .

[A17] The step of cutting the wafer (81) includes removing a portion of the sealing insulator (71) defining the wall surface of the opening (99) at the same time as cutting the wafer (81). A method for manufacturing a semiconductor device (1A to 1L) according to any one of A1 to A16, including

[A18] The step of cutting the wafer (81) includes cutting the wafer (81) at a position spaced apart from the wall surface of the opening (99) so that the sealing insulator (71) is not removed. A method for manufacturing a semiconductor device (1A to 1L) according to any one of A1 to A16, including

[A19] Any one of A1 to A18, wherein the step of forming the sealing insulator (71) includes a step of supplying a sealing agent (94) containing a thermosetting resin onto the main surface. A method for manufacturing the semiconductor device (1A to 1L) described.

[A20] The method for manufacturing a semiconductor device (1A to 1L) according to any one of A1 to A19, wherein the wafer (81) includes a wide bandgap semiconductor single crystal.

[B1] A chip (2) having a main surface (3) and side surfaces (5A to 5D), main surface electrodes (30, 32, 124) arranged on the main surface (3), and the main surface terminal electrodes (50, 60, 126) disposed on electrodes (30, 32, 124); a sealing insulator (71) covering the perimeter of said terminal electrodes (50, 60, 126) above and having an insulating sidewall (73) forming one flat surface with said side surfaces (5A-5D); semiconductor devices (1A-1L), including;

[B2] A chip (2) having a principal surface (3) and side surfaces (5A to 5D), principal surface electrodes (30, 32, 124) arranged on the principal surface (3), and the principal surface terminal electrodes (50, 60, 126) disposed on electrodes (30, 32, 124); insulating sidewalls covering the periphery of the terminal electrodes (50, 60, 126) above and spaced inwardly from the side surfaces (5A-5D) so as to define a stepped portion with the main surface (3); A semiconductor device (1A-1L) comprising an encapsulation insulator (71) having (73).

[B3] A chip (2) having a main surface (3) and side surfaces (5A to 5D), main surface electrodes (30, 32, 124) arranged on the main surface (3), and the main surface terminal electrodes (50, 60, 126) disposed on electrodes (30, 32, 124); Insulation covering the periphery of the terminal electrodes (50, 60, 126) on the top and protruding outward from the side surfaces (5A to 5D) so as to define a stepped portion with the side surfaces (5A to 5D) and an encapsulation insulator (71) having sidewalls (73).

[B4] The semiconductor device (1A-1L) according to any one of B1-B3, wherein the terminal electrodes (50, 60, 126) are thicker than the chip (2).

[B5] The semiconductor device (1A-1L) according to any one of B1-B4, wherein the sealing insulator (71) is thicker than the chip (2).

[B6] The semiconductor device (1A-1L) according to any one of B1-B5, wherein the side surfaces (5A-5D) of the chip (2) are ground surfaces having grinding marks.

[B7] The terminal electrodes (50, 60, 126) have terminal surfaces (51, 61, 127) and terminal sidewalls (52, 62, 128), and the sealing insulator (71) The semiconductor device (1A-1L) according to any one of B1-B6, wherein the surfaces (51, 61, 127) are exposed and the terminal sidewalls (52, 62, 128) are covered.

[B8] The semiconductor device according to B7 ( 1A-1L).

[B9] The semiconductor device (1A ~1 L).

[B10] The semiconductor device (1A-1L) according to any one of B1-B9, wherein the sealing insulator (71) contains a resin.

[B11] The semiconductor device (1A to 1L) according to B10, wherein the resin is a thermosetting resin.

[B12] The semiconductor device (1A to 1L) according to B10 or B11, wherein the sealing insulator (71) includes a plurality of fillers added to the resin.

[B13] The semiconductor device (1A to 1L) according to any one of B1 to B12, wherein the chip (2) includes a wide bandgap semiconductor single crystal.

[B14] The semiconductor device (1A-1L) according to any one of B1-B13, wherein the chip (2) has a laminated structure including a semiconductor substrate and an epitaxial layer.

[B15] The semiconductor device (1A to 1L) according to B14, wherein the epitaxial layer is thicker than the semiconductor substrate.

[B16] The semiconductor device (1A-1L) according to any one of B1-B13, wherein the chip (2) has a single-layer structure consisting of an epitaxial layer.

[B17] Further includes insulating films (25, 27) covering the peripheral edge of the main surface (3), and the sealing insulator (71) is disposed on the peripheral edge of the main surface (3). 25, 27), the semiconductor device (1A-1L) according to any one of B1-B16.

[B18] further includes an upper insulating film (38) covering the main surface electrodes (30, 32, 124), and the sealing insulator (71) has a portion covering the upper insulating film (38) The semiconductor device (1A-1L) according to any one of B1-B17.

[B19] The semiconductor device (1A-1L) according to B18, wherein the terminal electrodes (50, 60, 126) cover the main surface electrodes (30, 32, 124) and the upper insulating film (38) ).

[B20] The semiconductor device (1A to 1L) according to B18 or B19, wherein the upper insulating film (38) includes at least one of an inorganic insulating film (42) and an organic insulating film (43).

Although the embodiments have been described in detail above, these are only specific examples used to clarify the technical content, and the present invention should not be construed as being limited to these specific examples. The scope of the invention is limited by the appended claims.

1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 1F Semiconductor device 1G Semiconductor device 1H Semiconductor device 1I Semiconductor device 1J Semiconductor device 1K Semiconductor device 1L Semiconductor device 2 Chip 3 First main surface 5A First side surface 5B Second Side surface 5C Third side surface 5D Fourth side surface 25 Main surface insulating film 27 Interlayer insulating film 30 Gate electrode (main surface electrode)
32 source electrode (principal surface electrode)
38 Upper insulating film 42 Inorganic insulating film 43 Organic insulating film 50 Gate terminal electrode 51 Gate terminal surface 52 Gate terminal sidewall 60 Source terminal electrode 61 Source terminal surface 62 Source terminal sidewall 71 Sealing insulator 72 Insulating main surface 73 Insulating sidewall 80 Wafer Structure 81 Wafer 82 First wafer main surface 86 Device region 87 Planned cutting line 89 Second base conductor film 90 Resist mask (release mask)
93 Third opening 94 Sealant 95 Third base conductor film 95 (conductor)
97 dummy terminal electrode (dummy electrode)
98 resist mask (shielding mask)
99 dicing opening 124 first polarity electrode (principal surface electrode)
126 terminal electrode 127 terminal surface 128 terminal side wall

Claims (20)

1. a step of preparing a wafer having a main surface on which a device region and lines to be cut defining the device region are set;
   an electrode forming step of forming a dummy electrode on the line to be cut;
   forming a sealing insulator covering the periphery of the dummy electrode on the main surface so as to expose a portion of the dummy electrode;
   removing the dummy electrode and forming an opening in the sealing insulator extending along the line to be cut;
   and cutting the wafer along the opening.
2. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of thinning the wafer after the step of forming the sealing insulator and before the step of cutting the wafer.
3. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of thinning the wafer includes a step of thinning the wafer to a thickness less than the thickness of the encapsulation insulator.
4. The wafer has the main surface on which the planned cutting line surrounding the device region is set,
   the electrode forming step includes forming the dummy electrode surrounding the device region;
   4. The method of manufacturing a semiconductor device according to claim 1, wherein said step of removing said dummy electrode includes a step of forming said opening surrounding said device region.
5. The electrode forming step includes
   forming a conductor film covering the line to be cut;
   forming an open mask on the conductor film for exposing a portion of the conductor film covering the line to be cut;
   depositing a conductor by plating on a portion of the conductor film exposed from the open mask;
   5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing said release mask after said step of depositing said conductor.
6. The step of forming the sealing insulator comprises: forming the sealing insulator covering the entire area of the dummy electrode; and partially removing the sealing insulator until the dummy electrode is exposed. 6. The method of manufacturing a semiconductor device according to claim 1, comprising:
7. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of removing the sealing insulator includes a step of partially removing the sealing insulator by a grinding method.
8. further comprising providing a wafer structure having the wafer and a major surface electrode disposed over the device region of the wafer;
   The electrode forming step includes forming a terminal electrode on the main surface electrode and forming the dummy electrode on the line to be cut,
   The step of forming the sealing insulator includes forming the sealing insulator covering the periphery of the terminal electrode on the main surface so as to expose a part of the terminal electrode,
   8. The method of manufacturing a semiconductor device according to claim 1, wherein said step of removing said dummy electrode includes a step of removing said dummy electrode so as to leave said terminal electrode.
9. The main surface electrode is arranged on the device region with a gap from the line to cut,
   9. The method of manufacturing a semiconductor device according to claim 8, wherein said electrode forming step includes a step of forming said dummy electrode spaced apart from said main surface electrode.
10. 10. The method of manufacturing a semiconductor device according to claim 8, wherein said electrode forming step includes a step of forming said dummy electrode surrounding said terminal electrode.
11. 3. The step of removing the dummy electrode includes the step of exposing the dummy electrode and forming a shielding mask covering the terminal electrode, and removing the dummy electrode by an etching method through the shielding mask. 11. The method of manufacturing a semiconductor device according to any one of 8 to 10.
12. The method for manufacturing a semiconductor device according to any one of claims 8 to 11, further comprising a step of forming an insulating film covering said main surface electrode before said electrode forming step.
13. 13. The method of manufacturing a semiconductor device according to claim 12, wherein said electrode forming step includes a step of forming said dummy electrode on said line to be cut at a distance from said insulating film.
14. 14. The manufacturing of the semiconductor device according to claim 12, wherein said step of forming said sealing insulator includes a step of forming said sealing insulator having a portion covering said main surface electrode with said insulating film interposed therebetween. Method.
15. 15. The method of manufacturing a semiconductor device according to claim 12, wherein said electrode forming step includes a step of forming said terminal electrode having a portion covering said main surface electrode with said insulating film interposed therebetween. .
16. 16. The method of manufacturing a semiconductor device according to claim 12, wherein said insulating film forming step includes forming said insulating film including at least one of an inorganic insulating film and an organic insulating film. .
17. The step of cutting the wafer according to any one of claims 1 to 16, wherein the step of cutting the wafer includes a step of removing a portion of the sealing insulator that defines the wall surface of the opening simultaneously with cutting the wafer. A method of manufacturing a semiconductor device.
18. 17. The step of cutting the wafer comprises cutting the wafer at a position spaced from the walls of the opening such that the sealing insulator is not removed. A method of manufacturing a semiconductor device.
19. 19. The method of manufacturing a semiconductor device according to claim 1, wherein said sealing insulator forming step includes a step of supplying a sealing agent containing a thermosetting resin onto said main surface. .
20. The method of manufacturing a semiconductor device according to any one of claims 1 to 19, wherein the wafer includes a wide bandgap semiconductor single crystal.

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