WO2023077806A1

WO2023077806A1 - Semiconductor chip having asymmetric geometric structure and preparation method therefor

Info

Publication number: WO2023077806A1
Application number: PCT/CN2022/098174
Authority: WO
Inventors: 李鸿渐; 李璟; 王国宏
Original assignee: 南京阿吉必信息科技有限公司
Priority date: 2021-11-03
Filing date: 2022-06-10
Publication date: 2023-05-11
Also published as: CN114156372A

Abstract

Disclosed are a semiconductor chip having an asymmetric geometric structure, and a preparation method therefor. The semiconductor chip having an asymmetric geometric structure comprises a base having a recess, a substrate-free chip being provided in the recess of the base, the substrate-free chip having an asymmetric geometric structure, and a shape of the recess in the base having the recess being spatially complementary to the placed substrate-free chip. The semiconductor chip having an asymmetric geometric structure does not have a secondary axis of symmetry in its geometric structure. It is easy to identify and distinguish when the chip is reversed, overturned, or stood upright, and main front and back, top and bottom, and left and right sides of the chip, as well as positive and negative polarities of electrodes, of the chip can be identified without using an internal circuit structure or a surface marking pattern of the chip. Positioning (self-alignment) can be carried out autonomously according to a chip structure, reducing mechanical identification errors during a packaging application. When a large number of chips need to be placed in a display application, self-aligning positioning and placement are directly implemented according to complementarity of the structures of the chips and the base, improving working efficiency.

Description

A kind of asymmetric geometric structure semiconductor chip and its preparation method

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202111296104.8 and the application title "A method for preparing and using a semiconductor chip with an asymmetric geometric structure" submitted to the China Patent Office on November 03, 2021, the entire contents of which are incorporated by reference incorporated in this application.

technical field

The invention belongs to the field of semiconductor technology and application technology, and in particular relates to an asymmetric geometric structure semiconductor chip and a preparation method thereof.

Background technique

As shown in Figure 1(a) and Figure 1(b), the main geometric structure of a traditional semiconductor chip is a six-sided cuboid or cylinder, and there are multiple quadratic symmetric rotation axes in geometry. The circuit structure and logo pattern are easy to cause the front and back, up and down and left and right of the chip to be reversed during use, and the identification and positioning are confused. In chip packaging, higher requirements are put forward for the packaging process and packaging equipment.

Contents of the invention

Aiming at the deficiencies in the prior art, the object of the present invention is to provide a semiconductor chip with an asymmetric geometric structure and a preparation method thereof, which can be positioned independently according to the chip structure.

To achieve the above object, the present invention provides the following technical solutions:

A semiconductor chip with an asymmetric geometric structure, including a substrate with a groove, and a substrate-free chip in the groove of the substrate, the substrate-free chip is a geometrically asymmetric structure, and the substrate with the groove is concave The shape of the groove is spatially complementary to the substrateless chip being placed.

In the semiconductor chip with asymmetric geometric structure provided by the present invention, the substrateless chip is a geometrically asymmetric structure without a chip structure with a secondary rotational symmetry axis, and the chip can be identified without the circuit structure inside the chip and the iconic pattern on the surface. Positive and negative, up and down and left and right, and positive and negative polarity of chip electrodes. At the same time, the shape of the substrate groove is complementary to the placed chip in space. When a large number of chips need to be placed in display applications, self-alignment positioning and placement can be realized directly according to the complementarity between the chip's own structure and the substrate structure, which can improve work efficiency.

Optionally, the shape of the substrateless chip is a scalene pentahedron or a hexahedron, or a scalene heptahedron formed by a truncated rectangular parallelepiped.

Optionally, the substrateless chip is a substrateless chip with a sapphire or Si substrate peeled off, including u-GaN, n-GaN, InGaN/GaN multiple quantum wells and p-GaN, the u-GaN, n-GaN, InGaN/GaN multiple quantum wells and p-GaN together form a GaN epitaxial wafer.

Optionally, an ITO transparent conductive film is disposed above the GaN epitaxial wafer, a P electrode 1 is disposed above the ITO transparent conductive film, and an N electrode is disposed above the n-GaN on the side of the P electrode 1. electrode.

Optionally, the substrate-free chip is a substrate-free chip from which the n-GaAs substrate has been stripped, including n-AlAs and n+-GaInP, n-AlGaInP electron transport layer, AlxGa1-xInP/AlyGa1-yInP multiple quantum wells layer, a p-AlGaInP electron transport layer and a p+-GaInP ohmic contact layer, and a P electrode 2 is arranged above the p+-GaInP ohmic contact layer.

The invention provides a method for preparing a semiconductor chip with an asymmetric geometric structure, comprising the following steps:

obtain a substrate with grooves;

disposing the substrateless chip in the groove of the substrate;

Wherein, the substrate-less chip is a geometrically asymmetric structure, and the shape of the groove in the substrate with the groove is spatially complementary to the placed substrate-less chip.

The substrate-less chip prepared by the method for preparing a semiconductor chip with an asymmetric geometric structure provided by the present invention has a geometric asymmetric structure, does not have a chip structure with a secondary rotational symmetry axis, and does not need to pass through the circuit structure inside the chip and the iconic pattern on the surface It can identify the front and back, top and bottom, left and right sides of the chip, as well as the front and back polarity of the chip electrodes. At the same time, the shape of the substrate groove is complementary to the placed chip in space. When a large number of chips need to be placed in display applications, self-alignment positioning and placement can be realized directly according to the complementarity between the chip's own structure and the substrate structure, which can improve work efficiency.

Optionally, in the asymmetric geometry semiconductor chip, the substrateless chip is a substrateless chip with a sapphire or Si substrate removed, including u-GaN, n-GaN, InGaN/GaN multiple quantum wells and p-GaN, the u-GaN, n-GaN, InGaN/GaN multiple quantum wells and p-GaN jointly form a GaN epitaxial wafer; an ITO transparent conductive film is arranged above the GaN epitaxial wafer, and the ITO transparent When a P electrode 1 is arranged above the conductive film, and an N electrode is arranged above the n-GaN and on one side of the P electrode 1, the preparation method includes the following steps:

S1, growing u-GaN, n-GaN, InGaN/GaN multiple quantum wells and p-GaN sequentially on a sapphire or Si substrate to form a GaN epitaxial wafer;

S2, depositing an ITO transparent conductive film on the GaN epitaxial wafer;

S3. Etching the GaN epitaxial wafer deposited with the ITO transparent conductive film into a plurality of discrete geometrically asymmetric chip structures;

S4. Depositing a metal thin film on the discrete geometrically asymmetric chip structure, and forming electrodes of the chip by patterning;

S5, removing the sapphire or Si substrate to form a substrate-free GaN geometrically asymmetric chip;

S6. When packaging or die-bonding the above-mentioned substrate-less GaN geometrically asymmetric chip, position the substrate-less GaN geometrically asymmetric chip in the groove of the substrate with grooves having the same geometric structure.

Optionally, in step S1, the MOCVD process is used to sequentially grow u-GaN, n-GaN, InGaN/GaN multiple quantum wells and p-GaN on the sapphire or Si substrate to form a GaN epitaxial wafer;

And/or, in step S2, an ITO transparent conductive film is deposited on the GaN epitaxial wafer by an electron beam evaporation process;

And/or, in step S3, the GaN epitaxial wafer deposited with the ITO transparent conductive film is etched into a plurality of discrete geometrically asymmetric chip structures by using photolithography and ICP etching process;

And/or, in step S4, the electrode of the chip is formed by a photolithography etching process;

And/or, in step S5, the sapphire or Si substrate is removed by laser lift-off or chemical etching;

And/or, in step S6, the substrate-less GaN geometrically asymmetric chip is positioned in the groove of the substrate with grooves having the same geometric structure by mechanical vibration or fluid driving.

Optionally, in the step S4, the electrode of the chip is formed by a photolithographic etching process. If the chip has the same surface electrode structure, the P electrode 1 and the N electrode of the chip are formed; if the chip has a vertical structure, the P electrode 1 of the chip is formed. .

Optionally, in the step S6, the substrate-free GaN geometrically asymmetric chip is positioned in the groove of the substrate with grooves having the same geometric structure by mechanical vibration or fluid drive, wherein the fluid is water, ethanol , air, and nitrogen are sprayed onto the substrate-free GaN geometrically asymmetric chip under a certain pressure, and a certain mechanical thrust is given to the substrate-free GaN geometrically asymmetric chip to move the substrate-free GaN geometrically asymmetric chip into the groove.

Optionally, the bottom surface inside the groove is covered with a metal layer, and the metal layer forms a eutectic ohmic contact with the substrate-free GaN geometrically asymmetric chip electrode.

Optionally, the substrate-less GaN geometrically asymmetric chip is fixed in the groove through eutectic soldering or reflow soldering process.

Optionally, in the asymmetric geometry semiconductor chip, the substrate-free chip is a substrate-free chip with the n-GaAs substrate peeled off, including n-AlAs and n+-GaInP, n-AlGaInP electron transport layer, AlxGa1 -xInP/AlyGa1-yInP multi-quantum well layer, p-AlGaInP electron transport layer and p+-GaInP ohmic contact layer, when a P electrode 2 is arranged above the p+-GaInP ohmic contact layer, the preparation method comprises the following steps:

S1. On the n-GaAs substrate, grow n-AlAs, n+-GaInP, n-AlGaInP electron transport layer, AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer, p-AlGaInP electron transport layer and p+-GaInP ohmic contact layer to form an AlGaInP epitaxial wafer, in which n-AlAs is used as a sacrificial layer when the substrate is etched;

S2. Patterning the film layer above n-AlAs in each film layer of the AlGaInP epitaxial wafer to form a discrete geometric asymmetric phosphide chip structure;

S3, depositing a metal thin film on the above substrate, and forming a P electrode 2 through a patterning process;

Wherein, the substrate is the geometrically asymmetric phosphide chip structure prepared in step S2;

S4, carry out etching process to above-mentioned substrate, n-AlAs sacrificial layer is selectively etched away, and substrate-free chip comes off from n-GaAs substrate;

S5. When packaging or die-bonding the above-mentioned substrateless chip, position the substrateless chip in a groove having the same geometric structure as the substrate with the groove.

Optionally, in step S1, n-AlAs, n+-GaInP, n-AlGaInP electron transport layers, AlxGa1-xInP/AlyGa1-yInP multiple quantum well layers, p-AlGaInP Electron transport layer and p+-GaInP ohmic contact layer to form AlGaInP epitaxial wafer;

And/or, in step S2, photolithography and wet etching processes are performed on each film layer of the AlGaInP epitaxial wafer to etch onto the n-AlAs to form a discrete geometrically asymmetric phosphide chip structure;

And/or, in step S3, the P electrode 2 is formed by a photolithography etching process;

And/or, in step S4, the HF etching process is performed on the substrate, the n-AlAs sacrificial layer is selectively etched away by HF acid, and the substrate-free chip is detached from the n-GaAs substrate;

And/or, in step S5, when packaging or die-bonding the above-mentioned substrateless chip, the substrateless chip is positioned in a groove having the same geometric structure as the substrate with the groove by mechanical vibration or fluid drive.

Optionally, in step S5, when packaging or die-bonding the above-mentioned substrateless chip, the substrateless chip is positioned in a groove with the same geometric structure as the substrate with the groove by mechanical vibration or fluid drive ; Among them, the fluid is water, ethanol, air, nitrogen, which is sprayed onto the substrate-free chip under a certain pressure, and a certain mechanical thrust is given to the substrate-free chip to move the substrate-free chip into the groove to achieve self-alignment craft.

Optionally, the bottom surface inside the groove is plated with a fusible alloy to form an electrical conduction contact with the n+-GaInP of the substrate-free chip through heating or alloy melting.

Optionally, the bottom surface inside the groove is plated with AuSn alloy.

Description of drawings

Fig. 1 (a) is a schematic diagram of a traditional semiconductor chip with a secondary rotational symmetry axis structure, wherein the semiconductor chip is a cuboid chip;

Fig. 1 (b) is a schematic diagram of a traditional semiconductor chip with a secondary rotational symmetry axis structure, wherein the semiconductor chip is a columnar chip;

Fig. 2 (a) is the schematic diagram of the heptahedral semiconductor chip in the present invention formed after the cuboid semiconductor chip is truncated;

Fig. 2 (b) is the schematic diagram of the semiconductor chip of scalene pentahedron of the present invention;

Fig. 2 (c) is the schematic diagram of the unequal hexahedron semiconductor chip of the present invention;

Fig. 3 is a schematic structural view of a chip without a substrate in the present invention (with electrodes on the same surface, and the substrate has not been removed);

Fig. 4 is a schematic structural view of a chip without a substrate after etching in the present invention (the substrate has not been removed);

Figure 5(a) is a schematic structural view of the substrate-free chip with electrodes on the same surface after the substrate is peeled off;

Figure 5(b) is a schematic structural view of a vertical substrate-less chip after peeling off the substrate;

Fig. 6 is a structural schematic diagram of positioning a substrate-less chip in a groove with the same geometric structure;

FIG. 7 is a schematic structural diagram of another substrateless chip (phosphide semiconductor chip) in the present invention. In the figure: 11. Sapphire or Si substrate; 12. u-GaN; 13. n-GaN; 14. InGaN/GaN multiple quantum wells; 15. p-GaN; 16. ITO transparent conductive film; 17. P electrode one ; 18, N electrode;

21. n-GaAs substrate; 22. n-AlAs; 23. n+-GaInP; 24. n-AlGaInP electron transport layer; 25. AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer; 26. p-AlGaInP electron transport layer; 27, p+-GaInP ohmic contact layer; 28, P electrode two;

3. Substrate with grooves.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 6, the semiconductor chip with asymmetric geometric structure provided by this embodiment includes a substrate 3 with grooves. There are substrate-free chips in the grooves of the substrate. The shape of the recess in the substrate of the slot is spatially complementary to the chip to be placed.

In the semiconductor chip with asymmetric geometric structure provided in this embodiment, the substrate-less chip is a geometrically asymmetric structure without a chip structure with a secondary rotational symmetry axis, and the chip can be identified without the circuit structure inside the chip and the iconic pattern on the surface The front and back, up and down and left and right sides, and the front and back polarity of the chip electrodes. At the same time, the shape of the substrate groove is complementary to the placed chip in space. When a large number of chips need to be placed in display applications, self-alignment positioning and placement can be realized directly according to the complementarity between the chip's own structure and the substrate structure, which can reduce Mechanically identify errors during packaging applications and improve work efficiency.

The substrateless chip is a geometrically asymmetric structure. In an optional implementation, as shown in Figure 2(a)-Figure 2(c), the shape of the substrateless chip is a scalene pentahedron or hexahedron, or a sectional A scalene heptahedron formed by an angular cuboid.

When the above-mentioned substrateless chip is specifically set, as shown in FIG. 3, in an optional implementation mode, the substrateless chip is a substrateless chip with the sapphire or Si substrate 11 peeled off, including u-GaN12, n- GaN13, InGaN/GaN multiple quantum wells 14 and p-GaN15, the u-GaN12, n-GaN13, InGaN/GaN multiple quantum wells 14 and p-GaN15 jointly form a GaN epitaxial wafer.

Further, please continue to refer to FIG. 3. In an optional implementation mode, an ITO transparent conductive film 16 is disposed above the GaN epitaxial wafer, a P electrode-17 is disposed above the ITO transparent conductive film 16, and a p-electrode 17 is disposed above the n-GaN13. And an N electrode 18 is disposed on one side of the P electrode one 17 .

When specifically setting the above-mentioned substrateless chip, as shown in Figure 7, in another optional implementation, the substrateless chip is a substrateless chip with the n-GaAs21 substrate stripped off, including n-AlAs22 and n+- GaInP23, n-AlGaInP electron transport layer 24, AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer 25, p-AlGaInP electron transport layer 26 and p+-GaInP ohmic contact layer 27, above the p+-GaInP ohmic contact layer 27 A second P electrode 28 is provided.

The method for preparing a semiconductor chip with an asymmetric geometric structure provided in this embodiment includes the following steps:

Step 1, obtaining a substrate with grooves;

Step 2, disposing the substrateless chip in the groove of the substrate;

Wherein, the substrateless chip has a geometrically asymmetric structure, and the shape of the groove in the substrate with the groove is complementary to the placed chip in space.

The substrateless chip prepared by the method for preparing a semiconductor chip with an asymmetric geometric structure provided in this embodiment has a geometric asymmetric structure, and does not have a chip structure with a secondary rotational symmetry axis. It can identify the front and back, top and bottom, left and right sides of the chip, as well as the front and back polarity of the chip electrodes. At the same time, the shape of the substrate groove is complementary to the placed chip in space. When a large number of chips need to be placed in display applications, self-alignment positioning and placement can be realized directly according to the complementarity between the chip's own structure and the substrate structure, which can improve work efficiency.

It should be noted that the above-mentioned "the shape of the groove in the substrate with the groove is complementary to the placed chip in space", that is, the shape and size of the groove on the substrate are compatible with the shape and size of the placed chip. Suitably, the chips can be positioned in corresponding recesses on the substrate.

The substrateless chip has a geometrically asymmetric structure. Exemplarily, the substrateless chip can be in the shape of a scalene pentahedron or a hexahedron, or a scalene heptahedron formed by a truncated rectangular parallelepiped.

In an optional implementation, when the substrateless chip in the semiconductor chip with an asymmetric geometry is a substrateless chip with the sapphire or Si substrate 11 peeled off, the substrateless chip includes u-GaN12, n-GaN13, InGaN/GaN multi-quantum well 14 and p-GaN15, the u-GaN12, n-GaN13, InGaN/GaN multi-quantum well 14 and p-GaN15 jointly form a GaN epitaxial wafer; the top of the GaN epitaxial wafer is provided with ITO Transparent conductive film 16, when the top of the ITO transparent conductive film 16 is provided with a P electrode-17, and when an N-electrode 18 is provided above the n-GaN13 and on one side of the P-electrode 17, the semiconductor chip with asymmetric geometry The preparation method comprises the following steps:

S1, growing u-GaN12, n-GaN13, InGaN/GaN multiple quantum wells 14 and p-GaN15 sequentially on a sapphire or Si substrate 11 to form a GaN epitaxial wafer;

S2, depositing an ITO transparent conductive film 16 on the GaN epitaxial wafer;

S3. Etching the GaN epitaxial wafer deposited with the ITO transparent conductive film 16 into a plurality of discrete geometrically asymmetric chip structures;

S5. Remove the sapphire or Si substrate 11 to form a substrate-free GaN geometrically asymmetric chip (ie, the aforementioned substrate-free chip);

S6. When packaging or die-bonding the above-mentioned substrate-less GaN geometrically asymmetric chip, position the substrate-less GaN geometrically asymmetric chip in the groove of the substrate 3 with grooves having the same geometric structure.

Further, in an optional implementation mode, in step S1, u-GaN12, n-GaN13, InGaN/GaN multiple quantum wells 14 and p-GaN15 are sequentially grown on the sapphire or Si substrate 11 by MOCVD process to form GaN epitaxial wafer;

In an optional implementation, in step S2, an ITO transparent conductive film 16 is deposited on the GaN epitaxial wafer by an electron beam evaporation process;

In an optional implementation, in step S3, the GaN epitaxial wafer deposited with the ITO transparent conductive film 16 is etched into a plurality of discrete geometrically asymmetric chip structures by photolithography and ICP etching processes;

In an optional implementation manner, in step S4, the electrode of the chip is formed by a photolithography etching process; specifically, after coating, the electrode of the chip is formed by a photolithography etching process.

In an optional implementation, in step S4, the electrodes of the chip are formed by a photolithographic etching process, and if the chip has the same surface electrode structure, the P electrode 17 and the N electrode 18 of the chip are formed, as shown in Figure 5 (a) If it is a vertical structure chip, the P electrode-17 of the chip is formed, as shown in FIG. 5(b).

In an optional implementation, in step S5, the sapphire or Si substrate 11 is removed by laser lift-off or chemical etching;

In an optional implementation manner, in step S6, the substrate-less GaN geometrically asymmetric chip is positioned in the groove of the substrate 3 with grooves having the same geometric structure through mechanical vibration or fluid drive.

In an optional implementation, in step S6, the substrate-less GaN geometrically asymmetric chip is positioned in the groove of the substrate 3 with the same geometric structure by mechanical vibration or fluid drive, wherein the fluid Water, ethanol, air, and nitrogen are sprayed onto the substrate-free GaN geometrically asymmetric chip under a certain pressure, and a certain mechanical thrust is given to the substrate-free GaN geometrically asymmetric chip to move the substrate-free GaN geometrically asymmetric chip to in the groove.

With the application of Internet of Things and 5G communication network technology, Mini LED and Micro LED 4K/8K ultra-high-definition (UHD) smart displays equipped with 5G will become a hotspot for the next generation of new displays. The 4K full-color display requires 3×8kk light-emitting chips and corresponding driver chips. If the chips are placed using the traditional die-bonding process, the speed is slow, the cost is high, and the efficiency needs to be improved. In this embodiment, the chip is moved into the groove by the fluid, which is faster, lower in cost and higher in efficiency.

It should be noted that the specific values of the pressure of the fluid and the mechanical thrust of the fluid acting on the chip can be obtained through experiments, as long as the chip can be pushed into the corresponding groove without damaging the chip.

In an optional implementation manner, the bottom surface inside the groove is covered with a metal layer, and the metal layer forms a eutectic ohmic contact with the substrate-free GaN geometrically asymmetric chip electrode.

Further, in an optional implementation manner, the substrate-less GaN geometrically asymmetric chip is fixed in the groove through eutectic soldering or reflow soldering process.

In the asymmetric geometry semiconductor chip, the substrate-free chip is a substrate-free chip that has stripped the n-GaAs21 substrate, including n-AlAs22 and n+-GaInP23, n-AlGaInP electron transport layer 24, AlxGa1-xInP/AlyGa1- yInP multi-quantum well layer 25, p-AlGaInP electron transport layer 26 and p+-GaInP ohmic contact layer 27, when the top of the p+-GaInP ohmic contact layer 27 is provided with a P electrode 28, the semiconductor chip with asymmetric geometry The preparation method comprises the following steps:

S1. On the n-GaAs substrate 21, grow n-AlAs22, n+-GaInP23, n-AlGaInP electron transport layer 24, AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer 25, p-AlGaInP electron transport layer 26 and p+ -GaInP ohmic contact layer 27, forming an AlGaInP epitaxial wafer, wherein n-AlAs22 is used as a sacrificial layer when the substrate is etched;

S2. Patterning the film layer above n-AlAs22 in each film layer of the AlGaInP epitaxial wafer to form a discrete geometric asymmetric phosphide chip structure;

S3, depositing a metal thin film on the above substrate, and forming a P electrode 228 through a patterning process;

S4, performing an etching process on the above-mentioned substrate, selectively etching away the n-AlAs sacrificial layer, and the substrate-free chip falls off from the n-GaAs21 substrate;

S5. When packaging or die-bonding the above-mentioned substrateless chip, position the substrateless chip in a groove having the same geometric structure as the substrate 3 with the groove.

In an optional implementation, in step S1, n-AlAs22, n+-GaInP23, and n-AlGaInP electron transport layer 24 are sequentially grown on n-GaAs substrate 21 by using MOCVD process, and AlxGa1-xInP/AlyGa1-yInP multi The quantum well layer 25, the p-AlGaInP electron transport layer 26 and the p+-GaInP ohmic contact layer 27 form an AlGaInP epitaxial wafer.

In an optional implementation, in step S2, photolithography and wet etching processes are performed on each film layer of the AlGaInP epitaxial wafer, and etched onto the n-AlAs22 to form a discrete geometrically asymmetric phosphide chip structure;

In an optional implementation manner, in step S3, the second P electrode 28 is formed by a photolithography etching process; specifically, after the coating, the second P electrode 28 is formed by a photolithography etching process.

In an optional implementation, in step S4, the HF etching process is performed on the substrate, the HF acid selectively etches the n-AlAs sacrificial layer, and the substrate-free chip falls off from the n-GaAs21 substrate;

In an optional implementation mode, in step S5, when packaging or die-bonding the above-mentioned substrateless chip, the substrateless chip is positioned on the substrate 3 with the same geometric structure through mechanical vibration or fluid drive. in the groove.

In an optional implementation, in step S5, when packaging or die-bonding the above-mentioned substrateless chip, the substrateless chip is positioned on the substrate 3 with the same geometric structure by mechanical vibration or fluid drive In the groove; wherein, the fluid is water, ethanol, air, nitrogen, sprayed on the substrate-free chip under a certain pressure, and a certain mechanical thrust is given to the substrate-free chip to move the substrate-free chip into the groove. A self-aligned process is realized.

With the application of Internet of Things and 5G communication network technology, Mini LED and Micro LED 4K/8K ultra-high-definition (UHD) smart displays equipped with 5G will become a hot spot for the next generation of new displays. The 4K full-color display requires 3×8kk light-emitting chips and corresponding driver chips. If the chips are placed using the traditional die-bonding process, the speed is slow, the cost is high, and the efficiency needs to be improved. In this embodiment, the chip is moved into the groove by the fluid, which is faster, lower in cost and higher in efficiency.

In an optional implementation manner, the bottom surface inside the groove is plated with a fusible alloy, and forms an electrical conduction contact with the n+-GaInP of the substrate-less chip by heating or melting the alloy. Exemplarily, the bottom surface inside the groove is plated with AuSn alloy.

In the traditional semiconductor chip preparation, the wafer is split into chips by mechanical grinding wheel saw or laser. This splitting is often carried out along the lattice cleavage plane of the semiconductor wafer, and the semiconductor lattice cleavage plane often has crystallographic properties. High symmetry, especially in the cubic and hexagonal crystal systems, these cleavage planes have multiple secondary rotational symmetry axes, as shown in Figure 1(a) and Figure 1(b) below.

The shape of the substrateless chip in this embodiment is formed by chemical etching or ion bombardment etching. The chemical etching liquid or bombardment etching ions used for chip structures of different materials are different, the process is simple, and the application is wide and flexible. . The substrate or base of the chip is peeled off by laser vaporization to form an asymmetric independent chip separated from the substrate or base.

When the semiconductor chip of the present invention is packaged and solidified, it can be driven to the position to be placed by mechanical vibration or fluid, which has a groove whose shape can be matched with the placed chip. Complementary in space, that is, the chip can only be placed in the cavity in a certain direction. The mechanical vibration can be ultrasonic or infrasonic, and the fluid can be water, ethanol, air, or nitrogen sprayed onto the chip under a certain pressure to give the chip a certain mechanical thrust to move the chip. During chip packaging and die bonding, the accuracy requirements for the positioning recognition system are greatly reduced, and positioning can be achieved through vibration or fluid-driven self-assembly methods, greatly improving the speed of packaging and die bonding, and reducing costs. Although it is relatively complicated in terms of process preparation, it is compatible with conventional semiconductor processes, and the increase in manufacturing costs is limited. Overall, the package application cost of the semiconductor chip can be greatly reduced.

Compared with prior art, the beneficial effect of the present invention is:

1. The chip of this embodiment does not have a secondary symmetrical rotation axis in terms of geometric structure. When the chip is turned upside down, flipped or erected, it is easy to be identified and distinguished, and the chip can be identified without the circuit structure inside the chip and the iconic pattern on the surface The main front and back, up and down and left and right sides, as well as the front and back polarity of the chip electrodes.

2. The shape of the semiconductor chip in this embodiment is formed by selective mask chemical etching or ion bombardment etching. Different chemical etching solutions or bombardment etching ions are selected according to the material structure of the chip. The process is simple and the cost is low. Broad and flexible.

3. When the semiconductor chip in this embodiment is packaged and bonded, it is different from traditional die bonding by machine vision. It is driven by mechanical vibration or fluid, and realizes self-alignment positioning and positioning according to the geometric space complementarity between the structure of the chip itself and the structure of the substrate. Placement improves work efficiency and reduces costs.

Embodiment one:

Please refer to Fig. 2-6, present embodiment provides a kind of technical scheme: a kind of semiconductor chip of asymmetric geometry structure, comprises the substrate with the groove and the substrateless chip complementary on the space with groove, substrateless chip Including u-GaN12, n-GaN13, InGaN/GaN multiple quantum wells 14 and p-GaN15, u-GaN12, n-GaN13, InGaN/GaN multiple quantum wells 14 and p-GaN15 together form GaN epitaxial wafers, GaN epitaxial wafers An ITO transparent conductive film 16 is provided above the ITO transparent conductive film 16, a P electrode 17 is provided above the ITO transparent conductive film 16, and an N electrode 18 is provided above the n-GaN 13 and on one side of the P electrode 17.

A method for preparing a semiconductor chip with an asymmetric geometric structure: comprising the following steps:

Step S01 , growing u-GaN 12 , n-GaN 13 , InGaN/GaN multiple quantum wells 14 and p-GaN 15 sequentially on a sapphire or Si substrate 11 by MOCVD process to form a GaN epitaxial wafer.

Step S02 , depositing an ITO transparent conductive film 16 on the GaN epitaxial wafer by electron beam evaporation process.

Step S03, using photolithography and ICP etching process to etch the GaN epitaxial wafer deposited with the ITO transparent conductive film 16 into a plurality of discrete geometrically asymmetric chip structures. Exemplarily, the shape of the geometrically asymmetric chip structure can be A scalene pentahedron or hexahedron, or a scalene heptahedron formed by a truncated cuboid.

Step S04, depositing a metal thin film on the above-mentioned discrete geometrically asymmetric chip structure, forming the electrode of the chip through a photolithography etching process, if it is a chip with the same surface electrode structure, forming the P electrode 17 and the N electrode 18 of the chip; if it is vertical Structure the chip to form a P electrode 17 of the chip.

Step S05 , removing the sapphire or Si substrate 11 by laser lift-off or chemical etching to form a substrate-free GaN geometrically asymmetric chip.

Step S06, when packaging or bonding the above-mentioned substrate-less GaN geometrically asymmetric chip, the chip is positioned in the groove of the substrate 3 with the same geometric structure through mechanical vibration or fluid drive, wherein the fluid can It is water, ethanol, air, and nitrogen, which are sprayed onto the chip under a certain pressure, giving the chip a certain mechanical thrust to move the chip into the groove, and realizing the self-alignment process. The bottom surface inside the groove can be covered with a metal layer, and the metal layer can form eutectic ohmic contact with the chip electrode, and the chip can be firmly fixed in the groove through eutectic soldering or reflow soldering process.

Embodiment two:

Please refer to Fig. 7, present embodiment provides a kind of technical scheme: a kind of semiconductor chip of asymmetric geometry structure, comprises the substrate with the groove and the substrateless chip that is complementary in space with the groove, and the substrateless chip comprises n -AlAs22 and n+-GaInP23, n-AlGaInP electron transport layer 24, AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer 25, p-AlGaInP electron transport layer 26 and p+-GaInP ohmic contact layer 27, p+-GaInP ohmic contact layer The top of the 27 is provided with a P electrode 2 28 .

Step M1, growing n-AlAs22, n+-GaInP23, n-AlGaInP electron transport layer 24, AlxGa1-xInP/AlyGa1-yInP multi-quantum well layer 25, and p-AlGaInP electron transport layer sequentially on n-GaAs substrate 21 by MOCVD process Layer 26 and p+-GaInP ohmic contact layer 27 form an AlGaInP epitaxial wafer, wherein n-AlAs22 is used as a sacrificial layer when the substrate is etched.

Step M2, performing photolithography and wet etching processes on each film layer of the AlGaInP epitaxial wafer, etching onto the n-AlAs22 to form a discrete geometrically asymmetric phosphide chip structure, for example, a geometrically asymmetric phosphide chip structure The shape of can be a scalene pentahedron or hexahedron, or a scalene heptahedron formed by a truncated cuboid.

Step M3 , depositing a metal thin film on the above substrate (geometrically asymmetric phosphide chip structure), and forming a P electrode 2 28 through a photolithographic etching process.

Step M4, performing HF etching process on the above substrate, HF acid selectively etches away the n-AlAs sacrificial layer, and the geometrically asymmetric AlGaInP chip (ie, substrateless chip) falls off from the n-GaAs21 substrate.

Step M5, when packaging or solidifying the above-mentioned geometrically asymmetric AlGaInP chip, the chip is positioned in the groove with the same geometric structure on the substrate 3 with the groove through mechanical vibration or fluid drive, and the fluid can be water, ethanol, air , Nitrogen, sprayed onto the chip under a certain pressure, give the chip a certain mechanical thrust to move the chip into the groove, and realize the self-alignment process. The bottom surface inside the groove is plated with a fusible alloy (for example: AuSn alloy), which forms an electrical conduction contact with n+-GaInP of the chip by heating or alloy melting.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and modifications, the scope of the invention is defined by the appended claims and their equivalents.

Claims

A semiconductor chip with an asymmetric geometric structure is characterized in that: it includes a substrate (3) with a groove, and there is a substrate-free chip in the groove of the substrate, the substrate-free chip is a geometrically asymmetric structure, and the strip with The shape of the grooves in the grooved substrate is spatially complementary to the substrateless chip on which it is placed.
The semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the shape of the substrateless chip is a scalene pentahedron or a hexahedron, or a scalene heptahedron formed by a truncated rectangular parallelepiped.
A semiconductor chip with an asymmetric geometric structure according to claim 2, characterized in that: the substrateless chip is a substrateless chip that has been stripped of a sapphire or Si substrate (11), comprising u-GaN (12) , n-GaN (13), InGaN/GaN multiple quantum wells (14) and p-GaN (15), the u-GaN (12), n-GaN (13), InGaN/GaN multiple quantum wells (14) Together with p-GaN(15), GaN epitaxial wafers are formed.
A semiconductor chip with an asymmetric geometric structure according to claim 3, characterized in that: an ITO transparent conductive film (16) is provided above the GaN epitaxial wafer, and a transparent conductive film (16) is provided above the ITO transparent conductive film (16). P electrode one (17), an N electrode (18) is arranged above the n-GaN (13) and on one side of the P electrode one (17).
A semiconductor chip with an asymmetric geometric structure according to claim 1, characterized in that: the substrateless chip is a substrateless chip from which the n-GaAs (21) substrate has been stripped, comprising n-AlAs (22) And n+-GaInP (23), n-AlGaInP electron transport layer (24), AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer (25), p-AlGaInP electron transport layer (26) and p+-GaInP ohmic contact layer ( 27), a second P electrode (28) is arranged above the p+-GaInP ohmic contact layer (27).
A method for preparing a semiconductor chip with an asymmetric geometric structure, comprising the steps of:

obtaining a substrate with grooves;

disposing the substrateless chip in the groove of the substrate;

Wherein, the substrate-less chip is a geometrically asymmetric structure, and the shape of the groove in the substrate with the groove is spatially complementary to the placed substrate-less chip.
The method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 6, wherein the shape of the substrate-less chip is a scalene pentahedron or a hexahedron, or a scalene heptahedron formed by a truncated rectangular parallelepiped .
The method for preparing an asymmetric geometric structure semiconductor chip according to claim 7, wherein when the asymmetric geometric structure semiconductor chip is the asymmetric geometric structure semiconductor chip described in claim 4, the preparation method comprises the following steps: step:

S1, growing u-GaN (12), n-GaN (13), InGaN/GaN multiple quantum wells (14) and p-GaN (15) sequentially on a sapphire or Si substrate (11) to form a GaN epitaxial wafer;

S2, GaN epitaxial wafer deposition ITO transparent conductive film (16);

S3. Etching the GaN epitaxial wafer deposited with the ITO transparent conductive film (16) into a plurality of discrete geometric asymmetric chip structures;

S4. Depositing a metal thin film on the discrete geometrically asymmetric chip structure, and forming electrodes of the chip by patterning;

S5, removing the sapphire or Si substrate (11) to form a substrate-free GaN geometric asymmetric chip;

S6. When packaging or die-bonding the above-mentioned substrate-less GaN geometrically asymmetric chip, position the substrate-less GaN geometrically asymmetric chip in the groove of the substrate (3) with grooves having the same geometric structure.
The method for preparing an asymmetric geometry semiconductor chip according to claim 8, characterized in that:

In step S1, u-GaN (12), n-GaN (13), InGaN/GaN multiple quantum wells (14) and p-GaN (15) are sequentially grown on the sapphire or Si substrate (11) by MOCVD process, Form GaN epitaxial wafers;

And/or, in step S2, an ITO transparent conductive film (16) is deposited on the GaN epitaxial wafer by an electron beam evaporation process;

And/or, in step S3, the GaN epitaxial wafer deposited with the ITO transparent conductive film (16) is etched into a plurality of discrete geometrically asymmetric chip structures by photolithography and ICP etching process;

And/or, in step S4, the electrode of the chip is formed by a photolithography etching process;

And/or, in step S5, the sapphire or Si substrate (11) is removed by laser lift-off or chemical etching;

And/or, in step S6, the substrate-less GaN geometrically asymmetric chip is positioned in the groove of the substrate (3) with grooves having the same geometric structure through mechanical vibration or fluid driving.
A method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 9, characterized in that: in the step S4, the electrode of the chip is formed by a photolithographic etching process, and if the chip has the same electrode structure, the electrode of the chip is formed P electrode one (17) and N electrode (18); if the vertical structure chip, then form the P electrode one (17) of the chip.
The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 9, characterized in that: in the step S6, the substrate-less GaN geometrically asymmetric chip is positioned to have the same geometric structure by mechanical vibration or fluid drive In the grooves of the substrate (3) with grooves, the fluids are water, ethanol, air, nitrogen, which are sprayed on the substrate-free GaN geometry asymmetric chip under a certain pressure, giving the substrate-free GaN geometry Asymmetric chip A certain mechanical thrust moves the substrate-free GaN geometrically asymmetric chip into the groove.
A method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 11, characterized in that: the bottom surface inside the groove is covered with a metal layer, and the metal layer forms a eutectic with the substrate-free GaN geometric asymmetric chip electrode ohmic contact.
The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 12, characterized in that the substrate-less GaN geometric asymmetric chip is fixed in the groove through eutectic soldering or reflow soldering process.
The method for preparing an asymmetric geometric structure semiconductor chip according to claim 6, wherein when the asymmetric geometric structure semiconductor chip is the asymmetric geometric structure semiconductor chip described in claim 5, the preparation method comprises the following steps: step:

S1, growing n-AlAs (22), n+-GaInP (23), n-AlGaInP electron transport layer (24) sequentially on n-GaAs substrate (21), AlxGa1-xInP/AlyGa1-yInP multiple quantum well layer ( 25), a p-AlGaInP electron transport layer (26) and a p+-GaInP ohmic contact layer (27), forming an AlGaInP epitaxial wafer, wherein n-AlAs (22) is used as a sacrificial layer when the substrate is etched;

S2, patterning the film layer above n-AlAs(22) in each film layer of the AlGaInP epitaxial wafer to form a discrete geometric asymmetric phosphide chip structure;

S3, depositing a thin metal film on the substrate, and forming a P electrode 2 (28) through a patterning process;

Wherein, the substrate is the geometrically asymmetric phosphide chip structure prepared in step S2;

S4, performing an etching process on the above-mentioned substrate, selectively etching away the n-AlAs sacrificial layer, and the substrate-free chip falls off from the n-GaAs (21) substrate;

S5. When packaging or die-bonding the above-mentioned substrateless chip, position the substrateless chip in the groove with the same geometric structure of the substrate (3) with the groove.
The method for preparing an asymmetric geometry semiconductor chip according to claim 14, characterized in that:

In step S1, n-AlAs (22), n+-GaInP (23), n-AlGaInP electron transport layer (24), AlxGa1-xInP/AlyGa1-yInP are sequentially grown on the n-GaAs substrate (21) by MOCVD process A multi-quantum well layer (25), a p-AlGaInP electron transport layer (26) and a p+-GaInP ohmic contact layer (27), forming an AlGaInP epitaxial wafer;

And/or, in step S2, photolithography and wet etching processes are performed on each film layer of the AlGaInP epitaxial wafer to etch onto the n-AlAs(22) to form a discrete geometrically asymmetric phosphide chip structure;

And/or, in step S3, form P electrode 2 (28) by photolithography etching process;

And/or, in step S4, the HF etching process is performed on the substrate, and the n-AlAs sacrificial layer is selectively etched away by HF acid, and the substrate-free chip is detached from the n-GaAs (21) substrate;

And/or, in step S5, when packaging or bonding the above-mentioned substrateless chip, the substrateless chip is positioned in the groove with the same geometric structure of the substrate (3) with the groove through mechanical vibration or fluid drive .
The method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 15, characterized in that: in step S5, when packaging or solidifying the above-mentioned substrateless chip, the substrateless substrate is driven by mechanical vibration or fluid. The chip is positioned in the groove with the same geometric structure of the substrate (3) with the groove; wherein, the fluid is water, ethanol, air, nitrogen, and is sprayed on the substrate-free chip under a certain pressure to give the substrate-free A certain mechanical thrust of the chip makes the substrate-less chip move into the groove to realize the self-alignment process.
The method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 16, characterized in that: the bottom surface inside the groove is coated with a fusible alloy, and an electrical conduction is formed with n+-GaInP of the substrate-less chip by heating or alloy melting. contact.
The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 17, characterized in that: the bottom surface inside the groove is plated with AuSn alloy.