WO2023074382A1

WO2023074382A1 - Semiconductor element, imaging element, and electronic apparatus

Info

Publication number: WO2023074382A1
Application number: PCT/JP2022/038159
Authority: WO
Inventors: 卓朗楢村; 忍朝山; 進大小林; 進舍川
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2021-10-26
Filing date: 2022-10-13
Publication date: 2023-05-04
Also published as: JP2023064359A

Abstract

The present technology relates to a semiconductor element, an imaging element, and an electronic apparatus that allow for miniaturization of a semiconductor element comprising a plurality of transistors. The semiconductor element comprises a plurality of transistors connected in series, and sidewalls provided for the transistors. A first sidewall provided between adjacent transistors is provided without a gap between gate electrodes of the transistors. The width of the first sidewall is less than or equal to twice the width of a second sidewall provided in a region corresponding to sources or drains of the plurality of transistors. The present technology is applicable to a semiconductor element comprising a plurality of transistors and an imaging device comprising such semiconductor elements.

Description

Semiconductor devices, imaging devices, electronic devices

The present technology relates to a semiconductor device, an imaging device, and an electronic device, and, for example, to a semiconductor device, an imaging device, and an electronic device suitable for miniaturizing a semiconductor device on which a plurality of transistors are mounted.

An imaging device (image sensor) having a mechanism for switching the conversion efficiency of a floating diffusion (FD) provided in each pixel has been proposed (see Patent Document 1).

The technique according to Patent Document 1 is based on a general CMOS (Complementary Metal Oxide Semiconductor) image sensor, and a gate is provided to switch between the first FD and the second FD having a larger capacity than the first FD. there is When the conversion efficiency is to be high, the gate is turned off to minimize the parasitic capacitance to the first FD. to maximize the parasitic capacitance.

Japanese Patent Application Laid-Open No. 2014-112580

In the case of an image sensor equipped with a mechanism for switching conversion efficiency, a region is required for providing multiple FDs and arranging transistors for switching the FDs. In recent years, pixel miniaturization has progressed, and there is concern that an increase in the area for arranging an FD and a transistor will hinder miniaturization. In order to miniaturize pixels, it is desired to reduce the area for arranging transistors.

This technology has been developed in view of such circumstances, and enables the area for arranging transistors to be reduced.

A semiconductor device according to one aspect of the present technology includes a plurality of transistors connected in series and sidewalls provided in the transistors, wherein the first sidewalls provided between the adjacent transistors are , a semiconductor element provided without a gap between the gate electrodes of the transistor.

An imaging device according to one aspect of the present technology includes a photoelectric conversion unit that converts light into charge, a plurality of storage units that temporarily store the charge, and a plurality of transfer transistors that transfer the charge to the storage unit, A first sidewall provided between the plurality of transfer transistors is an imaging device provided without a gap between gate electrodes of the transfer transistors.

An electronic device according to one aspect of the present technology includes a photoelectric conversion unit that converts light into charge, a plurality of storage units that temporarily store the charge, and a plurality of transfer transistors that transfer the charge to the storage unit, The first sidewall provided between the plurality of transfer transistors includes an imaging device provided without a gap between gate electrodes of the transfer transistors, and a processing unit that processes signals from the imaging device. An electronic device comprising

A semiconductor device according to one aspect of the present technology includes a plurality of transistors connected in series and sidewalls provided in the transistors. It is provided without a gap between the gate electrodes.

An imaging device according to one aspect of the present technology includes a photoelectric conversion unit that converts light into electric charges, a plurality of storage units that temporarily store the charges, and a plurality of transfer transistors that transfer the charges to the storage units. , the sidewalls provided between the plurality of transfer transistors are provided without gaps between the gate electrodes of the transfer transistors.

An electronic device according to one aspect of the present technology is configured to include the imaging element.

It should be noted that the electronic device may be an independent device, or may be an internal block that constitutes one device.

It is a figure showing an example of circuit composition of a semiconductor element in one embodiment to which this art is applied. It is a figure which shows the cross-sectional structural example of the semiconductor element in 1st Embodiment. It is a figure which shows the example of a planar structure of the semiconductor element in 1st Embodiment. It is a figure for demonstrating the width of a sidewall. It is a figure which shows the circuit structural example of the semiconductor element in 2nd Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 2nd Embodiment. It is a figure which shows the planar structural example of the semiconductor element in 2nd Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 3rd Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 3rd Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 3rd Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 3rd Embodiment. It is a figure which shows the circuit structural example of the semiconductor element in 4th Embodiment. It is a figure which shows the planar structural example of the semiconductor element in 4th Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 4th Embodiment. It is a figure which shows the cross-sectional structural example of the semiconductor element in 4th Embodiment. It is a figure which shows the structural example of an imaging device. It is a figure which shows the circuit structural example of a pixel. It is a figure which shows the cross-sectional structural example of the semiconductor element in 5th Embodiment. FIG. 4 is a diagram for explaining the operation of a pixel; FIG. It is a figure which shows the structural example of an electronic device. 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system; FIG. 3 is a block diagram showing an example of functional configurations of a camera head and a CCU; FIG.

A form (hereinafter referred to as an embodiment) for implementing the present technology will be described below.

<First Embodiment>
FIG. 1 is a diagram showing a circuit configuration example in one embodiment of a semiconductor device to which the present technology is applied. The semiconductor element 10a is composed of a transistor 11 and a transistor 12 connected in series.

FIG. 2 is a diagram showing a cross-sectional configuration example of the semiconductor element 10a.

Diffusion regions

32 and 33 in which N-type impurities are diffused are provided in a P-type semiconductor substrate 31 .

Here, an N-type transistor will be taken as an example, but the present technology can also be applied to a P-type transistor.

The

diffusion regions

32 and 33 are regions corresponding to the sources or drains of the

transistors

11 and 12 .

An oxide film 36 is formed on the semiconductor substrate 31 . A gate electrode 37 of the transistor 11 and a gate electrode 38 of the transistor 12 are provided on the oxide film 36 .

The

gate electrodes

37 and 38 are each surrounded by sidewalls. In the cross-sectional configuration example shown in FIG. 2, a sidewall 39 is provided on the left side of the gate electrode 37 in the drawing, and a sidewall 40 is provided on the right side of the drawing. Similarly, a sidewall 40 is provided on the left side of the gate electrode 38 in the drawing, and a sidewall 41 is provided on the right side of the drawing.

The sidewall 40 is a sidewall formed between the gate electrode 37 and the gate electrode 38, and is configured to fill the gap between the gate electrode 37 and the gate electrode 38 without any gap.

It should be noted that filling without a gap means between the gate electrode 37 and the gate electrode 38 and includes forming a sidewall with a predetermined thickness on the oxide film 36 . As shown in FIG. 2, only the case where the sidewalls 40 are provided from the bottom surface of the gate electrode 37 and the gate electrode 38 to the height of the top surface is included in the scope of application of the present technology. It includes the case where it is not formed, the case where it covers the top of the gate electrode, in other words, the case where it is provided with a predetermined thickness from the bottom surface.

FIG. 3 is a diagram showing a planar configuration example of the semiconductor element 10a. A gate electrode 37 of the transistor 11 is surrounded by sidewalls. In the planar configuration example shown in FIG. 3, a sidewall 39 is provided on the left side of the gate electrode 37 in the drawing, a sidewall 40 is provided on the right side in the drawing, and a sidewall 42 is provided on the upper side in the drawing. A side wall 43 is provided on the lower side in the figure. Here, for the sake of explanation, the sidewalls surrounding the gate electrode 37 are divided into the left side, the right side, the upper side, and the lower side and denoted by reference numerals, but these side walls have a continuous structure. The same applies to the following description, and although the sidewalls are described separately for the sake of description, the sidewalls are continuously integrated.

Similarly, the gate electrode 38 of the transistor 11 is surrounded by sidewalls. In the planar configuration example shown in FIG. 3, a sidewall 40 is provided on the left side of the gate electrode 38 in the drawing, a sidewall 41 is provided on the right side in the drawing, and a sidewall 44 is provided on the upper side in the drawing. A side wall 45 is provided on the lower side in the figure.

A diffusion region 32 corresponding to the source or drain is provided on the left side of the transistor 11 . The left side of transistor 12 is provided with a diffusion region 33 corresponding to the source or drain.

Thus, the gate electrodes of the

transistors

11 and 12 are surrounded by sidewalls. A sidewall 40 formed between the gate electrode 37 of the transistor 11 and the gate electrode 38 of the transistor 12 functions both as a sidewall of the transistor 11 and as a sidewall of the transistor 12 .

Referring again to FIG. 2, the space between the gate electrodes of the

transistors

11 and 12 is filled with sidewalls 40 in a cross-sectional view, and the distance between the gate electrodes of the

transistors

11 and 12 is shortened. It is By adopting such a structure, as shown in FIG. 2, without providing an N-type diffusion region under the sidewall 40 in the P-type semiconductor substrate 31, the transistor operates only by gate modulation. It can be a structure that

The distance between the gate electrodes of the transistor 11 and the transistor 12 will be described with reference to FIG.

FIG. 4 is a cross-sectional configuration diagram shown in FIG. As shown in FIG. 4, the width of the sidewall 39 is width a, the width of the sidewall 40 is width b, and the width of the sidewall 39 is width c.

The width a of the sidewall 39 corresponds to the length of the base of the triangular shape in cross section as shown in FIG. . The width b of the sidewall 40 is the length of the side of the side in contact with the oxide film 36 when the side wall 40 is formed in a square shape in a cross-sectional view as shown in FIG. to the side of the gate electrode 38 of the transistor 12 . Width c of sidewall 39 corresponds to the length of the base of the triangular shape in cross section as shown in FIG. .

When the width a, the width b, and the width c are defined in this way, the width b can be the length defined by the following formula (1).
width b≦2×width a=2×width c (1)
The width b is a length equal to or less than twice the width a. If width a and width c have the same length, width b has a length equal to or less than twice width c.

The width b is twice or less than the width of the sidewalls (for example, the

sidewalls

39 and 41 in FIG. 4) formed in the portion where the source or drain is formed. For example, when the width a and the width b are 50 nm, the width b is 100 nm or less.

When the width b between the gate electrodes of the transistor 11 and the transistor 12 satisfies the formula (1), the impurity concentration in the region indicated by the dotted line in the figure can be reduced. In the example shown in FIG. 4, an N-type diffusion region is not formed under the sidewall 40 within the semiconductor substrate 31 . That is, the impurity concentration in the region between the gate electrodes of the

transistors

11 and 12 is set lower than the impurity concentration in the

diffusion regions

32 and 33 serving as the sources and drains of the transistors.

In this way, by reducing the impurity concentration in the region indicated by the dotted line in the figure, the electric field in the region is relaxed and the dark current can be suppressed. Further, the space between the transistor 11 and the transistor 12 can be narrowed, and the semiconductor element 10a can be miniaturized.

<Second Embodiment>
FIG. 5 is a diagram showing a circuit configuration example of a semiconductor element 10b according to the second embodiment. In the semiconductor element 10b of the second embodiment, the same parts as those of the semiconductor element 10a of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

As shown in FIG. 5, the semiconductor element 10b has a transistor 11, a transistor 12, and a transistor 13 connected in series. A semiconductor element 10b according to the second embodiment differs from the semiconductor element 10a (FIG. 1) according to the first embodiment in that a transistor 13 is added, but other points are the same.

FIG. 6 is a diagram showing a cross-sectional configuration example of the semiconductor element 10b. A gate electrode 37 of the transistor 11, a gate electrode 38 of the transistor 12, and a gate electrode 51 of the transistor 13 are provided on the oxide film 36 of the semiconductor element 10b shown in FIG.

The gate electrode 37, the gate electrode 38, and the gate electrode 51 are each surrounded by sidewalls. In the cross-sectional configuration example shown in FIG. 6, a sidewall 39 is provided on the left side of the gate electrode 37 in the drawing, and a sidewall 40 is provided on the right side of the drawing.

Similarly, a sidewall 40 is provided on the left side of the gate electrode 38 in the drawing, and a sidewall 52 is provided on the right side of the drawing. Similarly, a sidewall 52 is provided on the left side of the gate electrode 51 in the drawing, and a sidewall 53 is provided on the right side of the drawing.

The sidewall 40 is a sidewall formed between the gate electrode 37 and the gate electrode 38, and is formed so as to fill the space between the gate electrode 37 and the gate electrode 38 without any gap. The sidewall 52 is a sidewall formed between the gate electrode 38 and the gate electrode 51 and is formed so as to fill the gap between the gate electrode 38 and the gate electrode 51 without any gap.

FIG. 7 is a diagram showing a planar configuration example of the semiconductor element 10b. Gate electrode 37 of transistor 11, gate electrode 38 of transistor 12, and gate electrode 51 of transistor 13 are each surrounded by sidewalls.

In the planar configuration example shown in FIG. 7, a sidewall 39 is provided on the left side of the gate electrode 37 of the transistor 11 in the figure, a sidewall 40 is provided on the right side in the figure, and a side wall 40 is provided on the upper side in the figure. A wall 42 is provided, and a sidewall 43 is provided on the lower side in the drawing. These sidewalls are of continuous construction.

In the planar configuration example shown in FIG. 7, a sidewall 40 is provided on the left side of the gate electrode 38 of the transistor 12 in the drawing, a sidewall 52 is provided on the right side in the drawing, and a sidewall 52 is provided on the upper side in the drawing. A wall 44 is provided, and a sidewall 45 is provided on the lower side in the drawing. These sidewalls are of continuous construction.

In the planar configuration example shown in FIG. 7, a sidewall 52 is provided on the left side of the gate electrode 51 in the drawing, a sidewall 53 is provided on the right side in the drawing, and a sidewall 54 is provided on the upper side in the drawing. A side wall 55 is provided on the lower side in the figure. These sidewalls are of continuous construction.

A sidewall 40 is buried between the gate electrode 37 of the transistor 11 and the gate electrode 38 of the transistor 12 . Similarly, a sidewall 52 is buried between the gate electrode 38 of the transistor 12 and the gate electrode 51 of the transistor 13 .

With such a structure, the distance between the gate electrodes of the transistor 11 and the transistor 12 can be shortened. Further, the distance between the gate electrodes of the transistor 12 and the transistor 13 can be shortened.

With such a structure, as shown in FIG. 6, gate modulation can be performed without providing an N-type diffusion region under the sidewall 40 or under the sidewall 52 in the P-type semiconductor substrate 31 . A structure that operates as a transistor by itself can be employed.

The

sidewalls

40 and 52 are formed with a width corresponding to the width b described with reference to FIG. In other words, the

sidewalls

40 and 52 are configured with a width b that satisfies the formula (1) described with reference to FIG.

In this way, the present technology can also be applied to a semiconductor device in which three transistors are connected in series. Referring to FIG. 6 again, the sidewalls are filled without gaps between the

transistors

11 and 12 and between the

transistors

12 and 13, respectively. The impurity concentration in the semiconductor substrate 31 corresponding to (1) can be reduced.

In the example shown in FIG. 6, the regions in the semiconductor substrate 31 corresponding to the regions where the gate electrode 37, the sidewalls 40, the gate electrodes 38, the sidewalls 52, and the gate electrode 51 are formed have N-type diffusion. No region is formed. In this manner, a structure that operates as a transistor can be obtained only by gate modulation without providing an N-type diffusion region.

By reducing the impurity concentration in the region located under the gate electrode in this way, the electric field in the region is relaxed and the dark current can be suppressed. Moreover, the semiconductor element 10b in which the transistor 11, the transistor 12, and the transistor 13 are formed can be miniaturized.

The first embodiment shows an example in which two transistors are connected in series, and the second embodiment shows an example in which three transistors are connected in series. The present technology is not limited to a case where two or three transistors are connected in series, but can also be applied to a case where four or more transistors are connected in series. As will be described later, the present technology can also be applied to a case including transistors connected in parallel.

That is, the present technology can be applied to a plurality of transistors connected in series, and when the sidewalls between the gate electrodes of adjacent transistors among the plurality of transistors are filled without any gaps between the gate electrodes. can be applied to

<Third Embodiment>
8 to 11 are diagrams showing cross-sectional configuration examples of the semiconductor element 10c according to the third embodiment. In the semiconductor element 10c according to the third embodiment, the same parts as those of the semiconductor element 10a according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

A semiconductor device 10c-1 shown in FIG. 8 has a configuration in which an N− diffusion region 101 is added to the semiconductor device 10a in the first embodiment, and other points are the same.

As described in the first and second embodiments, the semiconductor device 10 that operates as a transistor only by gate modulation without forming a region in which an N-type impurity is diffused between adjacent transistors has been described. . In order to assist the operation as a transistor, a structure in which an N-type impurity is diffused may be provided.

The diffusion region 101 for assisting the operation as a transistor is formed as a region in which the N-type impurity is thinner than the

diffusion regions

32 and 33 . Here, the diffusion region 33 and the diffusion region 33 are described as an N+ diffusion region, and a region in which the N-type impurity is thinner than the N+ diffusion region is described as an N- diffusion region.

The semiconductor element 10c-1 shown in FIG. 8 is in the semiconductor substrate 31 below the sidewall 40, and the N- diffusion region 101 is provided on the surface of the semiconductor substrate 31. As shown in FIG. The N− diffusion region 101 is a region slightly longer than the width of the side wall 40 (corresponding to the width b described in FIG. 4), and is formed to a position where it slightly overlaps the

gate electrodes

37 and 38 .

In this way, in order to assist the

transistors

11 and 12 to operate reliably as transistors, the N- diffusion region 101 having an N-type impurity concentration lower than the impurity concentration of the source and drain may be provided. good.

A semiconductor device 10c-2 shown in FIG. 9 has a structure in which an N- diffusion region 102 is added to the semiconductor device 10a in the first embodiment, and other points are the same.

When comparing the semiconductor device 10c-2 shown in FIG. 9 with the semiconductor device 10c-1 shown in FIG. It is different in that it is formed at a deeper position in the semiconductor substrate 31 than the provided N- diffusion region 101, but the other points are the same.

The N- diffusion region 102 of the semiconductor element 10c-2 shown in FIG. It is formed at a deep position.

The N− diffusion region 102 is formed at a deeper position within the semiconductor substrate 31 than the

N+ diffusion regions

32 and 33 .

Since the N− diffusion region 102 is provided to assist the operation of the transistor 11 and the transistor 12, it should be formed at a position within the semiconductor substrate 31 that can assist the operation.

In this way, the N− diffusion region 102 may be provided to assist the

transistors

11 and 12 to operate reliably as transistors.

A semiconductor device 10c-3 shown in FIG. 10 has a configuration in which an N− diffusion region 103 is added to the semiconductor device 10a in the first embodiment, and other points are the same.

When comparing the semiconductor device 10c-3 shown in FIG. 10 with the semiconductor device 10c-1 shown in FIG. The difference is that the formed region is smaller (smaller in area and volume) than the provided N- diffusion region 101, and the other points are the same.

The N- diffusion region 103 of the semiconductor element 10c-3 shown in FIG. The N− diffusion region 103 is a region shorter than the width of the sidewall 40 (corresponding to the width b described in FIG. 4), and is formed in a size that does not overlap the gate electrode 37 and the gate electrode 38. there is

Since the N− diffusion region 103 is provided to assist the operation of the

transistors

11 and 12, it should be formed in a size that can assist the operation. Referring again to FIG. 4, the N- diffusion region 103 is located within the dotted rectangle in FIG. If the N− diffusion region 103 were formed large, the impurity concentration within the rectangle indicated by the dotted line in FIG. 4 would be high. As the impurity concentration increases, the possibility of generating dark current increases. For this reason, it is considered better to form the N- diffusion region 103 in a small region than to form it in a large region.

In this manner, the N− diffusion region 103 may be provided to assist the

transistors

11 and 12 to operate reliably as transistors.

A semiconductor device 10c-4 shown in FIG. 11 has a configuration in which an N- diffusion region 104 is added to the semiconductor device 10a in the first embodiment, and the other points are the same.

When comparing the semiconductor device 10c-4 shown in FIG. 11 with the semiconductor device 10c-2 shown in FIG. The difference is that the formed region is smaller (smaller in area and volume) than the N- diffusion region 102 provided, and the other points are the same.

The N- diffusion region 104 of the semiconductor device 10c-4 shown in FIG. It is provided at a position separated by a predetermined distance in the direction. Thus, the smaller N- diffusion region 104 may be formed at a predetermined depth in the semiconductor substrate 31. FIG.

In this manner, the N− diffusion region 104 may be provided to assist the

transistors

11 and 12 to reliably operate as transistors.

The N− diffusion regions 101 to 104 shown in FIGS. 8 to 11 are formed with a lower N-type impurity concentration than the

N+ diffusion regions

32 and 33 corresponding to the source or drain. Also, the N− diffusion regions 101 to 104 are formed equal to or smaller than the

N+ diffusion regions

32 and 33 corresponding to the source or drain.

Such N− diffusion regions 101 to 104 can be provided as regions for assisting operations when the

transistors

11 and 12 operate as transistors. This can also be applied to the first and second embodiments described above, and also to the fourth and fifth embodiments described below.

<Fourth Embodiment>
FIG. 12 is a diagram showing a circuit configuration example of a semiconductor element 10d according to the fourth embodiment.

The semiconductor element 10d has a configuration in which the

transistors

111 and 112 are connected in series, and the transistor 113 is connected in parallel to the

transistors

111 and 112. In this case, the transistor 111 , the transistor 112 , and the transistor 113 share the region 114 . A region 114 corresponds to a source or drain, and the

transistors

111, 112, and 113 share the source or drain.

FIG. 13 is a diagram showing a planar configuration example of the semiconductor element 10d. In the planar configuration example shown in FIG. 13, a sidewall 131 is provided on the upper side of the gate electrode 121 of the transistor 111 in the drawing, a sidewall 132 is provided on the left side of the drawing, and a sidewall 132 is provided on the lower side of the drawing. A sidewall 133 is provided, and a sidewall 134 is provided on the right side in the figure. These sidewalls are of continuous construction.

In the planar configuration example shown in FIG. 13, a sidewall 133 is provided on the upper side of the gate electrode 122 of the transistor 112 in the drawing, a sidewall 132 is provided on the left side of the drawing, and a sidewall 132 is provided on the lower side of the drawing. A sidewall 135 is provided, and a sidewall 134 is provided on the right side in the figure. These sidewalls are of continuous construction.

In the planar configuration example shown in FIG. 13, a sidewall 136 is provided on the upper side of the gate electrode 123 in the drawing, a sidewall 134 is provided on the left side of the drawing, and a sidewall 137 is provided on the lower side of the drawing. is provided, and a sidewall 138 is provided on the right side in the figure. These sidewalls are of continuous construction.

A diffusion region 124 in which an N-type impurity is diffused to serve as a source or a drain is provided on the upper side of the transistor 111 in the figure. A diffusion region 125 in which an N-type impurity is diffused to serve as a source or a drain is provided on the lower side of the transistor 112 in the figure. On the right side of the transistor 113 in the drawing, a diffusion region 126 in which N-type impurities are diffused is provided as a source or a drain.

A sidewall 132 is buried between the transistor 111 and the transistor 112 . A sidewall 134 is filled between the transistor 111 and the transistor 113 and between the transistor 112 and the transistor 113 . With such a structure, the distance between the transistor 111 and the transistor 112 can be shortened. Further, the distance between the transistor 112 and the transistor 113 can be shortened.

FIG. 14 is a diagram showing a cross-sectional configuration example of the semiconductor element 10d taken along the line segment A-A' in FIG. A gate electrode 121 of the transistor 111 and a gate electrode 122 of the transistor 112 are provided on the oxide film 36 of the semiconductor element 10d shown in FIG.

The

gate electrodes

121 and 122 are each surrounded by sidewalls. In the cross-sectional configuration example shown in FIG. 14, a sidewall 131 is provided on the left side of the gate electrode 121 in the drawing, and a sidewall 133 is provided on the right side of the drawing. Similarly, a sidewall 133 is provided on the left side of the gate electrode 122 in the drawing, and a sidewall 135 is provided on the right side of the drawing.

The sidewall 133 is a sidewall formed between the gate electrode 121 and the gate electrode 122, and is configured to fill the space between the gate electrode 121 and the gate electrode 122 without any gap. The sidewall 133 has a width corresponding to the width b described with reference to FIG. In other words, the sidewall 133 is configured with a width b that satisfies the formula (1) described with reference to FIG.

With such a configuration, the impurity concentration in the semiconductor substrate 31 under the sidewall 133 can be reduced. Therefore, the electric field in the region is relaxed, and dark current can be suppressed. Further, the semiconductor element 10d in which the

transistors

111 and 112 are formed can be miniaturized.

FIG. 15 is a diagram showing a cross-sectional configuration example of the semiconductor element 10d taken along line B-B' in FIG. A gate electrode 121 of the transistor 111 and a gate electrode 123 of the transistor 113 are provided on the oxide film 36 of the semiconductor element 10d shown in FIG.

The

gate electrodes

121 and 123 are each surrounded by sidewalls. In the cross-sectional configuration example shown in FIG. 15, a sidewall 132 is provided on the left side of the gate electrode 121 in the drawing, and a sidewall 134 is provided on the right side of the drawing. Similarly, a sidewall 134 is provided on the left side of the gate electrode 123 in the drawing, and a sidewall 138 is provided on the right side of the drawing.

The sidewall 134 is a sidewall formed between the gate electrode 121 and the gate electrode 123, and is configured to fill the gap between the gate electrode 121 and the gate electrode 123 without any gap. The sidewall 134 has a width corresponding to the width b described with reference to FIG. In other words, sidewall 134 is configured with a width b that satisfies equation (1) described with reference to FIG.

transistors

111 and 113 are formed can be miniaturized.

In this way, the present technology can also be applied to semiconductor devices in which three transistors are connected in parallel and in series.

In the examples shown in FIGS. 12 to 15, no N-type diffusion regions are formed in the semiconductor substrate 31 corresponding to the regions where the

gate electrodes

121, 122, and 123 are formed. In this manner, a structure that operates as a transistor can be obtained only by gate modulation without providing an N-type diffusion region.

In combination with the third embodiment, it is also possible to adopt a configuration in which an N- diffusion region for assisting the operation of the transistor is formed in the semiconductor substrate 31 under the sidewall.

By reducing the impurity concentration in the region where the gate electrode is formed in this way, the electric field in the region is relaxed and the dark current can be suppressed. Further, the semiconductor element 10d in which the

transistors

111, 112, and 113 are formed can be miniaturized.

In the fourth embodiment, three transistors have been described as an example, but the present technology can also be applied to a case where three or more transistors are connected in series and/or in parallel. can.

<Example of application to imaging device>
An example of a device on which the semiconductor elements 10a to 10d according to the first to fourth embodiments are mounted will be described. Here, an example of application to an imaging apparatus will be described.
<Configuration example of imaging device>
FIG. 16 shows a configuration example in one embodiment of an imaging device to which the present technology is applied.

An imaging device 201 in FIG. 16 includes a pixel array section 203 in which pixels 202 are arranged in a two-dimensional array, and a peripheral circuit section therearound. The peripheral circuit section includes a vertical drive circuit 204, a column signal processing circuit 205, a horizontal drive circuit 206, an output circuit 207, a control circuit 208, and the like.

The pixel 202 has a photodiode as a photoelectric conversion element and a plurality of pixel transistors. The plurality of pixel transistors are, for example, a transfer transistor, a selection transistor, a reset transistor, an amplification transistor, etc., and are composed of MOS transistors.

The control circuit 208 receives an input clock and data instructing the operation mode, etc., and outputs data such as internal information of the imaging device 201 . That is, the control circuit 208 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 204, the column signal processing circuit 205, the horizontal drive circuit 206, and the like, based on the vertical synchronization signal, horizontal synchronization signal, and master clock. do. The control circuit 208 outputs the generated clock signal and control signal to the vertical drive circuit 204, the column signal processing circuit 205, the horizontal drive circuit 206, and the like.

The vertical drive circuit 204 is composed of, for example, a shift register, selects a predetermined pixel drive line 210, supplies a pulse for driving the pixels 202 to the selected pixel drive line 210, and drives the pixels 202 row by row. do. That is, the vertical driving circuit 204 sequentially selectively scans the pixels 202 of the pixel array portion 203 in the vertical direction in units of rows, and generates pixel signals based on signal charges generated in the photoelectric conversion portion of each pixel 202 according to the amount of received light. is supplied to the column signal processing circuit 205 through the vertical signal line 209 .

The column signal processing circuit 205 is arranged for each column of the pixels 202, and performs signal processing such as noise removal on the signals output from the pixels 202 of one row for each pixel column. For example, the column signal processing circuit 205 performs signal processing such as CDS (Correlated Double Sampling) or DDS (double data sampling) for removing pixel-specific fixed pattern noise, and AD conversion.

The horizontal driving circuit 206 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 205 in turn, and outputs pixel signals from each of the column signal processing circuits 205 to the horizontal signal line. 211 for output.

The output circuit 207 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 205 through the horizontal signal line 211 and outputs the processed signals. For example, the output circuit 207 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like. The input/output terminal 213 exchanges signals with the outside.

The imaging device 201 configured as described above is a CMOS image sensor called a column AD system in which a column signal processing circuit 205 that performs CDS processing or DDS processing and AD conversion processing is arranged for each pixel column.

<Example of pixel circuit configuration>
A configuration of a unit pixel provided in the pixel array portion 203 will be described. A unit pixel provided in the pixel array section 203 is configured as shown in FIG. 17, for example. In FIG. 17, parts corresponding to those in FIG. 16 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

A pixel 202, which is a unit pixel, includes a photoelectric conversion portion 251, a first transfer transistor 252, a first FD (Floating Diffusion) portion 253, a second transfer transistor 254, a second FD portion 255, a third transfer transistor 256 , third FD section 257 , reset transistor 258 , amplification transistor 259 and selection transistor 260 .

For the pixels 202, for example, a plurality of drive lines are wired as pixel drive lines 210 for each pixel row. Then, a drive signal TG is applied from the vertical drive circuit 204 to each of the first transfer transistor 252, the second transfer transistor 254, the third transfer transistor 256, the reset transistor 258, and the selection transistor via a plurality of drive lines. , drive signal FDG, drive signal FCG, drive signal RST, and drive signal SEL are supplied.

These drive signals are pulse signals in which a high level state (eg, power supply voltage VDD) is active and a low level state (eg, negative potential) is inactive. That is, when each of the drive signals TG to SEL is set to a high level, the transistor to which it is supplied becomes conductive, that is, is turned on. The transistor is non-conducting, ie off.

The photoelectric conversion unit 251 is composed of, for example, a PN junction photodiode. The photoelectric conversion unit 251 receives and photoelectrically converts incident light, and accumulates electric charges obtained as a result. The PD 251 can be a planar photodiode or an embedded photodiode.

The first transfer transistor 252 is provided between the photoelectric conversion section 251 and the first FD section 253, and the drive signal TG is supplied to the gate electrode of the first transfer transistor 252. When the driving signal TG becomes high level, the first transfer transistor 252 is turned on, and the charges accumulated in the photoelectric conversion section 251 are transferred to the first FD section 253 via the first transfer transistor 252. transferred.

The first FD portion 253, the second FD portion 255, and the third FD portion 257 are floating diffusion regions called floating diffusion, and transfer charges and charges overflowing from the photoelectric conversion portion 251. It functions as a storage unit that temporarily stores data.

The second transfer transistor 254 is provided between the first FD section 253 and the second FD section 255, and the drive signal FDG is supplied to the gate electrode of the second transfer transistor 254. When the driving signal FDG becomes high level, the second transfer transistor 254 is turned on, and the charges from the first FD section 253 are transferred to the second FD section 255 via the second transfer transistor 254. be done.

By turning on the second transfer transistor 254, a region where charges are accumulated becomes a region where the first FD portion 253 and the second FD portion 255 are combined. It is possible to switch the conversion efficiency when converting to . The second transfer transistor 254 functions as a conversion efficiency switching transistor that switches conversion efficiency.

The third transfer transistor 256 is provided between the second FD section 255 and the third FD section 257, and the drive signal FCG is supplied to the gate electrode of the third transfer transistor 256. When the driving signal FCG becomes high level, the third transfer transistor 256 is turned on, and the charges from the second FD section 255 are transferred to the third FD section 257 via the third transfer transistor 256. be done.

By turning on the third transfer transistor 256, a region in which electric charges are accumulated becomes a region including the first FD portion 253, the second FD portion 255, and the third FD portion 257. It is possible to switch the conversion efficiency when converting the charge generated in the conversion unit into a voltage. The third transfer transistor 256 functions as a conversion efficiency switching transistor that switches conversion efficiency.

The reset transistor 258 is connected between the power supply VDD and the third FD section 257, and the drive signal RST is supplied to the gate electrode of the reset transistor 258. When the drive signal RST is set to high level, the reset transistor 258 is turned on and the potential of the third FD section 257 is reset to the level of the power supply voltage VDD.

The amplification transistor 259 has a gate electrode connected to the first FD section 253 and a drain connected to the power supply VDD. It becomes the input part of the source follower circuit. That is, the amplifying transistor 259 forms a source follower circuit with a constant current source (not shown) connected to one end of the vertical signal line 209 by connecting the source to the vertical signal line 209 via the selection transistor 260. do.

The selection transistor 260 is connected between the source of the amplification transistor 259 and the vertical signal line 209, and the gate electrode of the selection transistor 260 is supplied with the driving signal SEL. When the driving signal SEL is set to a high level, the selection transistor 260 is turned on and the pixel 202 is selected. Thereby, the pixel signal output from the amplification transistor 259 is output to the vertical signal line 209 via the selection transistor 260 .

Hereinafter, when each drive signal is in an active state, that is, at a high level, it is also referred to as turning on each drive signal. also say

The pixel 202 shown in FIG. 17 includes a first FD portion 253, a second FD portion 255, and a third FD portion 257. These FD portions are connected in series, and charge generated in the photoelectric conversion portion is It is configured such that the conversion efficiency when converting to voltage can be switched in three stages.

The high conversion efficiency (HCG) is composed of the first FD section 253 . The medium conversion efficiency (MCG) is composed of (first FD section 253+second FD section 255). The low conversion efficiency (LCG) is composed of (first FD section 253+second FD section 255+third FD section 257).

By turning on the first transfer transistor 252, the charge accumulated in the photoelectric conversion unit 251 is transferred to the first FD unit 253 (high conversion efficiency) or (first FD unit 253+second FD unit 255) is received and output at (middle conversion efficiency).

When the illuminance is high, the charges accumulated in the photoelectric conversion unit 251 overflow the first transfer transistor 252 to the first FD unit 253 side, and the first FD unit 253, the second FD unit 255, the 3 is stored in the FD unit 257.

When the amount of light received is small, a charge is accumulated in the first FD section 253, resulting in a high conversion efficiency. 257) is assumed to be a low conversion efficiency in which charge is accumulated. Further, here, an intermediate conversion efficiency between the high conversion efficiency and the low conversion efficiency is provided, and a conversion efficiency at which charges are accumulated in (the first FD section 253+the second FD section 255) is provided.

The charge accumulated in the first FD section 253, the second FD section 255, and the third FD section 257 by overflowing the photoelectric conversion section 251 is combined with the charge accumulated in the photoelectric conversion section 251 (the first FD 253+second FD unit 255+third FD unit 257) and output.

The high conversion efficiency, medium conversion efficiency, and low conversion efficiency readouts are AD-converted separately, and which readout signal to use is determined from the amount of each readout signal. Two readout signals may be blended and used at the junction between the high conversion efficiency signal and the medium conversion efficiency signal and at the junction between the medium conversion efficiency signal and the low conversion efficiency signal. By using the blended signal, deterioration in image quality at the joint is suppressed.

<Fifth Embodiment>
A case where the present technology is applied to the semiconductor element mounted on the imaging device 201 described with reference to FIGS. 16 and 17 will be added.

18, in the circuit configuration example of the pixel 202 shown in FIG. 17, the semiconductor element 10a in the first embodiment is applied to the second transfer transistor 254 and the third transfer transistor 256 connected in series. FIG. 10 is a diagram showing a cross-sectional configuration example of a semiconductor element 10e in a case where;

A diffusion region 271 and a diffusion region 272 in which N-type impurities are diffused are provided in the P-type semiconductor substrate 31 . The diffusion region 271 corresponds to the source of the second transfer transistor 254 , and the diffusion region 272 corresponds to the drain of the third transfer transistor 256 . Diffusion region 271 is connected to first FD section 253 , and diffusion region 272 is connected to third FD section 257 .

An oxide film 36 is formed on the semiconductor substrate 31 . A gate electrode 281 of the second transfer transistor 254 and a gate electrode 282 of the third transfer transistor 256 are provided on the oxide film 36 .

The

gate electrodes

281 and 282 are each surrounded by sidewalls. In the cross-sectional configuration example shown in FIG. 18, a sidewall 283 is provided on the left side of the gate electrode 281 in the drawing, and a sidewall 284 is provided on the right side of the drawing. Similarly, a sidewall 284 is provided on the left side of the gate electrode 282 in the drawing, and a sidewall 285 is provided on the right side of the drawing.

The sidewall 284 is a sidewall formed between the gate electrode 281 and the gate electrode 282, and is configured to fill the space between the gate electrode 281 and the gate electrode 282 without any gap. A portion where the sidewall 284 is formed, which is surrounded by a dotted line in the drawing, functions as the second FD portion 255 .

The sidewall 284 has a width corresponding to the width b described with reference to FIG. In other words, sidewall 284 is configured with a width b that satisfies equation (1) described with reference to FIG.

In combination with the third embodiment, the N- diffusion region for assisting the operation of the transistor is formed in the semiconductor substrate 31 under the sidewall, for example, in the semiconductor substrate 31 within the dotted line shown in FIG. It can also be configured as

In this way, the sidewalls are filled between the second transfer transistor 254 and the third transfer transistor 256 without any gap, so that the semiconductor substrate 31 corresponding to the region where the gate electrode is formed. can reduce the impurity concentration in the That is, in this case, the impurity concentration of the region corresponding to the source or drain of the second FD portion 255 is lower than the impurity concentration of the regions corresponding to the source or drain of the first FD portion 253 and the third FD portion 257. can be a structure. As a result, the electric field of the second FD portion 255 is lowered, and a structure that is advantageous against dark current can be obtained.

In driving, the second FD section 255 is designed to be deeper than the reset level, and the second transfer transistor 254 and the third transfer transistor 256 are designed to operate as transistors only by gate modulation. By driving in this manner, it is possible to obtain the effect of being less susceptible to dark current even in DDS (double data sampling) driving.

In order to explain the DDS drive, the operation of the pixel 202 shown in FIG. 17 will be explained with reference to the timing chart of FIG.

<Regarding the operation of the pixel 202>
The operation of the pixel 202 will be described with reference to FIG. In FIG. 19, HGC represents high conversion efficiency, MCG represents medium conversion efficiency, and LCG represents low conversion efficiency.

Time T1 is the time immediately after the shutter operation is performed. Referring to FIG. 19, immediately after the shutter operation is performed, the drive signal SEL supplied to the selection transistor 260, the drive signal RST supplied to the reset transistor 258, and the drive signal supplied to the third transfer transistor 256 FCG, the drive signal FDG supplied to the second transfer transistor 254, and the drive signal TG supplied to the first transfer transistor 252 are in the off state.

The exposure period starts at time T1, photoelectric conversion is performed in the PD 251, and signals are accumulated in the PD 251. Here, when the signal becomes more than the saturated number of electrons, it overflows under the first transfer transistor 252, and depending on the overflowed signal amount, the first FD section 253, the second FD section 255, A signal is accumulated in the third FD section 257 .

Time T2 is the reset period of the MCG (medium conversion efficiency) mode. During the reset period of the MCG mode, the drive signal SEL supplied to the selection transistor 58 and the drive signal FDG supplied to the second transfer transistor 254 are turned on. A reset signal in the MCG mode is acquired during the reset period of the MCG mode.

When the reset period of the MCG mode ends, it shifts to the reset period of the HCG (high conversion efficiency) mode at time T3. During the reset period of the HCG mode, the drive signal SEL supplied to the selection transistor 58 is kept on, and the drive signal FDG supplied to the second transfer transistor 254 is switched from on to off. A reset signal in the HCG mode is acquired during the reset period of the HCG mode.

When the reset period of the HCG mode ends, it shifts to the readout period of the HCG mode at time T4. During the transition from time T3 to time T4, the driving signal TRG supplied to the first transfer transistor 252 is turned on for a predetermined period of time. The signal accumulated in the PD 251 is read out by the first transfer transistor 252 by turning on the drive signal TRG. Reading from the PD 251 is performed by CDS (correlated double sampling) driving.

Image data in the HCG mode is generated and output by CDS driving using the reset signal obtained during the reset period of the HCG mode at time T3 and the signal read during the readout period of the HCG mode at time T4. be.

When the reading period of the HCG mode ends, it shifts to the reading period of the MCG mode at time T5. During the transition from time T4 to time T5, the drive signal FDG supplied to the second transfer transistor 254 is turned on. By turning on the drive signal FDG, the charges accumulated in the first FD section 253 and the second FD section 255 are read out.

At time T5, image data in the MCG mode is converted by CDS driving using a reset signal obtained during the reset period of the MCG mode at time T2 and a signal read during the readout period of the MCG mode at time T5. generated and output.

When the readout period of the MCG mode ends, the readout period of the LCG mode at time T6 is entered. During the transition from time T5 to time T6, the drive signal FCG supplied to the third transfer transistor 256 is turned on. At time T6, the second transfer transistor 254 and the third transfer transistor 256 are turned on.

By turning on the second transfer transistor 254 and the third transfer transistor 256, the signals accumulated in the first FD section 253, the second FD section 255, and the third FD section 257 are is read out.

When the readout period of the LCG mode ends, it shifts to the reset period at time T7. In the reset period at time T7, in order to make the black level signal in the LCG mode reset period at time T8 the same as the black level signal at the time of shutter, the reset operation is performed in the same state as at the time of shutter.

Referring to FIG. 19, in the reset period at time T7, the drive signal SEL supplied to the selection transistor 58 is turned off from time T6 to time T8. The drive signal RST supplied to the reset transistor 258 is turned on for a predetermined time from time T6 to time T8. The drive signal FCG supplied to the third transfer transistor 256 is turned on for a predetermined time from time T6 to time T8. The drive signal FDG supplied to the second transfer transistor 254 is turned on for a predetermined time from time T6 to time T8.

By performing the reset operation in the reset period at time T7, the signals accumulated in the first FD section 253, the second FD section 255, and the third FD section 257 are reset.

When the reset period at time T7 ends, the reset period of the LCG mode at time T8 is entered. During the reset period of the LCG mode at time T8, the drive signal SEL supplied to the selection transistor 58 is turned on. The drive signal FCG supplied to the third transfer transistor 256 and the drive signal FDG supplied to the second transfer transistor 254 are also turned on.

　Reading in LCG mode is performed by DDS (double data sampling) drive. The DDS driving is driving in which the signal charge held or accumulated in the FD is read out as a signal level, then the FD is reset to a predetermined potential and the predetermined potential is read out as a reset level.

Since reading in the LCG mode is performed by DDS driving, the signal read in the readout period in the LCG mode at time T6 and the reset signal read in the reset period in the LCG mode at time T8 are used. is generated and output. Since reading at time T6 is performed before resetting, if a dark current is generated, there is a possibility that the signal including the dark current will be read.

According to the present technology, as described above, it is possible to suppress the influence of dark current due to the structure capable of suppressing the generation of dark current. Therefore, the present technology can obtain an effect even for reading by DDS driving.

Returning to the description with reference to FIG. 19, the drive signal SEL, the drive signal FCG, and the drive signal FDG are turned off at the end of the readout period in the LCG mode.

By performing such a series of operations, a signal at HCG (high conversion efficiency), a signal at MCG (medium conversion efficiency), and a signal at LCG (low conversion efficiency) are read out. By using such three conversion efficiencies to read data three times, it is possible to suppress deterioration of the S/N step at the joint.

This technology can be applied to an imaging device that has such a structure and operates.

Here, the case where the present technology is applied to the second transfer transistor 254 and the third transfer transistor 256 that are connected in series has been described as an example. The present technology is applied to any two transistors, three transistors, or four transistors among the transfer transistor 252, the second transfer transistor 254, the third transfer transistor 256, and the reset transistor 258. You can also

The present technology may be applied to the amplification transistor 259 and selection transistor 260 that are connected in series.

For example, the fourth embodiment described with reference to FIGS. 12 to 15 may be applied to the first transfer transistor 252, the second transfer transistor 254, and the amplification transistor 259. FIG.

According to this technology, pixels can be miniaturized. According to the present technology, the impurity concentration in the region between transistors can be reduced, the electric field in the region can be relaxed, and dark current can be suppressed. As pixels are miniaturized, the impurity concentration increases and the electric field is more likely to increase. However, according to the present technology, as described above, it is possible to achieve both miniaturization of pixels and relaxation of the electric field. .

<Example of application to electronic equipment>
The present technology is not limited to application to imaging devices. That is, the present technology can be applied to an image capture unit (photoelectric conversion unit) such as an image capturing device such as a digital still camera or a video camera, a mobile terminal device having an image capturing function, or a copier using an image sensor as an image reading unit. It is applicable to electronic devices in general that use elements. The imaging element may be formed as a single chip, or may be in the form of a module having an imaging function in which an imaging section and a signal processing section or an optical system are packaged together.

FIG. 20 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

The imaging element 1000 in FIG. 20 includes an optical unit 1001 including a lens group, an imaging element (imaging device) 1002 adopting the configuration of the imaging apparatus 201 in FIG. 16, and a DSP (Digital Signal Processor) that is a camera signal processing circuit. A circuit 1003 is provided. The imaging device 1000 also includes a frame memory 1004 , a display section 1005 , a recording section 1006 , an operation section 1007 and a power supply section 1008 . DSP circuit 1003 , frame memory 1004 , display unit 1005 , recording unit 1006 , operation unit 1007 and power supply unit 1008 are interconnected via bus line 1009 .

The optical unit 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1002 . The imaging element 1002 converts the amount of incident light imaged on the imaging surface by the optical unit 1001 into an electric signal for each pixel, and outputs the electric signal as a pixel signal. As the imaging device 1002, the imaging device 201 in FIG. 16 can be used.

A display unit 1005 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the imaging device 1002 . A recording unit 1006 records a moving image or still image captured by the image sensor 1002 in a recording medium such as a hard disk or a semiconductor memory.

The operation unit 1007 issues operation commands for various functions of the imaging device 1000 under the user's operation. A power supply unit 1008 appropriately supplies various power supplies as operating power supplies for the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007 to these supply targets.

<Example of application to an endoscopic surgery system>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

FIG. 21 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (this technology) can be applied.

FIG. 21 illustrates a situation in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000 . As illustrated, an endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, and a support arm device 11120 for supporting the endoscope 11100. , and a cart 11200 loaded with various devices for endoscopic surgery.

An endoscope 11100 is composed of a lens barrel 11101 whose distal end is inserted into the body cavity of a patient 11132 and a camera head 11102 connected to the proximal end of the lens barrel 11101 . In the illustrated example, an endoscope 11100 configured as a so-called rigid scope having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel. good.

The tip of the lens barrel 11101 is provided with an opening into which the objective lens is fitted. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel 11101 by a light guide extending inside the lens barrel 11101, where it reaches the objective. Through the lens, the light is irradiated toward the observation object inside the body cavity of the patient 11132 . Note that the endoscope 11100 may be a straight scope, a perspective scope, or a side scope.

An optical system and an imaging element are provided inside the camera head 11102, and the reflected light (observation light) from the observation target is focused on the imaging element by the optical system. The imaging device photoelectrically converts the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to a camera control unit (CCU: Camera Control Unit) 11201 as RAW data.

The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the operations of the endoscope 11100 and the display device 11202 in an integrated manner. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing such as development processing (demosaicing) for displaying an image based on the image signal.

The display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201 .

The light source device 11203 is composed of a light source such as an LED (light emitting diode), for example, and supplies the endoscope 11100 with irradiation light for imaging a surgical site or the like.

The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204 . For example, the user inputs an instruction or the like to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100 .

The treatment instrument control device 11205 controls driving of the energy treatment instrument 11112 for tissue cauterization, incision, blood vessel sealing, or the like. The pneumoperitoneum device 11206 inflates the body cavity of the patient 11132 for the purpose of securing the visual field of the endoscope 11100 and securing the operator's working space, and injects gas into the body cavity through the pneumoperitoneum tube 11111. send in. The recorder 11207 is a device capable of recording various types of information regarding surgery. The printer 11208 is a device capable of printing various types of information regarding surgery in various formats such as text, images, and graphs.

It should be noted that the light source device 11203 that supplies the endoscope 11100 with irradiation light for photographing the surgical site can be composed of, for example, a white light source composed of an LED, a laser light source, or a combination thereof. When a white light source is configured by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. It can be carried out. Further, in this case, the observation target is irradiated with laser light from each of the RGB laser light sources in a time-division manner, and by controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing, each of RGB can be handled. It is also possible to pick up images by time division. According to this method, a color image can be obtained without providing a color filter in the imaging element.

Further, the driving of the light source device 11203 may be controlled so as to change the intensity of the output light every predetermined time. By controlling the drive of the imaging device of the camera head 11102 in synchronism with the timing of the change in the intensity of the light to obtain an image in a time-division manner and synthesizing the images, a high dynamic A range of images can be generated.

Also, the light source device 11203 may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissues is used to irradiate a narrower band of light than the irradiation light (i.e., white light) used during normal observation, thereby observing the mucosal surface layer. So-called Narrow Band Imaging, in which a predetermined tissue such as a blood vessel is imaged with high contrast, is performed. Alternatively, in special light observation, fluorescence observation may be performed in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, the body tissue is irradiated with excitation light and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and the body tissue is examined. A fluorescence image can be obtained by irradiating excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to be able to supply narrowband light and/or excitation light corresponding to such special light observation.

FIG. 22 is a block diagram showing an example of functional configurations of the camera head 11102 and CCU 11201 shown in FIG.

The camera head 11102 has a lens unit 11401, an imaging section 11402, a drive section 11403, a communication section 11404, and a camera head control section 11405. The CCU 11201 has a communication section 11411 , an image processing section 11412 and a control section 11413 . The camera head 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400 .

A lens unit 11401 is an optical system provided at a connection with the lens barrel 11101 . Observation light captured from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401 . A lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

The number of imaging elements constituting the imaging unit 11402 may be one (so-called single-plate type) or plural (so-called multi-plate type). When the image pickup unit 11402 is configured as a multi-plate type, for example, image signals corresponding to RGB may be generated by each image pickup element, and a color image may be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for respectively acquiring right-eye and left-eye image signals corresponding to 3D (dimensional) display. The 3D display enables the operator 11131 to more accurately grasp the depth of the living tissue in the surgical site. Note that when the imaging unit 11402 is configured as a multi-plate type, a plurality of systems of lens units 11401 may be provided corresponding to each imaging element.

Also, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102 . For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.

The drive unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under control from the camera head control unit 11405 . Thereby, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

The communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400 .

Also, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies it to the camera head control unit 11405 . The control signal includes, for example, information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and/or information to specify the magnification and focus of the captured image. Contains information about conditions.

Note that the imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately designated by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. good. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

The camera head control unit 11405 controls driving of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.

The communication unit 11411 is composed of a communication device for transmitting and receiving various information to and from the camera head 11102 . The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400 .

Also, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102 . Image signals and control signals can be transmitted by electric communication, optical communication, or the like.

The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data transmitted from the camera head 11102 .

The control unit 11413 performs various controls related to imaging of the surgical site and the like by the endoscope 11100 and display of the captured image obtained by imaging the surgical site and the like. For example, the control unit 11413 generates control signals for controlling driving of the camera head 11102 .

In addition, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site and the like based on the image signal that has undergone image processing by the image processing unit 11412 . At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 detects the shape, color, and the like of the edges of objects included in the captured image, thereby detecting surgical instruments such as forceps, specific body parts, bleeding, mist during use of the energy treatment instrument 11112, and the like. can recognize. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition result to display various types of surgical assistance information superimposed on the image of the surgical site. By superimposing and presenting the surgery support information to the operator 11131, the burden on the operator 11131 can be reduced and the operator 11131 can proceed with the surgery reliably.

A transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable of these.

Here, in the illustrated example, wired communication is performed using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

In this specification, the system represents an entire device composed of multiple devices.

It should be noted that the effects described in this specification are only examples and are not limited, and other effects may also occur.

It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

Note that the present technology can also take the following configuration.
(1)
a plurality of transistors connected in series;
sidewalls provided on the transistor;
A first sidewall provided between the adjacent transistors is provided without a gap between gate electrodes of the transistors.
(2)
The semiconductor according to (1), wherein the width of the first sidewall is twice or less than the width of the second sidewall provided in the regions corresponding to the sources or drains of the plurality of transistors. element.
(3)
The semiconductor device according to (1) or (2), further comprising one or more transistors connected in parallel at a position where the first sidewall is provided.
(4)
The semiconductor device according to any one of (1) to (3), wherein the impurity concentration of the region where the first sidewall is located is lower than the impurity concentration of the regions corresponding to the sources or drains of the plurality of transistors.
(5)
Any one of (1) to (4) above, further comprising a diffusion region having an impurity concentration lower than that of the regions corresponding to the sources or drains of the plurality of transistors, in the region where the first sidewall is located. A semiconductor device as described.
(6)
The semiconductor element according to (5), wherein the diffusion region is formed at a position deeper than the regions corresponding to the source and the drain in the semiconductor substrate in which the source and the drain are formed.
(7)
The semiconductor device according to (5) or (6), wherein the diffusion region is formed in a region smaller than a region corresponding to the source or the drain.
(8)
a photoelectric conversion unit that converts light into an electric charge;
a plurality of storage units that temporarily store charges;
a plurality of transfer transistors that transfer charges to the storage unit,
The first sidewalls provided between the plurality of transfer transistors are provided without gaps between the gate electrodes of the transfer transistors.
(9)
The width of the first sidewall is twice or less than the width of the second sidewall provided in the regions corresponding to the sources or drains of the plurality of transfer transistors. image sensor.
(10)
The image pickup device according to (8) or (9), wherein the region where the first sidewall is located is the accumulation portion.
(11)
The imaging device according to any one of (8) to (10), wherein the impurity concentration of the accumulation portion in the region where the first sidewall is located is lower than the impurity concentration of other accumulation portions.
(12)
The imaging device according to any one of (8) to (11), wherein the accumulation portion in the region where the first sidewall is located includes a diffusion region having an impurity concentration lower than that of other accumulation portions.
(13)
a photoelectric conversion unit that converts light into an electric charge;
a plurality of storage units that temporarily store charges;
a plurality of transfer transistors that transfer charges to the storage unit,
an imaging device, wherein first sidewalls provided between the plurality of transfer transistors are provided without gaps between gate electrodes of the transfer transistors;
An electronic device comprising: a processing unit that processes a signal from the imaging device.

10 semiconductor element, 11, 12, 13 transistor, 31 semiconductor substrate, 32, 33 diffusion region, 36 oxide film, 37, 38 gate electrode, 39, 40, 41, 42, 43, 44, 45 sidewall, 51 gate electrode , 52, 53, 54, 55 sidewalls, 101, 102, 103, 104 diffusion regions, 111, 112, 113 transistors, 114 regions, 121, 122, 123 gate electrodes, 124, 125, 126 diffusion regions, 131, 132 , 133, 134, 135, 136, 137, 138 sidewalls, 201 imaging device, 202 pixels, 203 pixel array section, 204 vertical drive circuit, 205 column signal processing circuit, 206 horizontal drive circuit, 207 output circuit, 208 control circuit , 209 vertical signal line, 210 pixel drive line, 211 horizontal signal line, 213 input/output terminal, 251 photoelectric conversion section, 252 first transfer transistor, 253 first FD section, 254 second transfer transistor, 255 second FD section, 256 third transfer transistor, 257 third FD section, 258 reset transistor, 259 amplification transistor, 260 selection transistor, 271, 272 diffusion region, 281, 282 gate electrode, 283, 284, 285 sidewall

Claims

a plurality of transistors connected in series;
sidewalls provided on the transistor;
A first sidewall provided between the adjacent transistors is provided without a gap between gate electrodes of the transistors.
2. The semiconductor device according to claim 1, wherein the width of the first sidewall is twice or less than the width of the second sidewall provided in the regions corresponding to the sources or drains of the plurality of transistors. .
2. The semiconductor device according to claim 1, further comprising one or more transistors connected in parallel at the location where the first sidewall is provided.
2. The semiconductor device according to claim 1, wherein the impurity concentration of the region where the first sidewall is located is lower than the impurity concentration of the regions corresponding to sources or drains of the plurality of transistors.
2. The semiconductor device of claim 1, further comprising a diffusion region having an impurity concentration lower than that of regions corresponding to the sources or drains of the plurality of transistors, in the region where the first sidewall is located.
6. The semiconductor device according to claim 5, wherein said diffusion region is formed at a position deeper than a region corresponding to said source and said drain in a semiconductor substrate in which said source and said drain are formed.
6. The semiconductor device according to claim 5, wherein said diffusion region is formed in a region smaller than a region corresponding to said source or said drain.
a photoelectric conversion unit that converts light into an electric charge;
a plurality of storage units that temporarily store charges;
a plurality of transfer transistors that transfer charges to the storage unit,
The first sidewalls provided between the plurality of transfer transistors are provided without gaps between the gate electrodes of the transfer transistors.
9. The imaging according to claim 8, wherein the width of the first sidewall is twice or less than the width of the second sidewall provided in the regions corresponding to the sources or drains of the plurality of transfer transistors. element.
The image pickup device according to claim 8, wherein the region where the first sidewall is located is the accumulation portion.
9. The imaging device according to claim 8, wherein the impurity concentration of the accumulation portion in the region where the first sidewall is located is lower than the impurity concentration of other accumulation portions.
9. The imaging device according to claim 8, wherein the accumulation portion in the region where the first sidewall is located has a diffusion region with an impurity concentration lower than that of other accumulation portions.
a photoelectric conversion unit that converts light into an electric charge;
a plurality of storage units that temporarily store charges;
a plurality of transfer transistors that transfer charges to the storage unit,
an imaging device, wherein first sidewalls provided between the plurality of transfer transistors are provided without gaps between gate electrodes of the transfer transistors;
An electronic device comprising: a processing unit that processes a signal from the imaging device.