WO2023074137A1 - トランスチップ、信号伝達装置 - Google Patents

トランスチップ、信号伝達装置 Download PDF

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Publication number
WO2023074137A1
WO2023074137A1 PCT/JP2022/033692 JP2022033692W WO2023074137A1 WO 2023074137 A1 WO2023074137 A1 WO 2023074137A1 JP 2022033692 W JP2022033692 W JP 2022033692W WO 2023074137 A1 WO2023074137 A1 WO 2023074137A1
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Prior art keywords
potential
coil
transformer
chip
wiring
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PCT/JP2022/033692
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English (en)
French (fr)
Japanese (ja)
Inventor
友嗣 北田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202280063884.8A priority Critical patent/CN118020158A/zh
Priority to JP2023556164A priority patent/JPWO2023074137A1/ja
Publication of WO2023074137A1 publication Critical patent/WO2023074137A1/ja
Priority to US18/610,509 priority patent/US20240221992A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2804—Printed windings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/288—Shielding
    • H01F27/2885—Shielding with shields or electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H01F27/292—Surface mounted devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00—Fixed transformers or mutual inductances of the signal type
    • H01F19/04—Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • H01F19/08—Transformers having magnetic bias, e.g. for handling pulses
    • H01F2019/085—Transformer for galvanic isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2804—Printed windings
    • H01F2027/2809—Printed windings on stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
    • H01F38/14—Inductive couplings
    • H01F2038/143—Inductive couplings for signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
    • H01F38/14—Inductive couplings

Definitions

  • the invention disclosed in this specification relates to a transformer chip and a signal transmission device.
  • Patent Document 1 by the applicant of the present application can be cited.
  • the invention disclosed in the present specification provides a signal transmission device that is less susceptible to common mode noise and a transformer chip used therein in view of the above problems found by the inventors of the present application. intended to
  • the transformer chip disclosed in this specification includes, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding formed on the first wiring layer, and the a secondary winding formed on the second wiring layer so as to be magnetically coupled with the primary winding; a pad connected to the signal end of the secondary winding; A substrate having a potential and a shield electrode interposed between the substrate and the pad are provided.
  • FIG. 1 is a diagram showing the basic configuration of a signal transmission device.
  • FIG. 2 is a diagram showing how potential fluctuations occur between GND1 and GND2.
  • FIG. 3 is a diagram showing an example of malfunction due to common mode noise.
  • FIG. 4 is a diagram showing the principle of occurrence of abnormal signal transmission (ideal transformer, normal signal input).
  • FIG. 5 is a diagram showing the principle of occurrence of signal transmission abnormality (ideal transformer, when CM noise is input).
  • FIG. 6 is a diagram showing the principle of occurrence of signal transmission abnormality (actual transformer, when a normal signal is input).
  • FIG. 7 is a diagram showing the principle of occurrence of signal transmission abnormality (actual transformer, when CM noise is input).
  • FIG. 8 is a diagram showing an introduction example of a noise canceller.
  • FIG. 1 is a diagram showing the basic configuration of a signal transmission device.
  • FIG. 2 is a diagram showing how potential fluctuations occur between GND1 and GND2.
  • FIG. 3 is a diagram
  • FIG. 9 is a diagram showing an example of noise cancellation operation.
  • FIG. 10 is a diagram showing the basic structure of a transformer chip.
  • FIG. 11 is a perspective view of a semiconductor device used as a two-channel transformer chip.
  • 12 is a plan view of the semiconductor device shown in FIG. 11.
  • FIG. 13 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. 11.
  • FIG. 14 is a plan view showing a layer in which a high potential coil is formed in the semiconductor device of FIG. 11.
  • FIG. 15 is a cross-sectional view taken along line VIII-VIII shown in FIG. 14.
  • FIG. 16 is a cross-sectional view taken along line IX-IX shown in FIG. 14.
  • FIG. 17 is an enlarged view of the area X shown in FIG. 14.
  • FIG. FIG. 18 is an enlarged view of area XI shown in FIG.
  • FIG. 19 is an enlarged view of region XII shown in FIG.
  • FIG. 20 is an enlarged view of the region XIII shown in FIG. 15 showing the isolation structure.
  • FIG. 21 is a diagram schematically showing a layout example of a transformer chip.
  • FIG. 22 is a diagram showing an introduction example of a shield electrode.
  • FIG. 23 is a diagram showing the vertical structure of a transformer chip with shield electrodes.
  • FIG. 24 is a diagram showing the noise reduction effect by introducing the shield electrode.
  • FIG. 25 is a diagram (solid over one side) showing the relationship between the layout of the shield electrode and the signal transmission capability.
  • FIG. 26 is a diagram (O type) showing the relationship between the layout of the shield electrode and the signal transmission capability.
  • FIG. 27 is a diagram (C type) showing the relationship between the layout of the shield electrodes and the signal transmission capability.
  • FIG. 28 is a diagram showing a first planar layout example (C type) of the shield electrode.
  • FIG. 29 is a diagram showing a second planar layout example (size change of C type) of the shield electrode.
  • FIG. 30 is a diagram showing a third planar layout example (O-type) of the shield electrode.
  • FIG. 31 is a diagram showing a fourth plane layout example (single-stroke type) of the shield electrode.
  • FIG. 32 is a diagram showing a first cross-sectional structure example of a primary winding, a secondary winding, and a shield electrode.
  • FIG. 33 is a diagram showing a second cross-sectional structural example of the primary winding, the secondary winding, and the shield electrode.
  • FIG. 34 is a diagram showing a third cross-sectional structure example of the primary winding, the secondary winding, and the shield electrode.
  • FIG. 35 is a diagram showing a fourth cross-sectional structural example of the primary winding, the secondary winding, and the shield electrode.
  • FIG. 36 is a diagram showing a fifth cross-sectional structure example of the primary winding, the secondary winding, and the shield electrode.
  • FIG. 37 is a diagram showing the relationship between the presence/absence and shape of the shield electrode and the inter-coil capacitance.
  • FIG. 38 is a diagram showing a planar layout of pads and coils.
  • FIG. 39 is a diagram showing a first planar layout of shield electrodes overlapping the coils of FIG. 38.
  • FIG. FIG. 40 is a diagram in which FIGS. 38 and 39 are superimposed.
  • 41 is a diagram showing a second planar layout of shield electrodes overlapping the coils of FIG. 38.
  • FIG. FIG. 42 is a diagram in which FIGS. 38 and 41 are superimposed.
  • FIG. 43 is a diagram showing the presence of substrate-to-pad capacitance.
  • FIG. 44 is a diagram showing how the substrate-to-pad capacitance is unshielded.
  • FIG. 45 is a diagram showing a first planar layout of the shield electrode in the region overlapping the pad.
  • FIG. 46 is a diagram showing a cross-sectional structure of primary windings, secondary windings, pads, and shield electrodes.
  • FIG. 47 is a diagram showing how the substrate-to-pad capacitance is shielded.
  • FIG. 48 is a diagram showing a second planar layout of the shield electrode in the region overlapping the pad.
  • FIG. 1 is a diagram showing the basic configuration of a signal transmission device.
  • the signal transmission device 200 of this configuration isolates between the primary circuit system 200p (VCC1-GND1 system) and the secondary circuit system 200s (VCC2-GND2 system), and the secondary circuit system 200s from the primary circuit system 200p
  • a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal to the secondary circuit system 200s and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s.
  • the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.
  • the controller chip 210 is a semiconductor chip that operates by being supplied with a power supply voltage VCC1 (for example, a maximum of 7 V based on GND1).
  • VCC1 for example, a maximum of 7 V based on GND1.
  • a pulse transmission circuit 211 and buffers 212 and 213 are integrated in the controller chip 210 .
  • the pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 according to the input pulse signal IN. More specifically, when the pulse transmission circuit 211 notifies that the input pulse signal IN is at a high level, the transmission pulse signal S11 is pulse-driven (single-shot or multiple-shot transmission pulse output) and the input pulse signal S11 is output. When notifying that the signal IN is at low level, the transmission pulse signal S21 is pulse-driven. That is, the pulse transmission circuit 211 pulse-drives one of the transmission pulse signals S11 and S21 according to the logic level of the input pulse signal IN.
  • the buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).
  • the buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).
  • the driver chip 220 is a semiconductor chip that operates by being supplied with a power supply voltage VCC2 (for example, 30 V maximum based on GND2). Buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 are integrated in the driver chip 220, for example.
  • VCC2 power supply voltage
  • Buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 are integrated in the driver chip 220, for example.
  • the buffer 221 waveform-shapes the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231 ) and outputs it to the pulse receiving circuit 223 .
  • the buffer 222 waveform-shapes the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs it to the pulse receiving circuit 223.
  • the pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 according to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 raises the output pulse signal OUT to a high level in response to the pulse drive of the reception pulse signal S12, and raises the output pulse signal OUT in response to the pulse drive of the reception pulse signal S22. Driver 224 is driven to fall to low level. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. As the pulse receiving circuit 223, for example, an RS flip-flop can be preferably used.
  • the driver 224 generates the output pulse signal OUT based on the driving control of the pulse receiving circuit 223.
  • the transformer chip 230 uses transformers 231 and 232 to provide DC isolation between the controller chip 210 and the driver chip 220, while transforming the transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 into the reception pulse signal S12. and output to the pulse receiving circuit 223 as S22.
  • the phrase "directly insulate" means that objects to be insulated are not connected by a conductor.
  • the transformer 231 outputs the reception pulse signal S12 from the secondary coil 231s in response to the transmission pulse signal S11 input to the primary coil 231p.
  • the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s according to the transmission pulse signal S21 input to the primary coil 232p.
  • the signal transmission device 200 of this configuration example independently has a transformer chip 230 on which only the transformers 231 and 232 are mounted separately from the controller chip 210 and the driver chip 220, and these three chips are integrated into a single chip. It is sealed in a package.
  • both the controller chip 210 and the driver chip 220 can be formed by a general low-to-medium-voltage process (withstand voltage of several V to several tens of V). It is no longer necessary to use a high withstand voltage process (several kV withstand voltage), making it possible to reduce manufacturing costs.
  • the signal transmission device 200 can be suitably used, for example, as a power supply device or a motor drive device for in-vehicle equipment mounted in a vehicle.
  • the above vehicles include electric vehicles (BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or FCEV / FCV (xEV such as fuel cell electric vehicle/fuel cell vehicle) is also included.
  • both the controller chip 210 and the driver chip 220 can be produced by existing proven processes, and there is no need to conduct a new reliability test, which shortens the development period and reduces the development cost. can contribute to reduction.
  • the controller chip 210 and the driver chip 220 can be It eliminates the need for redevelopment, which contributes to shortening the development period and reducing the development cost.
  • FIG. 2 is a diagram showing how potential fluctuations occur between GND1 and GND2. As shown in the figure, when a potential change ⁇ V/ ⁇ t (that is, noise) occurs between the ground potential GND1 of the primary circuit system 200p and the ground potential GND2 of the secondary circuit system 200s, the secondary side of the transformer chip 230 Noise may appear and interfere with signal transmission.
  • ⁇ V/ ⁇ t that is, noise
  • FIG. 3 is a diagram showing an example of malfunction due to common mode noise, depicting the input pulse signal IN, the received pulse signals S12 and S22, and the output pulse signal OUT in order from the top.
  • the normal pulse signal transmission operation will be briefly explained.
  • the transformer 231 is pulse-driven, so a normal pulse rises in the received pulse signal S12.
  • the output pulse signal OUT rises to high level.
  • the transformer 232 is pulse-driven, so a normal pulse rises in the received pulse signal S22.
  • the output pulse signal OUT falls to low level.
  • 4 to 7 are diagrams showing the principle of occurrence of abnormal signal transmission due to the common mode noise.
  • the signal transmission device 200 is required to have high common mode transient immunity (so-called CMTI [common mode transient immunity]).
  • FIG. 8 is a diagram showing an introduction example of a noise canceller (noise mask circuit) in the signal transmission device 200. As shown in FIG. In the signal transmission device 200 of this configuration example, a noise canceller 225 is introduced in the front stage of the pulse receiving circuit 223 in the driver chip 220 .
  • the noise canceller 225 of this configuration example includes buffers BUF1 to BUF4, delay units DLY1 to DLY4, and AND gates AND1 and AND2.
  • the buffer BUF1 raises the output signal to a high level when the received pulse signal S12 becomes higher than the threshold voltage Vth1, and raises the output signal to a low level when the received pulse signal S12 becomes lower than the threshold voltage Vth. Lower.
  • the buffer BUF2 raises the output signal to a high level when the received pulse signal S12 becomes higher than the threshold voltage Vth2 ( ⁇ Vth1), and raises the output signal when the received pulse signal S12 becomes lower than the threshold voltage Vth2. Drop to low level.
  • the buffer BUF3 raises the output signal to a high level when the received pulse signal S22 becomes higher than the threshold voltage Vth1, and raises the output signal to a low level when the received pulse signal S22 becomes lower than the threshold voltage Vth. Lower.
  • the buffer BUF4 raises the output signal to a high level when the received pulse signal S22 becomes higher than the threshold voltage Vth2 ( ⁇ Vth1), and raises the output signal when the received pulse signal S22 becomes lower than the threshold voltage Vth2. Drop to low level.
  • the delay unit DLY1 generates the main signal A1 by giving a predetermined delay to the output signal of the buffer BUF1.
  • the delay unit DLY2 generates a mask signal B2 by giving a predetermined delay to the output signal of the buffer BUF2. For example, the mask signal B2 falls to a low level without delay when the output signal of the buffer BUF2 rises to a high level, and rises to a high level when a predetermined mask period elapses.
  • the delay unit DLY3 generates the main signal B1 by giving a predetermined delay to the output signal of the buffer BUF3.
  • the delay unit DLY4 generates a mask signal A2 by giving a predetermined delay to the output signal of the buffer BUF4. For example, the mask signal A2 falls to a low level without delay when the output signal of the buffer BUF4 rises to a high level, and rises to a high level when a predetermined mask period elapses.
  • the pulse receiving circuit 223 sets the output pulse signal OUT to high level when the set signal A rises to high level, and resets the output pulse signal OUT to low level when the reset signal B rises to high level. do.
  • FIG. 9 is a diagram showing an example of noise canceling operation. From the top, the input pulse signal IN, the received pulse signal S12, the main signal A1, the mask signal A2, the set signal A, the received pulse signal S22, the main signal B1, A mask signal B2, a reset signal B, and an output pulse signal OUT are depicted.
  • the mask signal A2 falls to low level, so the set signal A is fixed to low level.
  • the set signal A should originally be maintained at a low level, so no mismatch occurs.
  • noise pulses rise in both the received pulse signals S12 and S22, and when they exceed the threshold voltages Vth1 and Vth2 of the buffers BUF1 to BUF4, respectively, pulses are generated in the main signals A1 and B1 and the mask signals A2 and B2. be.
  • the set signal A is fixed at low level regardless of the logic level of the main signal A1.
  • the reset signal B is fixed at low level regardless of the logic level of the main signal B1. Therefore, the common mode noise superimposed on both the received pulse signals S12 and S22 can be properly removed, so that malfunction of the output pulse signal OUT can be suppressed.
  • FIG. 10 is a diagram showing the basic structure of the transformer chip 230.
  • the transformer 231 includes a primary side coil 231p and a secondary side coil 231s facing each other in the vertical direction.
  • the transformer 232 includes a primary side coil 232p and a secondary side coil 232s facing each other in the vertical direction.
  • Both the primary side coils 231p and 232p are formed on the first wiring layer (lower layer) 230a of the transformer chip 230 .
  • the secondary coils 231 s and 232 s are both formed on the second wiring layer (upper layer in this figure) 230 b of the transformer chip 230 .
  • the secondary coil 231s is arranged directly above the primary coil 231p and faces the primary coil 231p.
  • the secondary coil 232s is arranged directly above the primary coil 232p and faces the primary coil 232p.
  • the primary coil 231p is spirally laid so as to surround the internal terminal X21 in a clockwise direction, starting from the first end connected to the internal terminal X21, and the second end corresponding to the end point is the internal terminal X21. It is connected to the terminal X22.
  • the primary coil 232p is spirally laid so as to surround the internal terminal X23 in a counterclockwise direction, starting from the first end connected to the internal terminal X23, and the second coil 232p corresponds to the end point.
  • the end is connected to the internal terminal X22.
  • the internal terminals X21, X22 and X23 are linearly arranged in the order shown.
  • the internal terminal X21 is connected to the external terminal T21 of the second layer 230b via the conductive wiring Y21 and via Z21.
  • the internal terminal X22 is connected to the external terminal T22 of the second layer 230b through a conductive wiring Y22 and via Z22.
  • the internal terminal X23 is connected to the external terminal T23 of the second layer 230b through the conductive wiring Y23 and via Z23.
  • the external terminals T21 to T23 are linearly arranged and used for wire bonding with the controller chip 210.
  • the secondary coil 231s is spirally laid so as to surround the external terminal T24 in a counterclockwise direction, starting from a first end connected to the external terminal T24, and a second end corresponding to the end point of the secondary coil 231s. is connected to the external terminal T25.
  • the secondary coil 232s is spirally laid so as to surround the periphery of the external terminal T26 in a clockwise direction, starting from the first end connected to the external terminal T26. The end is connected to the external terminal T25.
  • the external terminals T24, T25 and T26 are linearly arranged in the order shown in the figure and used for wire bonding with the driver chip 220.
  • the secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-insulated from the primary coils 231p and 232p. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230 and DC-insulated from the controller chip 210 by the transformer chip 230 .
  • FIG. 11 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip.
  • 12 is a plan view of the semiconductor device 5 shown in FIG. 11.
  • FIG. 13 is a plan view showing a layer in which the low potential coil 22 (corresponding to the primary side coil of the transformer) is formed in the semiconductor device 5 shown in FIG.
  • 15 is a cross-sectional view taken along line VIII-VIII shown in FIG. 14.
  • FIG. 16 is a cross-sectional view taken along line IX-IX shown in FIG. 14.
  • FIG. 17 is an enlarged view of the area X shown in FIG. 14.
  • FIG. FIG. 18 is an enlarged view of area XI shown in FIG.
  • FIG. 19 is an enlarged view of region XII shown in FIG.
  • FIG. 20 is an enlarged view of region XIII shown in FIG. 15 showing isolation structure 130 .
  • semiconductor device 5 includes a semiconductor chip 41 having a rectangular parallelepiped shape.
  • Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.
  • a wide bandgap semiconductor consists of a semiconductor that exceeds the bandgap of silicon (approximately 1.12 eV).
  • the bandgap of the wide bandgap semiconductor is preferably 2.0 eV or more.
  • the wide bandgap semiconductor may be SiC (silicon carbide).
  • the compound semiconductor may be a III-V compound semiconductor.
  • the compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).
  • the semiconductor chip 41 includes a semiconductor substrate made of silicon in this form.
  • the semiconductor chip 41 may be an epitaxial substrate having a laminated structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon.
  • the conductivity type of the semiconductor substrate may be n-type or p-type.
  • the epitaxial layer may be n-type or p-type.
  • the semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip side walls 44A to 44D connecting the first main surface 42 and the second main surface 43.
  • the first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular shape in this embodiment) in plan view (hereinafter simply referred to as "plan view") as seen from their normal direction Z. .
  • the chip sidewalls 44A-44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C and a fourth chip sidewall 44D.
  • the first chip side wall 44A and the second chip side wall 44B form long sides of the semiconductor chip 41 .
  • the first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y.
  • the third chip side wall 44C and the fourth chip side wall 44D form short sides of the semiconductor chip 41 .
  • the third chip side wall 44C and the fourth chip side wall 44D extend in the second direction Y and face the first direction X.
  • Chip side walls 44A-44D are ground surfaces.
  • the semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41 .
  • the insulating layer 51 has an insulating main surface 52 and insulating side walls 53A-53D.
  • the insulating main surface 52 is formed in a quadrangular shape (rectangular shape in this embodiment) matching the first main surface 42 in plan view.
  • the insulating main surface 52 extends parallel to the first main surface 42 .
  • the insulating sidewalls 53A-53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C and a fourth insulating sidewall 53D.
  • the insulating side walls 53A to 53D extend from the peripheral edge of the insulating main surface 52 toward the semiconductor chip 41 and connect to the chip side walls 44A to 44D. Specifically, the insulating sidewalls 53A-53D are formed flush with the chip sidewalls 44A-44D.
  • the insulating sidewalls 53A-53D form ground surfaces flush with the chip sidewalls 44A-44D.
  • the insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55 , a top insulating layer 56 and a plurality of (eleven layers in this embodiment) interlayer insulating layers 57 .
  • the bottom insulating layer 55 is an insulating layer that directly covers the first major surface 42 .
  • the top insulating layer 56 is an insulating layer that forms the insulating main surface 52 .
  • a plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56 .
  • the bottom insulating layer 55 has a single layer structure containing silicon oxide in this embodiment.
  • the top insulating layer 56 has a single layer structure containing silicon oxide in this form.
  • the thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 ⁇ m or more and 3 ⁇ m or less (for example, about 2 ⁇ m).
  • the plurality of interlayer insulating layers 57 each have a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side.
  • the first insulating layer 58 may contain silicon nitride.
  • the first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59 .
  • the thickness of the first insulating layer 58 may be 0.1 ⁇ m or more and 1 ⁇ m or less (for example, about 0.3 ⁇ m).
  • a second insulating layer 59 is formed on the first insulating layer 58 . It contains an insulating material different from the first insulating layer 58 .
  • the second insulating layer 59 may contain silicon oxide.
  • the thickness of the second insulating layer 59 may be 1 ⁇ m or more and 3 ⁇ m or less (for example, about 2 ⁇ m). The thickness of the second insulating layer 59 preferably exceeds the thickness of the first insulating layer 58 .
  • the total thickness DT of the insulating layer 51 may be 5 ⁇ m or more and 50 ⁇ m or less.
  • the total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary, and are adjusted according to the dielectric breakdown voltage (dielectric breakdown tolerance) to be achieved.
  • Insulating materials for the lowermost insulating layer 55, the uppermost insulating layer 56, and the interlayer insulating layer 57 are arbitrary, and are not limited to specific insulating materials.
  • the semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51.
  • the first functional device 45 includes one or more (in this form, more than one) transformers 21 (corresponding to the previously mentioned transformers).
  • the semiconductor device 5 is a multi-channel device including multiple transformers 21 .
  • a plurality of transformers 21 are formed in the inner portion of the insulating layer 51 spaced apart from the insulating sidewalls 53A-53D.
  • a plurality of transformers 21 are formed at intervals in the first direction X. As shown in FIG.
  • the plurality of transformers 21 are, in plan view, a first transformer 21A, a second transformer 21B, a third transformer 21C, and a first transformer 21A, a second transformer 21B, and a A fourth transformer 21D is included.
  • a plurality of transformers 21A-21D each have a similar structure.
  • the structure of the first transformer 21A will be described below as an example. Descriptions of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.
  • the first transformer 21A includes a low potential coil 22 and a high potential coil 23.
  • the low potential coil 22 is formed within the insulating layer 51 .
  • the high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. As shown in FIG.
  • the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (that is, the plurality of interlayer insulating layers 57) in this embodiment.
  • the low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41 ) side within the insulating layer 51
  • the high potential coil 23 is formed on the uppermost insulating layer 56 with respect to the low potential coil 22 within the insulating layer 51 . It is formed on the (insulating main surface 52) side. That is, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 interposed therebetween.
  • the low-potential coil 22 and the high-potential coil 23 can be arranged at any position. Also, the high-potential coil 23 may face the low-potential coil 22 with one or more interlayer insulating layers 57 interposed therebetween.
  • the distance between the low-potential coil 22 and the high-potential coil 23 (that is, the number of layers of the interlayer insulation layers 57) is appropriately adjusted according to the withstand voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23.
  • the low-potential coil 22 is formed on the third interlayer insulating layer 57 counted from the bottom insulating layer 55 side.
  • the high-potential coil 23 is formed on the first interlayer insulating layer 57 counted from the uppermost insulating layer 56 side.
  • the low-potential coil 22 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57 .
  • the low potential coil 22 includes a first inner end 24 , a first outer end 25 and a first helix 26 helically routed between the first inner end 24 and the first outer end 25 .
  • the first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in plan view. A portion forming the innermost peripheral edge of the first spiral portion 26 defines an elliptical first inner region 66 in plan view.
  • the number of turns of the first spiral portion 26 may be 5 or more and 30 or less.
  • the width of the first spiral portion 26 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the first spiral portion 26 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the first spiral portion 26 is defined by the width in the direction orthogonal to the spiral direction.
  • the first winding pitch of the first spiral portion 26 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first winding pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction orthogonal to the helical direction.
  • the winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary, and are not limited to the shapes shown in FIG. 13 and the like.
  • the first spiral portion 26 may be wound in a polygonal shape such as a triangular shape, a square shape, or a circular shape in a plan view.
  • the first inner region 66 may be divided into a polygonal shape such as a triangular shape, a quadrangular shape, or a circular shape in plan view according to the winding shape of the first spiral portion 26 .
  • the low potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum and tungsten.
  • the low potential coil 22 may have a laminated structure including barrier layers and body layers.
  • the barrier layer defines a recess space within the interlayer insulating layer 57 .
  • a body layer is embedded in the recessed space defined by the barrier layer.
  • the barrier layer may include at least one of titanium and titanium nitride.
  • the body layer may include at least one of copper, aluminum and tungsten.
  • the high-potential coil 23 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57 .
  • the high potential coil 23 includes a second inner end 27 , a second outer end 28 and a second helix 29 helically routed between the second inner end 27 and the second outer end 28 .
  • the second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in plan view.
  • the portion forming the innermost peripheral edge of the second spiral portion 29 defines an elliptical second inner region 67 in plan view.
  • the second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z. As shown in FIG.
  • the number of turns of the second spiral portion 29 may be 5 or more and 30 or less.
  • the number of turns of the second spiral portion 29 relative to the number of turns of the first spiral portion 26 is adjusted according to the voltage value to be boosted.
  • the number of turns of the second spiral portion 29 preferably exceeds the number of turns of the first spiral portion 26 .
  • the number of turns of the second spiral portion 29 may be less than the number of turns of the first spiral portion 26 or may be equal to the number of turns of the first spiral portion 26 .
  • the width of the second spiral portion 29 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the second spiral portion 29 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the second spiral portion 29 is defined by the width in the direction orthogonal to the spiral direction.
  • the width of the second spiral portion 29 is preferably equal to the width of the first spiral portion 26 .
  • the second winding pitch of the second spiral portion 29 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the second winding pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction orthogonal to the helical direction.
  • the second winding pitch is preferably equal to the first winding pitch of the first helix 26 .
  • the winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary, and are not limited to the shapes shown in FIG. 14 and the like.
  • the second spiral portion 29 may be wound in a polygonal shape such as a triangular shape, a square shape, or a circular shape in a plan view.
  • the second inner region 67 may be divided into a polygonal shape such as a triangular shape, a square shape, or a circular shape in plan view according to the winding shape of the second spiral portion 29 .
  • the high-potential coil 23 is preferably made of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes barrier layers and body layers, similar to the low-potential coil 22 .
  • semiconductor device 5 includes a plurality of (12 in this drawing) low potential terminals 11 and a plurality of (12 in this drawing) high potential terminals 12 .
  • a plurality of low potential terminals 11 are electrically connected to low potential coils 22 of corresponding transformers 21A to 21D, respectively.
  • a plurality of high potential terminals 12 are electrically connected to high potential coils 23 of corresponding transformers 21A to 21D, respectively.
  • a plurality of low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51 . Specifically, the plurality of low-potential terminals 11 are formed in a region on the side of the insulating sidewall 53B at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X. It is
  • the plurality of low potential terminals 11 includes a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. include.
  • Each of the plurality of low potential terminals 11A to 11F is formed two by two in this embodiment.
  • the number of the plurality of low potential terminals 11A-11F is arbitrary.
  • the first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view.
  • the second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view.
  • the third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view.
  • the fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view.
  • the fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view.
  • the sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.
  • the first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22).
  • the second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22).
  • the third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22).
  • the fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).
  • the fifth low potential terminal 11E is electrically connected to the first outer terminal 25 of the first transformer 21A (low potential coil 22) and the first outer terminal 25 of the second transformer 21B (low potential coil 22).
  • the sixth low potential terminal 11F is electrically connected to the first outer terminal 25 of the third transformer 21C (low potential coil 22) and the first outer terminal 25 of the fourth transformer 21D (low potential coil 22).
  • the plurality of high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low-potential terminals 11 . Specifically, the plurality of high-potential terminals 12 are formed in a region on the side of the insulating sidewall 53A spaced apart from the plurality of low-potential terminals 11 in the second direction Y, and are arranged in the first direction X at intervals. ing.
  • a plurality of high-potential terminals 12 are formed in regions adjacent to the corresponding transformers 21A to 21D in plan view.
  • the high potential terminal 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12. means.
  • the plurality of high-potential terminals 12 are formed at intervals along the first direction X so as to face the plurality of transformers 21A to 21D along the first direction X in plan view. . More specifically, the plurality of high potential terminals 12 are arranged along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and the region between the adjacent high potential coils 23 in plan view. formed with a gap. As a result, the plurality of high-potential terminals 12 are arranged in line with the plurality of transformers 21A to 21D in the first direction X in plan view.
  • the plurality of high potential terminals 12 includes a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E and a sixth high potential terminal 12F. include.
  • Each of the plurality of high-potential terminals 12A to 12F is formed two by two in this embodiment.
  • the number of high potential terminals 12A to 12F is arbitrary.
  • the first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in plan view.
  • the second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in plan view.
  • the third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in plan view.
  • the fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in plan view.
  • the fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in plan view.
  • the sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in plan view.
  • the first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23).
  • the second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23).
  • the third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23).
  • the fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).
  • the fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23).
  • the sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).
  • semiconductor device 5 includes first low-potential wiring 31, second low-potential wiring 32, first high-potential wiring 33 and second high-potential wiring formed in insulating layer 51, respectively. 34.
  • a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33 and a plurality of second high potential wirings 34 are formed.
  • the first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential.
  • the first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential.
  • the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.
  • the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Also, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D at the same potential in this form.
  • the plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively.
  • the multiple first low-potential wirings 31 have the same structure.
  • the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described below as an example.
  • the description of the structure of the other first low potential wiring 31 is omitted because the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.
  • the first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, and one or more (in this embodiment, more than one) pad plug electrodes. 76 , and one or more (in this form, more than one) substrate plug electrodes 77 .
  • the through wiring 71, the low potential connection wiring 72, the lead wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are made of the same conductive material as the low potential coil 22 and the like. It is preferable that they are formed respectively. That is, the through wiring 71, the low potential connection wiring 72, the lead wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are similar to the low potential coil 22 and the like. It preferably includes a barrier layer and a body layer, respectively.
  • the through wiring 71 penetrates the plurality of interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. As shown in FIG. Through wire 71 is formed in a region between lowermost insulating layer 55 and uppermost insulating layer 56 in insulating layer 51 in this embodiment.
  • the through wire 71 has an upper end portion on the uppermost insulating layer 56 side and a lower end portion on the lowermost insulating layer 55 side.
  • the upper end of the through wire 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and covered with the uppermost insulating layer 56 .
  • the lower end of the through wire 71 is formed on the same interlayer insulating layer 57 as the low potential coil 22 .
  • the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80 in this embodiment.
  • the first electrode layer 78, the second electrode layer 79, and the wire plug electrode 80 are made of the same conductive material as the low potential coil 22 and the like. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a body layer, like the low-potential coil 22 and the like.
  • the first electrode layer 78 forms the upper end of the through wire 71 .
  • the second electrode layer 79 forms the lower end of the through wire 71 .
  • the first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z.
  • the second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z. As shown in FIG.
  • a plurality of wiring plug electrodes 80 are embedded in a plurality of interlayer insulating layers 57 positioned between the first electrode layer 78 and the second electrode layer 79, respectively.
  • a plurality of wiring plug electrodes 80 are laminated from the bottom insulating layer 55 toward the top insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79 to each other. Connected.
  • the plurality of wiring plug electrodes 80 each have a planar area less than the planar area of the first electrode layer 78 and the planar area of the second electrode layer 79 .
  • the number of lamination of the plurality of wiring plug electrodes 80 matches the number of lamination of the plurality of interlayer insulating layers 57 .
  • the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary.
  • one or more wiring plug electrodes 80 may be formed penetrating the plurality of interlayer insulating layers 57 .
  • the low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22.
  • the low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. As shown in FIG.
  • the low-potential connection wiring 72 preferably has a plane area larger than that of the wiring plug electrode 80 .
  • a low potential connecting wire 72 is electrically connected to the first inner end 24 of the low potential coil 22 .
  • the lead wiring 73 is formed in a region between the semiconductor chip 41 and the through wiring 71 within the interlayer insulating layer 57 .
  • the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counted from the lowermost insulating layer 55 in this embodiment.
  • Lead wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end.
  • a first end of lead-out wiring 73 is located in a region between semiconductor chip 41 and the lower end of through-wiring 71 .
  • a second end of the lead wire 73 is located in a region between the semiconductor chip 41 and the low potential connection wire 72 .
  • the wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in a region between the first end portion and the second end portion.
  • the first connection plug electrode 74 is formed in a region between the through wire 71 and the lead wire 73 within the interlayer insulating layer 57 and is electrically connected to first ends of the through wire 71 and the lead wire 73 .
  • the second connection plug electrode 75 is formed in a region between the low-potential connection wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connection wiring 72 and the lead-out wiring 73 . It is
  • a plurality of pad plug electrodes 76 are formed in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wire 71 in the uppermost insulating layer 56, and are formed at the upper ends of the low potential terminal 11 and the through wire 71. They are electrically connected to each other.
  • a plurality of substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the lead wiring 73 within the lowermost insulating layer 55 . In this embodiment, the substrate plug electrode 77 is formed in a region between the semiconductor chip 41 and the first ends of the lead wires 73 and electrically connected to the semiconductor chip 41 and the first ends of the lead wires 73, respectively.
  • a plurality of second low potential wires 32 are electrically connected to corresponding low potential terminals 11E, 11F and first outer ends 25 of low potential coils 22 of corresponding transformers 21A-21D, respectively. It is The multiple second low-potential wirings 32 each have a similar structure.
  • the structure of the second low-potential wiring 32 connected to the fifth low-potential terminal 11E and the first transformer 21A (second transformer 21B) will be described below as an example.
  • the description of the structure of the second low-potential wiring 32 is omitted because the description of the structure of the second low-potential wiring 32 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis. .
  • the second low potential wiring 32 includes a through wiring 71, a low potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, a pad plug electrode 76 and a A substrate plug electrode 77 is included.
  • the second low potential wiring 32 has a low potential connecting wiring 72 connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). It has the same structure as the first low-potential wiring 31 except that it is electrically connected.
  • the low-potential connection wiring 72 of the second low-potential wiring 32 is formed around the low-potential coil 22 in the same interlayer insulating layer 57 as the low-potential coil 22 . Specifically, the low-potential connection wiring 72 is formed in a region between two adjacent low-potential coils 22 in plan view.
  • the pad plug electrode 76 is formed in a region between the low potential terminal 11 (fifth low potential terminal 11E) and the low potential connection wiring 72 in the uppermost insulating layer 56, and electrically connects the low potential terminal 11 and the low potential connection wiring 72. properly connected.
  • a plurality of first high potential wires 33 are electrically connected to corresponding high potential terminals 12A-12D and second inner ends 27 of corresponding transformers 21A-21D (high potential coils 23), respectively. It is connected.
  • the multiple first high-potential wirings 33 each have a similar structure.
  • the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described below as an example.
  • the description of the structure of the other first high-potential wiring 33 is omitted because the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.
  • the first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more than one) pad plug electrodes 82 .
  • the high potential connection wiring 81 and the pad plug electrode 82 are preferably made of the same conductive material as the low potential coil 22 and the like. That is, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a body layer like the low potential coil 22 and the like.
  • the high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23 .
  • the high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z.
  • a high potential connecting wire 81 is electrically connected to the second inner end 27 of the high potential coil 23 .
  • the high-potential connection wiring 81 is spaced from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z. As shown in FIG. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the withstand voltage of the insulation layer 51 is increased.
  • a plurality of pad plug electrodes 82 are formed in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connection wiring 81 in the uppermost insulating layer 56, are electrically connected to each other.
  • Each of the plurality of pad plug electrodes 82 has a plane area smaller than the plane area of the high-potential connection wiring 81 in plan view.
  • a plurality of second high potential wires 34 are electrically connected to corresponding high potential terminals 12E, 12F and second outer ends 28 of corresponding transformers 21A-21D (high potential coils 23), respectively. It is connected.
  • the multiple second high-potential wirings 34 each have a similar structure.
  • the structure of the second high potential wiring 34 connected to the fifth high potential terminal 12E and the first transformer 21A (second transformer 21B) will be described below as an example.
  • the description of the structure of the other second high potential wiring 34 shall apply mutatis mutandis, and is omitted. .
  • the second high-potential wiring 34 includes a high-potential connection wiring 81 and a pad plug electrode 82 like the first high-potential wiring 33 .
  • the second high potential wiring 34 has a high potential connecting wiring 81 to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). It has the same structure as the first high-potential wiring 33 except that it is electrically connected.
  • the high-potential connection wiring 81 of the second high-potential wiring 34 is formed around the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23 .
  • the high-potential connection wiring 81 is formed in a region between two adjacent high-potential coils 23 in plan view, and faces the high-potential terminal 12 (fifth high-potential terminal 12E) in the normal direction Z.
  • the high-potential connection wiring 81 is spaced from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z. As shown in FIG.
  • a plurality of pad plug electrodes 82 are formed in a region between the high potential terminal 12 (fifth high potential terminal 12E) and the high potential connection wiring 81 in the uppermost insulating layer 56 . are electrically connected to each other.
  • the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 ⁇ D1).
  • the distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT ⁇ D1).
  • a ratio D2/D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less.
  • the distance D1 is preferably 100 ⁇ m or more and 500 ⁇ m or less.
  • the distance D2 may be 1 ⁇ m or more and 50 ⁇ m or less.
  • the distance D2 is preferably 5 ⁇ m or more and 25 ⁇ m or less.
  • the values of the distance D1 and the distance D2 are arbitrary, and are appropriately adjusted according to the dielectric breakdown voltage to be achieved.
  • semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be positioned around transformers 21A to 21D in plan view. 17 to 19, dummy patterns 85 are indicated by hatching. Dummy pattern 85 includes a conductor. The dummy pattern 85 is preferably made of the same conductive material as the low potential coil 22 and the like. That is, the dummy pattern 85 preferably includes a barrier layer and a main body layer, like the low-potential coil 22 and the like.
  • the dummy pattern 85 is formed in a pattern (discontinuous pattern) different from that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. In other words, the dummy pattern 85 does not function as the transformers 21A-21D.
  • the dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D and suppresses electric field concentration on the high-potential coil 23.
  • the dummy pattern 85 is routed in a dense line shape so as to partially cover and partially expose the area around one or more high-potential coils 23 in plan view.
  • the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area.
  • the fact that the line density of the dummy patterns 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy patterns 85 is within ⁇ 20% of the line density of the high-potential coil 23 .
  • the dummy pattern 85 is preferably formed in a region close to the high potential coil 23 with respect to the low potential terminal 11 in plan view. That the dummy pattern 85 is close to the high potential coil 23 in plan view means that the distance between the dummy pattern 85 and the high potential coil 23 is less than the distance between the dummy pattern 85 and the low potential terminal 11 . .
  • the depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary, and is adjusted according to the electric field strength to be alleviated.
  • the dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 with respect to the normal direction Z. As shown in FIG.
  • the dummy pattern 85 being close to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is equal to the distance between the dummy pattern 85 and the low-potential coil 22 in the normal direction Z. means less than the distance of
  • electric field concentration on the high-potential coil 23 can be appropriately suppressed.
  • the electric field concentration on the high-potential coil 23 can be suppressed.
  • Dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as high-potential coil 23 . In this case, electric field concentration on the high-potential coil 23 can be suppressed more appropriately.
  • the dummy pattern 85 is preferably formed around the multiple high potential coils 23 so as to be interposed between the multiple high potential coils 23 adjacent to each other in plan view.
  • the area between the adjacent high-potential coils 23 can be used to suppress unwanted electric field concentration on the high-potential coils 23 .
  • the dummy pattern 85 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in plan view. In this case, unwanted conduction between the low potential terminal 11 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed. Dummy pattern 85 is preferably interposed in a region between low potential terminal 11 and high potential terminal 12 in plan view. In this case, unwanted conduction between the low potential terminal 11 and the high potential terminal 12 due to electric field concentration of the high potential coil 23 can be suppressed.
  • the dummy pattern 85 is formed along the multiple high-potential coils 23 in a plan view, and intervenes in regions between the multiple adjacent high-potential coils 23 . Moreover, the dummy pattern 85 collectively surrounds a region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12 in plan view. Also, the dummy pattern 85 is interposed in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential coils 23 in plan view. Also, the dummy pattern 85 is interposed in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential terminals 12A to 12F in plan view.
  • dummy pattern 85 includes a plurality of dummy patterns having different electrical states.
  • Dummy patterns 85 include high potential dummy patterns 86 .
  • the high-potential dummy pattern 86 is formed in the insulating layer 51 so as to be positioned around the transformers 21A to 21D in plan view.
  • the high-potential dummy pattern 86 is formed in a pattern (discontinuous pattern) different from that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. In other words, the high potential dummy pattern 86 does not function as the transformers 21A-21D.
  • the high-potential dummy pattern 86 is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in plan view.
  • the high potential dummy pattern 86 is routed with a line density equal to the line density of the high potential coil 23 per unit area.
  • the line density of the high-potential dummy pattern 86 being equal to the line density of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 is within ⁇ 20% of the line density of the high-potential coil 23. .
  • the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D, and suppresses electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 , thereby keeping the electric field leaking to the upper side of the high-potential coil 23 away from the high-potential coil 23 . As a result, electric field concentration in the high potential coil 23 caused by the electric field leaking to the upper side of the high potential coil 23 is suppressed.
  • a voltage exceeding the voltage applied to the low potential coil 22 is applied to the high potential dummy pattern 86 .
  • the voltage applied to the high potential coil 23 is preferably applied to the high potential dummy pattern 86 . That is, the high potential dummy pattern 86 is preferably fixed at the same potential as the high potential coil 23 .
  • the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86 can be reliably suppressed, so that the electric field concentration on the high-potential coil 23 can be appropriately suppressed.
  • the depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary, and is adjusted according to the electric field strength to be alleviated.
  • the high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 with respect to the normal direction Z. As shown in FIG.
  • the high-potential dummy pattern 86 being close to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is equal to the high-potential dummy pattern 86 and the low-potential coil 23 . It means less than the distance between the coils 22 .
  • electric field concentration on the high-potential coil 23 can be appropriately suppressed.
  • the electric field concentration on the high-potential coil 23 can be suppressed.
  • the high potential dummy pattern 86 is preferably formed in the same interlayer insulating layer 57 as the high potential coil 23 . In this case, electric field concentration on the high-potential coil 23 can be suppressed more appropriately.
  • the high-potential dummy pattern 86 is preferably formed in a region close to the high-potential coil 23 with respect to the low-potential terminal 11 in plan view.
  • the high-potential dummy pattern 86 being close to the high-potential coil 23 in plan view means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11 . It means that there is
  • the high-potential dummy pattern 86 is preferably formed around the high-potential coils 23 so as to be interposed between the high-potential coils 23 adjacent to each other in plan view.
  • the area between the adjacent high-potential coils 23 can be used to suppress unwanted electric field concentration on the high-potential coils 23 .
  • the high potential dummy pattern 86 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in plan view. In this case, unwanted conduction between the low potential terminal 11 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed.
  • High potential dummy pattern 86 is preferably interposed in a region between low potential terminal 11 and high potential terminal 12 in plan view. In this case, unwanted conduction between the low potential terminal 11 and the high potential terminal 12 due to electric field concentration of the high potential coil 23 can be suppressed.
  • the high potential dummy pattern 86 is formed along the plurality of high potential coils 23 in plan view, and intervenes in regions between the plurality of adjacent high potential coils 23 . Also, the high potential dummy pattern 86 collectively surrounds a region including the plurality of high potential coils 23 and the plurality of high potential terminals 12 in plan view. Also, the high potential dummy pattern 86 is interposed in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential coils 23 in plan view. Also, the high potential dummy pattern 86 is interposed in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential terminals 12A to 12F in plan view.
  • the high-potential dummy pattern 86 is drawn around the high-potential terminals 12E and 12F so as to expose regions immediately below the high-potential terminals 12E and 12F in regions between the plurality of high-potential coils 23 that are adjacent in plan view. being turned. A portion of the high potential dummy pattern 86 may face the high potential terminals 12A to 12F in the normal direction Z. FIG. In this case, the high potential terminals 12 ⁇ /b>E and 12 ⁇ /b>F, like the high potential dummy pattern 86 , suppress the electric field leaking to the upper side of the high potential coil 23 by shielding the electric field. That is, the high-potential terminals 12E and 12F are formed as shield conductor layers for suppressing electric field concentration on the high-potential coil 23 together with the high-potential dummy pattern 86 .
  • the high-potential dummy pattern 86 is preferably formed to have ends. In this case, formation of a current loop circuit (closed circuit) in the high-potential dummy pattern 86 can be suppressed. Thereby, noise caused by the current flowing through the high-potential dummy pattern 86 is suppressed. As a result, it is possible to suppress unwanted electric field concentration caused by noise, and at the same time, it is possible to suppress variations in the electrical characteristics of the transformers 21A to 21D.
  • the high potential dummy pattern 86 specifically includes a first high potential dummy pattern 87 and a second high potential dummy pattern 88 .
  • the first high-potential dummy pattern 87 is formed in a region between the plurality of transformers 21A to 21D (the plurality of high-potential coils 23) adjacent to each other in plan view.
  • the second high-potential dummy pattern 88 is formed in an area outside the area between the plurality of transformers 21A to 21D (the plurality of high-potential coils 23) adjacent to each other in plan view.
  • a region between the adjacent first transformer 21A (high potential coil 23) and second transformer 21B (high potential coil 23) is hereinafter referred to as a first region 89.
  • a region between the second transformer 21B (high potential coil 23) and the third transformer 21C (high potential coil 23) is called a second region 90.
  • FIG. A region between the third transformer 21C (high potential coil 23) and the fourth transformer 21D (high potential coil 23) is called a third region 91.
  • the first high-potential dummy pattern 87 is electrically connected to the high-potential terminal 12 (fifth high-potential terminal 12E) through the first high-potential wiring 33 in this embodiment.
  • the first high-potential dummy pattern 87 specifically includes a first connection portion 92 connected to the first high-potential wiring 33 .
  • the position of the first connecting portion 92 is arbitrary. Thereby, the first high-potential dummy pattern 87 is fixed to the same potential as the plurality of high-potential coils 23 .
  • the first high-potential dummy pattern 87 is a first pattern 93 formed in the first region 89, a second pattern 94 formed in the second region 90, and a third pattern 94 formed in the third region 91.
  • a third pattern 95 is included.
  • the first high-potential dummy pattern 87 suppresses the electric field leaking to the upper side of the high-potential coil 23 in the first region 89, the second region 90, and the third region 91, and prevents the adjacent high-potential coils 23 from leaking out. Suppress electric field concentration for
  • the first pattern 93, the second pattern 94 and the third pattern 95 are integrally formed and fixed at the same potential.
  • the first pattern 93, the second pattern 94 and the third pattern 95 may be separated as long as they are fixed at the same potential.
  • the first pattern 93 is connected to the first high-potential wiring 33 via the first connecting portion 92.
  • the first pattern 93 is drawn in a dense line shape so as to partially cover the first region 89 in plan view.
  • the first pattern 93 is formed in the first region 89 spaced apart from the high potential terminal 12 (fifth high potential terminal 12E) in plan view, and does not face the high potential terminal 12 in the normal direction Z.
  • the first pattern 93 is formed spaced apart from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z.
  • the insulation distance between the first pattern 93 and the low-potential connection wiring 72 is increased, and the withstand voltage of the insulation layer 51 is increased.
  • the first pattern 93 includes a first perimeter line 96 , a second perimeter line 97 and a plurality of first intermediate lines 98 .
  • the first outer peripheral line 96 extends in a strip shape along the periphery of the high-potential coil 23 of the first transformer 21A.
  • the first outer peripheral line 96 is formed in a ring shape having an open end in the first region 89 in plan view.
  • the width of the open end of the first peripheral line 96 is less than the width along the second direction Y of the high-potential coil 23 .
  • the width of the first peripheral line 96 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the first peripheral line 96 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the first perimeter line 96 is defined by the width in the direction perpendicular to the direction in which the first perimeter line 96 extends.
  • the width of the first peripheral line 96 is preferably equal to the width of the high potential coil 23 . That the width of the first outer peripheral line 96 is equal to the width of the high potential coil 23 means that the width of the first outer peripheral line 96 is within ⁇ 20% of the width of the high potential coil 23 .
  • the first pitch between the first outer peripheral line 96 and the high-potential coil 23 (first transformer 21A) may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the first pitch is preferably equal to the second winding pitch of the high potential coil 23 . That the first pitch is equal to the first winding pitch means that the first pitch falls within ⁇ 20% of the first winding pitch.
  • the second outer circumference line 97 extends in a belt shape along the circumference of the high-potential coil 23 of the second transformer 21B.
  • the second outer peripheral line 97 is formed in a ring shape having an open end in the first region 89 in plan view.
  • the width of the open end of the second outer peripheral line 97 is less than the width along the second direction Y of the high potential coil 23 .
  • the open end of the second outer peripheral line 97 faces the open end of the first outer peripheral line 96 along the first direction X. As shown in FIG.
  • the width of the second peripheral line 97 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the second peripheral line 97 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the second peripheral line 97 is defined by the width in the direction orthogonal to the direction in which the second peripheral line 97 extends.
  • the width of the second peripheral line 97 is preferably equal to the width of the high potential coil 23 . That the width of the second peripheral line 97 is equal to the width of the high-potential coil 23 means that the width of the second peripheral line 97 is within ⁇ 20% of the width of the high-potential coil 23 .
  • the second pitch between the second outer peripheral line 97 and the high potential coil 23 (second transformer 21B) may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the second pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the second pitch is preferably equal to the second winding pitch of the high potential coil 23 . That the second pitch is equal to the second winding pitch means that the second pitch falls within ⁇ 20% of the second winding pitch.
  • a plurality of first intermediate lines 98 extend in a strip shape in the first region 89 between the first outer peripheral line 96 and the second outer peripheral line 97 .
  • the plurality of first intermediate lines 98 includes at least one (one in this embodiment) first connection line 99 electrically connecting the first peripheral line 96 and the second peripheral line 97 .
  • the plurality of first intermediate lines 98 include only one first connection line 99 .
  • the position of the first connection line 99 is arbitrary.
  • At least one of the plurality of first intermediate lines 98 is formed with a slit 100 that cuts off a current loop circuit.
  • the positions of the slits 100 are appropriately adjusted by designing the plurality of first intermediate lines 98 .
  • the plurality of first intermediate lines 98 are preferably formed in strips extending along the facing direction of the plurality of high-potential coils 23 .
  • the plurality of first intermediate lines 98 are each formed in a band shape extending in the first direction X and are formed in the second direction Y at intervals.
  • the plurality of first intermediate lines 98 are formed in stripes extending in the first direction X as a whole when viewed from above.
  • the plurality of first intermediate lines 98 specifically includes a plurality of first lead-out portions 101 and a plurality of second lead-out portions 102 .
  • the plurality of first lead-out portions 101 are led out in stripes from the first outer peripheral line 96 toward the second outer peripheral line 97 .
  • the distal end portions of the plurality of first drawn portions 101 are spaced from the first outer peripheral line 96 toward the second outer peripheral line 97 side.
  • the plurality of second lead-out portions 102 are led out in stripes from the second outer peripheral line 97 toward the first outer peripheral line 96 .
  • the distal end portions of the plurality of second lead-out portions 102 are spaced from the second outer peripheral line 97 toward the first outer peripheral line 96 side.
  • the plurality of second lead-out portions 102 are alternately spaced apart from the plurality of first lead-out portions 101 in the second direction Y so as to sandwich one first lead-out portion 101 therebetween.
  • the plurality of second drawer portions 102 may sandwich the plurality of first drawer portions 101 . Also, the group including the plurality of second lead-out portions 102 may be formed so as to be adjacent to the group including the plurality of first lead-out portions 101 .
  • the slits 100 , the plurality of first lead portions 101 and the plurality of second lead portions 102 suppress the formation of current loop circuits in the first pattern 93 .
  • the width of the first intermediate line 98 in the second direction Y may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the first intermediate line 98 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the first intermediate line 98 is preferably equal to the width of the high potential coil 23 . That the width of the first intermediate line 98 is equal to the width of the high potential coil 23 means that the width of the first intermediate line 98 is within ⁇ 20% of the width of the high potential coil 23 .
  • the third pitch between two adjacent first intermediate lines 98 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the third pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • a third pitch is defined by the distance between adjacent first intermediate lines 98 with respect to the second direction Y. As shown in FIG.
  • the third pitches are preferably equal to each other. That the third pitches are equal to each other means that the third pitches fall within ⁇ 20% of the third pitch.
  • the third pitch is preferably equal to the second winding pitch of the high potential coil 23 . That the third pitch is equal to the second winding pitch means that the third pitch falls within ⁇ 20% of the second winding pitch.
  • the second pattern 94 is electrically connected to the high potential terminal 12 via the first high potential wiring 33. As shown in FIG. The second pattern 94 is electrically connected to the first high-potential wiring 33 (fifth high-potential terminal 12E) via the second outer peripheral line 97 of the first pattern 93 in this embodiment. The second pattern 94 is drawn in a dense line shape so as to cover the second region 90 .
  • the second pattern 94 includes the aforementioned second peripheral line 97 , third peripheral line 103 and a plurality of second intermediate lines 104 .
  • the third outer circumference line 103 extends in a belt shape along the circumference of the high potential coil 23 of the third transformer 21C.
  • the third outer peripheral line 103 is formed in a ring shape having an open end in the third region 91 in plan view.
  • the width of the open end of the third outer peripheral line 103 is less than the width along the second direction Y of the high potential coil 23 of the third transformer 21C.
  • the width of the third outer peripheral line 103 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the third outer peripheral line 103 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the third perimeter line 103 is defined by the width in the direction orthogonal to the direction in which the third perimeter line 103 extends.
  • the width of the third peripheral line 103 is preferably equal to the width of the high potential coil 23 . That the width of the third outer peripheral line 103 is equal to the width of the high potential coil 23 means that the width of the third outer peripheral line 103 is within ⁇ 20% of the width of the high potential coil 23 .
  • the fourth pitch between the third outer peripheral line 103 and the high potential coil 23 (third transformer 21C) may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the fourth pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the fourth pitch is preferably equal to the second winding pitch of the high potential coil 23 . That the fourth pitch is equal to the second winding pitch means that the fourth pitch falls within ⁇ 20% of the second winding pitch.
  • a plurality of second intermediate lines 104 extend in a strip shape in the second region 90 between the second outer peripheral line 97 and the third outer peripheral line 103 .
  • the plurality of second intermediate lines 104 includes at least one (one in this embodiment) second connection line 105 electrically connecting the second peripheral line 97 and the third peripheral line 103 .
  • the plurality of second intermediate lines 104 include only one second connection line 105 .
  • the second connecting line 105 may have a width exceeding that of the other second intermediate lines 104 .
  • the position of the second connection line 105 is arbitrary.
  • At least one of the plurality of second intermediate lines 104 is formed with a slit 106 that cuts off a current loop circuit. The positions of the slits 106 are appropriately adjusted by designing the plurality of second intermediate lines 104 .
  • the plurality of second intermediate lines 104 are preferably formed in strips extending along the facing direction of the plurality of high-potential coils 23 .
  • the plurality of second intermediate lines 104 are each formed in a band shape extending in the first direction X and are formed in the second direction Y at intervals.
  • the plurality of second intermediate lines 104 are formed in a stripe shape extending in the first direction X as a whole in plan view.
  • the plurality of second intermediate lines 104 specifically includes a plurality of third lead portions 107 and a plurality of fourth lead portions 108 .
  • a plurality of third lead portions 107 are led out in stripes from the second outer peripheral line 97 toward the third outer peripheral line 103 .
  • the distal end portions of the plurality of third drawn portions 107 are spaced from the third outer peripheral line 103 toward the second outer peripheral line 97 side.
  • the plurality of fourth lead-out portions 108 are led out in stripes from the third outer peripheral line 103 toward the second outer peripheral line 97 .
  • the distal end portions of the plurality of fourth drawn portions 108 are spaced apart from the second outer peripheral line 97 toward the third outer peripheral line 103 .
  • the plurality of fourth lead-out portions 108 are alternately spaced apart from the plurality of third lead-out portions 107 in the second direction Y so as to sandwich one third lead-out portion 107 therebetween.
  • the plurality of fourth drawer portions 108 may sandwich the plurality of third drawer portions 107 . Also, a group including a plurality of fourth lead portions 108 may be formed so as to be adjacent to a group including a plurality of third lead portions 107 .
  • the slits 106 , the plurality of third lead portions 107 and the plurality of fourth lead portions 108 suppress the formation of current loop circuits in the second pattern 94 .
  • the width of the second intermediate line 104 in the second direction Y may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the second intermediate line 104 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the second intermediate line 104 is preferably equal to the width of the high potential coil 23 . That the width of the second intermediate line 104 is equal to the width of the high potential coil 23 means that the width of the second intermediate line 104 is within ⁇ 20% of the width of the high potential coil 23 .
  • the fifth pitch between two adjacent second intermediate lines 104 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the fifth pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • a fifth pitch is defined by the distance between adjacent second intermediate lines 104 with respect to the second direction Y. As shown in FIG.
  • the fifth pitches are preferably equal to each other. That the fifth pitches are equal to each other means that the fifth pitches fall within a range of ⁇ 20% of the fifth pitch.
  • the fifth pitch is preferably equal to the second winding pitch of the high potential coil 23 . That the fifth pitch is equal to the second winding pitch means that the fifth pitch falls within ⁇ 20% of the second winding pitch.
  • the third pattern 95 is electrically connected to the first high-potential wiring 33. As shown in FIG. The third pattern 95 is electrically connected to the first high-potential wiring 33 via the second pattern 94 and the first pattern 93 in this embodiment.
  • the third pattern 95 is drawn in a dense line shape so as to cover a part of the third region 91 .
  • the third pattern 95 is formed in the third region 91 spaced apart from the high potential terminal 12 (sixth high potential terminal 12F) in plan view, and does not face the high potential terminal 12 in the normal direction Z.
  • the third pattern 95 is spaced apart from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the third pattern 95 and the low-potential connection wiring 72 is increased in the normal direction Z, and the withstand voltage of the insulation layer 51 is increased.
  • the third pattern 95 includes the aforementioned third peripheral line 103 , fourth peripheral line 109 and a plurality of third intermediate lines 110 .
  • the fourth outer circumference line 109 extends in a belt shape along the circumference of the high potential coil 23 of the fourth transformer 21D.
  • the fourth outer peripheral line 109 is formed in a ring shape having an open end in the third region 91 in plan view.
  • the width of the open end of the fourth outer peripheral line 109 is less than the width along the second direction Y of the high potential coil 23 of the fourth transformer 21D.
  • the open end of the fourth perimeter line 109 faces the open end of the third perimeter line 103 along the first direction X. As shown in FIG.
  • the width of the fourth outer peripheral line 109 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the fourth outer peripheral line 109 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the fourth perimeter line 109 is defined by the width in the direction orthogonal to the direction in which the fourth perimeter line 109 extends.
  • the width of the fourth peripheral line 109 is preferably equal to the width of the high potential coil 23 . That the width of the fourth outer peripheral line 109 is equal to the width of the high potential coil 23 means that the width of the fourth outer peripheral line 109 is within ⁇ 20% of the width of the high potential coil 23 .
  • the sixth pitch between the fourth outer peripheral line 109 and the high potential coil 23 (fourth transformer 21D) may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the sixth pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the sixth pitch means equal to the second winding pitch of the high potential coil 23 . That the sixth pitch is equal to the second winding pitch means that the sixth pitch falls within ⁇ 20% of the second winding pitch.
  • a plurality of third intermediate lines 110 extend in a strip shape in the third region 91 between the third outer peripheral line 103 and the fourth outer peripheral line 109 .
  • the plurality of third intermediate lines 110 includes at least one (one in this embodiment) third connection line 111 electrically connecting the third peripheral line 103 and the fourth peripheral line 109 .
  • the plurality of third intermediate lines 110 include only one third connection line 111 .
  • the position of the third connection line 111 is arbitrary.
  • At least one of the plurality of third intermediate lines 110 is formed with a slit 112 that cuts off a current loop circuit.
  • the positions of the slits 112 are appropriately adjusted by designing the plurality of third intermediate lines 110 .
  • the plurality of third intermediate lines 110 are preferably formed in strips extending along the facing direction of the plurality of high-potential coils 23 .
  • the plurality of third intermediate lines 110 are each formed in a band shape extending in the first direction X and are formed in the second direction Y at intervals.
  • the plurality of third intermediate lines 110 are formed in a stripe shape as a whole in plan view.
  • the plurality of third intermediate lines 110 includes a plurality of fifth lead portions 113 and a plurality of sixth lead portions 114 in this embodiment.
  • a plurality of fifth lead portions 113 are led out in stripes from the third outer peripheral line 103 toward the fourth outer peripheral line 109 .
  • the distal end portions of the plurality of fifth drawn portions 113 are spaced from the fourth outer peripheral line 109 toward the third outer peripheral line 103 side.
  • the plurality of sixth lead-out portions 114 are led out in stripes from the fourth outer peripheral line 109 toward the third outer peripheral line 103 .
  • the distal end portions of the plurality of sixth drawn portions 114 are spaced from the third outer peripheral line 103 toward the fourth outer peripheral line 109 side.
  • the plurality of sixth drawn portions 114 are formed alternately with the plurality of fifth drawn portions 113 in the second direction Y so as to sandwich one fifth drawn portion 113 .
  • the plurality of sixth drawn portions 114 may sandwich the plurality of fifth drawn portions 113 . Also, the group including the plurality of sixth drawn portions 114 may be formed adjacent to the group including the plurality of fifth drawn portions 113 .
  • the slits 112 , the plurality of fifth lead portions 113 and the plurality of sixth lead portions 114 suppress the formation of current loop circuits in the third pattern 95 .
  • the width of the third intermediate line 110 in the second direction Y may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the third intermediate line 110 is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the third intermediate line 110 is preferably equal to the width of the high potential coil 23 . That the width of the third intermediate line 110 is equal to the width of the high potential coil 23 means that the width of the third intermediate line 110 is within ⁇ 20% of the width of the high potential coil 23 .
  • the seventh pitch between two adjacent third intermediate lines 110 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the seventh pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • a seventh pitch is defined by the distance between adjacent third intermediate lines 110 with respect to the second direction Y. As shown in FIG.
  • the seventh pitches are preferably equal to each other. That the seventh pitches are equal to each other means that the seventh pitches fall within a range of ⁇ 20% of the seventh pitch.
  • the seventh pitch is preferably equal to the second winding pitch of the high potential coil 23 . That the seventh pitch is equal to the second winding pitch means that the seventh pitch falls within ⁇ 20% of the second winding pitch.
  • the second high potential dummy pattern 88 is electrically connected to the high potential terminal 12 via the first high potential dummy pattern 87 in this embodiment.
  • the second high potential dummy pattern 88 specifically includes a second connection portion 115 connected to the first high potential dummy pattern 87 .
  • the position of the second connecting portion 115 is arbitrary. Thereby, the second high-potential dummy pattern 88 is fixed at the same potential as the plurality of high-potential coils 23 .
  • the second high-potential dummy pattern 88 suppresses the electric field leaking to the upper side of the high-potential coils 23 in regions other than the first region 89 , the second region 90 and the third region 91 , and suppresses the electric field to the plurality of high-potential coils 23 . curb concentration.
  • the second high-potential dummy pattern 88 collectively surrounds a region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12A to 12F in plan view.
  • the second high-potential dummy pattern 88 is formed in an oval ring shape (elliptical ring shape) in plan view.
  • the second high potential dummy pattern 88 is interposed in the region between the plurality of low potential terminals 11A to 11F and the plurality of high potential coils 23 in plan view. Also, the second high potential dummy pattern 88 is interposed in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential terminals 12A to 12F in plan view.
  • the second high potential dummy pattern 88 includes a plurality (six in this embodiment) of high potential lines 116A, 116B, 116C, 116D, 116E and 116F.
  • the number of high potential lines is adjusted according to the electric field to be relieved.
  • the plurality of high potential lines 116A to 116F are spaced apart in this order in the direction away from the plurality of high potential coils 23. As shown in FIG.
  • the plurality of high potential lines 116A to 116F collectively surround the plurality of high potential coils 23 in plan view. Specifically, the plurality of high potential lines 116A to 116F collectively surrounds a region including the plurality of high potential coils 23 and the plurality of high potential terminals 12A to 12F in plan view.
  • the plurality of high-potential lines 116A to 116F are formed in an oval ring shape (elliptical ring shape) in plan view in this embodiment.
  • a plurality of high potential lines 116A to 116F each include a slit 117 that cuts off a current loop circuit.
  • the positions of the slits 117 are appropriately adjusted according to the design of the plurality of high potential lines 116A-116F.
  • the width of the high potential lines 116A to 116F may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the high potential lines 116A to 116F is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the high potential lines 116A-116F is defined by the width in the direction orthogonal to the direction in which the high potential lines 116A-116F extend.
  • the width of the high potential lines 116A-116F is preferably equal to the width of the high potential coil 23.
  • FIG. That the width of the high potential lines 116A to 116F is equal to the width of the high potential coil 23 means that the width of the high potential lines 116A to 116F is within ⁇ 20% of the width of the high potential coil 23.
  • the eighth pitch between two adjacent high potential lines 116A to 116F may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the eighth pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the eighth pitches are preferably equal to each other. That the eighth pitches are equal to each other means that the eighth pitches fall within ⁇ 20% of the eighth pitches.
  • the ninth pitch between the adjacent first high-potential dummy pattern 87 and second high-potential dummy pattern 88 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the ninth pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the ninth pitch is preferably equal to the second winding pitch of the high potential coil 23 .
  • the ninth pitch being equal to the second winding pitch means that the ninth pitch falls within ⁇ 20% of the second winding pitch.
  • the number, width, pitch, etc. of the plurality of high potential lines 116A to 116F are arbitrary and adjusted according to the electric field to be relieved.
  • dummy pattern 85 includes floating dummy pattern 121 formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D in plan view. .
  • the floating dummy pattern 121 is formed in a pattern (discontinuous pattern) different from that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. In other words, the floating dummy pattern 121 does not function as the transformers 21A-21D.
  • the floating dummy pattern 121 is drawn in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in plan view.
  • the floating dummy pattern 121 may be formed in a shape with an end, or may be formed in a shape without an end.
  • the floating dummy pattern 121 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the floating dummy patterns 121 is equal to the line density of the high-potential coil 23 means that the line density of the floating dummy patterns 121 is within ⁇ 20% of the line density of the high-potential coil 23 .
  • the floating dummy pattern 121 is routed with a line density equal to the line density of the high-potential dummy pattern 86 per unit area.
  • the line density of the floating dummy pattern 121 being equal to the line density of the high potential dummy pattern 86 means that the line density of the floating dummy pattern 121 is within ⁇ 20% of the line density of the high potential dummy pattern 86. .
  • the floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D and suppresses electric field concentration on the high-potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential coil 23 in the direction away from the high-potential coil 23 . As a result, electric field concentration on the high-potential coil 23 can be suppressed.
  • the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in the direction away from the high-potential coil 23 and the high-potential dummy pattern 86 .
  • electric field concentration on the high-potential dummy pattern 86 can be suppressed, and electric field concentration on the high-potential coil 23 can be appropriately suppressed.
  • the depth position of the floating dummy pattern 121 inside the insulating layer 51 is arbitrary, and is adjusted according to the electric field strength to be relaxed.
  • the floating dummy pattern 121 is preferably formed in a region closer to the high potential coil 23 with respect to the normal direction Z than the low potential coil 22 .
  • the fact that the floating dummy pattern 121 is close to the high potential coil 23 in the normal direction Z means that the distance between the floating dummy pattern 121 and the high potential coil 23 in the normal direction Z is equal to that of the floating dummy pattern 121 and the low potential coil 22. means less than the distance between
  • electric field concentration on the high-potential coil 23 can be appropriately suppressed.
  • electric field concentration on the high-potential coil 23 can be suppressed.
  • the floating dummy pattern 121 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23 . In this case, electric field concentration on the high-potential coil 23 can be suppressed more appropriately.
  • the floating dummy pattern 121 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in plan view. In this case, unwanted conduction between the low potential terminal 11 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed.
  • Floating dummy pattern 121 is preferably interposed in a region between low potential terminal 11 and high potential terminal 12 in plan view. In this case, unwanted conduction between the low potential terminal 11 and the high potential terminal 12 due to electric field concentration of the high potential coil 23 can be suppressed.
  • the floating dummy pattern 121 is formed along the multiple high-potential coils 23 in plan view. Specifically, the floating dummy pattern 121 collectively surrounds a region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12 in plan view. In this form, the floating dummy pattern 121 collectively covers a region including the plurality of high potential coils 23 and the plurality of high potential terminals 12 with the high potential dummy pattern 86 (second high potential dummy pattern 88) sandwiched therebetween in plan view. Surrounding.
  • the floating dummy pattern 121 is interposed in the region between the plurality of low potential terminals 11A to 11F and the plurality of high potential coils 23 in plan view. Further, the floating dummy pattern 121 is interposed in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential terminals 12A to 12F in plan view.
  • the number of floating lines is arbitrary and adjusted according to the electric field to be relaxed.
  • the floating dummy pattern 121 in this form includes a plurality of (six in this figure) floating lines 122A, 122B, 122C, 122D, 122E, and 122F.
  • the plurality of floating lines 122A to 122F are spaced apart in this order in the direction away from the plurality of high-potential coils 23. As shown in FIG.
  • the multiple floating lines 122A to 122F collectively surround the multiple high-potential coils 23 in plan view. Specifically, the plurality of floating lines 122A to 122F collectively surrounds a region including the plurality of high potential coils 23 and the plurality of high potential terminals 12A to 12F with the high potential dummy pattern 86 interposed therebetween in plan view. . In this form, the plurality of floating lines 122A to 122F are formed in an oval ring shape (elliptic ring shape) in plan view.
  • the width of the floating lines 122A to 122F may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the floating lines 122A-122F is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the floating lines 122A-122F is defined by the width in the direction orthogonal to the direction in which the floating lines 122A-122F extend.
  • a tenth pitch between two adjacent floating lines 122A to 122F may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the tenth pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the width of floating lines 122A-122F is preferably equal to the width of high potential coil . That the width of the floating lines 122A to 122F is equal to the width of the high potential coil 23 means that the width of the floating lines 122A to 122F is within ⁇ 20% of the width of the high potential coil .
  • the eleventh pitch between the floating dummy pattern 121 and the high potential dummy pattern 86 (second high potential dummy pattern 88) may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the eleventh pitch is preferably 1 ⁇ m or more and 3 ⁇ m or less.
  • the eleventh pitches are preferably equal to each other. That the 11th pitches are equal to each other means that the 11th pitches fall within ⁇ 20% of the 11th pitch.
  • the eleventh pitch is preferably equal to the second winding pitch of the high potential coil 23.
  • the eleventh pitch between the floating lines 122A-122F being equal to the second winding pitch means that the eleventh pitch is within ⁇ 20% of the second winding pitch. 12 to 14 show examples in which the eleventh pitch exceeds the second winding pitch for clarity.
  • the twelfth pitch between the floating dummy pattern 121 and the high potential dummy pattern 86 is preferably equal to the second winding pitch.
  • the twelfth pitch being equal to the second winding pitch means that the twelfth pitch is within ⁇ 20% of the second winding pitch.
  • the number, width, pitch, etc. of the plurality of floating lines 122A-122F are adjusted according to the electric field to be relieved, and are not limited to specific values.
  • the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in the device region 62.
  • the second functional device 60 is formed using the surface layer portion of the first main surface 42 of the semiconductor chip 41 and/or the region above the first main surface 42 of the semiconductor chip 41, and includes the insulating layer 51 (lowermost It is covered by an insulating layer 55).
  • the second functional device 60 is simply indicated by the dashed line on the surface layer of the first main surface 42. As shown in FIG.
  • the second functional device 60 is electrically connected to the low potential terminal 11 via the low potential wiring and electrically connected to the high potential terminal 12 via the high potential wiring.
  • the low potential wiring has the same structure as the first low potential wiring 31 (second low potential wiring 32) except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. have.
  • the high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34) except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. have.
  • a detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 is omitted.
  • the second functional device 60 may include at least one of a passive device, a semiconductor rectifying device and a semiconductor switching device.
  • the passive device, the second functional device 60 may include a network in which any two or more of passive devices, semiconductor rectifying devices and semiconductor switching devices are selectively combined.
  • the circuitry may form part or all of an integrated circuit.
  • Passive devices may include semiconductor passive devices. Passive devices may include either or both resistors and capacitors.
  • the semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode and a fast recovery diode.
  • the semiconductor switching device may include at least one of BJT [Bipolar Junction Transistor], MISFET [Metal Insulator Field Effect Transistor], IGBT [Insulated Gate Bipolar Junction Transistor] and JFET [Junction Field Effect Transistor].
  • the semiconductor device 5 further includes a seal conductor 61 embedded within the insulating layer 51.
  • the seal conductor 61 is embedded in the insulating layer 51 in a wall shape with a gap from the insulating side walls 53A to 53D in plan view, and partitions the insulating layer 51 into a device region 62 and an outer region 63 .
  • the seal conductor 61 suppresses entry of moisture and cracks from the outer region 63 into the device region 62 .
  • the device region 62 includes a first functional device 45 (plurality of transformers 21), a second functional device 60, a plurality of low potential terminals 11, a plurality of high potential terminals 12, a first low potential wiring 31, and a second low potential wiring. 32 , first high potential wiring 33 , second high potential wiring 34 and dummy pattern 85 .
  • the outer area 63 is an area outside the device area 62 .
  • the seal conductor 61 is electrically separated from the device region 62 .
  • the seal conductor 61 includes the first functional device 45 (the plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, It is electrically separated from the second low potential wiring 32 , the first high potential wiring 33 , the second high potential wiring 34 and the dummy pattern 85 . More specifically, the seal conductor 61 is fixed in an electrically floating state. Seal conductor 61 does not form a current path leading to device region 62 .
  • the seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view.
  • the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view.
  • the seal conductor 61 defines a quadrangular (specifically rectangular) device region 62 in plan view.
  • the seal conductor 61 defines an outer region 63 of a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view.
  • the seal conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending like a wall between the upper end portion and the lower end portion.
  • the upper end of the seal conductor 61 is spaced from the insulating main surface 52 toward the semiconductor chip 41 and positioned within the insulating layer 51 .
  • the upper end of the seal conductor 61 is covered with the top insulating layer 56 in this embodiment.
  • the upper ends of the seal conductors 61 may be covered by one or more interlayer insulation layers 57 .
  • the top end of the seal conductor 61 may be exposed from the top insulating layer 56 .
  • the bottom end of the seal conductor 61 is spaced from the semiconductor chip 41 toward the top end.
  • the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12 .
  • the seal conductor 61 includes the first functional device 45 (the plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, and the second high-potential wiring within the insulating layer 51. It faces the wiring 34 and the dummy pattern 85 in a direction parallel to the insulating main surface 52 .
  • the seal conductor 61 may face a portion of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating main surface 52 .
  • the seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, more than one) seal via conductors 65 .
  • the number of seal via conductors 65 is arbitrary.
  • An uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61 .
  • a plurality of seal via conductors 65 form the lower ends of the seal conductors 61 respectively.
  • Seal plug conductor 64 and seal via conductor 65 are preferably made of the same conductive material as low potential coil 22 . That is, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a body layer like the low potential coil 22 and the like.
  • the plurality of seal plug conductors 64 are respectively embedded in the plurality of interlayer insulating layers 57 and formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view.
  • a plurality of seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other.
  • the number of laminated seal plug conductors 64 matches the number of laminated interlayer insulating layers 57 .
  • one or more seal plug conductors 64 may be formed to penetrate the multiple interlayer insulating layers 57 .
  • an assembly of a plurality of seal plug conductors 64 forms one annular seal conductor 61, it is not necessary for all of the plurality of seal plug conductors 64 to be annular.
  • at least one of the plurality of seal plug conductors 64 may be formed with ends.
  • at least one of the plurality of seal plug conductors 64 may be divided into a plurality of band-like portions with ends.
  • the plurality of seal plug conductors 64 be endless (annular).
  • a plurality of seal via conductors 65 are formed in regions between the semiconductor chip 41 and the seal plug conductors 64 in the bottom insulating layer 55 .
  • a plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductors 64 .
  • the plurality of seal via conductors 65 have plane areas less than the plane area of the seal plug conductors 64 .
  • the single seal via conductor 65 may have a planar area equal to or larger than the planar area of the seal plug conductor 64 .
  • the width of the seal conductor 61 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the seal conductor 61 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the seal conductor 61 is defined by the width in the direction orthogonal to the extending direction of the seal conductor 61 .
  • semiconductor device 5 further includes isolation structure 130 interposed between semiconductor chip 41 and seal conductor 61 for electrically isolating seal conductor 61 from semiconductor chip 41 .
  • Isolation structure 130 preferably includes an insulator.
  • the isolation structure 130 consists of the field insulating film 131 formed in the 1st main surface 42 of the semiconductor chip 41 in this form.
  • the field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film).
  • the field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41 .
  • the thickness of the field insulating film 131 is arbitrary as long as the semiconductor chip 41 and the seal conductor 61 can be insulated.
  • Field insulating film 131 may have a thickness of 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in plan view.
  • the separation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view.
  • the separation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected.
  • the connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65 ) of the seal conductor 61 bites toward the semiconductor chip 41 side.
  • the connecting portion 132 may be formed flush with the main surface of the isolation structure 130 .
  • the isolation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a body portion 130C between the inner end portion 130A and the outer end portion 130B.
  • the inner end portion 130A defines a region in which the second functional device 60 is formed (that is, the device region 62) in plan view.
  • the inner end portion 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41 .
  • the outer end portion 130B is exposed from the chip side walls 44A to 44D of the semiconductor chip 41 and continues to the chip side walls 44A to 44D of the semiconductor chip 41. As shown in FIG. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. As shown in FIG. The outer end portion 130B forms a flush ground surface between the chip side walls 44A to 44D of the semiconductor chip 41 and the insulating side walls 53A to 53D of the insulating layer 51. As shown in FIG. Of course, in another form, the outer end 130B may be formed in the first major surface 42 spaced apart from the chip sidewalls 44A-44D.
  • the main body portion 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41 .
  • the body portion 130C has a connecting portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected.
  • the connecting portion 132 is formed at a portion of the body portion 130C spaced apart from the inner end portion 130A and the outer end portion 130B.
  • the isolation structure 130 can take various forms other than the field insulating film 131 .
  • semiconductor device 5 further includes inorganic insulating layer 140 formed on insulating main surface 52 of insulating layer 51 so as to cover seal conductor 61 .
  • Inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52 .
  • the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142 in this form.
  • the first inorganic insulating layer 141 may contain silicon oxide.
  • the first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide with no impurity added.
  • the thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less.
  • the second inorganic insulating layer 142 may contain silicon nitride.
  • the thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less.
  • the breakdown voltage (V/cm) of USG exceeds the breakdown voltage (V/cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142 .
  • the first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass) as an example of silicon oxide. However, in this case, since silicon oxide contains impurities (boron or phosphorus), it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the withstand voltage on the high-potential coil 23 . .
  • the inorganic insulating layer 140 may have a single layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142 .
  • the inorganic insulating layer 140 covers the entire area of the seal conductor 61 and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed outside the seal conductor 61 .
  • a plurality of low potential pad openings 143 expose a plurality of low potential terminals 11 respectively.
  • a plurality of high potential pad openings 144 respectively expose a plurality of high potential terminals 12 .
  • the inorganic insulating layer 140 may have an overlapping portion that runs over the peripheral portion of the low potential terminal 11 .
  • the inorganic insulating layer 140 may have an overlapping portion overlying the peripheral portion of the high potential terminal 12 .
  • the semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140 .
  • the organic insulating layer 145 may contain a photosensitive resin.
  • Organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole.
  • Organic insulating layer 145 comprises polyimide in this form.
  • the thickness of the organic insulating layer 145 may be 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140 . Furthermore, the total thickness of inorganic insulating layer 140 and organic insulating layer 145 is preferably equal to or greater than distance D2 between low potential coil 22 and high potential coil 23 . In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 ⁇ m or more and 10 ⁇ m or less. Also, the thickness of the organic insulating layer 145 is preferably 5 ⁇ m or more and 50 ⁇ m or less.
  • the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 appropriately increases the withstand voltage of the high-potential coil 23. be able to.
  • the organic insulating layer 145 includes a first portion 146 covering the low potential side region and a second portion 147 covering the high potential side region.
  • the first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 interposed therebetween.
  • the first portion 146 has a plurality of low potential terminal openings 148 exposing the plurality of low potential terminals 11 (low potential pad openings 143 ) respectively in a region outside the seal conductor 61 .
  • the first portion 146 may have an overlap portion that runs over the periphery (overlap portion) of the low potential pad opening 143 .
  • the second portion 147 is spaced apart from the first portion 146 and exposes the inorganic insulating layer 140 between the first portion 146 and the second portion 147 .
  • the second portion 147 has a plurality of high potential terminal openings 149 that respectively expose a plurality of high potential terminals 12 (high potential pad openings 144).
  • the second portion 147 may have an overlapping portion that runs over the periphery (overlap portion) of the high potential pad opening 144 .
  • the second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121. are doing.
  • the plurality of high potential coils 23, the plurality of high potential terminals 12, the seal conductor 61, and the first high potential dummy pattern are caused by the filler contained in the package body (mold resin).
  • the second high potential dummy pattern 88 and the floating dummy pattern 121 may be damaged. This kind of damage is called a filler attack.
  • the organic insulating layer 145 includes a plurality of high-potential coils 23, a plurality of high-potential terminals 12, a seal conductor 61, a first high-potential dummy pattern 87, a second high-potential dummy pattern, and a filler contained in a package body (mold resin). 88 and the floating dummy pattern 121 are protected. A slit between the first portion 146 and the second portion 147 functions as an anchor portion for the package body (mold resin).
  • a portion of the package body (mold resin) enters the slit between the first portion 146 and the second portion 147 and is connected to the inorganic insulating layer 140 .
  • the adhesion of the package body (mold resin) to the semiconductor device 5 is enhanced.
  • the first portion 146 and the second portion 147 may be integrally formed.
  • the organic insulating layer 145 may include only one of the first portion 146 and the second portion 147 . However, in this case, it is necessary to pay attention to filler attacks.
  • Embodiments of the present invention can be implemented in other forms.
  • an example in which the first functional device 45 and the second functional device 60 are formed has been described.
  • a form having only the second functional device 60 without having the first functional device 45 may be employed.
  • dummy pattern 85 may be removed.
  • the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).
  • the second functional device 60 is formed.
  • the second functional device 60 is not necessarily required and may be removed.
  • the dummy pattern 85 is formed.
  • the dummy pattern 85 is not necessarily required and may be removed.
  • the first functional device 45 is of a multi-channel type including a plurality of transformers 21 .
  • a single-channel first functional device 45 including a single transformer 21 may be employed.
  • FIG. 21 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel type transformer chip 300 (corresponding to the semiconductor device 5 described above).
  • the transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, and pads a1 to a8. , pads b1 to b8, pads c1 to c4, and pads d1 to d4.
  • pads a1 and b1 are connected to one end of the secondary coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. ing.
  • Pads a2 and b2 are connected to one end of the secondary coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.
  • Pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s.
  • Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.
  • the primary coils L1p to L4p basically have the same configuration as the secondary coils L1s to L4s, respectively. It is arranged directly under each of L1s to L4s.
  • the pads a5 and b5 are connected to one end of the primary coil L1p forming the first transformer 301, and the pads c3 and d3 are connected to the other end of the primary coil L1p.
  • Pads a6 and b6 are connected to one end of the primary coil L2p forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil L2p.
  • Pads a7 and b7 are connected to one end of the primary coil L3p forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil L3p.
  • Pads a8 and b8 are connected to one end of the primary coil L4p forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil L4p.
  • pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are pulled out from the inside of the transformer chip 300 to the surface via vias (not shown).
  • pads a1 to a8 respectively correspond to first current supply pads
  • pads b1 to b8 respectively correspond to first voltage measurement pads
  • Pads c1 to c4 respectively correspond to second current supply pads
  • pads d1 to d4 respectively correspond to second voltage measurement pads.
  • the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, in addition to rejecting defective products in which each coil is disconnected, it is also necessary to appropriately reject defective products in which the resistance value of each coil is abnormal (for example, a short circuit between coils). is possible, and by extension, it becomes possible to prevent the outflow of defective products to the market.
  • the plurality of pads may be used as connection means with the primary side chip and the secondary side chip (for example, the controller chip 210 and the driver chip 220 described above). .
  • pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input end or signal output end of the secondary chip, respectively.
  • Pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.
  • pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input end or signal output end of the primary chip, respectively.
  • Pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.
  • the first to fourth transformers 301 to 304 are coupled and arranged for each signal transmission direction.
  • a first transformer 301 and a second transformer 302 that transmit signals from the primary chip to the secondary chip are formed into a first pair by a first guard ring 305 .
  • a third transformer 303 and a fourth transformer 304 that transmit signals from the secondary chip to the primary chip are formed into a second pair by a second guard ring 306 .
  • the reason for such coupling is that when the primary side coils and secondary side coils forming the first to fourth transformers 301 to 304 are laminated in the vertical direction of the substrate of the transformer chip 300, This is to ensure a withstand voltage between the primary coil and the secondary coil.
  • the first guard ring 305 and the second guard ring 306 are not necessarily essential components.
  • first guard ring 305 and the second guard ring 306 may be connected to low-impedance wiring such as ground terminals via pads e1 and e2, respectively.
  • the pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s.
  • the pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s.
  • the pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p.
  • the pads c4 and d4 are shared between the primary coil L3p and the primary coil L4p.
  • the primary coils and secondary coils forming the first to fourth transformers 301 to 304 are rectangular (or tracks with rounded corners) in plan view of the transformer chip 300 . shape). With such a configuration, the area of the portion where the primary side coil and the secondary side coil overlap becomes large, and it is possible to improve the transmission efficiency of the transformer.
  • transformer arrangement in this figure is only an example, and the number, shape, and arrangement of coils and the arrangement of pads are arbitrary. Also, the chip structure and transformer arrangement described so far can be applied to general semiconductor devices in which coils are integrated on a semiconductor chip.
  • FIG. 22 is a diagram showing an example of introducing a shield electrode in the transformer chip 230.
  • FIG. For comparison, the left side of the figure shows a transformer chip 230 having a conventional structure in which no shield electrode is introduced.
  • the right side of the drawing shows a transformer chip 230 with a novel structure in which shield electrodes SLD1 and SLD2 are introduced. Only one of the shield electrodes SLD1 and SLD2 may be introduced.
  • the primary coils 231p and 232p and the secondary coils 231s and 232s may be referred to as primary windings 231p and 232p and secondary windings 231s and 232s, respectively. .
  • the transformer chip 230 has six external terminals T21 to T26.
  • the external terminal T21 is connected to the first end of the primary winding 231p.
  • the external terminal T22 is connected to the second end of the primary winding 231p and the second end of the primary winding 232p.
  • the external terminal T23 is connected to the second end of the primary winding 232p.
  • the external terminal T24 is connected to the first end of the secondary winding 231s.
  • the external terminal T25 is connected to the second end of the secondary winding 231s and the second end of the secondary winding 232s.
  • the external terminal T26 is connected to the second end of the secondary winding 232s.
  • inter-coil capacitances C1 and C1 are provided between the primary winding 231p and the secondary winding 231s and between the primary winding 232p and the secondary winding 232s, respectively.
  • C2 is attached.
  • Shield electrodes SLD1 and SLD2 interposed between the primary windings 231p and 232p and the secondary windings 231s and 232s are introduced into the transformer chip 230 of the new structure (on the right side of the figure). ing.
  • FIG. 23 is a diagram showing a vertical structure of a transformer chip 230 having shield electrodes SLD1 and SLD2.
  • the transformer chip 230 with a new structure is formed by stacking metal layers (wiring layers) 1MT, 2MT and 3MT in order from the bottom.
  • the metal layer 1MT and the metal layer 2MT are electrically connected via a single via 1VIA.
  • the metal layer 2MT and the metal layer 3MT are electrically connected through three stages of vias 2VIA.
  • the outermost surface of the transformer chip 230 is covered with a passivation layer PSV except for the exposed portions of the pads.
  • the primary winding 231p is formed in the intermediate metal layer 2MT.
  • the secondary winding 231s is formed on the uppermost metal layer 3MT so as to be magnetically coupled with the primary winding 231p.
  • the shield electrodes SLD1 and SLD2 are both interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s). and the metal layer 3MT.
  • the shield electrodes SLD1 and SLD2 are formed to extend in the left-to-right direction of the drawing, directly above the primary winding 231p and directly below the secondary winding 231s, and At their right ends, they are connected to ground ends ⁇ and ⁇ .
  • the ground terminal ⁇ is electrically connected to the pad TMT (corresponding to the external terminal T25) via the via TVIA.
  • the ground terminal ⁇ is connected to an external terminal T22 (not shown) through metal layers 1MT to 3MT and vias 1VIA and 2VIA.
  • the noise canceller 225 (FIG. 8) is introduced, if a noise pulse is superimposed on the regular pulse at the same timing, the regular pulse may be erroneously masked, resulting in a delay of one pulse (FIG. 9). (see time t26 in ). Moreover, since the noise canceller 225 includes the delay units DLY1 to DLY4, there is also the problem that the band is limited.
  • the current flowing through the inter-coil capacitances C1 and C2 when common mode noise is superimposed flows through the shield electrodes SLD1 and SLD2 to the ground terminal ⁇ and ⁇ . That is, since the common mode noise itself transmitted via the inter-coil capacitances C1 and C2 can be effectively reduced, malfunction can be suppressed without depending on the noise canceller 225 .
  • FIG. 24 is a diagram showing the noise reduction effect due to the introduction of the shield electrodes SLD1 and SLD2. Similar to FIG. OUT is depicted.
  • ⁇ Shield electrode layout and signal transmission capability> 25 to 27 are diagrams showing the relationship between the layout of the shield electrodes SLD (corresponding to the shield electrodes SLD1 and SLD2 described above) and the signal transmission capability.
  • a solid line arrow indicates a current
  • a broken line arrow indicates a magnetic field.
  • the shield electrode SLD is formed in a solid pattern so as to be interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s). ing. If such a layout is adopted, it is considered that a large number of eddy currents are generated on the shield electrode SLD, so that the demagnetizing field greatly hinders transmission.
  • the shield electrode SLD is concentric or circular in plan view so as to be interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s).
  • a plurality of concentric rings are formed. If such a layout is employed, it is possible to suppress the generation of eddy currents as compared with the above-described one-sided solid pattern (FIG. 25), so it is considered that the transmission inhibition due to the demagnetizing field is reduced.
  • an eddy current is generated in the loop of the shield electrode SLD, it is difficult to completely eliminate the transmission inhibition due to the demagnetizing field.
  • the shield electrode SLD is interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s) as in FIG. 2, a plurality of concentric rings or concentric rings (comb teeth in cross section) are formed in a plan view, and are formed in an open ring form in a plan view. That is, since the shield electrode SLD does not have a loop that serves as an eddy current path, it is possible to minimize transmission inhibition due to the demagnetizing field.
  • FIG. 28 is a diagram showing a first planar layout example of the shield electrode SLD.
  • a plurality of shield electrodes SLD in this figure are formed concentrically or concentrically and openly in a plan view.
  • This planar layout corresponds to FIG. 27 (C-shaped pattern) previously described.
  • FIG. 29 is a diagram showing a second planar layout example of the shield electrode SLD.
  • the shield electrode SLD in this figure is similar to that in FIG. The fact that it can be changed is clearly indicated by a white arrow.
  • FIG. 30 is a diagram showing a third planar layout example of the shield electrode SLD.
  • a plurality of shield electrodes SLD in this figure are formed concentrically or concentrically in a plan view.
  • This planar layout corresponds to FIG. 26 (O-type pattern) previously described.
  • the shield electrode SLD may have the same shape as the primary and secondary windings.
  • FIG. 31 is a diagram showing a fourth planar layout example of the shield electrode SLD.
  • the shield electrode SLD in this figure has a planar layout similar to that of FIG. 28 (C-shaped pattern), but is formed as a series of single-stroke patterns. Even if such a pattern is employed, it is possible to suppress the generation of eddy currents (and, by extension, the inhibition of transmission due to the demagnetizing field).
  • FIG. 32 is a diagram showing a first cross-sectional structure example of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2.
  • the shield electrodes SLD1 and SLD2 in this figure are formed to extend outside the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively, and extend to the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively. It is formed to the inner side of the inner circumference.
  • the shield electrodes SLD1 and SLD2 are designed to have the same line width/line spacing ratio as the primary winding 231p and the secondary winding 231s, respectively.
  • FIG. 33 is a diagram showing a second cross-sectional structural example of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2.
  • the shield electrodes SLD1 and SLD2 in this figure are formed up to the same positions as the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively, and also extend to the outermost circumferences of the primary winding 231p and the secondary winding 231s. It is formed up to the same position as the inner circumference.
  • FIG. 34 is a diagram showing a third cross-sectional structure example of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2.
  • the shield electrodes SLD1 and SLD2 in this figure are formed to extend outside the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively, and extend to the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively. It is formed up to the same position as the inner circumference.
  • FIG. 35 is a diagram showing a fourth cross-sectional structure example of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2.
  • the shield electrodes SLD1 and SLD2 in this figure are formed only to the inner side of the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively, and the primary winding 231p and the secondary winding 231s, respectively. is formed only up to the outer side of the innermost circumference.
  • FIG. 36 is a diagram showing a fifth cross-sectional structural example of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2.
  • the shield electrodes SLD1 and SLD2 in this figure are formed outside the outermost circumferences of the primary winding 231p and the secondary winding 231s, respectively, as in the first cross-sectional structure example (FIG. 33). It is formed inside the innermost circumferences of the winding 231p and the secondary winding 231s.
  • the shield electrodes SLD1 and SLD2 are designed to have a smaller line width/line spacing ratio than the primary winding 231p and the secondary winding 231s, respectively.
  • the sizes and line width/line spacing ratios of the primary winding 231p and the secondary winding 231s and the shield electrodes SLD1 and SLD2 can be arbitrarily adjusted.
  • the upper structure secondary winding 231s and shield electrode SLD2
  • the lower structure may be shifted from the upper structure to the upper structure. It is also optional to gradually increase the size toward .
  • FIG. 37 is a diagram showing the relationship between the presence/absence and shape of the shield electrode and the inter-coil capacitance. As shown in this figure, by introducing the shield electrode, it is possible to reduce the inter-coil capacitance of the transformer chip.
  • the shield electrode is desirably designed to have the same line width/line spacing ratio (same diameter) as the primary and secondary windings.
  • FIG. 38 is a diagram showing a planar layout of pads and coils formed on a transformer chip.
  • pads 401 and 402 and a coil 403 formed on a transformer chip 400 are depicted.
  • the pad 401 corresponds to, for example, the external terminal T25 (GND pad of the secondary circuit system 200s), and the pad 402 corresponds to, for example, the external terminal T24 or T26 (of the secondary circuit system 200s). signal pad).
  • the coil 403 corresponds to, for example, the secondary winding 231s or 232s.
  • FIG. 39 is a diagram showing a first planar layout of the shield electrode 404 that overlaps the coil 403 of FIG. Also, FIG. 40 is a diagram in which FIG. 38 and FIG. 39 are superimposed.
  • the shield electrode 404 corresponds to the shield electrode SLD1 or SLD2 in FIG. 23 or the shield electrode SLD in FIG. 27 or 28, for example.
  • the shield electrode 404 is formed in a wiring layer different from that of the coil 403 (for example, a wiring layer one layer below the wiring layer in which the coil 403 is formed).
  • the shield electrode 404 is laid in such a manner as to trace the coil 403 so as to overlap the coil 403 partially or entirely (mostly 80% or more in this figure) in a plan view of the transformer chip 400 .
  • Such a layout pattern makes it possible to enhance the effect of reducing common mode noise.
  • the shield electrode 404 is basically laid in the same shape (spiral shape) as the coil 403, but has an open end 404x so as to inhibit the generation of eddy current. have. That is, in the shield electrode 404, the series of spiral shapes is interrupted at the portion where the open end 404x is provided. Therefore, since the shield electrode 404 does not have a loop that serves as a path for the eddy current, it is possible to minimize transmission inhibition due to the demagnetizing field. This point is as described in FIG. 27 above.
  • Each part of the shield electrode 404 is electrically connected to the pad 401 through the connecting part 404y. Therefore, the effect of reducing common mode noise is not hindered. Although this point is also self-evident from the previous FIG. 28, it will be specified again here.
  • FIG. 41 is a diagram showing a second planar layout of the shield electrode 405 overlapping the coil 403 of FIG.
  • FIG. 42 is a diagram in which FIG. 38 and FIG. 41 are superimposed.
  • the shield electrode 405 is laid in such a manner as to trace the coil 403 so as to overlap the coil 403 partially or entirely (almost 100% in this figure) in a plan view of the transformer chip 400, like the shield electrode 404 described above.
  • the shield electrode 405 has an open end 405x at its terminal end, not in the middle of the series of spiral shapes. According to such a layout pattern, it is possible to increase the overlapping portion of the coil 403 and the shield electrode 405, so that it is possible to further enhance the effect of reducing common mode noise.
  • a plurality of concentric rings may be formed, or a spiral shape may be formed when the transformer chip is viewed from above.
  • the relationship between the secondary winding and the shield electrode is mainly given as an example, but the relationship between the primary winding and the shield electrode is the same as above.
  • FIG. 43 is a diagram showing the existence of a substrate-to-pad capacitance in the transformer chip 230.
  • a pad PAD includes a metal electrode P1, an internal wiring P2, and a plurality of vias P3.
  • the metal electrode P1 corresponds to the high-potential terminal 12 (12A) described above, and at least a portion thereof is exposed outside from the uppermost insulating layer as a wire bonding region.
  • the internal wiring P2 corresponds to the high-potential connection wiring 81 described above, and is formed in an island shape facing the metal electrode P1 in the wiring layer common to the second winding 231s.
  • a plurality of vias P3 correspond to the previously described pad plug electrodes 82, and electrically connect between the metal electrodes P1 and the internal wirings P2.
  • the shield electrodes SLD1 and SLD2 described above are interposed between the primary winding 231p and the secondary winding 231s. Therefore, although the common mode noise through the aforementioned inter-coil capacitance C can be reduced, it must be said that the shielding effect of the substrate-to-pad capacitance CP is poor.
  • FIG. 44 is a diagram showing how the substrate-to-pad capacitance CP is unshielded.
  • a substrate-to-pad capacitance CP1 associated with the transformer 231 and a substrate-to-pad capacitance CP2 associated with the transformer 232 are depicted.
  • the shield electrodes SLD1 and SLD2 are introduced, the substrate-to-pad capacitance CP that accompanies between the substrate SUB and the pad PAD cannot be adequately shielded. Therefore, it can be said that there is room for further improvement in terms of the common mode noise reduction effect.
  • FIG. 45 is a diagram showing the first planar layout of the shield electrode SLD in the region overlapping with the pad PAD.
  • a plurality of shield electrodes SLD may be formed concentrically or concentrically at positions overlapping the pads PAD in plan view.
  • the shield electrode SLD preferably has an open end SLDx so as to inhibit the generation of eddy currents. That is, the series of loops of the shield electrode SLD formed concentrically or concentrically is interrupted at the portion where the open end SLDx is provided. Therefore, since the shield electrode SLD does not have a loop that serves as a path for eddy currents, it is possible to minimize transmission inhibition due to the demagnetizing field. This point is as described in FIG. 27 above.
  • FIG. 46 is a diagram showing cross-sectional structures of the primary winding 231p, the secondary winding 231s, the pad PAD, and the shield electrodes SLD1 and SLD2. This figure is based on the previous FIG. 43 and is a vertical cross-sectional view clearly showing the shield electrodes SLD1 and SLD2 formed so as to be interposed between the substrate SUB and the pad PAD.
  • the SLD2, the secondary winding 231s, and the internal wiring P2 of the pad PAD are laminated in this order.
  • the aforementioned shield electrodes SLD1 and SLD2 formed so as to be interposed between the primary winding 231p and the secondary winding 231s are extended to the area immediately below the pad PAD.
  • a substrate-to-pad shield electrode may be introduced by forming a Also, the shield electrode between the coils and the shield electrode between the substrate and the pad may be formed separately.
  • FIG. 47 is a diagram showing how the substrate-to-pad capacitances CP1 and CP2 are shielded. As shown in FIG. 46, by providing the shield electrodes SLD1 and SLD2 between the substrate SUB and the pad PAD, not only the common mode noise passing through the inter-coil capacitance C but also the substrate-pad capacitance CP It is also possible to appropriately shield common mode noise that passes through.
  • FIG. 48 is a diagram showing the second plane layout of the shield electrode SLD in the region overlapping with the pad PAD.
  • the shield electrode SLD formed in the region immediately below the pad PAD may be formed in a spiral shape.
  • the end portion of the shield electrode SLD becomes the open end SLDx. Since eddy currents do not flow even with such a layout pattern, it is possible to minimize transmission hindrance due to the demagnetizing field.
  • the transformer chip disclosed in this specification includes, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding formed on the first wiring layer, and the a secondary winding formed on the second wiring layer so as to be magnetically coupled with the primary winding; and a shield electrode formed to be interposed between the primary winding and the secondary winding. (first configuration).
  • the shield electrode is connected to the first ground terminal of the primary winding and the second ground terminal of the secondary winding. and a second shield electrode (second configuration).
  • the shield electrodes are formed in a plurality of concentric circles or concentric rings in a plan view, or formed in a spiral shape in a plan view (the first shield electrode). 3).
  • the shield electrode may be configured to have an open annular shape in plan view (fourth configuration).
  • the shield electrode is designed to have the same line width/line spacing ratio as the primary winding or the secondary winding (fifth configuration). ).
  • the shield electrode is formed outside the outermost circumference of the primary winding or the secondary winding (sixth configuration). configuration).
  • the shield electrode is formed inside the innermost circumference of the primary winding or the secondary winding (seventh configuration). configuration).
  • the shield electrode is arranged such that the shield electrode partially or entirely overlaps the primary winding or the secondary winding in a plan view.
  • a configuration (eighth configuration) in which the secondary winding is laid in a traced manner may be employed.
  • the shield electrode may have a configuration (ninth configuration) having an open end configured to inhibit the generation of eddy current.
  • the transformer chip disclosed in this specification includes, for example, a first wiring layer, a second wiring layer different from the first wiring layer, and a first transformer formed on the first wiring layer.
  • the primary winding and the primary winding of the second transformer are formed on the second wiring layer so as to be magnetically coupled to the primary winding of the first transformer and the primary winding of the second transformer, respectively.
  • a configuration (tenth configuration) is provided in which shield electrodes are formed so as to be interposed between the primary winding and the secondary winding of the second transformer.
  • the transformer chip according to the tenth configuration has a first terminal to which a first end of the primary winding of the first transformer is connected, a second end of the primary winding of the first transformer and the first terminal. a second terminal to which the first end of the primary winding of two transformers is connected; a third terminal to which the second end of the primary winding of the second transformer is connected; and the secondary of the first transformer.
  • a configuration (eleventh configuration) having a terminal and a sixth terminal to which the second end of the secondary winding of the second transformer is connected may be employed.
  • the signal transmission device disclosed in this specification includes, for example, a controller chip, a driver chip, and the first to eleventh configurations, and provides insulation between the controller chip and the driver chip. and a transformer chip that transmits the pulse signal while transmitting the pulse signal (a twelfth configuration).
  • the transformer chip disclosed in this specification includes, for example, a first wiring layer, a second wiring layer different from the first wiring layer, and a primary winding formed on the first wiring layer. a secondary winding formed on the second wiring layer so as to be magnetically coupled with the primary winding; a pad to which a signal terminal of the secondary winding is connected; and a first ground terminal of the primary winding. and a shield electrode interposed between the substrate and the pad (a thirteenth configuration).
  • the shield electrodes are formed in a plurality of concentric circles or concentric rings at positions overlapping the pads in plan view, or formed in a spiral shape ( 14th configuration).
  • the shield electrode may have a configuration (fifteenth configuration) having an open end configured to inhibit the generation of an eddy current.
  • the secondary winding may be laid in a spiral shape surrounding the pad (sixteenth configuration).
  • the shield electrode is also formed to be interposed between the primary winding and the secondary winding (a seventeenth configuration). ).
  • the shield electrode is laid so as to trace the primary winding or the secondary winding at a position overlapping the primary winding or the secondary winding in a plan view. (18th configuration) may be used.
  • the pad may include an electrode at least partially exposed, an island-like internal wiring facing the electrode, and an internal wiring between the electrode and the internal wiring. and a plurality of vias for electrically connecting between them (nineteenth configuration).
  • the shield electrode includes a first shield electrode connected to the first ground terminal of the primary winding and a second ground terminal of the secondary winding. and a second shield electrode connected to (a twentieth configuration).
  • the primary winding, the secondary winding, the first shield electrode, and the second shield electrode are, when viewed from the substrate side, the primary winding, the first The shield electrode, the second shield electrode and the secondary winding may be stacked in this order (21st configuration).
  • the signal transmission device disclosed in this specification includes, for example, a controller chip, a driver chip, and the thirteenth to twenty-first configurations, and provides insulation between the controller chip and the driver chip. and a transformer chip that transmits the pulse signal while transmitting the pulse signal (22nd configuration).
  • the invention disclosed in this specification can be applied to general applications that require signal transmission while isolating input and output (for example, isolated gate drivers, motor drivers, isolators, or other ICs that handle high voltage). etc.).

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WO2025009421A1 (ja) * 2023-07-03 2025-01-09 ローム株式会社 トランスチップおよび信号伝達装置
JP2025017247A (ja) * 2023-07-24 2025-02-05 合肥晶合集成電路股▲ふん▼有限公司 半導体装置及び半導体装置の設計支援装置

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WO2021215237A1 (ja) * 2020-04-24 2021-10-28 ローム株式会社 パルス受信回路、信号伝達装置

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JP2000150802A (ja) * 1998-11-18 2000-05-30 Nec Corp アナログ信号パッドのシールド法、および半導体集積回路
JP2014053365A (ja) * 2012-09-05 2014-03-20 Renesas Electronics Corp 半導体装置
JP2017220607A (ja) * 2016-06-09 2017-12-14 ルネサスエレクトロニクス株式会社 半導体装置、及び通信回路
WO2019074130A1 (ja) * 2017-10-13 2019-04-18 ローム株式会社 電子部品および電子部品モジュール

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JP2000150802A (ja) * 1998-11-18 2000-05-30 Nec Corp アナログ信号パッドのシールド法、および半導体集積回路
JP2014053365A (ja) * 2012-09-05 2014-03-20 Renesas Electronics Corp 半導体装置
JP2017220607A (ja) * 2016-06-09 2017-12-14 ルネサスエレクトロニクス株式会社 半導体装置、及び通信回路
WO2019074130A1 (ja) * 2017-10-13 2019-04-18 ローム株式会社 電子部品および電子部品モジュール

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WO2025009421A1 (ja) * 2023-07-03 2025-01-09 ローム株式会社 トランスチップおよび信号伝達装置
JP2025017247A (ja) * 2023-07-24 2025-02-05 合肥晶合集成電路股▲ふん▼有限公司 半導体装置及び半導体装置の設計支援装置

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