WO2023071508A1 - 线程间中断信号发送 - Google Patents

线程间中断信号发送 Download PDF

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Publication number
WO2023071508A1
WO2023071508A1 PCT/CN2022/116160 CN2022116160W WO2023071508A1 WO 2023071508 A1 WO2023071508 A1 WO 2023071508A1 CN 2022116160 W CN2022116160 W CN 2022116160W WO 2023071508 A1 WO2023071508 A1 WO 2023071508A1
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WIPO (PCT)
Prior art keywords
thread
interrupt signal
interrupt
processor
pci device
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PCT/CN2022/116160
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English (en)
French (fr)
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谈鉴锋
别体伟
周介龙
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支付宝(杭州)信息技术有限公司
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Publication of WO2023071508A1 publication Critical patent/WO2023071508A1/zh
Priority to US18/353,020 priority Critical patent/US11960924B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication

Definitions

  • the embodiments of this specification generally relate to the field of computer technology, and in particular, to a method and device for sending interrupt signals between threads.
  • the interrupt of the multi-core multi-thread processor can be uniformly controlled by the Programmable Interrupt Controller (PIC).
  • PIC allows one hardware thread to interrupt other hardware threads, which is called Inter-Processor Interrupts (IPI).
  • IPI Inter-Processor Interrupts
  • the PIC has a 32-bit inter-core interrupt register IPIBase, which stores the number, interrupt vector, and interrupt type (whether to interrupt multiple hardware threads) of the purpose thread and so on.
  • the inter-core interrupt can be generated by writing the required value to the inter-core interrupt register IPIBase. If hardware thread A wants to send an inter-core interrupt to hardware thread B, it only needs to write the thread ID, interrupt vector, interrupt type and other values of hardware thread B to the inter-core interrupt register IPIBase.
  • the PIC will notify the core where the hardware thread B is located to suspend its current execution sequence, and jump to the entry of the interrupt service routine ISR according to the interrupt vector.
  • the CPU can use IPI to send interrupt signals between hardware threads, but in some application scenarios, IPI cannot be used to send interrupt signals between hardware threads.
  • the embodiments of this specification provide a method and device for sending interrupt signals between threads.
  • the inter-thread interrupt signal sending method and device By using the inter-thread interrupt signal sending method and device, the inter-thread interrupt signal sending in all running states can be realized.
  • a method for sending an interrupt signal between a first thread and a second thread the method is executed by a PCI device, and the method includes: receiving the first thread via the PCI bus The notification message sent by the processor by the MMIO write operation, the MMIO write operation is realized based on the virtual space address of the first thread mapped by the memory address of the MMIO memory of the PCI device; in response to receiving the notification message , generating an interrupt signal intended for the second thread; and sending the interrupt signal to the processor where the second thread is located according to the interrupt signal sending mode configured by the interrupt configuration information of the PCI device, wherein the interrupt configuration information According to the state information configuration of the second thread, the state information of the second thread includes the running state of the second thread and whether the second thread is running.
  • the configuration of the interrupt configuration information according to the state information of the second thread may include: if the second thread is in the Host Kernel, configuring the interrupt signal sending mode as Send the interrupt signal to the interrupt handle configured for the second thread in the processor where the second thread is located; if the second thread is in the Guest Kernel and the second thread is running, it will interrupt Configured as Posted Interrupt, and the interrupt signal sending mode is configured to send the interrupt signal to the processor where the second thread is located; if the second thread is in the Guest Kernel and the second thread is not running, then The interrupt signal sending mode is configured to send the interrupt signal to the physical processor corresponding to the virtual processor where the second thread is located in the Host Kernel, and the physical processor wakes up the virtual processor where the second thread is located If the second thread is in the user state, the interrupt signal sending mode is configured to send the interrupt signal to the processor where the second thread is located.
  • configuring the interrupt signal sending method to send the interrupt signal to the processor where the second thread resides may include: If the second thread is in the user state, the interrupt signal sending method is configured to send the interrupt signal to the processor where the second thread is located by using a semaphore sending method or an eventfd sending method.
  • the notification message includes a mov instruction
  • the source operand of the mov instruction stores the value required by the MMIO memory of the PCI device
  • the destination address of the mov instruction is the The virtual space address of the first thread to which the MMIO memory is mapped.
  • the required value of the MMIO memory includes one of multiple values, and each value corresponds to a type of interrupt signal.
  • generating an interrupt signal may include: in response to receiving the mov instruction, generating an interrupt signal corresponding to the required value of the MMIO memory in the mov instruction.
  • the MMIO memory includes a doorbell memory.
  • the PCI device has a current limiting policy
  • the method may further include: after generating the interrupt signal, performing a current limiting judgment according to the current limiting policy.
  • the interrupt signal is not sent
  • the interrupt signal transmission mode configured according to the interrupt configuration information of the PCI device Send the interrupt signal to the processor where the second thread is located.
  • the PCI device has a distribution policy.
  • Sending the interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured by the device interrupt configuration information of the PCI device may include: according to the distribution strategy in the PCI device, according to the PCI device The interrupt signal sending manner configured by the interrupt configuration information sends the interrupt signal to the processor where the second thread resides.
  • the PCI device has an interrupt remapping table.
  • the method may further include: performing interrupt remapping on the interrupt signal based on the interrupt remapping table.
  • sending the interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device may include: an interrupt signal configured in accordance with the interrupt configuration information of the PCI device In a sending mode, the interrupt signal after the interrupt remapping is sent to the processor where the second thread is located.
  • an apparatus for sending an interrupt signal between a first thread and a second thread the apparatus is applied to PCI equipment execution, and the apparatus includes: a notification receiving unit, Receive the notification message sent by the processor where the first thread is located through the MMIO write operation via the PCI bus, and the MMIO write operation is based on the virtual space address of the first thread mapped by the memory address of the MMIO memory of the PCI device; interrupt signal A generation unit, in response to receiving the notification message, generates an interrupt signal aimed at the second thread; an interrupt configuration information configuration unit configures the interrupt configuration information of the PCI device according to the state information of the second thread, and the second thread
  • the status information includes the running state of the second thread and whether the second thread is running; and the interrupt signal sending unit transmits the interrupt signal to the first thread according to the interrupt signal sending mode configured by the interrupt configuration information of the PCI device.
  • the processor where the second thread is located sends the interrupt signal.
  • the interrupt configuration information configuration unit configures the interrupt signal sending method to send the interrupt signal to the second thread.
  • the interrupt handle configured for the second thread in the processor where the thread is located; if the second thread is in the Guest Kernel and the second thread is running, the interrupt configuration information configuration unit is configured to interrupt as Posted Interrupt , and the interrupt signal sending mode is configured to send the interrupt signal to the processor where the second thread is located; if the second thread is in the Guest Kernel and the second thread is not running, the interrupt configuration
  • the information configuration unit configures the interrupt signal sending mode as sending the interrupt signal to the physical processor corresponding to the virtual processor where the second thread is located in the Host Kernel, and the physical processor wakes up the second thread
  • the virtual processor where the second thread resides; if the second thread is in user mode, the interrupt configuration information configuration unit configures the interrupt signal sending mode to send the interrupt signal to the processor where the second thread resides.
  • the interrupt configuration information configuration unit configures the interrupt signal sending method to send the interrupt signal through the semaphore sending method or eventfd sending method.
  • the interrupt signal is sent to the processor where the second thread is located.
  • the notification message includes a mov instruction
  • the source operand of the mov instruction stores the value required by the MMIO memory of the PCI device
  • the destination address of the mov instruction is the The virtual space address of the first thread to which the MMIO memory is mapped.
  • the required value of the MMIO memory includes one of multiple values, and each value corresponds to a type of interrupt signal.
  • the interrupt signal generating unit in response to receiving the mov instruction, the interrupt signal generating unit generates an interrupt signal corresponding to the required value according to the required value of the MMIO memory in the mov instruction.
  • the PCI device has a current limiting policy.
  • the device may further include: a current limiting judging unit, after generating the interruption signal, performing a current limiting judgment according to the current limiting strategy.
  • the interrupt signal sending unit does not send the interrupt signal;
  • the interrupt signal sending unit follows the The interrupt signal sending mode configured by the interrupt configuration information of the PCI device sends the interrupt signal to the processor where the second thread resides.
  • the PCI device has a distribution policy.
  • the interrupt signal sending unit sends the interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device according to the distribution strategy.
  • the PCI device has an interrupt remapping table.
  • the device may further include: an interrupt remapping unit, configured to perform interrupt remapping on the interrupt signal based on the interrupt remapping table.
  • the interrupt signal sending unit sends the interrupt remapped interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device.
  • an apparatus for sending an interrupt signal between a first thread and a second thread includes: at least one processor coupled to the at least one processor memory, and a computer program stored in said memory, said at least one processor executing said computer program to implement the method for sending an interrupt signal between a first thread and a second thread as described above.
  • a computer-readable storage medium storing a computer program, the computer program being executed by a processor to implement Methods for sending interrupt signals between.
  • a computer program product comprising a computer program executed by a processor to implement the above-mentioned method for sending an interrupt between a first thread and a second thread. Signal method.
  • Fig. 1 shows an example block diagram of the system architecture of the inter-core notification system according to the embodiment of the specification.
  • Fig. 2 shows a schematic diagram of deployment of an interrupt signal sender Sender and an interrupt signal receiver receiver according to an embodiment of the present specification.
  • Fig. 3 shows an exemplary schematic diagram of an initialization process of an interrupt signal sender Sender according to an embodiment of the present specification.
  • Fig. 4 shows an example flow chart of a configuration process of interrupt configuration information according to an embodiment of the specification.
  • Fig. 5 shows a flowchart of a method for sending an interrupt signal between a first thread and a second thread according to an embodiment of the specification.
  • Fig. 6 shows a block diagram of an apparatus for sending an interrupt signal between a first thread and a second thread according to an embodiment of the present specification.
  • FIG. 7 shows a schematic diagram of a computer-based interrupt signal sending device according to an embodiment of the present specification.
  • the term “comprising” and its variants represent open terms meaning “including but not limited to”.
  • the term “based on” means “based at least in part on”.
  • the terms “one embodiment” and “an embodiment” mean “at least one embodiment.”
  • the term “another embodiment” means “at least one other embodiment.”
  • the terms “first”, “second”, etc. may refer to different or the same object. The following may include other definitions, either express or implied. Unless the context clearly indicates otherwise, the definition of a term is consistent throughout the specification.
  • the CPU can use IPI to send interrupt signals between hardware threads, but in some application scenarios, due to permission reasons, the IPI mechanism cannot be used to realize the interrupt signal notification between the CPUs where the threads are located. Examples of the above application scenarios may include vCPU synchronous operation, Para-virtualized (PV) driver and two-level scheduler.
  • V Para-virtualized
  • vCPU synchronous operation In the application scenario of vCPU synchronous operation, the thread Sender as the sender of the interrupt signal is in the Guest Kernel, and the thread Receiver as the receiver of the interrupt signal is in the Guest Kernel.
  • many operations in the Guest Kernel require vCPU synchronous operations, such as: TLB shootdown, RCU, CPU frequency scaling, and Schedule.
  • PV driver In the application scenario of PV driver, the thread Sender as the sender of the interrupt signal is in the Guest Kernel, and the thread Receiver as the receiver of the interrupt signal is in the Host Kernel.
  • PV driver is divided into front-end driver and back-end driver. After the front-end driver completes the request, it needs to activate or wake up (kick) the back-end driver to work.
  • the thread Sender as the sender of the interrupt signal is in the Guest Kernel or Host Kernel
  • the thread Receiver as the receiver of the interrupt signal is in the Host Kernel.
  • the L1 scheduler such as Linux CFS
  • the L2 scheduler is used to schedule the Guest Kernel or HR3 tasks in .
  • the Work-Stealing or Work-Sharing model when the task is busy, it needs to wake up a new vCPU or thread to work.
  • Fig. 1 shows an example block diagram of the system architecture of an inter-core notification system 1 according to an embodiment of the present specification.
  • the inter-core notification system 1 includes an interrupt signal sender Sender 10 , a PCI device 20 and an interrupt signal receiver Receiver 30 .
  • Sender 10 can be an HR3 thread running in user mode, an HR0 thread running by a physical processor (for example, pCPU0) in the Host Kernel, or a Guest thread running by a virtual processor (for example, vCPU0) in the Guest Kernel.
  • Receiver 30 can be the HR3 thread running in the user mode, the HR0 thread running by the physical processor (for example, pCPU1) in the Host Kernel, or the Guest thread running by the virtual processor (for example, vCPU1) in the Guest Kernel.
  • Fig. 2 shows a schematic diagram of deployment of an interrupt signal sender Sender and an interrupt signal receiver receiver according to an embodiment of the present specification.
  • Sender 10 and Receiver 30 correspond to the first thread and the second thread respectively.
  • the PCI device 20 can be implemented, for example, by adding a customized notification distribution function and/or a notification restrictor function to a general PCI device.
  • general-purpose PCI devices may include, but are not limited to, NIC devices, APIC devices, and Intel DLB (Dynamic Load Balancer) devices.
  • NIC devices may include, but are not limited to, generic network card devices such as ixgbe and i40e or smart network card devices.
  • Sender 10 and Receiver 30 need to be initialized.
  • the memory address of the PCI device 20 is mapped to the virtual space address of the Sender10.
  • Fig. 3 shows an exemplary schematic diagram of an initialization process of an interrupt signal sender Sender according to an embodiment of the present specification.
  • the thread accesses the PCI device 20 usually adopts MMIO write operation.
  • the PCI device 20 usually adopts MMIO write operation.
  • additional memory mapping needs to be introduced, that is, the memory address of the MMIO memory (such as Doorbell) of the PCI device 20 is mapped to the thread virtual address space in the VM.
  • the following takes mapping a Doorbell during device initialization as an example to illustrate the above process.
  • the front-end thread calls the Verbs interface "open_device" to initialize the device context.
  • the above initialization call is divided into three parts as shown in Figure 3, steps 2a, 2b and 2c.
  • the virtualized backend applies for a Doorbell on the RNIC, and the backend driver obtains the HPA (HOST physical address) doorbell_hpa of the applied Doorbell.
  • the front-end driver identifies the MMIO memory where the Doorbell of the PCI device is located, and then calls mmap() to map the memory address of the MMIO memory to the virtual address space of the thread.
  • the requested memory can be called vDoorbell, which corresponds to the virtual address space doorbell_hva in QEMU.
  • step 2c the backend driver creates a mapping between doorbell_hva and doorbell_hpa by modifying the page table of QEMU, so that the front-end thread accessing vDoorBell will be directed to the real Doorbell on the PCI device. In this way, threads in the VM can directly access the Doorbell on the PCI device through MMIO write operations.
  • the interrupt configuration information of the PCI device needs to be configured according to the state information of the Receiver 30.
  • the state information of the thread may include the running state of the thread and whether the thread is running.
  • the interrupt configuration information may include an interrupt signal sending method and a target CPU.
  • FIG. 4 shows an example flowchart of an interrupt configuration information configuration process 400 according to an embodiment of the specification.
  • the interrupt configuration information of PCI device 20 is configured as interrupt configuration information 1, that is, the interrupt signal transmission mode in the interrupt configuration information is configured as sending the interrupt signal to where Receiver 30 is located.
  • the interrupt handler Interrupt Handler configured for Receiver 30 in the processor. For example, when Receiver 30 is in the Host Kernel, a suitable Interrupt Handler can be configured for Receiver 30 in the Host Kernel. Then, the interrupt signal is sent to the configured Interrupt Handler.
  • Interrupt Handler performs corresponding processing in response to the received interrupt signal.
  • processor on which a thread resides refers to the processor on which the thread is running. Examples of processors may include, but are not limited to, CPUs, MPUs, GPUs, and the like.
  • the interrupt configuration information of PCI device 20 is configured as interrupt configuration information 2, that is, the interrupt signal in the interrupt configuration information is sent
  • the mode is configured to send the interrupt signal to the processor where the Receiver 30 is located.
  • the interrupt signal sending mode may be configured to send the interrupt signal to the processor where the Receiver 30 is located through a semaphore (semaphore) sending mechanism or eventfd.
  • the semaphore sending mechanism uses the PV operation to process the semaphore.
  • the data structure of the semaphore is a value and a pointer, and the pointer points to the next process waiting for the semaphore.
  • the value of the semaphore is related to the usage of the corresponding resource. When the value of the semaphore is greater than 0, it indicates the number of currently available resources. When the value of the semaphore is less than 0, its absolute value represents the number of processes waiting to use the resource.
  • the value of a semaphore is changed by a PV operation. Executing a P operation means requesting the allocation of a unit resource, and the value of the semaphore is decremented by 1. Executing a V operation means releasing a unit resource, and the value of the semaphore is incremented by 1.
  • PV operations are composed of P operation primitives and V operation primitives.
  • P operation (wait) applies for a unit resource, and the process enters.
  • the V operation (signal) releases a unit resource, and the process comes out.
  • the interrupt configuration information of PCI device 20 is configured as interrupt configuration information 3, that is, the interrupt is configured as Posted Interrupt, and the interrupt signal transmission mode in the interrupt configuration information is configured as Send the interrupt signal to the processor where Receiver 30 resides.
  • Posted Interrupt allows APIC interrupts to be injected directly into the guest without VM-Exit.
  • the interrupt configuration information of PCI device 20 is configured as interrupt configuration information 4, that is, the interrupt signal transmission mode in the interrupt configuration information is configured to send the interrupt signal to the host in the Host Kernel
  • interrupt configuration information 4 the interrupt signal transmission mode in the interrupt configuration information is configured to send the interrupt signal to the host in the Host Kernel
  • the physical processor can bind and wake up the virtual processor where Receiver 30 resides through irqfd. If necessary, an interrupt signal can be injected into the Guest Kernel, and the IRQ response in the Guest Kernel can be adjusted as needed.
  • Fig. 5 shows a flowchart of a method 500 for sending an interrupt signal between a first thread and a second thread according to an embodiment of the present specification.
  • Method 500 is performed by PCI device 20 .
  • the PCI device 20 receives, via the PCI bus, a notification message sent by the processor where the first thread resides through an MMIO write operation.
  • the MMIO write operation is based on the virtual space address of the Sender 10 mapped to the memory address of the MMIO memory of the PCI device.
  • the MMIO memory may include Doorbell memory, for example.
  • the notification message may be a mov instruction.
  • the source operand of the mov instruction stores the required value of the MMIO memory of the PCI device 20, and the destination address of the mov instruction is the virtual space address of the Sender 10 to which the MMIO memory is mapped.
  • the mov instruction can be mov reg, mem, wherein the reg register stores the value required by the Doorbell memory, and mem represents the virtual space address of the Sender 10 to which the Doorbell memory is mapped.
  • PCI device 20 generates an interrupt signal to Receiver 30 in response to receiving the notification message.
  • the interrupt signal aimed at the Receiver 30 means that the generated interrupt signal is intended to go to the processor where the Receiver 30 is located.
  • the MMIO memory required value stored by the source operand may include a fixed value.
  • PCI device 20 after receiving the notification message, PCI device 20 generates a fixed type of interrupt signal.
  • the required value of the MMIO memory stored in the source operand may include one of multiple values, and each value corresponds to a type of interrupt signal.
  • an interrupt signal corresponding to the required value is generated.
  • an interrupt signal is sent to the processor where the Receiver 30 is located according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device.
  • the processor where the Receiver 30 is located executes corresponding processing in response to the received interrupt signal.
  • PCI device 20 may have a current limiting policy.
  • An example of the current limiting strategy may include, but not limited to: the maximum number of times the PCI device 20 sends an interrupt signal within a specified period. For example, PCI device 20 sends each interrupt at most M times in one second.
  • the main reason for introducing the current limiting strategy is to prevent untrusted users from using the interrupt sending mechanism to carry out DOS attacks.
  • a current limiting judgment may be performed according to the current limiting policy, so as to determine whether to perform current limiting processing on the interrupt signal. For example, when the number of times the interruption signal is sent within a predetermined time period reaches the maximum number of times of sending, it is determined that the interruption signal needs to be subjected to current limiting processing. When the number of transmissions of the interrupt signal within the predetermined time period does not reach the maximum number of transmissions, it is determined that the interrupt signal does not need to be subjected to current limiting processing. When the current limiting judgment result is that current limiting is required, the interruption signal is not sent. When the current limiting judgment result is that no current limiting is required, the interrupt signal is sent to the processor where the Receiver 30 is located according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device.
  • PCI device 20 may have a distribution policy.
  • the distribution strategy may include, but are not limited to: broadcast distribution mode, semaphore distribution mode, 1:1 directional distribution mode, and 1:N directional distribution mode.
  • the PCI device 20 in response to receiving the notification message, the PCI device 20 generates N interrupt signals aimed at the N Receivers 30 respectively.
  • the PCI device 20 sends the generated interrupt signal to the processor where the Receiver 30 is located according to the distribution strategy according to the interrupt signal transmission mode configured by the interrupt configuration information of the PCI device 20.
  • PCI device 20 may have an interrupt remapping table.
  • the PCI device 20 when generating the interrupt signal, the PCI device 20 performs interrupt remapping on the interrupt signal based on the interrupt remapping table, so as to obtain the interrupt remapped interrupt signal. Then, the PCI device 20 sends the interrupt remapped interrupt signal to the processor where the Receiver 30 is located according to the interrupt signal sending mode configured by the interrupt configuration information of the PCI device 20.
  • the current limiting policy and the distribution policy can be generated according to specific application scenarios, and delivered to the PCI device 20 .
  • Sender 10 can execute functions out of order (out-of-order) through the processor (CPU), and continue Perform other functions.
  • the operation of "initiating interrupt notification (kick)" by Sender 10 will not prevent Sender 10 from executing subsequent codes, so that the overhead of interrupt notification at Sender 10 is extremely small.
  • Sender 10 can run in any running state, such as HR3/HR0, GR3 shown in Figure 2 /GR0, as long as the Sender 10 can access the memory address of the PCI device 20.
  • the entire time delay is mainly related to the data transmission on the PCI bus, so that the interrupt signal sending time delay can be effectively reduced.
  • the interrupt signal sending solution according to the embodiment of this specification by setting the current limiting policy in the PCI device 20, DOS attacks can be effectively prevented.
  • FIG. 6 shows a block diagram of an apparatus (hereinafter referred to as “interrupt signal sending apparatus”) 600 for sending an interrupt signal between a first thread and a second thread according to an embodiment of the present specification.
  • the interrupt signal sending device 600 includes a notification receiving unit 610 , an interrupt signal generating unit 620 , an interrupt configuration information configuration unit 630 and an interrupt signal sending unit 640 .
  • the notification receiving unit 610 is configured to receive a notification message sent by the processor where the first thread resides through an MMIO write operation via the PCI bus, and the MMIO write operation is based on the virtual space address of the first thread mapped to the memory address of the MMIO memory of the PCI device accomplish.
  • the operation of the notification receiving unit 610 may refer to the operation described above with reference to 510 of FIG. 5 .
  • the interrupt signal generation unit 620 is configured to generate an interrupt signal intended for the second thread in response to receiving the notification message.
  • the operation of the interrupt signal generating unit 620 may refer to the operation described above with reference to 520 of FIG. 5 .
  • the interrupt configuration information configuration unit 630 is configured to configure the interrupt configuration information of the PCI device according to the state information of the second thread.
  • the state information of the second thread may include the running state of the second thread and whether the second thread is running.
  • the interrupt signal sending unit 640 is configured to send an interrupt signal to the processor where the second thread resides according to the interrupt signal sending manner configured by the interrupt configuration information of the PCI device.
  • the interrupt configuration information configuration unit 630 configures the interrupt signal sending mode as sending the interrupt signal to the second thread configured for the second thread in the processor where the second thread is located.
  • Interrupt Handler If the second thread is in the Guest Kernel and the second thread is running, the interrupt configuration information configuration unit 630 configures the interrupt as Posted Interrupt, and the interrupt signal sending mode is configured to send the interrupt signal to the processor where the second thread is located.
  • the interrupt configuration information configuration unit 630 configures the interrupt signal sending mode to send the interrupt signal to the physical processor corresponding to the virtual processor where the second thread is located in the Host Kernel , the physical processor wakes up the virtual processor where the second thread resides. If the second thread is in the user state, the interrupt configuration information configuration unit 630 configures the interrupt signal sending mode to send the interrupt signal to the processor where the second thread is located.
  • the interrupt configuration information configuration unit 630 configures the interrupt signal sending method to send the interrupt signal to the second thread through the semaphore sending mechanism or the eventfd sending mechanism where the processor is located.
  • the notification message may include a mov instruction, wherein the source operand of the mov instruction stores the value required by the MMIO memory of the PCI device, and the destination address of the mov instruction is the MMIO memory mapped to The virtual space address of the first thread.
  • the MMIO memory required value stored by the source operand may include a fixed value.
  • the interrupt signal generating unit 620 after receiving the notification message, the interrupt signal generating unit 620 generates a fixed type of interrupt signal.
  • the required value of the MMIO memory stored in the source operand may include one of multiple values, and each value corresponds to a type of interrupt signal.
  • the interrupt signal generating unit 620 after receiving the mov instruction, the interrupt signal generating unit 620 generates an interrupt signal corresponding to the required value according to the required value of the MMIO memory in the mov instruction.
  • a PCI device may have a current limiting policy.
  • the interrupt signal sending device 600 may also include a current limit judging unit (not shown). After generating the interrupt signal, the current limiting judging unit performs a current limiting judgment according to a current limiting policy. When the current limiting judging unit determines that the current limiting is performed, the interrupt signal sending unit 640 does not send an interrupt signal. When the current limiting judging unit determines that the current limiting is not performed, the interrupt signal sending unit 640 sends an interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device.
  • a PCI device has a distribution policy.
  • the interrupt signal sending unit 640 sends the interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured in the interrupt configuration information of the PCI device according to the distribution policy.
  • a PCI device may have an interrupt remapping table.
  • the interrupt signaling device may further include an interrupt remapping unit (not shown).
  • the interrupt remapping unit performs interrupt remapping on the interrupt signal based on the interrupt remapping table.
  • the interrupt signal sending unit 640 sends the interrupt remapped interrupt signal to the processor where the second thread resides according to the interrupt signal sending mode configured by the interrupt configuration information of the PCI device.
  • interrupt signal sending method and the interrupt signal sending device are described.
  • the above interrupt signal sending device can be implemented by hardware, or by software or a combination of hardware and software.
  • FIG. 7 shows a schematic diagram of a computer-based interrupt signal sending device 700 according to an embodiment of the present specification.
  • the interrupt signal sending device 700 may include at least one processor 710, a memory (for example, a non-volatile memory) 720, a memory 730, and a communication interface 740, and at least one processor 710, a memory 720, a memory 730 and the communication interface 740 are connected together via a bus 750 .
  • At least one processor 710 executes a computer program (ie, the above-mentioned elements implemented in software) stored or encoded in a memory.
  • a computer program ie, the above-mentioned elements implemented in software
  • a computer program is stored in the memory, and when executed, at least one processor 710: receives a notification message sent by the processor where the first thread is located through the MMIO write operation via the PCI bus, and the MMIO write operation is based on the PCI device The virtual space address of the first thread mapped by the memory address of the MMIO memory is realized; in response to receiving the notification message, an interrupt signal aimed at the second thread is generated; and according to the interrupt signal transmission mode configured by the interrupt configuration information of the PCI device to The processor where the second thread is located sends an interrupt signal, wherein the interrupt configuration information is configured according to the state information of the second thread, and the state information of the second thread includes the running state of the second thread and whether the second thread is running.
  • a program product such as a computer-readable medium (eg, a non-transitory computer-readable medium) is provided.
  • the computer-readable medium may have a computer program (that is, the above-mentioned elements implemented in the form of software), and when the computer program is executed by the processor, the processor executes the various functions described in conjunction with FIGS. 1-6 in various embodiments of this specification. operations and functions.
  • a system or device equipped with a readable storage medium can be provided, on which a software program code for realizing the functions of any one of the above embodiments is stored, and the computer or device of the system or device can The processor reads and executes the computer program stored in the readable storage medium.
  • the program code itself read from the readable medium can realize the function of any one of the above-mentioned embodiments, so the computer readable code and the readable storage medium storing the computer readable code constitute the present specification a part of.
  • Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tape, non- Volatile memory card and ROM.
  • the program code can be downloaded from a server computer or cloud via a communication network.
  • a computer program product includes a computer program, and when the computer program is executed by a processor, the processor executes the above described in conjunction with FIGS. 1-6 in various embodiments of this specification. Various operations and functions.
  • the execution order of each step is not fixed, and can be determined as required.
  • the device structures described in the above embodiments may be physical structures or logical structures, that is, some units may be realized by the same physical entity, or some units may be realized by multiple physical entities, or may be realized by multiple physical entities. Certain components in individual devices are implemented together.
  • the hardware units or modules may be implemented mechanically or electrically.
  • a hardware unit, module, or processor may include permanently dedicated circuitry or logic (such as a dedicated processor, FPGA, or ASIC) to perform the corresponding operations.
  • the hardware unit or processor may also include programmable logic or circuits (such as a general-purpose processor or other programmable processors), which can be temporarily set by software to complete corresponding operations.
  • the specific implementation mechanical way, or a dedicated permanent circuit, or a temporary circuit

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Abstract

本说明书的实施例提供线程间中断信号发送方法及装置。在该线程间中断信号发送方法中，第一线程所在处理器通过MMIO写操作来经由PCI总线向PCI设备发送通知消息。MMIO写操作基于PCI设备的MMIO内存的内存地址所映射的第一线程的虚拟空间地址实现。响应于接收到通知消息，PCI设备生成旨在第二线程的中断信号，并且按照PCI设备的中断配置信息所配置的中断信号发送方式向第二线程所在处理器发送中断信号。PCI设备的中断配置信息预先根据第二线程的状态信息配置，第二线程的状态信息包括第二线程所处运行态以及第二线程是否处于运行中。

Description

线程间中断信号发送 技术领域
本说明书实施例通常涉及计算机技术领域，尤其涉及线程间中断信号发送方法及装置。
背景技术
多核多线程处理器的中断可以由可编程中断控制器(Programmable Interrupt Controller，PIC)统一控制。PIC允许一个硬件线程中断其他硬件线程，这种方式被称为核间中断(Inter-Processor Interrupts，IPI)。PIC具有宽度为32位的核间中断寄存器IPIBase，该寄存器存储目的线程的编号、中断向量及中断类型(是否中断多个硬件线程)等内容。核间中断可以通过向核间中断寄存器IPIBase写入需要的值来产生。若硬件线程A想要发送核间中断给硬件线程B，它只需向核间中断寄存器IPIBase中写入硬件线程B的线程ID、中断向量、中断类型等值。PIC会通知硬件线程B所在的内核挂起它当前的执行序列，并根据中断向量跳转到中断服务例程ISR的入口。
在Host Kernel下，CPU可以利用IPI来实现硬件线程之间的中断信号发送，但是在一些应用场景下，不能利用IPI来实现硬件线程之间的中断信号发送。
发明内容
鉴于上述，本说明书实施例提供一种线程间中断信号发送方法及装置。利用该线程间中断信号发送方法及装置，可以实现所有运行态的线程间的中断信号发送。
根据本说明书实施例的一个方面，提供一种用于在第一线程和第二线程之间发送中断信号的方法，所述方法由PCI设备执行，所述方法包括：经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息，所述MMIO写操作基于所述PCI设备的MMIO内存的内存地址所映射的所述第一线程的虚拟空间地址实现；响应于接收到所述通知消息，生成旨在第二线程的中断信号；以及按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号，其中，所述中断配置信息根据所述第二线程的状态信息配置，所述第二线程的状态信息包括所述第二线程所处运行态以及所述第二线程是否处于运行中。
可选地，在上述方面的一个示例中，所述中断配置信息根据所述第二线程的状态信 息配置可以包括：如果所述第二线程处于Host Kernel，则将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器中的为所述第二线程配置的中断句柄；如果所述第二线程处于Guest Kernel且所述第二线程在运行中，则将中断配置为Posted Interrupt，并且将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器；如果所述第二线程处于Guest Kernel且所述第二线程未运行，则将所述中断信号发送方式配置为将所述中断信号发送给Host Kernel中的与所述第二线程所在虚拟处理器对应的物理处理器，所述物理处理器唤醒所述第二线程所在虚拟处理器；如果所述第二线程处于用户态，则将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器。
可选地，在上述方面的一个示例中，如果所述第二线程处于用户态，则将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器可以包括：如果所述第二线程处于用户态，则将所述中断信号发送方式配置为通过信号量发送方式或eventfd发送方式将所述中断信号发送给所述第二线程所在处理器。
可选地，在上述方面的一个示例中，所述通知消息包括mov指令，所述mov指令的源操作数存储所述PCI设备的MMIO内存所需值，以及所述mov指令的目的地址是所述MMIO内存所映射到的所述第一线程的虚拟空间地址。
可选地，在上述方面的一个示例中，所述MMIO内存所需值包括多个取值中的一个取值，每个取值对应一种类型的中断信号。相应地，响应于接收到所述通知消息，生成中断信号可以包括：响应于接收到所述mov指令，根据所述mov指令中的MMIO内存所需值，生成与所需值对应的中断信号。
可选地，在上述方面的一个示例中，所述MMIO内存包括doorbell内存。
可选地，在上述方面的一个示例中，所述PCI设备具有限流策略，所述方法还可以包括：在生成所述中断信号后，根据所述限流策略进行限流判断。在所述限流判断结果为进行限流时，不发送所述中断信号，在所述限流判断结果为不进行限流时，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
可选地，在上述方面的一个示例中，所述PCI设备具有分发策略。按照所述PCI设备的设备中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号可以包括：根据所述PCI设备中的分发策略，按照所述PCI设备的中断配置 信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
可选地，在上述方面的一个示例中，所述PCI设备具有中断重映射表。所述方法还可以包括：基于所述中断重映射表来对所述中断信号进行中断重映射。相应地，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号可以包括：按照所述PCI设备的中断配置信息所配置的中断信号发送方式，向所述第二线程所在处理器发送经过中断重映射后的中断信号。
根据本说明书的实施例的另一方面，提供一种用于在第一线程和第二线程之间发送中断信号的装置，所述装置应用于PCI设备执行，所述装置包括：通知接收单元，经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息，所述MMIO写操作基于所述PCI设备的MMIO内存的内存地址所映射的所述第一线程的虚拟空间地址；中断信号生成单元，响应于接收到所述通知消息，生成旨在第二线程的中断信号；中断配置信息配置单元，根据第二线程的状态信息配置所述PCI设备的中断配置信息，所述第二线程的状态信息包括所述第二线程所处运行态以及所述第二线程是否处于运行中；以及中断信号发送单元，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
可选地，在上述方面的一个示例中，如果所述第二线程处于Host Kernel，则所述中断配置信息配置单元将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器中的为所述第二线程配置的中断句柄；如果所述第二线程处于Guest Kernel且所述第二线程在运行中，则所述中断配置信息配置单元将中断配置为Posted Interrupt，并且将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器；如果所述第二线程处于Guest Kernel且所述第二线程未运行，则所述中断配置信息配置单元将所述中断信号发送方式配置为将所述中断信号发送给Host Kernel中的与所述第二线程所在虚拟处理器对应的物理处理器，所述物理处理器唤醒所述第二线程所在虚拟处理器；如果所述第二线程处于用户态，则所述中断配置信息配置单元将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器。
可选地，在上述方面的一个示例中，如果所述第二线程处于用户态，则所述中断配置信息配置单元将所述中断信号发送方式配置为通过信号量发送方式或eventfd发送方式将所述中断信号发送给所述第二线程所在处理器。
可选地，在上述方面的一个示例中，所述通知消息包括mov指令，所述mov指令的源操作数存储所述PCI设备的MMIO内存所需值，以及所述mov指令的目的地址是 所述MMIO内存所映射到的所述第一线程的虚拟空间地址。
可选地，在上述方面的一个示例中，所述MMIO内存所需值包括多个取值中的一个取值，每个取值对应一种类型的中断信号。相应地，响应于接收到所述mov指令，所述中断信号生成单元根据所述mov指令中的MMIO内存所需值，生成与所需值对应的中断信号。
可选地，在上述方面的一个示例中，所述PCI设备具有限流策略。所述装置还可以包括：限流判断单元，在生成所述中断信号后，根据所述限流策略进行限流判断。在所述限流判断单元判断为进行限流时，所述中断信号发送单元不发送所述中断信号，在所述限流判断单元判断为不进行限流时，所述中断信号发送单元按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
可选地，在上述方面的一个示例中，所述PCI设备具有分发策略。所述中断信号发送单元根据所述分发策略，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
可选地，在上述方面的一个示例中，所述PCI设备具有中断重映射表。所述装置还可以包括：中断重映射单元，基于所述中断重映射表来对所述中断信号进行中断重映射。所述中断信号发送单元按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送经过中断重映射后的中断信号。
根据本说明书的实施例的另一方面，提供一种用于在第一线程和第二线程之间发送中断信号的装置，所述装置包括：至少一个处理器，与所述至少一个处理器耦合的存储器，以及存储在所述存储器中的计算机程序，所述至少一个处理器执行所述计算机程序来实现如上所述的用于在第一线程和第二线程之间发送中断信号的方法。
根据本说明书的实施例的另一方面，提供一种计算机可读存储介质，其存储有计算机程序，所述计算机程序被处理器执行来实现如上所述的用于在第一线程和第二线程之间发送中断信号的方法。
根据本说明书的实施例的另一方面，提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行来实现如上所述的用于在第一线程和第二线程之间发送中断信号的方法。
附图说明
通过参照下面的附图，可以实现对于本说明书内容的本质和优点的进一步理解。在附图中，类似组件或特征可以具有相同的附图标记。
图1示出了根据本说明书的实施例的核间通知系统的系统架构的示例框图。
图2示出了根据本说明书的实施例的中断信号发送方Sender和中断信号接收方Receiver的部署示意图。
图3示出了根据本说明书的实施例的中断信号发送方Sender的初始化过程的示例示意图。
图4示出了根据本说明书的实施例的中断配置信息配置过程的示例流程图。
图5示出了根据本说明书的实施例的用于在第一线程和第二线程之间发送中断信号的方法的流程图。
图6示出了根据本说明书的实施例的用于在第一线程和第二线程之间发送中断信号的装置的方框图。
图7示出了根据本说明书的实施例的基于计算机实现的中断信号发送装置的示意图。
具体实施方式
现在将参考示例实施方式讨论本文描述的主题。应该理解，讨论这些实施方式只是为了使得本领域技术人员能够更好地理解从而实现本文描述的主题，并非是对权利要求书中所阐述的保护范围、适用性或者示例的限制。可以在不脱离本说明书内容的保护范围的情况下，对所讨论的元素的功能和排列进行改变。各个示例可以根据需要，省略、替代或者添加各种过程或组件。例如，所描述的方法可以按照与所描述的顺序不同的顺序来执行，以及各个步骤可以被添加、省略或者组合。另外，相对一些示例所描述的特征在其它例子中也可以进行组合。
如本文中使用的，术语“包括”及其变型表示开放的术语，含义是“包括但不限于”。术语“基于”表示“至少部分地基于”。术语“一个实施例”和“一实施例”表示“至少一个实施例”。术语“另一个实施例”表示“至少一个其他实施例”。术语“第一”、“第二”等可以指代不同的或相同的对象。下面可以包括其他的定义，无论是明确的还是隐含的。除非上下文中明确地指明，否则一个术语的定义在整个说明书中是一致的。
在Host Kernel下，CPU可以利用IPI来实现硬件线程之间的中断信号发送，但是在一些应用场景下，由于权限原因，无法使用IPI机制来实现线程所在的CPU之间的中断信号通知。上述应用场景的示例可以包括vCPU同步操作、Para-virtualized(PV)driver和两级调度器。
在vCPU同步操作的应用场景下，作为中断信号发送方的线程Sender处于Guest Kernel，以及作为中断信号接收方的线程Receiver处于Guest Kernel。在硬件虚拟化背景下，Guest Kernel中的很多操作需要vCPU同步操作，比如：TLB shootdown、RCU、CPU frequency scaling、Schedule。
在PV driver的应用场景下，作为中断信号发送方的线程Sender处于Guest Kernel，以及作为中断信号接收方的线程Receiver处于Host Kernel。PV driver分为前端driver和后端driver，当前端driver完成请求填写后，需要激活或唤醒(kick)后端driver进行工作。
在两级调度器的应用场景下，作为中断信号发送方的线程Sender处于Guest Kernel或Host Kernel，以及作为中断信号接收方的线程Receiver处于Host Kernel。在两级调度器系统中，除了Host Kernel中的L1调度器(比如Linux CFS)之外，在Guest Kernel或者HR3中存在另外一个调度器(L2调度器)，L2调度器用于调度Guest Kernel或者HR3中的任务。无论采用Work-Stealing还是Work-Sharing模型，在任务繁忙时，需要唤醒新的vCPU或线程进行工作。
下面将参照附图来详细描述根据本说明书的实施例的用于在第一线程和第二线程之间发送中断信号的方法及装置。
图1示出了根据本说明书的实施例的核间通知系统1的系统架构的示例框图。
如图1所示，核间通知系统1包括中断信号发送方Sender 10、PCI设备20和中断信号接收方Receiver 30。Sender 10可以是运行在用户态的HR3线程，由处于Host Kernel的物理处理器(例如，pCPU0)运行的HR0线程，或者由处于Guest Kernel的虚拟处理器(例如，vCPU0)运行的Guest线程。Receiver 30可以是运行在用户态的HR3线程，由处于Host Kernel的物理处理器(例如，pCPU1)运行的HR0线程，或者由处于Guest Kernel的虚拟处理器(例如，vCPU1)运行的Guest线程。
图2示出了根据本说明书的实施例的中断信号发送方Sender和中断信号接收方Receiver的部署示意图。在本说明书中，Sender 10以及Receiver 30分别对应于第一线 程和第二线程。
PCI设备20例如可以通过向通用PCI设备加入定制的通知分发(notification distribution)功能和/或通知限流(notification restrictor)功能来实现。通用PCI设备的示例可以包括但不限于NIC设备、APIC设备和Intel DLB(Dynamic Load Balancer)设备。NIC设备的示例可以包括但不限于比如ixgbe和i40e的通用网卡设备或者智能网卡设备。
在进行核间通知之前，需要对Sender 10和Receiver 30进行初始化处理。在对Sender10初始化处理时，将PCI设备20的内存地址映射到Sender 10的虚拟空间地址。
图3示出了根据本说明书的实施例的中断信号发送方Sender的初始化过程的示例示意图。
在HOST场景下，线程访问PCI设备20(例如，RNIC)通常采用MMIO写操作。为了让VM场景下的线程也可以按照上述方式访问PCI设备20，需要引入额外的内存映射，即，将PCI设备20的MMIO内存(如Doorbell)的内存地址映射到VM中的线程虚拟地址空间。下面以在设备初始化过程中映射一个Doorbell为例说明上述过程。
前端线程调用Verbs接口“open_device”来初始化设备上下文。上述初始化调用被分为如图3所示的三个部分，步骤2a、2b和2c。
如图3所示，在2a，在虚拟化后端收到前端请求后，在RNIC上申请一个Doorbell，由此后端驱动获取所申请的Doorbell的HPA(HOST物理地址)doorbell_hpa。在2b，前端驱动识别PCI设备的Doorbell所在的MMIO内存，然后调用mmap()将该MMIO内存的内存地址映射到线程的虚拟地址空间。所申请的内存可以称为vDoorbell，它对应QEMU中的虚拟地址空间doorbell_hva。在步骤2c，后端驱动通过修改QEMU的页表创建doorbell_hva和doorbell_hpa之间的映射，由此，前端线程访问vDoorBell就会被定向到PCI设备上的真实Doorbell。按照这种方式，VM中的线程可以通过MMIO写操作的方式直接访问PCI设备上的Doorbell。
在对Receiver 30进行初始化时，需要根据Receiver 30的状态信息配置PCI设备的中断配置信息。在本说明书中，线程的状态信息可以包括线程所处运行态以及线程是否处于运行中。中断配置信息可以包括中断信号发送方式、目标CPU。
图4示出了根据本说明书的实施例的中断配置信息配置过程400的示例流程图。
如图4所示，在对Receiver 30进行初始化时，在410，判断Receiver 30是否处于 Host Kernel。如果判断为Receiver 30处于Host Kernel，则在420，将PCI设备20的中断配置信息配置为中断配置信息1，即，将中断配置信息中的中断信号发送方式配置为将中断信号发送给Receiver 30所在处理器中的为Receiver 30配置的中断句柄Interrupt Handler。例如，在Receiver 30处于Host Kernel时，可以在Host Kernel中为Receiver 30配置合适的Interrupt Handler。然后，将中断信号发送给所配置的Interrupt Handler。Interrupt Handler响应于所接收的中断信号执行相应处理。在本说明书中，术语“线程所在处理器”是指运行线程的处理器。处理器的示例可以包括但不限于CPU、MPU、GPU等。
如果判断为Receiver 30未处于Host Kernel，则在430，判断Receiver 30是否处于Guest Kernel。如果判断为Receiver 30未处于Guest Kernel(即，处于用户态，HR3线程)，则在440，将PCI设备20的中断配置信息配置为中断配置信息2，即，将中断配置信息中的中断信号发送方式配置为将中断信号发送给Receiver 30所在处理器。例如，在一个示例中，可以将中断信号发送方式配置为通过信号量(semaphore)发送机制或eventfd将中断信号发送给Receiver 30所在处理器。
信号量发送机制利用PV操作来对信号量进行处理。信号量的数据结构为一个值和一个指针，指针指向等待该信号量的下一个进程。信号量的值与相应资源的使用情况有关。当信号量的值大于0时，表示当前可用资源的数量。当信号量的值小于0时，其绝对值表示等待使用该资源的进程个数。信号量的值由PV操作来改变。执行一次P操作意味着请求分配一个单位资源，信号量的值减1。执行一个V操作意味着释放一个单位资源，信号量的值加1。
PV操作由P操作原语和V操作原语组成。P操作(wait)申请一个单位资源，进程进入。V操作(signal)释放一个单位资源，进程出来。在执行P(S)操作后，将信号量S的值减1，即S＝S-1。如果S<＝0，则该进程继续执行。否则，将该进程置为等待状态，排入等待队列。在执行V(S)操作后，将信号量S的值加1，即S＝S+1。如果S>0，则该进程继续执行。否则，释放队列中第一个等待信号量的进程。
如果判断为Receiver 30处于Guest Kernel，则在450，判断Receiver 30是否在运行中。如果判断为Receiver 30在运行中，则在460，将PCI设备20的中断配置信息配置为中断配置信息3，即，将中断配置为Posted Interrupt，并且将中断配置信息中的中断信号发送方式配置为将中断信号发送给Receiver 30所在处理器。Posted Interrupt允许APIC中断直接注入到guest而不需要VM-Exit。
如果判断为Receiver 30未运行，则在470，将PCI设备20的中断配置信息配置为中断配置信息4，即，将中断配置信息中的中断信号发送方式配置为将中断信号发送给Host Kernel中的与Receiver 30所在虚拟处理器对应的物理处理器，所述物理处理器唤醒Receiver 30所在虚拟处理器。例如，物理处理器可以通过irqfd绑定并唤醒Receiver 30所在虚拟处理器。如有需要，可以将中断信号注入Guest Kernel，Guest Kernel中的IRQ响应可以根据需要进行调整。
图5示出了根据本说明书的实施例的用于在第一线程和第二线程之间发送中断信号的方法500的流程图。方法500由PCI设备20执行。
如图5所示，在510，PCI设备20经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息。这里，MMIO写操作基于PCI设备的MMIO内存的内存地址所映射的Sender 10的虚拟空间地址。这里，MMIO内存例如可以包括Doorbell内存。在一个示例中，通知消息可以是mov指令。mov指令的源操作数存储PCI设备20的MMIO内存所需值，以及mov指令的目的地址是MMIO内存所映射到的Sender 10的虚拟空间地址。例如，mov指令可以是mov reg,mem，其中，reg寄存器存储Doorbell内存所需值，mem表示Doorbell内存映射到的Sender 10的虚拟空间地址。
在520，响应于接收到通知消息，PCI设备20生成旨在Receiver 30的中断信号。这里，旨在Receiver 30的中断信号是指所生成的中断信号意在去往Receiver 30所在处理器。
在一个示例中，源操作数所存储的MMIO内存所需值可以包括固定值。相应地，在接收通知消息后，PCI设备20生成固定类型的中断信号。在另一示例中，源操作数所存储的MMIO内存所需值可以包括多个取值中的一个取值，每个取值对应一种类型的中断信号。相应地，响应于接收到mov指令，根据mov指令中的MMIO内存所需值，生成与所需值对应的中断信号。
在如上生成中断信号后，在530，按照PCI设备的中断配置信息所配置的中断信号发送方式向Receiver 30所在处理器发送中断信号。Receiver 30所在处理器接收到中断信号后，响应于所接收的中断信号执行相应处理。
可选地，在另一示例中，PCI设备20可以具有限流策略。所述限流策略的示例可以包括但不限于：PCI设备20在规定时段内针对中断信号的最大发送次数。例如，PCI设备20在一秒内针对每个中断最多发送M次。引入限流策略的主要原因是防止不信任 用户利用该中断发送机制进行DOS攻击。在上述限流策略中，需要在PCI设备20中为每个中断信号设置一个计数器Counter，利用该计数器Counter来计数该中断信号在规定时段内的发送次数。
在PCI设备20具有限流策略的情况下，在生成中断信号后，可以根据限流策略进行限流判断，以判断是否需要对该中断信号执行限流处理。例如，在中断信号在规定时段内的发送次数达到最大发送次数时，判断为需要对该中断信号进行限流处理。在中断信号在规定时段内的发送次数未达到最大发送次数时，判断为不需要对该中断信号进行限流处理。在限流判断结果为需要限流时，不发送所述中断信号。在限流判断结果为不需要限流时，按照PCI设备的中断配置信息所配置的中断信号发送方式向Receiver 30所在处理器发送该中断信号。
可选地，在另一示例中，PCI设备20可以具有分发策略。所述分发策略的示例可以包括但不限于：广播分发模式、信号量分发模式、1：1定向分发模式、1：N定向分发模式。在1：N定向分发模式下，响应于接收到通知消息，PCI设备20生成N个分别旨在N个Receiver 30的中断信号。
在PCI设备20具有分发策略的情况下，PCI设备20根据分发策略，按照PCI设备20的中断配置信息所配置的中断信号发送方式向Receiver 30所在处理器发送所生成的中断信号。
可选地，在另一示例中，PCI设备20可以具有中断重映射表。在这种情况下，在生成中断信号，PCI设备20基于中断重映射表来对中断信号进行中断重映射，从而得到经过中断重映射后的中断信号。然后，PCI设备20按照PCI设备20的中断配置信息所配置的中断信号发送方式向Receiver 30所在处理器发送经过中断重映射后的中断信号。
在一些实施例中，限流策略以及分发策略可以根据具体应用场景生成，并下发给PCI设备20。
利用根据本说明书的实施例的中断信号发送方案，通过将MMIO写操作交给Sender10所在处理器来执行，Sender 10可以通过处理器(CPU)的无序(out-of-order)执行功能，继续执行其它功能。按照这种处理方式，对于Sender 10，Sender 10“发起中断通知(kick)”的操作不会阻碍Sender 10执行后续代码，从而使得Sender 10处的中断通知的开销极小。
此外，由于Sender 10的kick操作的触发条件只是基于PCI设备20的内存地址的 MMIO写(Doorbell)操作，从而Sender 10可以运行在任何一个运行态，如图2中示出的HR3/HR0,GR3/GR0，只要Sender 10能够访问PCI设备20的内存地址即可。
此外，利用根据本说明书的实施例的中断信号发送方案，整个时延主要涉及PCI总线上的数据传输，从而可以有效降低中断信号发送时延。而且，在根据本说明书的实施例的中断信号发送方案中，通过在PCI设备20中设置限流策略，可以有效地防止DOS攻击。
图6示出了根据本说明书的实施例的用于在第一线程和第二线程之间发送中断信号的装置(下文中称为“中断信号发送装置”)600的方框图。如图6所示，中断信号发送装置600包括通知接收单元610、中断信号生成单元620、中断配置信息配置单元630和中断信号发送单元640。
通知接收单元610被配置为经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息，所述MMIO写操作基于PCI设备的MMIO内存的内存地址所映射的第一线程的虚拟空间地址实现。通知接收单元610的操作可以参考上面参照图5的510描述的操作。
中断信号生成单元620被配置为响应于接收到通知消息，生成旨在第二线程的中断信号。中断信号生成单元620的操作可以参考上面参照图5的520描述的操作。
中断配置信息配置单元630被配置为根据第二线程的状态信息配置PCI设备的中断配置信息。第二线程的状态信息可以包括第二线程所处运行态以及第二线程是否处于运行中。
中断信号发送单元640被配置为按照PCI设备的中断配置信息所配置的中断信号发送方式向第二线程所在处理器发送中断信号。
可选地，在一个示例中，如果第二线程处于Host Kernel，则中断配置信息配置单元630将中断信号发送方式配置为将中断信号发送给第二线程所在处理器中的为第二线程配置的Interrupt Handler。如果第二线程处于Guest Kernel且第二线程在运行中，则中断配置信息配置单元630将中断配置为Posted Interrupt，并且将中断信号发送方式配置为将中断信号发送给第二线程所在处理器。如果第二线程处于Guest Kernel且第二线程未运行，则中断配置信息配置单元630将中断信号发送方式配置为将中断信号发送给Host Kernel中的与第二线程所在虚拟处理器对应的物理处理器，所述物理处理器唤醒第二线程所在虚拟处理器。如果第二线程处于用户态，则中断配置信息配置单元630将中断信 号发送方式配置为将中断信号发送给第二线程所在处理器。
此外，可选地，在一个示例中，如果第二线程处于用户态，则中断配置信息配置单元630将中断信号发送方式配置为通过信号量发送机制或eventfd发送机制将中断信号发送给第二线程所在处理器。
此外，可选地，在一个示例中，所述通知消息可以包括mov指令，其中，mov指令的源操作数存储PCI设备的MMIO内存所需值，以及mov指令的目的地址是MMIO内存所映射到的第一线程的虚拟空间地址。
在一个示例中，源操作数所存储的MMIO内存所需值可以包括固定值。相应地，在接收通知消息后，中断信号生成单元620生成固定类型的中断信号。在另一示例中，源操作数所存储的MMIO内存所需值可以包括多个取值中的一个取值，每个取值对应一种类型的中断信号。相应地，在接收到mov指令后，中断信号生成单元620根据mov指令中的MMIO内存所需值，生成与所需值对应的中断信号。
可选地，在一个示例中，PCI设备可以具有限流策略。中断信号发送装置600还可以包括限流判断单元(未示出)。在生成中断信号后，所述限流判断单元根据限流策略进行限流判断。在限流判断单元判断为进行限流时，中断信号发送单元640不发送中断信号。在限流判断单元判断为不进行限流时，中断信号发送单元640按照PCI设备的中断配置信息所配置的中断信号发送方式向第二线程所在处理器发送中断信号。
可选地，在一个示例中，PCI设备具有分发策略。在这种情况下，中断信号发送单元640根据分发策略，按照PCI设备的中断配置信息所配置的中断信号发送方式向第二线程所在处理器发送中断信号。
可选地，在一个示例中，PCI设备可以具有中断重映射表。中断信号发送装置还可以包括中断重映射单元(未示出)。中断重映射单元基于中断重映射表来对中断信号进行中断重映射。然后，中断信号发送单元640按照PCI设备的中断配置信息所配置的中断信号发送方式向第二线程所在处理器发送经过中断重映射后的中断信号。
如上参照图1到图6，对根据本说明书实施例的中断信号发送方法和中断信号发送装置进行了描述。上面的中断信号发送装置可以采用硬件实现，也可以采用软件或者硬件和软件的组合来实现。
图7示出了根据本说明书的实施例的基于计算机实现的中断信号发送装置700的示意图。如图7所示，中断信号发送装置700可以包括至少一个处理器710、存储器(例 如，非易失性存储器)720、内存730和通信接口740，并且至少一个处理器710、存储器720、内存730和通信接口740经由总线750连接在一起。至少一个处理器710执行在存储器中存储或编码的计算机程序(即，上述以软件形式实现的元素)。
在一个实施例中，在存储器中存储计算机程序，其当执行时使得至少一个处理器710：经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息，MMIO写操作基于PCI设备的MMIO内存的内存地址所映射的第一线程的虚拟空间地址实现；响应于接收到通知消息，生成旨在第二线程的中断信号；以及按照PCI设备的中断配置信息所配置的中断信号发送方式向第二线程所在处理器发送中断信号，其中，中断配置信息根据第二线程的状态信息配置，第二线程的状态信息包括第二线程所处运行态以及第二线程是否处于运行中。
应该理解，在存储器中存储的计算机程序被执行时使得至少一个处理器710执行本说明书的各个实施例中的结合图1-图6描述的各种操作和功能。
根据一个实施例，提供了一种比如计算机可读介质(例如，非暂时性计算机可读介质)的程序产品。计算机可读介质可以具有计算机程序(即，上述以软件形式实现的元素)，该计算机程序被处理器执行时，使得处理器执行本说明书的各个实施例中的结合图1-图6描述的各种操作和功能。具体地，可以提供配有可读存储介质的系统或者装置，在该可读存储介质上存储着实现上述实施例中任一实施例的功能的软件程序代码，且使该系统或者装置的计算机或处理器读出并执行存储在该可读存储介质中的计算机程序。
在这种情况下，从可读介质读取的程序代码本身可实现上述实施例中任何一项实施例的功能，因此计算机可读代码和存储计算机可读代码的可读存储介质构成了本说明书的一部分。
可读存储介质的实施例包括软盘、硬盘、磁光盘、光盘(如CD-ROM、CD-R、CD-RW、DVD-ROM、DVD-RAM、DVD-RW、DVD-RW)、磁带、非易失性存储卡和ROM。可选择地，可以由通信网络从服务器计算机上或云上下载程序代码。
根据一个实施例，提供一种计算机程序产品，该计算机程序产品包括计算机程序，该计算机程序当被处理器执行时，使得处理器执行本说明书的各个实施例中以上结合图1-图6描述的各种操作和功能。
本领域技术人员应当理解，上面公开的各个实施例可以在不偏离发明实质的情况下做出各种变形和修改。因此，本公开的保护范围应当由所附的权利要求书来限定。
需要说明的是，上述各流程和各系统结构图中不是所有的步骤和单元都是必须的，可以根据实际的需要忽略某些步骤或单元。各步骤的执行顺序不是固定的，可以根据需要进行确定。上述各实施例中描述的装置结构可以是物理结构，也可以是逻辑结构，即，有些单元可能由同一物理实体实现，或者，有些单元可能分由多个物理实体实现，或者，可以由多个独立设备中的某些部件共同实现。
以上各实施例中，硬件单元或模块可以通过机械方式或电气方式实现。例如，一个硬件单元、模块或处理器可以包括永久性专用的电路或逻辑(如专门的处理器，FPGA或ASIC)来完成相应操作。硬件单元或处理器还可以包括可编程逻辑或电路(如通用处理器或其它可编程处理器)，可以由软件进行临时的设置以完成相应操作。具体的实现方式(机械方式、或专用的永久性电路、或者临时设置的电路)可以基于成本和时间上的考虑来确定。
上面结合附图阐述的具体实施方式描述了示例性实施例，但并不表示可以实现的或者落入权利要求书的保护范围的所有实施例。在整个本说明书中使用的术语“示例性”意味着“用作示例、实例或例示”，并不意味着比其它实施例“优选”或“具有优势”。出于提供对所描述技术的理解的目的，具体实施方式包括具体细节。然而，可以在没有这些具体细节的情况下实施这些技术。在一些实例中，为了避免对所描述的实施例的概念造成难以理解，公知的结构和装置以框图形式示出。
本公开内容的上述描述被提供来使得本领域任何普通技术人员能够实现或者使用本公开内容。对于本领域普通技术人员来说，对本公开内容进行的各种修改是显而易见的，并且，也可以在不脱离本公开内容的保护范围的情况下，将本文所定义的一般性原理应用于其它变型。因此，本公开内容并不限于本文所描述的示例和设计，而是与符合本文公开的原理和新颖性特征的最广范围相一致。

Claims (20)

  1. 一种用于在第一线程和第二线程之间发送中断信号的方法，所述方法由PCI设备执行，所述方法包括：
    经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息，所述MMIO写操作基于所述PCI设备的MMIO内存的内存地址所映射的所述第一线程的虚拟空间地址实现；
    响应于接收到所述通知消息，生成旨在第二线程的中断信号；以及
    按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号，其中，所述中断配置信息根据所述第二线程的状态信息配置，所述第二线程的状态信息包括所述第二线程所处运行态以及所述第二线程是否处于运行中。
  2. 如权利要求1所述的方法，其中，所述中断配置信息根据所述第二线程的状态信息配置包括：
    如果所述第二线程处于Host Kernel，则将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器中的为所述第二线程配置的中断句柄；
    如果所述第二线程处于Guest Kernel且所述第二线程在运行中，则将中断配置为Posted Interrupt，并且将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器；
    如果所述第二线程处于Guest Kernel且所述第二线程未运行，则将所述中断信号发送方式配置为将所述中断信号发送给Host Kernel中的与所述第二线程所在虚拟处理器对应的物理处理器，所述物理处理器唤醒所述第二线程所在虚拟处理器；
    如果所述第二线程处于用户态，则将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器。
  3. 如权利要求2所述的方法，其中，如果所述第二线程处于用户态，则将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器包括：
    如果所述第二线程处于用户态，则将所述中断信号发送方式配置为通过信号量发送机制或eventfd发送机制将所述中断信号发送给所述第二线程所在处理器。
  4. 如权利要求1所述的方法，其中，所述通知消息包括mov指令，所述mov指令的源操作数存储所述PCI设备的MMIO内存所需值，以及所述mov指令的目的地址是所述MMIO内存所映射到的所述第一线程的虚拟空间地址。
  5. 如权利要求4所述的方法，其中，所述MMIO内存所需值包括多个取值中的一 个取值，每个取值对应一种类型的中断信号；
    响应于接收到所述通知消息，生成中断信号包括：
    响应于接收到所述mov指令，根据所述mov指令中的MMIO内存所需值，生成与所需值对应的中断信号。
  6. 如权利要求1所述的方法，其中，所述MMIO内存包括doorbell内存。
  7. 如权利要求1所述的方法，其中，所述PCI设备具有限流策略，所述方法还包括：
    在生成所述中断信号后，根据所述限流策略进行限流判断；
    其中，在所述限流判断结果为进行限流时，不发送所述中断信号，在所述限流判断结果为不进行限流时，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
  8. 如权利要求1所述的方法，其中，所述PCI设备具有分发策略，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号包括：
    根据所述PCI设备中的分发策略，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
  9. 如权利要求1所述的方法，其中，所述PCI设备具有中断重映射表，所述方法还包括：
    基于所述中断重映射表来对所述中断信号进行中断重映射；
    按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号包括：
    按照所述PCI设备的中断配置信息所配置的中断信号发送方式，向所述第二线程所在处理器发送经过中断重映射后的中断信号。
  10. 一种用于在第一线程和第二线程之间发送中断信号的装置，所述装置应用于PCI设备执行，所述装置包括：
    通知接收单元，经由PCI总线接收第一线程所在处理器通过MMIO写操作发送的通知消息，所述MMIO写操作基于所述PCI设备的MMIO内存的内存地址所映射的所述第一线程的虚拟空间地址实现；
    中断信号生成单元，响应于接收到所述通知消息，生成旨在第二线程的中断信号；
    中断配置信息配置单元，根据第二线程的状态信息配置所述PCI设备的中断配置信息，所述第二线程的状态信息包括所述第二线程所处运行态以及所述第二线程是否处于 运行中；以及
    中断信号发送单元，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
  11. 如权利要求10所述的装置，其中：
    如果所述第二线程处于Host Kernel，则所述中断配置信息配置单元将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器中的为所述第二线程配置的中断句柄；
    如果所述第二线程处于Guest Kernel且所述第二线程在运行中，则所述中断配置信息配置单元将中断配置为Posted Interrupt，并且将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器；
    如果所述第二线程处于Guest Kernel且所述第二线程未运行，则所述中断配置信息配置单元将所述中断信号发送方式配置为将所述中断信号发送给Host Kernel中的与所述第二线程所在虚拟处理器对应的物理处理器，所述物理处理器唤醒所述第二线程所在虚拟处理器；
    如果所述第二线程处于用户态，则所述中断配置信息配置单元将所述中断信号发送方式配置为将所述中断信号发送给所述第二线程所在处理器。
  12. 如权利要求11所述的装置，其中，如果所述第二线程处于用户态，则所述中断配置信息配置单元将所述中断信号发送方式配置为通过信号量发送机制或eventfd发送机制将所述中断信号发送给所述第二线程所在处理器。
  13. 如权利要求10所述的装置，其中，所述通知消息包括mov指令，所述mov指令的源操作数存储所述PCI设备的MMIO内存所需值，以及所述mov指令的目的地址是所述MMIO内存所映射到的所述第一线程的虚拟空间地址。
  14. 如权利要求13所述的装置，其中，所述MMIO内存所需值包括多个取值中的一个取值，每个取值对应一种类型的中断信号；
    响应于接收到所述mov指令，所述中断信号生成单元根据所述mov指令中的MMIO内存所需值，生成与所需值对应的中断信号。
  15. 如权利要求10所述的装置，其中，所述PCI设备具有限流策略，所述装置还包括：
    限流判断单元，在生成所述中断信号后，根据所述限流策略进行限流判断；
    其中，在所述限流判断单元判断为进行限流时，所述中断信号发送单元不发送所述中断信号，在所述限流判断单元判断为不进行限流时，所述中断信号发送单元按照所述 PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
  16. 如权利要求10所述的装置，其中，所述PCI设备具有分发策略，所述中断信号发送单元根据所述分发策略，按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送所述中断信号。
  17. 如权利要求10所述的装置，其中，所述PCI设备具有中断重映射表，所述装置还包括：
    中断重映射单元，基于所述中断重映射表来对所述中断信号进行中断重映射；
    所述中断信号发送单元按照所述PCI设备的中断配置信息所配置的中断信号发送方式向所述第二线程所在处理器发送经过中断重映射后的中断信号。
  18. 一种用于在第一线程和第二线程之间发送中断信号的装置，所述装置包括：
    至少一个处理器；
    与所述至少一个处理器耦合的存储器，以及
    存储在所述存储器中的计算机程序，所述至少一个处理器执行所述计算机程序来实现如权利要求1到9中任一所述的方法。
  19. 一种计算机可读存储介质，其存储有计算机程序，所述计算机程序被处理器执行来实现如权利要求1到9中任一所述的方法。
  20. 一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行来实现如权利要求1到9中任一所述的方法。
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