WO2023071161A1 - 一种太阳能电池的pn结制备方法及太阳能电池 - Google Patents

一种太阳能电池的pn结制备方法及太阳能电池 Download PDF

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WO2023071161A1
WO2023071161A1 PCT/CN2022/094518 CN2022094518W WO2023071161A1 WO 2023071161 A1 WO2023071161 A1 WO 2023071161A1 CN 2022094518 W CN2022094518 W CN 2022094518W WO 2023071161 A1 WO2023071161 A1 WO 2023071161A1
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diffusion
silicon wafer
dopant
textured surface
oxide layer
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English (en)
French (fr)
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赵赞良
王茹
王武林
韩晓辉
陈宇晖
史晨燕
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宁夏隆基乐叶科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the field of solar photovoltaic technology, in particular to a method for preparing a PN junction of a solar cell and the solar cell.
  • the flat surface is usually textured to form a light trapping structure, so that the incident light is reflected multiple times on the front surface to reduce the reflection loss. Increase light absorption.
  • the textured surface is uneven, and there are size differences and height differences.
  • the pyramid suede structure there is a height difference between the pyramid peak and the valley bottom, and there are also size differences between different pyramids.
  • the tensile stress at the top of the tower is conducive to the diffusion of dopants
  • the compressive stress at the bottom of the valley is not conducive to the diffusion of dopants. Deeper, lower square resistance, and less dopant elements deposited at the bottom of the valley, shallow junction depth, high square resistance.
  • the PN junction on the textured surface is thicker at the top of the top and thinner at the bottom of the valley, resulting in poor uniformity, resulting in poor uniformity on the front surface of the battery.
  • the square resistance has a large difference and poor uniformity, which affects the conversion efficiency of the battery.
  • the junction depth gap can be reduced by reducing the size of the pyramids, thereby improving the uniformity of the square resistance.
  • reducing the size of the pyramids will reduce the multiple reflection effect of the light trapping structure on the incident light, thereby causing optical loss.
  • the present invention provides a method for preparing a PN junction of a solar cell and a solar cell, aiming at ensuring the depth of the PN junction and the uniformity of surface doping on the textured surface of the silicon wafer.
  • an embodiment of the present invention provides a method for preparing a PN junction of a solar cell, the method is applied to a textured surface of a silicon wafer, and the method includes:
  • the diffusion time of the first diffusion is less than or equal to 120 seconds.
  • the oxidation time of the oxidation is less than or equal to 180 seconds.
  • the diffusion time of the second diffusion is less than or equal to 180 seconds.
  • the propulsion temperature of the propulsion is greater than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation and the diffusion temperature of the second diffusion.
  • the diffusion temperature of the first diffusion is 770°C-800°C;
  • the oxidation temperature of the oxidation is 770°C to 800°C;
  • the diffusion temperature of the second diffusion is 770°C-800°C.
  • the propulsion temperature of the propulsion is 840°C-870°C.
  • the silicon wafer is a boron-doped silicon wafer, and the dopant is a phosphorus source.
  • the embodiment of the present invention also provides a solar cell, the solar cell includes a silicon wafer with a textured surface, the silicon wafer includes a PN junction, and the PN junction is prepared by the PN junction preparation method described in the first aspect get.
  • the silicon wafer in the solar cell has an intra-wafer non-uniformity of less than 7%.
  • the PN junction preparation method provided in the embodiment of the present invention is applied to the textured surface of the silicon wafer, including performing first diffusion on the textured surface with a dopant, and the conductivity type of the dopant is different from that of the silicon wafer, At this time, the doping at the top of the textured surface is deeper, and the doping at the bottom of the valley is shallower; then the textured surface after the first diffusion is oxidized to obtain an oxide layer. At this time, due to the deep doping at the top of the textured surface The oxidation rate is fast, so that the oxide layer at the top of the tower is thicker, and the doping at the bottom of the valley is shallower.
  • the dopant diffused in the oxide layer is pushed forward, because the oxide layer at the top of the tower is thicker and the speed of advancement is slower, so that the dopant at the top of the tower re-enters the silicon wafer is less, and the oxide layer at the bottom of the valley is thicker.
  • Figure 1 shows a method for preparing a PN junction of a solar cell provided by an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of a textured surface of a silicon wafer after the first diffusion provided by an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view of an oxidized textured surface of a silicon wafer provided by an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view of a test silicon wafer provided by an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of a comparative silicon wafer provided by an embodiment of the present invention.
  • Fig. 6 is a schematic diagram of an ECV test location provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an ECV test curve of a test silicon wafer provided by an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an ECV test curve of a comparative silicon wafer provided by an embodiment of the present invention.
  • FIG. 1 shows a method for preparing a PN junction of a solar cell provided by an embodiment of the present invention.
  • the method is applied to the textured surface of a silicon wafer, and the method includes:
  • Step 101 performing first diffusion on the textured surface of the silicon wafer with a dopant, the conductivity type of the dopant being different from that of the silicon wafer.
  • the textured surface of the silicon wafer can be a regular pyramid textured surface, or other textured textured structures with periodic protrusions and depressions.
  • Texture, nanoimprint texturing and other texturing processes will form peak-valley structures with different heights on the surface of the silicon wafer, and there is compressive stress at the bottom of the valley, which is not conducive to the diffusion of dopants. Therefore, deposition at the top of the tower will be caused during diffusion junction More doping, deeper junction depth, lower square resistance, and the opposite problem at the bottom of the valley.
  • the textured surface described in the embodiment of the present invention may be a textured surface formed by using an existing texturing process, wherein the first diffusion of dopants is performed on the textured surface of the silicon wafer
  • dopants with different conductivity types can be used in the silicon wafer to form a PN junction in the silicon wafer.
  • the conductivity type of the silicon chip can be N type or P type, and the conductivity type of the dopant is different.
  • the conductivity type of the silicon chip is N type
  • the conductivity type of the dopant is P Type
  • the conductivity type of the silicon wafer is P-type
  • the conductivity type of the dopant is N-type, so that after the dopant is used to diffuse the textured surface of the silicon wafer, a PN junction can be formed on the silicon wafer
  • the silicon wafer may be phosphorus-doped silicon wafer, boron-doped silicon wafer, etc.
  • the dopant may be phosphorus source, boron source, etc.
  • the diffusion can be carried out in a tube furnace.
  • the silicon wafer can be put into a quartz boat and sent into the furnace tube, and the furnace tube is tested for air tightness, and a negative pressure vacuum is drawn at the same time. , to complete the preparation for the first diffusion.
  • the silicon wafer is a boron-doped silicon wafer, and the dopant is a phosphorus source.
  • a PN junction can be prepared by diffusing an N-type dopant on a P-type silicon wafer, wherein the silicon wafer can be a boron-doped silicon wafer, and the dopant can be a phosphorus source
  • the diffusion temperature of the first diffusion is 770°C-800°C.
  • the diffusion time of the first diffusion is less than or equal to 120 seconds.
  • the diffusion temperature and diffusion time in the first diffusion process can be regulated according to the requirements of process conditions and application requirements on the concentration and depth of diffusion, wherein the diffusion temperature can be between 770°C and 800°C. Any temperature, such as 770°C, 775°C, 780°C, 790°C, 800°C, etc.; the diffusion time should be less than or equal to 120 seconds and greater than 0 seconds, such as 120 seconds, 110 seconds, 100 seconds, etc., by controlling the diffusion The amount of time can effectively control the junction depth of the diffusion.
  • the first diffusion is performed on the textured surface, so that the junction depth of the pyramid tip on the surface is deeper, the junction depth of the valley bottom is shallower, and the square resistance uniformity is poor.
  • Step 102 oxidizing the textured surface after the first diffusion to obtain an oxide layer.
  • the oxide layer can be obtained by oxidizing the textured surface of the silicon wafer after the first diffusion at the oxidation temperature.
  • the oxide layer has a blocking effect on element diffusion and thus reduces the rate of element diffusion.
  • the oxide layer may be a silicon dioxide layer. Due to the deeper junction depth of the pyramid tip and the shallower junction depth of the valley bottom on the textured surface, the oxidation rate at the top of the pyramid is faster and the thickness of the oxide layer is thicker, while the oxidation rate at the bottom of the valley is slower and the thickness of the oxide layer is thinner, making The barrier effect of the oxide layer is stronger at the top of the tower, and weaker at the bottom of the valley.
  • the oxidation temperature of the oxidation is 770°C-800°C.
  • the oxidation time of the oxidation is less than or equal to 180 seconds.
  • the oxidation time for the textured surface should be less than or equal to 180 seconds and greater than 0 seconds, for example, it can be 180 seconds, 170 seconds, 160 seconds, etc.
  • the oxide layer can be effectively controlled thickness;
  • the oxidation temperature for the textured surface can be any temperature between 770°C and 800°C, such as 770°C, 775°C, 780°C, 790°C, 800°C, etc.
  • Step 103 using the dopant to perform a second diffusion on the oxide layer, and the diffusion time of the second diffusion is longer than the diffusion time of the first diffusion.
  • a dopant can be used to perform the second diffusion on the oxide layer at the diffusion temperature of the second diffusion.
  • the second diffusion causes phosphorus atoms to accumulate in the oxide layer formed by oxidation in step 102, and the diffusion time of the second diffusion should be longer than that of the first diffusion, so as to control the final junction depth of the PN junction.
  • the diffusion temperature of the second diffusion is 770°C-800°C.
  • the diffusion time of the second diffusion is less than or equal to 180 seconds.
  • the diffusion time of the second diffusion should be less than or equal to 180 seconds and greater than 0, and greater than the diffusion time of the first diffusion.
  • the second diffusion The diffusion time should be greater than 120 seconds and less than or equal to 180 seconds.
  • the diffusion time of the second diffusion should be greater than 100 seconds and less than or equal to 180 seconds, etc.;
  • the diffusion temperature of the second diffusion can be 770 Any temperature between °C and 800 °C, such as 770 °C, 775 °C, 780 °C, 790 °C, 800 °C, etc., is not specifically limited in this embodiment of the present invention.
  • Step 104 advancing the dopant diffused in the oxide layer.
  • the dopant accumulated in the oxide layer can be pushed forward, so that the dopant can diffuse from the oxide layer into the silicon wafer. Since the oxide layer at the tip of the pyramid on the textured surface is thicker, the junction process The diffusion rate of the middle dopant is slow, and the oxide layer at the bottom of the valley is thinner, so the diffusion rate of the dopant is faster in the process of pushing the junction, so that it can fill in the deeper junction at the top of the pyramid on the textured surface in the first diffusion. Deep, the shallower junction depth difference at the bottom of the valley improves the uniformity of diffusion on the surface of the silicon wafer.
  • the propulsion temperature of the propulsion is greater than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation and the diffusion temperature of the second diffusion.
  • the propulsion temperature of the propulsion is 840°C-870°C.
  • a high-temperature propulsion process can be used to propel the dopant accumulated in the oxide layer.
  • the propulsion temperature of the propulsion is higher than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation and the diffusion of the second diffusion.
  • Temperature, where the propulsion temperature can be any temperature between 840°C and 870°C, such as 840°C, 845°C, 850°C, 860°C, 870°C, etc., which is not specifically limited in the embodiment of the present invention.
  • steps such as temperature reduction, back pressure, and boating can be performed after pushing the junction, so as to obtain a silicon wafer with a PN junction.
  • a test silicon wafer and a comparison silicon wafer were also prepared, wherein a boron-doped silicon wafer was used for preparation, the diffusion source was a phosphorus source, the surface of the boron-doped silicon wafer was a textured surface, and the PN junction in the test silicon wafer was made of
  • the PN junction preparation method shown in Figure 1 is prepared, and the specific process parameters are shown in Table 1 below:
  • pre-preparation is carried out in steps No. 1 to 5, including putting the silicon wafer into the quartz boat and sending it into the furnace tube, and then vacuumizing the furnace tube, checking for air tightness, and heating up;
  • step 6 a phosphorus source is used for power supply, and the first diffusion is performed on the textured surface of the silicon wafer at a temperature of 770° C. to 800° C., and the diffusion time is less than or equal to 120 seconds.
  • Fig. 2 is a schematic cross-sectional view of a textured surface of a silicon wafer after the first diffusion provided by an embodiment of the present invention.
  • the phosphorus source diffuses deeper at the spire 201, and the junction depth is deeper, and at the bottom of the valley
  • the diffusion of phosphorus source at position 202 is shallow, the junction depth is shallow, and the distribution of junction depth is uneven on the textured surface.
  • step 7 the surface after the first diffusion is oxidized, and an oxide layer is prepared on the textured surface of the silicon wafer at a temperature of 770° C. to 800° C., and the oxidation time is less than or equal to 180 seconds.
  • Figure 3 is a schematic cross-sectional view of an oxidized textured surface of a silicon wafer provided by an embodiment of the present invention.
  • the textured surface of a silicon wafer is oxidized to form carbon dioxide
  • SiO2 silicon
  • the thickness of the silicon dioxide layer at the spire 201 is thicker after oxidation, and the silicon dioxide layer at the valley bottom 202 is thinner.
  • step 8 a phosphorus source is used for power supply, and the second diffusion is performed on the oxide layer at a temperature of 770° C. to 800° C.
  • the diffusion time is greater than that of the first diffusion and less than or equal to 180 seconds.
  • steps 9 and 10 the phosphorus atoms diffused in the oxide layer are propelled at 840°C to 870°C.
  • steps 11-18 processes such as temperature reduction, power supply, propulsion, oxidation, back pressure, and boat discharge are performed to obtain test silicon wafers.
  • Fig. 4 is a schematic cross-sectional view of a test silicon wafer provided by an embodiment of the present invention.
  • the silicon dioxide layer is diffused for the second time, so that phosphorus atoms are diffused in the silicon dioxide layer , and propel phosphorus atoms, while the propulsion rate at the spire 201 position with a thicker silicon dioxide layer is slower, and the propulsion rate at the valley bottom 202 position with a thinner silicon dioxide layer is faster, so that during the propulsion process, the position at the valley bottom 202
  • the junction depth increases faster than the position of the spire 201 , so that there is a consistency of junction depth between the position of the spire 201 and the position of the valley 202 on the surface of the final test silicon wafer.
  • the PN junction in the comparison silicon wafer was prepared by the conventional pre-oxidation process, and the specific process parameters are shown in Table 2 below:
  • the pre-preparation is carried out in steps No. 1 to 5, including putting the silicon wafer into the quartz boat and sending it into the furnace tube, and then vacuumizing the furnace tube, air-tight leak detection, and heating up;
  • step 6 the textured surface of the silicon wafer is oxidized, and an oxide layer is prepared on the textured surface of the silicon wafer at a temperature of 770 ° C to 800 ° C, and the oxidation time is less than or equal to 180 seconds;
  • step 7 a phosphorus source is used for power supply, and the textured surface of the silicon wafer is diffused once at a temperature of 770° C. to 800° C., and the diffusion time is less than or equal to 200 seconds.
  • step 8 a phosphorus source is used for power supply, and the textured surface of the silicon wafer is subjected to secondary diffusion at a temperature of 770° C. to 800° C.
  • the diffusion time is greater than that of the first diffusion and less than or equal to 390 seconds.
  • steps 9 and 10 the phosphorus atoms diffused in the oxide layer are propelled at 840°C to 870°C.
  • Fig. 5 is a schematic cross-sectional view of a comparative silicon wafer provided by an embodiment of the present invention.
  • a silicon dioxide layer is prepared by oxidation of a phosphorus source on the textured surface of a boron-doped silicon wafer, and then passed through two passes The source and the two advances form a PN junction, wherein the junction depth at the spire 301 on the surface of the silicon wafer is deeper, the junction depth at the valley bottom 302 is shallower, and the junction depth uniformity is poor.
  • Fig. 6 is a kind of ECV (Electrochemical capacitance-voltage profiler, electrochemical differential capacitance voltage) test position schematic diagram provided by the embodiment of the present invention, wherein, ECV adopts electrolytic solution to form potential barrier to measure carrier concentration, and P-type semiconductor Apply forward bias voltage, or apply reverse bias voltage and light to the N-type semiconductor to corrode the surface, so as to remove the electrolyzed material, repeat the above "corrosion-measurement" cycle, and then apply Faraday's law to integrate the corrosion current.
  • the etching depth can be obtained continuously, so as to obtain the measurement curve of carrier concentration and semiconductor depth.
  • ECV can be used to test the relationship between the carrier concentration and the semiconductor depth of the asymmetric A1 position and B1 position on the test silicon wafer 1, and the asymmetric A2 position and B2 position on the comparison silicon wafer 2. test.
  • FIG. 7 is a schematic diagram of an ECV test curve of a test silicon wafer provided by an embodiment of the present invention. As shown in FIG. The uniformity of the junction depth at different positions on the test silicon wafer is better. Since the test silicon wafer is a textured surface, the pyramid distribution is random, so it can be determined that the distribution of doping concentration at the top and bottom of the pyramid structure is relatively uniform. On this basis, the square resistance uniformity of the test silicon wafer should be better. At the same time, the concentration of the surface area of the test silicon wafer is more concentrated, which can improve product yield, reduce black spots, and reduce series resistance within a certain range, thereby improving filling. factor to ensure the conversion efficiency of solar cells made of silicon wafers.
  • Fig. 8 is a schematic diagram of an ECV test curve of a comparative silicon wafer provided by an embodiment of the present invention.
  • the curves of carrier concentration and junction depth at positions A2 and B2 on the comparative silicon wafer are quite different, that is, different
  • the PN junction depth and concentration of the dots are different, and the dopant concentration in the top and valley areas of the textured pyramid is different.
  • the uniformity of the junction depth at different positions on the comparison silicon wafer is poor, and it can be determined that different positions on the comparison silicon wafer
  • the doping structure is different. On this basis, the square resistance uniformity of the comparative silicon wafer is poor.
  • the diffusion time of steps 7 and 8 in the preparation process of the comparison silicon wafer is greater than the diffusion time of steps 6 and 8 in the preparation process of the test silicon wafer, and according to Figures 7 and 8, the test The doping concentration of the surface area of the silicon wafer is close to that of the comparison silicon wafer, that is, the test silicon wafer further reduces the process time consumption and improves the preparation efficiency of the PN junction on the basis of ensuring the doping quality.
  • a four-probe square resistance tester is used to test the square resistance of the test silicon wafer and the comparison silicon wafer based on the five-point method. Among them, the four-probe square resistance tester is used to test 50 test silicon wafers and 50 comparison silicon wafers.
  • Carry out the square resistance test take the average value of the square resistance at five points on each test silicon wafer as the test square resistance corresponding to the test silicon wafer, and take the average value of the square resistance at five points on each comparison silicon wafer as the comparison silicon
  • the contrast square resistance corresponding to the slices, the difference and the ratio of the difference and the sum of the maximum value and the minimum value of the test square resistance in 50 test silicon slices are used to determine the unevenness between the slices of the test silicon slices, and five test slices are used in each test slice.
  • the ratio of the difference between the maximum value and the minimum value of the square resistance at the point position and the sum determines the inhomogeneity of the test silicon wafer, and takes 170 ⁇ /sq as the central value of the square resistance, and determines the test square resistance in 50 test silicon wafers. Within the range of 170 ⁇ 5, that is, the ratio of the quantity between 165 ⁇ and 175 ⁇ to the total quantity determines the degree of concentration. It has been determined that the inhomogeneity of the silicon wafer is usually 7.77%, while the inhomogeneity of the silicon wafer prepared by the PN junction preparation method in the solar cell provided by the application is lower than 7%, that is, it can include 5%, 5.5%, 6%, 6.5%, 7%, etc. any value lower than 7%.
  • the test silicon wafer concentration of the PN junction prepared by the preparation method provided by the application is significantly higher than that of the comparison silicon wafer prepared by the conventional process, and the unevenness in the slice and the unevenness between the slices are reduced.
  • the square resistance uniformity of the test silicon wafer is better, the yield rate is higher, and the quality is better.
  • the present application effectively improves the uniformity of the PN junction of the pyramid spire and valley bottom on the textured surface, avoids the limitation on the size of the pyramid, reduces the optical loss on the surface, and at the same time , because the oxide layer will reduce the diffusion rate, therefore, the oxide layer is prepared in the gap between the two diffusions, and there is no barrier of the oxide layer in the first diffusion, so that the influence of the oxide layer on the diffusion rate can be reduced, and the diffusion uniformity can be ensured at the same time. overall diffusion efficiency.
  • the PN junction preparation method provided in the embodiment of the present invention is applied to the textured surface of the silicon wafer, including performing first diffusion on the textured surface with a dopant, and the conductivity type of the dopant is different from that of the silicon wafer, At this time, the doping at the top of the textured surface is deeper, and the doping at the bottom of the valley is shallower; then the textured surface after the first diffusion is oxidized to obtain an oxide layer. At this time, due to the deep doping at the top of the textured surface The oxidation rate is fast, so that the oxide layer at the top of the tower is thicker, and the doping at the bottom of the valley is shallower.
  • the dopant diffused in the oxide layer is pushed forward, because the oxide layer at the top of the tower is thicker and the speed of advancement is slower, so that the dopant at the top of the tower re-enters the silicon wafer is less, and the oxide layer at the bottom of the valley is thicker.
  • the embodiment of the present invention also provides a solar cell, the solar cell includes a silicon wafer with a textured surface, the silicon wafer includes a PN junction, and the PN junction is prepared by the following steps:
  • the intra-chip non-uniformity of the silicon wafer in the solar cell includes 5%-7%.

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Abstract

本发明提供了一种太阳能电池的PN结制备方法及太阳能电池，涉及太阳能光伏技术领域。该方法应用于硅片的织构化表面，包括采用掺杂剂在织构化表面上进行第一扩散，且掺杂剂与硅片的导电类型不同；再对第一扩散后的织构化表面氧化获得氧化层；再采用掺杂剂对氧化层进行第二扩散，使得掺杂剂留存于氧化层中；再对氧化层中扩散的掺杂剂进行推进，从而在硅片织构化表面的两次扩散中，第一扩散从塔尖进入硅片的掺杂剂较多，从谷底进入硅片的掺杂剂较少，第二扩散则相反，使得硅片不同位置进入的掺杂剂总量较为平均，有效保证了硅片PN结的结深均匀性。

Description

一种太阳能电池的PN结制备方法及太阳能电池
本申请要求在2021年10月25日提交中国专利局、申请号为2021112428335、发明名称为“一种太阳能电池的PN结制备方法及太阳能电池”的中国专利申请的优先权，其全部内容通过引用均结合在本申请中。
技术领域
本发明涉及太阳能光伏技术领域，特别是涉及一种太阳能电池的PN结制备方法及太阳能电池。
背景技术
在太阳能光伏产业中，为了减少电池前表面的反射损失，提高光吸收，通常采用对平整表面进行织构化以形成陷光结构的方式，使得入射光在前表面多次反射以减少反射损失，增加光吸收。
但是，织构化表面不平整，存在尺寸差、高度差等，如金字塔绒面结构中存在金字塔的塔尖与谷底之间的高度差，也存在不同金字塔之间的尺寸差异。而在织构化表面制备PN结时，由于塔尖存在拉应力利于掺杂剂扩散，谷底存在压应力不利于掺杂剂扩散，因此，会造成沉积在塔尖处掺杂较多、结深较深、方阻偏低，而沉积在谷底处的掺杂元素较少、结深较浅、方阻偏高的问题。进一步的，由于金字塔的尺寸不一，且塔尖和谷底掺杂程度存在差异，使得织构化表面的PN结在塔尖处较厚在谷底处较薄均匀性较差，进而造成电池前表面方阻差异性较大、均匀性差，影响电池的转换效率。
目前，可以通过减少金字塔尺寸的方式降低结深差距，从而提高方阻的均匀性，但是，减少金字塔尺寸会降低陷光结构对入射光的多次反射效果，进而造成光学损失。
发明内容
针对上述问题，本发明提供一种太阳能电池的PN结制备方法及太阳能电池，旨在保证硅片的织构化表面的PN结结深及表面掺杂的均匀性。
第一方面，本发明实施例提供了一种太阳能电池的PN结制备方法，该方法应用于硅片的织构化表面，该方法包括：
采用掺杂剂在所述硅片的所述织构化表面上进行第一扩散，所述掺杂剂与所述硅片的导电类型不同；
氧化所述第一扩散后的所述织构化表面，获得氧化层；
采用所述掺杂剂在所述氧化层上进行第二扩散，所述第二扩散的扩散时间大于所述 第一扩散的扩散时间；
对所述氧化层中扩散的所述掺杂剂进行推进。
可选地，所述第一扩散的扩散时间为小于或等于120秒。
可选地，所述氧化的氧化时间为小于或等于180秒。
可选地，所述第二扩散的扩散时间为小于或等于180秒。
可选地，所述推进的推进温度大于所述第一扩散的扩散温度、所述氧化的氧化温度以及所述第二扩散的扩散温度。
可选地，所述第一扩散的扩散温度为770℃～800℃；
所述氧化的氧化温度为770℃～800℃；
所述第二扩散的扩散温度为770℃～800℃。
可选地，所述推进的推进温度为840℃～870℃。
可选地，所述硅片为掺硼硅片，所述掺杂剂为磷源。
第二方面，本发明实施例还提供了一种太阳能电池，该太阳能电池包括织构化表面的硅片，该硅片包括PN结，该PN结通过第一方面所述的PN结制备方法制备得到。
可选地，该太阳能电池中硅片的片内不均匀度低于7％。
在本发明实施例中提供的PN结制备方法应用于硅片的织构化表面，包括采用掺杂剂在织构化表面上进行第一扩散，且掺杂剂与硅片的导电类型不同，此时，织构化表面上塔尖处掺杂较深，谷底处掺杂较浅；再对第一扩散后的织构化表面氧化获得氧化层，此时，由于塔尖处掺杂较深氧化速率快，使得塔尖处氧化层较厚，谷底处掺杂较浅氧化速率慢，使得谷底处氧化层较薄；再采用掺杂剂对氧化层进行第二扩散，使得掺杂剂扩散在氧化层中；对氧化层中扩散的掺杂剂进行推进，由于塔尖处氧化层较厚，推进速率较慢，使得塔尖处再次进入硅片的掺杂剂较少，谷底处氧化层较薄，推进速率较快，使得谷底处再次进入硅片的掺杂剂较多，从而在硅片织构化表面的两次扩散中，第一扩散从塔尖进入硅片的掺杂剂较多，从谷底进入硅片的掺杂剂较少，第二扩散则相反，使得硅片不同位置进入的掺杂剂总量较为平均，有效保证了PN结的结深及表面掺杂的均匀性。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例的描述中所需 要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
附图用于更好地理解本申请，不构成对本申请的不当限定。其中：
图1示出了本发明实施例提供的一种太阳能电池的PN结制备方法；
图2是本发明实施例提供的一种第一扩散后的硅片织构化表面的剖面示意图；
图3是本发明实施例提供的一种氧化后的硅片织构化表面的剖面示意图；
图4是本发明实施例提供的一种测试硅片的剖面示意图；
图5是本发明实施例提供的一种对比硅片的剖面示意图；
图6是本发明实施例提供的一种ECV测试位置示意图；
图7是本发明实施例提供的一种测试硅片的ECV测试曲线示意图；
图8是本发明实施例提供的一种对比硅片的ECV测试曲线示意图。
具体实施例
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参照图1，图1示出了本发明实施例提供的一种太阳能电池的PN结制备方法，该方法应用于硅片的织构化表面，该方法包括：
步骤101、采用掺杂剂在所述硅片的所述织构化表面上进行第一扩散，所述掺杂剂与所述硅片的导电类型不同。
本发明实施例中，硅片的织构化表面可以是正金字塔绒面，也可以是其他具有周期性凸起、凹陷的绒面结构，由于酸、碱制绒，等离子制绒，金属离子催化制绒，纳米压印制绒等制绒工艺会在硅片表面形成高度不同的峰谷结构，而谷底存在压应力，不利于掺杂剂扩散，因此，在扩散制结时会造成塔尖处沉积掺杂较多、结深较深、方阻偏低，而谷底处相反的问题。在此基础上，本发明实施例所述的织构化表面可以是采用现有制绒工艺形成的织构化表面，其中，在硅片的织构化表面上采用掺杂剂进行第一扩散时，可以采用于硅片的导电类型不同的掺杂剂，从而在硅片中形成PN结。
本发明实施例中，硅片的导电类型可以是N型，也可以是P型，掺杂剂的导电类型不同，如在硅片的导电类型为N型时，掺杂剂的导电类型为P型，在硅片的导电类型为P型时，掺杂剂的导电类型为N型，以使得采用掺杂剂对硅片的织构化表面进行扩散后，可以在硅片上形成PN结，其中，硅片可以是掺磷硅片、掺硼硅片等，掺杂剂可以是磷 源、硼源等。
本发明实施例中，扩散可以在管式炉中进行，在进行第一扩散前可以将硅片放入石英舟中送入炉管，并对炉管进行气密性检测，同时抽负压真空，以完成第一扩散的准备。
可选地，所述硅片为掺硼硅片，所述掺杂剂为磷源。
本发明实施例中，可以采用在P型硅片上扩散N型掺杂剂的方式制备PN结，其中，硅片可以是掺硼硅片，掺杂剂可以是磷源
可选地，所述第一扩散的扩散温度为770℃～800℃。
可选地，所述第一扩散的扩散时间为小于或等于120秒。
本发明实施例中，根据工艺条件、应用需求等对扩散浓度、深度的要求，可以对第一扩散过程中的扩散温度以及扩散时间进行调控，其中，扩散温度可以是770℃～800℃间的任意温度，如770℃、775℃、780℃、790℃、800℃等；扩散时间应小于或等于120秒，且大于0秒，如可以是120秒、110秒、100秒等，通过控制扩散时间的大小可以有效控制扩散的结深，在织构化表面进行第一扩散，使得表面上金字塔塔尖结深较深，谷底结深较浅，方阻均匀性较差。
步骤102、氧化所述第一扩散后的所述织构化表面，获得氧化层。
本发明实施例中，可以在氧化的氧化温度下对硅片第一扩散后的织构化表面进行氧化获得氧化层，氧化层对元素扩散的有阻挡作用从而降低元素扩散的速率，在此基础上，部分减小硅片不同部位扩散的不均匀度，该氧化层可以是二氧化硅层。由于织构化表面上金字塔塔尖结深较深，谷底结深较浅，因此，塔尖处氧化速率较快，氧化层厚度较厚，谷底处氧化速率较慢，氧化层厚度较薄，使得氧化层在塔尖处阻挡作用较强，在谷底处阻挡作用较弱。
可选地，所述氧化的氧化温度为770℃～800℃。
可选地，所述氧化的氧化时间为小于或等于180秒。
本发明实施例中，对织构化表面的氧化时间应小于或等于180秒，且大于0秒，如可以是180秒、170秒、160秒等，通过控制氧化时间的大小可以有效控制氧化层的厚度；对织构化表面的氧化温度可以是770℃～800℃间的任意温度，如770℃、775℃、780℃、790℃、800℃等。
步骤103、采用所述掺杂剂在所述氧化层上进行第二扩散，所述第二扩散的扩散时间大于所述第一扩散的扩散时间。
本发明实施例中，可以在获得氧化层后，在第二扩散的扩散温度下，采用掺杂剂在氧化层上再进行第二扩散，其中，第二扩散可对应参照前述第一扩散的相关说明，为避免重复，在此不再赘述。另外，第二扩散使得磷原子累积在步骤102氧化形成的氧化层 中，第二扩散的扩散时间应大于第一扩散的扩散时间，以控制PN结的最终结深。
可选地，所述第二扩散的扩散温度为770℃～800℃。
可选地，所述第二扩散的扩散时间为小于或等于180秒。
本发明实施例中，第二扩散的扩散时间应在小于或等于180秒，且大于0的基础上，大于第一扩散的扩散时间，如当第一扩散时间为120秒时，第二扩散的扩散时间应大于120秒且小于或等于180秒，当第一扩散时间为100秒时，第二扩散的扩散时间应大于100秒且小于或等于180秒等；第二扩散的扩散温度可以是770℃～800℃间的任意温度，如770℃、775℃、780℃、790℃、800℃等，本发明实施例对此不做具体限制。
步骤104、对所述氧化层中扩散的所述掺杂剂进行推进。
本发明实施例中，可以对氧化层中累积的掺杂剂进行推进，使掺杂剂从氧化层扩散入硅片中，由于织构化表面上金字塔尖处氧化层较厚，因此推结过程中掺杂剂的扩散速率较慢，谷底处氧化层较薄，因此推结过程中掺杂剂的扩散速率较快，从而能够填补第一扩散中织构化表面上金字塔塔尖处结深较深，谷底处结深较浅的差异，提升硅片表面扩散的均匀性。
可选地，所述推进的推进温度大于所述第一扩散的扩散温度、所述氧化的氧化温度以及所述第二扩散的扩散温度。
可选地，所述推进的推进温度为840℃～870℃。
本发明实施例中，可以采用高温推进工艺对氧化层中累积的掺杂剂进行推进，在此基础上，推进的推进温度大于第一扩散的扩散温度、氧化的氧化温度以及第二扩散的扩散温度，其中，推进的推进温度可以是840℃～870℃间的任意温度，如可以是840℃、845℃、850℃、860℃、870℃等，本发明实施例对此不作具体限制。
本发明实施例中，采用管式炉制备PN结时，可以在推结后进行降温、回压、出舟等步骤，以获得具有PN结的硅片。
本发明实施例中，还制备了测试硅片与对比硅片，其中，采用掺硼硅片制备，扩散源为磷源，掺硼硅片表面为织构化表面，测试硅片中PN结采用如图1所示的PN结制备方法制备得到，具体工艺参数如下表1所示：
表1
Figure PCTCN2022094518-appb-000001
表1中，在步骤序号1～5先进行制备的预先准备，包括将硅片放入石英舟中送入炉管，再对炉管进行抽真空、气密性检漏以及升温等；
在步骤6采用磷源进行通源，在770℃～800℃温度下，对硅片的织构化表面进行第一扩散，扩散时间小于或等于120秒。
图2是本发明实施例提供的一种第一扩散后的硅片织构化表面的剖面示意图，如图2所示，在塔尖201位置磷源扩散较深，结深较深，在谷底202位置磷源扩散较浅，结深较浅，在织构化表面上结深分布不均匀。
在步骤7对第一扩散后的表面进行氧化，在770℃～800℃温度下，在硅片的织构化表面上制备氧化层，氧化时间小于或等于180秒。
图3是本发明实施例提供的一种氧化后的硅片织构化表面的剖面示意图，如图3所示，在图2的基础上，对硅片的织构化表面进行氧化形成二氧化硅(SiO2)层，由于氧化速率不同，在氧化后塔尖201位置的二氧化硅层厚度较厚，谷底202位置的二氧化硅层较薄。
在步骤8采用磷源进行通源，在770℃～800℃温度下，对氧化层进行第二扩散，扩散时间大于第一扩散的扩散时间，且小于或等于180秒。
在步骤9、10中，在840℃～870℃下对氧化层中扩散的磷原子进行推进。
在后续步骤11～18中，进行降温、通源、推进、氧化、回压、出舟等工序，从而获得测试硅片。
图4是本发明实施例提供的一种测试硅片的剖面示意图，如图4所示，在图3的基础上，对二氧化硅层进行第二扩散，使得磷原子扩散在二氧化硅层中，并对磷原子进行推进，而二氧化硅层较厚的塔尖201位置推进速率较慢，二氧化硅层较薄的谷底202位置推进速率较快，从而在推进过程中谷底202位置的结深增长快于塔尖201位置，使得最终测试硅片表面的塔尖201位置与谷底202位置之间存在结深的一致性。
对比硅片中PN结采用常规前氧工艺制备得到，具体工艺参数如下表2所示：
表2
Figure PCTCN2022094518-appb-000002
其中，表2中，在步骤序号1～5先进行制备的预先准备，包括将硅片放入石英舟中送入炉管，再对炉管进行抽真空、气密性检漏以及升温等；
在步骤6对硅片的织构化表面进行氧化，在770℃～800℃温度下，在硅片的织构化表面上制备氧化层，氧化时间小于或等于180秒；
在步骤7采用磷源进行通源，在770℃～800℃温度下，对硅片的织构化表面进行一次扩散，扩散时间小于或等于200秒。
在步骤8采用磷源进行通源，在770℃～800℃温度下，对硅片的织构化表面进行二次扩散，扩散时间大于第一扩散的扩散时间，且小于或等于390秒。
在步骤9、10中，在840℃～870℃下对氧化层中扩散的磷原子进行推进。
在后续步骤11～17中，进行降温、通源、推进、氧化、回压、出舟等工序，从而获得对比硅片。
图5是本发明实施例提供的一种对比硅片的剖面示意图，如图5所示，在掺硼硅片的织构化表面采用磷源先氧化制备二氧化硅层，再通过两次通源、两次推进形成PN结，其中，对比硅片表面的塔尖301位置结深较深，谷底302位置结深较浅，结深均匀性较差。
示例一
图6是本发明实施例提供的一种ECV(Electrochemical capacitance-voltage profiler，电化学微分电容电压)测试位置示意图，其中，ECV采用电解液形成势垒已测量测流子浓度，并对P型半导体施加正向偏压，或对N型半导体施加反向偏压与光照进行表面腐蚀，从而去除已电解的材料，通过重复上述“腐蚀-测量”循环，然后应用法拉第定律，对腐蚀电流进行积分就可以连续得到腐蚀深度，从而得到载流子浓度与半导体深度的测量曲线。如图6所示，可以采用ECV分别对测试硅片1上不对称的A1位置、B1位置，以及对比硅片2上不对称的A2位置、B2位置的载流子浓度与半导体深度关系曲线进行测试。
图7是本发明实施例提供的一种测试硅片的ECV测试曲线示意图，如图7所示，测试硅片上A1位置、B1位置载流子浓度与结深变化曲线具有一致性，即在测试硅片上不同位置结深的均匀性较好。由于测试硅片为织构化表面，金字塔分布具有随机性，由此可以确定金字塔结构中塔尖、谷底的掺杂浓度分布较为均匀。在此基础上，测试硅片的方阻均匀性应较好，同时测试硅片的表面区域浓度更加集中，能够提升产品良率，降低黑斑，并在一定范围内降低串阻，从而提高填充因子，保证硅片制备的太阳能电池的转换效率。
图8是本发明实施例提供的一种对比硅片的ECV测试曲线示意图，如图8所示，对比硅片上A2位置、B2位置载流子浓度与结深变化曲线差别较大，即不同点的PN结结深与浓度不同、绒面金字塔的塔尖、谷底区的掺杂剂浓度不一，在对比硅片上不同位置结深的均匀性较差，可以确定对比硅片上不同位置掺杂结构不同。在此基础上，对比硅片的方阻均匀性较差。
而且，根据表1、2所示，对比硅片在制备过程中步骤7、8的扩散时间大于测试硅片在制备过程中步骤6、8的扩散时间，而根据图7、8所示，测试硅片与对比硅片的表面区域掺杂浓度接近，即测试硅片在保证掺杂质量的基础上，进一步减少了工艺耗时，提高了PN结的制备效率。
示例二
采用四探针方阻测试仪，基于五点法对测试硅片、对比硅片的方阻进行测试，其中，分别采用四探针方阻测试仪对50张测试硅片与50张对比硅片进行方阻测试，在每张测 试硅片上取五点位置方阻的均值作为该测试硅片对应的测试方阻，在每张对比硅片上取五点位置方阻的均值作为该对比硅片对应的对比方阻，在50张测试硅片中采用测试方阻的最大值与最小值的差与和的比值确定测试硅片的片间不均匀度，在每张测试硅片中采用五点位置方阻的最大值与最小值的差与和的比值确定测试硅片的片内不均匀度，并以170Ω/sq作为方阻中心值，在50张测试硅片中确定测试方阻在170Ω±5范围内，即165Ω～175Ω之间的数量与总数量的比值确定集中度。经测定，对比硅片的片内不均匀度通常为7.77％，而本申请提供的太阳能电池中PN结制备方法制备得到的硅片片内不均匀度低于7％，即可以包括5％、5.5％、6％、6.5％、7％等低于7％的任意数值。
具体的，参照上述过程，分别确定对比硅片的片间不均匀度、片内不均匀度与集中度，如表3所示：
表3
硅片 集中度(170Ω±5) 片内不均匀度 片间不均匀度 方阻中心值
对比硅片 80.6％ 7.77％ 4.09％ 170Ω/sq
测试硅片 87.2％ 6.54％ 3.62％ 170Ω/sq
由表3可知，由本申请提供的制备方法制备PN结的测试硅片集中度显著高于由常规工艺制备的对比硅片，片内不均匀度、片间不均匀度有所降低，在此基础上，可以确定相比于对比文件硅片，测试硅片的方阻均匀性更好，良率更高、质量更好。本申请通过在两次通源间制备氧化层，有效提升了织构化表面上金字塔塔尖、谷底的PN结均匀性，并且避免了对金字塔尺寸的限制，减少了表面上的光学损失，同时，由于氧化层会降低扩散速度，因此，在两次扩散的间隙制备氧化层，在第一扩散中无氧化层阻挡，从而能够降低氧化层对扩散速度的影响，在保证扩散均匀性的同时保证整体的扩散效率。
在本发明实施例中提供的PN结制备方法应用于硅片的织构化表面，包括采用掺杂剂在织构化表面上进行第一扩散，且掺杂剂与硅片的导电类型不同，此时，织构化表面上塔尖处掺杂较深，谷底处掺杂较浅；再对第一扩散后的织构化表面氧化获得氧化层，此时，由于塔尖处掺杂较深氧化速率快，使得塔尖处氧化层较厚，谷底处掺杂较浅氧化速率慢，使得谷底处氧化层较薄；再采用掺杂剂对氧化层进行第二扩散，使得掺杂剂扩散在氧化层中；对氧化层中扩散的掺杂剂进行推进，由于塔尖处氧化层较厚，推进速率较慢，使得塔尖处再次进入硅片的掺杂剂较少，谷底处氧化层较薄，推进速率较快，使得谷底处再次进入硅片的掺杂剂较多，从而在硅片织构化表面的两次扩散中，第一扩散从塔尖进入硅片的掺杂剂较多，从谷底进入硅片的掺杂剂较少，第二扩散则相反，使得硅片不同位置进入的掺杂剂总量较为平均，有效保证了PN结的结深均匀性。
本发明实施例还提供了一种太阳能电池，该太阳能电池包括织构化表面的硅片，所 述硅片包括PN结，所述PN结通过以下步骤制备得到：
采用掺杂剂在所述硅片的所述织构化表面上进行第一扩散，所述掺杂剂与所述硅片的导电类型不同；
氧化所述第一扩散后的所述织构化表面，获得氧化层；
采用所述掺杂剂在所述氧化层上进行第二扩散，所述第二扩散的扩散时间大于所述第一扩散的扩散时间；
对所述氧化层中扩散的所述掺杂剂进行推进。
可选地，所述太阳能电池中所述硅片的片内不均匀度包括5％～7％。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请实施例并不受所描述的动作顺序的限制，因为依据本申请实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定都是本申请实施例所必须的。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本发明各个实施例所述的方法。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (10)

  1. 一种太阳能电池的PN结制备方法，所述方法应用于硅片的织构化表面，其特征在于，所述方法包括：
    采用掺杂剂在所述硅片的所述织构化表面上进行第一扩散，所述掺杂剂与所述硅片的导电类型不同；
    氧化所述第一扩散后的所述织构化表面，获得氧化层；
    采用所述掺杂剂在所述氧化层上进行第二扩散，所述第二扩散的扩散时间大于所述第一扩散的扩散时间；
    对所述氧化层中扩散的所述掺杂剂进行推进。
  2. 根据权利要求1所述的方法，其特征在于，所述第一扩散的扩散时间为小于或等于120秒。
  3. 根据权利要求1所述的方法，其特征在于，所述氧化的氧化时间为小于或等于180秒。
  4. 根据权利要求1所述的方法，其特征在于，所述第二扩散的扩散时间为小于或等于180秒。
  5. 根据权利要求1所述的方法，其特征在于，所述推进的推进温度大于所述第一扩散的扩散温度、所述氧化的氧化温度以及所述第二扩散的扩散温度。
  6. 根据权利要求5所述的方法，其特征在于，所述第一扩散的扩散温度为770℃～800℃；
    所述氧化的氧化温度为770℃～800℃；
    所述第二扩散的扩散温度为770℃～800℃。
  7. 根据权利要求5所述的方法，其特征在于，所述推进的推进温度为840℃～870℃。
  8. 根据权利要求1所述的方法，其特征在于，所述硅片为掺硼硅片，所述掺杂剂为磷源。
  9. 一种太阳能电池，其特征在于，所述太阳能电池包括织构化表面的硅片，所述硅片包括PN结，所述PN结通过以下步骤制备得到：
    采用掺杂剂在所述硅片的所述织构化表面上进行第一扩散，所述掺杂剂与所述硅片的导电类型不同；
    氧化所述第一扩散后的所述织构化表面，获得氧化层；
    采用所述掺杂剂在所述氧化层上进行第二扩散，所述第二扩散的扩散时间大于所述第一扩散的扩散时间；
    对所述氧化层中扩散的所述掺杂剂进行推进。
  10. 根据权利要求9所述的太阳能电池，其特征在于，所述太阳能电池中所述硅片的片内不均匀度低于7％。
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