WO2023070584A1 - 一种功率变换器、电源适配器、电子设备和功率变换方法 - Google Patents

一种功率变换器、电源适配器、电子设备和功率变换方法 Download PDF

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WO2023070584A1
WO2023070584A1 PCT/CN2021/127677 CN2021127677W WO2023070584A1 WO 2023070584 A1 WO2023070584 A1 WO 2023070584A1 CN 2021127677 W CN2021127677 W CN 2021127677W WO 2023070584 A1 WO2023070584 A1 WO 2023070584A1
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Prior art keywords
signal
switch
circuit
voltage
electrode
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PCT/CN2021/127677
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English (en)
French (fr)
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秦俊良
宋树超
于国磊
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华为数字能源技术有限公司
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Priority to CN202180099436.9A priority Critical patent/CN117501606A/zh
Priority to PCT/CN2021/127677 priority patent/WO2023070584A1/zh
Publication of WO2023070584A1 publication Critical patent/WO2023070584A1/zh

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the present application relates to the field of power electronics, in particular to a power converter, a power adapter, electronic equipment and a power conversion method.
  • the buck conversion circuit is one of the common variable circuit topologies, and it is used in various types of power systems because it can reduce the number and volume of passive components.
  • voltage conversion circuits in power systems such as power management systems of electric/hybrid vehicles, photovoltaic power generation systems, communication power supply systems, and data centers often need to use three-level Buck conversion to achieve voltage conversion.
  • the Buck conversion circuit mostly adopts a voltage control method, that is, the driving signal of the switch in the Buck conversion circuit is determined according to the output voltage of the Buck conversion circuit, so as to control the working state of the Buck circuit.
  • the clock cycle of the control device used to generate the switch drive signal is fixed, resulting in a fixed cycle of the drive signal.
  • the application provides a power converter, a power adapter, electronic equipment and a power conversion method, which can timely adjust the working state of the conversion circuit according to the load condition, so that the output voltage can meet the demand of the load.
  • the present application provides a power converter, which includes a first conversion circuit and a control device connected to the first conversion circuit.
  • the control device can control the working state of the first conversion circuit.
  • control device can detect the output voltage of the first conversion circuit to obtain the voltage value of the first voltage; use the voltage value of the first voltage to generate a slope compensation signal; combine the voltage value of the first voltage with Amplifying the error between the voltage values of the reference voltage to obtain an error signal; comparing the slope compensation signal with the error signal to obtain a comparison signal; generating a drive for the first conversion circuit according to the comparison signal Signal.
  • the voltage value of the first voltage can be used for slope compensation to obtain a slope compensation signal.
  • the amplitude of the slope compensation signal changes, resulting in a deviation at the moment when the difference with the error signal is zero.
  • the level inversion time of the comparison signal is changed, and the corresponding time of generating the driving signal is also changed, so as to realize the purpose of adjusting the driving signal in time according to the load condition.
  • control device may include: a detection circuit, an amplification circuit, a slope compensation circuit, a comparison circuit and a signal generation circuit.
  • the input end of the detection circuit is connected to the output end of the first conversion circuit, the output end of the detection circuit is connected to the slope compensation circuit and the amplification circuit, and the detection circuit is used to detect the
  • the first conversion circuit outputs a voltage, obtains the voltage value of the first voltage, and outputs the voltage value of the first voltage to the slope compensation circuit and the amplification circuit;
  • the amplification circuit is connected to the comparison circuit , the amplification circuit is used to amplify the error between the voltage value of the first voltage and the voltage value of the reference voltage to obtain the error signal, and output the error signal to the comparison circuit;
  • the slope The compensation circuit is connected to the comparison circuit, and the slope compensation circuit is used to generate the slope compensation signal according to the voltage value of the first voltage;
  • the comparison circuit is connected to the signal generation circuit, and the comparison circuit uses Comparing the slope compensation signal with the error signal to obtain the comparison signal, and outputting the comparison signal to the signal generation circuit;
  • the signal generation circuit is used to generate the comparison signal according to the comparison
  • the slope compensation circuit can be connected with the detection circuit, and perform slope compensation by using the voltage value of the first voltage value output by the detection circuit to represent the output of the first conversion circuit , the amplitude of the slope compensation signal after slope compensation changes, resulting in a shift in the time when the difference with the error signal is zero, thus changing the level inversion time of the comparison signal, and the time when the corresponding signal generating circuit sends the driving signal Also changes, so as to achieve the purpose of adjusting the driving signal in time according to the load condition.
  • the slope compensation circuit includes: a slope signal compensation module and a control module.
  • the slope signal compensation module is respectively connected with the detection circuit and the control module, and the slope signal generation module is used to generate the slope compensation signal according to the voltage value of the first voltage;
  • the control module is connected with the The comparison circuit is connected, and the control module controls the working state of the slope signal compensation module according to the comparison signal.
  • the slope signal compensation device can use the voltage value of the first voltage to perform slope compensation to obtain a slope compensation signal whose slope and amplitude meet requirements.
  • the slope signal compensation module includes: a first switch S1, a second switch S2, a third switch S3, a first current source I1, a second current source I2, and a first capacitor C1.
  • the first electrode of the first switch S1 is used to connect to the first power supply VCC1, and the second electrode of the first switch S1 is connected to the first end of the first current source I1; the first power supply I1
  • the second terminal of the first capacitor C1 is connected to the first terminal of the first capacitor C1, the first electrode of the second switch S2 and the first electrode of the third switch S3; the second electrode of the second switch S2 is connected to the The second end of the first capacitor C1 is connected; the second electrode of the third switch S3 is connected to the first end of the second current source I2; the second end of the second current source I2 is connected to the first The second end of the capacitor C1 is connected; the second end of the first capacitor C1 is connected to the output end of the detection circuit, and the first end of the first capacitor C1 is connected to the comparison circuit; the first switch The control electrode of S1, the control electrode of the second switch S2 and the control electrode of the third switch S3 are all connected to the first control module.
  • the control module includes: a first RS flip-flop RS1, a second RS flip-flop RS2, a first timer TD1, a second timer TD2, and a first inverter Z1.
  • the first end of the first RS flip-flop RS1 is connected to the comparison circuit, the second end of the first RS flip-flop RS1 is connected to the first end of the first timer TD1, and the second The output end of an RS flip-flop RS1 is connected with the control electrode of the first switch S1, the input end of the first inverter Z1 and the second end of the first timer TD1; the second RS flip-flop The first end of the trigger RS2 is connected to the comparison circuit, the second end of the second RS flip-flop RS2 is connected to the first end of the second timer TD2, and the output end of the second RS flip-flop RS2 It is connected with the control electrode of the second switch S2 and the second terminal of the second timer TD2; the output terminal of the first inverter Z1 is connected with the control electrode of the third switch S3.
  • the first capacitor C1 can be controlled to charge and discharge by controlling the working state of the switch in the slope signal compensation module to generate the slope compensation signal.
  • control module includes: a third RS flip-flop RS3, a fourth RS flip-flop RS4, a fifth RS flip-flop RS5, a third timer TD3, a fourth timer TD4, and a fifth Timer TD5.
  • the first end of the third RS flip-flop RS3 is connected to the comparison circuit
  • the second end of the third RS flip-flop RS3 is connected to the first end of the third timer TD3 and the fourth
  • the first end of the timer TD4 is connected
  • the output end of the third RS flip-flop RS3 is connected with the control electrode of the first switch S1 and the second end of the third timer TD3
  • the fourth RS triggers The first end of the timer RS4 is connected to the second end of the fourth timer TD4, the second end of the fourth RS flip-flop RS4 is connected to the comparison circuit, and the output end of the fourth RS flip-flop RS4 It is connected to the control electrode of the third switch S3;
  • the first end of the fifth RS flip-flop RS5 is connected to the comparison circuit, and the second end of the fifth RS flip-flop RS5 is connected to the fifth timer
  • the first end of TD5 is connected, and the output end of the fifth
  • the first capacitor C1 can be controlled to charge and discharge by controlling the working state of the switch in the slope signal compensation module.
  • the slope signal compensation module includes: a fourth switch S4, a fifth switch S5, a sixth switch S6, a second capacitor C2, a third current source I3, a fourth current source I4 and Adder ⁇ .
  • the first electrode of the fourth switch S4 is used to connect to the second power supply VCC2, and the second electrode of the fourth switch S4 is connected to the first end of the third current source I3; the third current The second end of the source I3 is respectively connected to the first end of the second capacitor C2, the first electrodes of the ninth switches S5 and 9, and the first electrode of the sixth switch S6; the first electrode of the fifth switch S5
  • the second electrode is connected to the second electrode of the sixth switch S6; the second electrode of the sixth switch S6 is connected to the first end of the fourth current source I4; the second end of the fourth current source I4 connected to the second end of the second capacitor C2; the second end of the second capacitor C2 is used to receive the reference voltage, and the first end of the second capacitor C2 is connected to the first input of the adder
  • the second end of the adder is connected to the detection circuit, and the output end of the adder is connected to the comparison circuit; the control electrode of the fourth switch S4, the control electrode of the fifth switch S5 Both electrodes and
  • the adder can be used to superimpose the second voltage to perform slope compensation.
  • the adder includes: a fifth current source I5, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth The switch S12, the thirteenth switch S13, the first resistor R1 and the second resistor R2.
  • the first electrode of the seventh switch S7 is connected to the third power supply VCC3
  • the second electrode of the eleventh switch S11 is connected to the first electrode of the tenth switch S10 and the first electrode of the eleventh switch S11
  • the control electrode of the seventh switch S7 is connected to the control electrode of the twelfth switch 12 and the control electrode of the ninth switch S9
  • the first electrode of the eighth switch S8 is connected to the third power supply VCC3 is connected
  • the second electrode of S12 of the twelfth switch is connected with the first electrode of the twelfth switch S12 and the first electrode of the thirteenth switch S13
  • the first electrode of the ninth switch S9 is connected with
  • the third power supply VCC3 is connected, the second electrode of S13 of the thirteenth switch is connected to the first end of the fifth current source I5; the second end of the fifth current source I5 is connected to the ground wire;
  • the second electrode of the tenth switch S10 is connected to the comparison circuit and the first end of the first resistor
  • the comparison circuit includes: a fourteenth switch S14, a fifteenth switch S15, a sixteenth switch S16, and a first comparator COMP1.
  • the first electrode of the fourteenth switch S14 is connected to the third power supply VCC3, and the second electrode of the fourteenth switch S14 is respectively connected to the first electrode of the fifteenth switch S15 and the sixteenth switch S16.
  • the first electrode is connected, the control electrode of the fourteenth switch S14 is connected to the control electrode of the seventh switch S7; the second electrode of the fifteenth switch S15 is connected to the first input of the first comparator COPM1
  • the control electrode of the fifteenth switch S15 is used to receive the reference signal;
  • the second electrode of the sixteenth switch S16 is connected to the second input end of the first comparator COMP1, the first The control electrode of the sixteenth switch S16 is connected to the amplifying circuit;
  • the first input terminal of the first comparator COMP1 is connected to the second electrode of the tenth switch S10 and the second electrode of the twelfth switch S12 , the second input terminal of the first comparator COMP1 is connected to the second electrode of the eleventh switch S11 and the second electrode of the thirteenth switch S13,
  • the signal generation circuit includes: a frequency division module, a first signal generation module, and a second signal generation module.
  • the input terminal of the frequency division module is connected to the comparison circuit
  • the output terminal of the frequency division module is connected to the first signal generation module and the second signal generation module
  • the frequency division module is used for Perform frequency division processing on the comparison signal to obtain a first frequency division signal and a second frequency division signal, and output the first frequency division signal to the first signal generation module, and convert the second frequency division module output to the second signal generation module
  • the first signal generation module is used to generate a first drive signal according to the first frequency division signal and the voltage conversion ratio of the first conversion circuit
  • the second signal The generation module is used to generate a second driving signal according to the second frequency division signal and the voltage conversion ratio of the first conversion circuit.
  • the driving signal of the first conversion circuit includes the first driving signal and the second driving signal.
  • the first conversion circuit is composed of a plurality of switches, the first driving signal can be generated by the first signal generating module, and the second driving signal can be generated by the second signal generating module.
  • the first signal generation module includes: a first conduction time control module and a first logic module.
  • the first on-time control module is connected to the input terminal of the first conversion circuit, the output terminal of the first conversion circuit and the frequency division module, and the first on-time control module is used for After receiving the first frequency division signal, according to the comparison result of the input voltage of the first conversion circuit and the output voltage of the first conversion circuit, a first on-time control signal is generated;
  • the first logic The modules are respectively connected to the first on-time control module and the frequency division module, and generate the first driving signal according to the first on-time control signal and the first frequency division signal;
  • the second signal generation module includes: a second on-time control module and a second logic module;
  • the second on-time control module is connected to the input terminal of the first conversion circuit, the output terminal of the first conversion circuit and the The frequency division module is connected, and the second conduction time control module is configured to, after receiving the second frequency division signal, according to the input voltage of the first conversion circuit and the output voltage of the first conversion circuit As a result of the comparison, a second on-time control signal is generated; the
  • the first on-time control module can be used to control the duty ratios of the first drive signal and the fourth drive signal
  • the second on-time control module can be used to control the duty ratios of the second drive signal and the third drive signal. empty ratio.
  • the first on-time control module includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventeenth switch S17, a third capacitor C3, and a second comparator COMP2, the eighth RS flip-flop RS8 and the eighth timer TD8.
  • the first end of the third resistor R3 is connected to the output end of the first conversion circuit, and the second end of the third resistor R3 is connected to the first end of the fourth resistor R4;
  • the first end of the four resistance R4 is connected to the first input end of the second comparator COMP2, the second end of the fourth resistance R4 is connected to the ground wire; the first end of the fifth resistance R5 is connected to the ground wire.
  • the input end of the first conversion circuit is connected, the second end of the fifth resistor R5 is connected with the first electrode of the seventeenth switch S17 and the first end of the third capacitor C3; the third The first end of the capacitor C3 is connected to the second input end of the second comparator COMP2, the second end of the third capacitor C3 is connected to the ground line; the second electrode of the seventeenth switch S17 is connected to the The ground wire is connected, the control circuit of the seventeenth switch S17 is connected to the output terminal of the eighth RS flip-flop RS8; the output terminal of the second comparator COMP2 is connected to the first logic module and the The first end of the eighth timer TD8 is connected; the first input end of the eighth RS flip-flop RS8 is connected to the output end of the frequency division module, and the second input end of the eighth RS flip-flop RS8 is connected to the The second terminal of the eighth timer TD8 is connected.
  • the first logic module includes: a ninth RS flip-flop RS9.
  • the first input end of the ninth RS flip-flop RS9 is connected to the output end of the frequency division module, and the second input end of the ninth RS flip-flop RS9 is connected to the first on-time control module , the output end of the ninth RS flip-flop RS9 is used to connect with the first group of switches of the first conversion circuit, and output the first driving signal to the first group of switches.
  • the first group of switches is used to control the charging of the inductor in the first conversion circuit.
  • the first logic module includes a tenth RS flip-flop RS10 and a third inverter Z3.
  • the first input end of the tenth RS flip-flop RS10 is connected to the output end of the frequency division module, and the second input end of the tenth RS flip-flop RS10 is connected to the first on-time control module connection, the output terminal of the tenth RS flip-flop RS10 is used to connect with the first group of switches of the first transformation circuit, and output the first driving signal to the first group of switches; the third inverter The input end of the phaser Z3 is connected to the output end of the tenth RS flip-flop RS10, the output end of the third inverter Z3 is connected to the third group of switches, and outputs the first Three drive signals.
  • the first group of switches, the second group of switches, the third group of switches and the fourth group of switches are connected in series, the first end of the first switch is the first input end of the first conversion circuit, The second end of the fourth group of switches is the second output end of the first conversion circuit.
  • the first driving signal received by the first group of switches, the second driving signal received by the second group of switches, the third driving signal received by the third group of switches and the fourth group of The fourth driving signal received by the switch constitutes the driving signal of the first converting circuit.
  • the conversion circuit control device is also connected to at least one second conversion circuit, the output terminal of each second conversion circuit is connected in parallel with the output terminal of the first conversion circuit, and the signal
  • the generation circuit further includes: a third signal generation module and a fourth signal generation module corresponding to each of the second transformation circuits.
  • the frequency division module is connected to each of the third signal generation modules and each of the fourth signal generation modules, and the frequency division module is also used for performing frequency division processing on the comparison signal to obtain the A third frequency-divided signal corresponding to each of the third signal generating modules and a fourth frequency-divided signal corresponding to each of the fourth signal generating modules; each of the third signal generating modules and the described third signal generating module
  • the frequency division module is connected, and the third signal generation module is used to receive the corresponding third frequency division signal, and generate the fifth driving signal according to the received third frequency division signal and the voltage conversion ratio of the corresponding second conversion circuit signal;
  • the fourth signal generation module is connected to the frequency division module, the fourth signal generation module is used to receive the corresponding fourth frequency division signal, and according to the received fourth frequency division signal and the corresponding first frequency division signal
  • the voltage conversion ratio of the second conversion circuit is used to generate a sixth drive signal; and the fifth drive signal and the sixth drive signal are output to the corresponding second conversion circuit.
  • control device in the scenario where the output terminals of multiple conversion circuits are connected in parallel, the output voltages of the multiple conversion circuits are equal.
  • control device can be used to control the working states of the multiple conversion circuits.
  • control device provided in the embodiment of the present application further includes: a voltage dividing circuit.
  • the input end of the voltage dividing circuit is connected to the output end of the first conversion circuit
  • the output end of the voltage dividing circuit is connected to the input end of the detection circuit
  • the voltage dividing circuit is used to step down the voltage output by the first conversion circuit processing to obtain the first voltage, and output the first voltage to the detection circuit.
  • the processing voltage value of multiple devices in the control device is larger, the processing difficulty and processing cost of the device are higher.
  • the voltage to be detected can be stepped down first, To reduce the difficulty of subsequent data processing of the control device.
  • the present application provides a power conversion method, which can be applied to a power conversion device.
  • the power conversion method includes the following steps: detecting the output voltage of the conversion circuit, and obtaining the voltage value of the first voltage ; using the voltage value of the first voltage to generate a slope compensation signal; according to the error between the voltage value of the first voltage and the voltage value of the reference voltage, an error signal is obtained; combining the slope compensation signal with the error The signals are compared to obtain a comparison signal; according to the comparison signal, a driving signal for the conversion circuit is generated.
  • the slope compensation signal can be generated by using the voltage value of the first voltage representing the load power supply situation, the difference between the slope compensation signal and the error signal is sent when the level state of the error signal changes, and the corresponding generated drive signal The time conversion is sent, so that the state of the conversion circuit is changed, so that the output voltage of the time conversion circuit meets the needs of the load.
  • the generating the slope compensation signal by using the voltage value of the first voltage includes: superimposing the voltage value of the first voltage and the slope signal to obtain the slope compensation signal.
  • the voltage value of the first voltage representing the power supply of the load is superimposed on the slope signal to obtain the slope compensation signal. If the amplitude of the slope compensation signal changes, the difference between the slope compensation signal and the error signal changes. , the sending time of the corresponding driving signal has changed.
  • generating the driving signal of the conversion circuit according to the comparison signal includes: dividing the frequency of the comparison signal to obtain The first frequency division signal and the second frequency division signal; according to the first frequency division signal and the voltage conversion ratio of the conversion circuit, a first drive signal is generated; according to the second frequency division signal and the voltage conversion ratio of the conversion circuit The voltage conversion ratio is used to generate a second driving signal; the driving signal of the conversion circuit includes the first driving signal and the second driving signal.
  • generating the driving signal of the conversion circuit according to the comparison signal includes: dividing the frequency of the comparison signal to obtain The first frequency-division signal and the second frequency-division signal; according to the first frequency-division signal and the voltage conversion ratio of the conversion circuit, generate a first drive signal and a third drive signal; according to the second frequency-division signal and The voltage conversion by the converting circuit generates the second driving signal and the fourth driving signal.
  • the present application provides a power adapter, which includes a casing, a connection port, and the power converter provided in any one of the above-mentioned first aspects of the present application.
  • the power adapter can be connected between the electronic device and the power supply, and the power adapter can convert the voltage output by the power supply into the charging voltage of the electronic device, and output the charging voltage to the electronic device to charge the electronic device.
  • the present application provides an electronic device, which includes: a battery, a load, and the power converter provided in any one of the above-mentioned first aspects of the present application.
  • the power converter is connected to the battery, and the power converter is used to convert the output voltage of the battery to obtain a target voltage, and output the target voltage to the load.
  • FIG. 1 is a schematic structural diagram of a three-level Buck circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of fluctuations in driving signals of a three-level Buck circuit provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a three-level Buck circuit control device provided in an embodiment of the present application.
  • FIG. 4 is a first structural schematic diagram of a power converter provided by an embodiment of the present application.
  • FIG. 5 is a second structural schematic diagram of a power converter provided by an embodiment of the present application.
  • FIG. 6 is a structural schematic diagram 1 of a slope signal compensation module provided by an embodiment of the present application.
  • FIG. 7 is a first structural schematic diagram of a control module provided by an embodiment of the present application.
  • Fig. 8 is a structural schematic diagram II of a control module provided by the embodiment of the present application.
  • FIG. 9 is a second structural schematic diagram of a slope signal compensation module provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram III of a control module provided in the embodiment of the present application.
  • Fig. 11 is a structural schematic diagram 4 of a control module provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an adder provided in an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a comparison circuit provided in an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a signal generating circuit provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a frequency division module provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of an output waveform of a two-frequency divider provided in an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a first signal generating module provided in an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a second signal generation module provided by an embodiment of the present application.
  • Fig. 19 is a schematic structural diagram III of a power converter provided by an embodiment of the present application.
  • FIG. 20 is a schematic diagram of a comparison signal waveform provided by an embodiment of the present application.
  • Fig. 21 is a structural schematic diagram 4 of a power converter provided by the embodiment of the present application.
  • Fig. 22 is a schematic flowchart of a power conversion method provided by an embodiment of the present application.
  • connection in the embodiments of the present application refers to electrical connection, and the connection of two electrical components may be a direct or indirect connection between two electrical components.
  • connection between A and B can be either direct connection between A and B, or indirect connection between A and B through one or more other electrical components, such as A and B connection, or A and C direct connection, C and B are directly connected, and A and B are connected through C.
  • the "voltage conversion ratio” in the embodiment of the present application refers to the ratio between the input voltage and the output voltage of the voltage conversion circuit. If the voltage conversion circuit performs step-down conversion, the output voltage of the voltage conversion circuit is less than the input voltage. voltage, that is, the voltage conversion ratio of the voltage conversion circuit is less than 1. If the voltage conversion circuit performs boost conversion, the output voltage of the voltage conversion circuit is greater than the input voltage, that is, the voltage conversion ratio of the voltage conversion circuit is greater than 1.
  • the switch in the embodiment of the present application may be a relay, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate double One or more of various types of switching devices such as insulated gate bipolar transistor (IGBT), gallium nitride field effect transistor (GaN), silicon carbide (SiC) power transistor, etc. No longer list them one by one.
  • Each switch device may include a first electrode, a second electrode and a control electrode, wherein the control electrode is used to control the switch device to be turned on or off.
  • the control electrode of the switching device is the gate
  • the first electrode of the switching device may be the source of the switching device
  • the second electrode may be the drain of the switching device
  • the first electrode may be the drain of the switching device pole
  • the second electrode may be the source of the switching device.
  • power converters are installed in most electronic devices or connected to power converters.
  • the power converters in electronic devices can be used to realize voltage (or current) conversion inside electronic devices to meet the needs of electronic devices. voltage or current requirements.
  • DC-DC (DC/DC) voltage conversion circuits DC-AC (DC/AC) voltage conversion circuits, AC-DC (AC/DC) voltage conversion devices, etc.
  • the power converter connected to the electronic equipment is used to realize the voltage (or current) conversion of the power supply to meet the demand of the electronic equipment for the power supply voltage or the power supply current.
  • the voltage conversion circuit may be an adapter.
  • electronic devices can be smart phones, tablet computers, smart watches and other electronic devices, and can support cutting-edge technologies such as 5G and folding screens.
  • a power converter with any function can be realized by using a step-up chopper Boost circuit and a step-down conversion Buck circuit.
  • the voltage conversion circuit may be called a step-down conversion circuit.
  • the Buck circuit is a step-down voltage conversion circuit topology. Since the transmission power of electronic equipment is gradually increasing, the Buck circuit is widely used because it can realize high-power conversion.
  • the Buck circuit is mainly divided into a two-level Buck circuit and a three-level Buck circuit. The working principle of the Buck circuit will be described below by taking the three-level Buck circuit as an example.
  • the three-level Bcuk circuit mainly includes: the first group of switches Q1, the second group of switches Q2, the third group of switches Q3, the fourth group of switches Q4, the output inductor Lm, the flying capacitor Cf and the output capacitor cl.
  • the first electrode of the first group of switches Q1 constitutes the first port of the input end of the three-level Buck circuit
  • the second electrode of the first group of switches Q1 is connected to the first electrode of the second group of switches Q2
  • the second electrode of the second group of switches Q2 The first electrode is connected to the first end of the flying capacitor Cf
  • the second electrode of the second group of switches Q2 is connected to the first electrode of the third group of switches Q3
  • the first electrode of the third group of switches Q3 is connected to the first electrode of the flying capacitor Cf
  • the second end is connected, the second electrode of the third group switch Q3 is connected with the first electrode of the fourth group switch Q4;
  • the second electrode of the fourth group switch Q4 constitutes the second port of the input end of the three-level Buck circuit
  • the output inductance Lm The first end of the output inductor Lm is connected to the second electrode of the second group switch Q2, the second end of the output inductor Lm is connected to the first end of the output capacitor CL, and the second end
  • the first port of the input end may be the endpoint of the three-level Buck circuit receiving the high potential
  • the second port of the input end may be the endpoint of the three-level Buck circuit receiving the low level
  • the first port and the second port of the input end constitute three The input terminal of the level Buck circuit.
  • the first port of the output terminal can be the endpoint of the three-level Buck circuit outputting high potential
  • the second port of the output terminal can be the port of the three-level Buck circuit outputting low level
  • the first port and the second port of the output terminal form a three-level The output of the Buck circuit.
  • the duty cycle of the driving signal from the first group of switches Q1 to the fourth group of switches Q4 in the three-level Buck circuit can be greater than 0.5, and the duty cycle of the driving signal can also be greater than 0.5.
  • the duty cycle of the driving signal is less than 0.5 and when the driving signal is greater than 0.5, the three-level Buck circuit works differently.
  • the working process of the three-level Buck will be described in detail by taking the duty ratio of the switch driving signal less than 0.5 as an example.
  • the working process of the three-level Buck circuit mainly includes the following four stages.
  • Phase 1 Control the first group of switches Q1 and the third group of switches Q3 to conduct, and the input voltage Vin output by the input power supply charges the flying capacitor Cf and the output inductor Lm through the first group of switches Q1 and the third group of switches Q3, and the flying capacitor
  • the capacitor Cf and the output inductor Lm store energy, and the current value of the output current Lm gradually increases.
  • Stage 2 When it is determined that the output voltage Vout of the three-level Buck circuit reaches the target value, the first group of switches Q1 and the third group of switches Q3 are controlled to be cut off, and the output inductance Lm can pass through the third group of switches Q3 and the fourth group of switches Q4.
  • the parasitic diode performs freewheeling, and as the electric energy stored in the output inductor Lm decreases, the current value flowing through the output inductor Lm gradually decreases.
  • Stage 3 After it is determined that the output inductor Lm is fully discharged, the second group of switches Q2 and the fourth group of switches Q4 are controlled to be turned on. At this time, the flying capacitor Cf charges the output inductor Lm through the second group of switches Q2 and the fourth group of switches Q4. The output inductor Lm stores energy.
  • Stage 4 After it is determined that the output inductor Lm is fully discharged, the second group of switches Q2 and the fourth group of switches Q4 are controlled to be turned on. At this time, the flying capacitor Cf charges the output inductor Lm through the second group of switches Q2 and the fourth group of switches Q4. The output inductor Lm stores energy.
  • the second group of switches Q2 and the fourth group of switches Q4 are controlled to be cut off, and the output inductance Lm can pass through the third group of switches Q3 and the fourth group of switches Q4.
  • the parasitic diode performs freewheeling, and as the electric energy stored in the output inductor Lm gradually decreases, the current flowing through the output inductor Lm gradually decreases.
  • the change of the voltage value of the output voltage Vout lags behind the change of the current value of the output current Lm. That is, when the three-level Buck circuit is in the second stage, and the current value of the output current Lm reaches the allowable minimum value, the control switch is switched so that the three-level Buck circuit enters the third stage, and the voltage value of the output voltage Vout continues to drop State, and after a certain period of time reaches the allowable minimum value and then gradually rises, it is necessary to switch the switch state at the target value of the output voltage output when the current value of the output current Lm is at the lowest value.
  • one cycle of the driving signal of the four switches can control the three-level Buck circuit to repeatedly execute the above four stages once.
  • the current waveform of the output inductor Lm can be referred to as shown in FIG. 2 .
  • the three-level Buck circuit can be controlled to enter the corresponding stage by controlling the turn-on time of the four switches in the circuit, so that the three-level Buck circuit enters different stages.
  • the current value of the output current Lm of the flat Buck circuit in different stages is different, and the output voltage of the corresponding time-delayed three-level Buck circuit is also different.
  • control electrodes of the first group of switches Q1, the control electrodes of the second group of switches Q2, the control electrodes of the third group of switches Q3 and the control electrodes of the fourth group of switches Q4 are all connected to the control device of the three-level Buck circuit , the control device can provide suitable driving signals for the control circuits of the four switches, and the switches can adjust the working state under the action of the driving signals.
  • FIG. 3 it is a schematic structural diagram of a three-level Buck circuit control device.
  • the control device detects the voltage at the output terminal of the three-level Buck circuit, and steps down the voltage at the output terminal through resistors R1 and R2 to obtain the voltage to be detected, and the operating amplifier U1 converts the voltage between the voltage to be detected and the reference voltage The error is amplified to obtain the error voltage.
  • Comparators U2 and U3 compare the error voltage output by U1 with the ramp signal output by the ramp generator, and output the comparison result to the RS flip-flop connected to the back end, and the RS flip-flop gives the corresponding The switch provides the drive signal.
  • the reference voltage may be a voltage value obtained by stepping down the target voltage through the resistors R1 and R2.
  • the target voltage may be the rated working voltage of the electrical equipment connected to the rear end of the three-level Buck circuit.
  • the embodiment of the present application provides a power converter, a power adapter, an electronic device and a power conversion method.
  • the power converter may include a first conversion circuit and a control device connected to the first conversion circuit.
  • the device can timely adjust the driving signal provided to the first converter circuit according to the load condition, so that the voltage output by the first converter circuit meets the requirement of the load.
  • the three-level Buck circuit shown in FIG. 1 is a possible structural example of the first conversion circuit.
  • the first conversion circuit has many possible implementation structures, such as a two-level Buck circuit, which are not listed in this application, but all of these step-down Buck circuits are applicable to this application.
  • the power converter may include a first conversion circuit 200 and a control device 400 connected to the first conversion circuit.
  • the control device 400 can detect the output voltage of the first conversion circuit 200 to obtain the voltage value of the first voltage; use the voltage value of the first voltage to generate a slope compensation signal; The error between voltage values of the reference voltage is obtained to obtain an error signal; the slope compensation signal is compared with the error signal to obtain a comparison signal; according to the comparison signal, a driving signal for the first conversion circuit 200 is generated.
  • control device 400 may include: a detection circuit 401 , an amplification circuit 402 , a slope compensation circuit 403 , a comparison circuit 404 and a signal generation circuit 405 .
  • the input end of the detection circuit 401 is connected to the output end of the first transformation circuit, and the output end of the detection circuit 401 is connected to the slope compensation circuit 403 and the amplification circuit 402; the amplification circuit 402 is connected to the
  • the comparison circuit 404 is connected; the slope compensation circuit 403 is connected with the comparison circuit 404; the comparison circuit 404 is connected with the signal generation circuit 405; connected and provide driving signals for the switches in the first conversion circuit 200 .
  • the detection circuit 401 can detect the voltage output by the first conversion circuit 200, obtain the voltage value of the first voltage, and output the voltage value of the first voltage to the slope compensation circuit 403 and the amplifying circuit 402; the amplifying circuit 402 can amplify the error between the voltage value of the first voltage and the voltage value of the reference voltage to obtain an error signal, and output the error signal to the comparison circuit 404;
  • the slope compensation circuit 403 can generate a slope compensation signal according to the voltage value of the first voltage, and output the slope compensation signal to the comparison circuit 404;
  • the comparison circuit 404 can compare the slope compensation signal and the The error signals are compared to obtain a comparison signal, and the comparison signal is output to the signal generation circuit 405; the signal generation circuit 405 can generate a driving signal for the first conversion circuit 200 according to the comparison signal.
  • the control device 400 may further include a voltage divider circuit.
  • the voltage dividing branch may be composed of a plurality of voltage dividing resistors connected in series.
  • the input end of the voltage divider circuit is connected to the output end of the first conversion circuit 200
  • the output end of the voltage divider circuit is connected to the input end of the detection circuit 401
  • the voltage divider circuit can reduce the output voltage of the first conversion circuit 200. voltage processing to obtain the first voltage, and output the first voltage to the detection circuit.
  • control device 400 may be fixed on the first conversion circuit 200 .
  • control device 400 can also be set in a flexible and detachable form, that is, the first conversion circuit 200 is provided with a fixed interface to realize the connection between the control device 400 and the first conversion circuit 200.
  • the control device 400 can be regarded as a device independent of the first conversion circuit 200 .
  • control device 400 can adjust the working state of the switch by providing a corresponding driving signal for the switch in the first conversion circuit 200 , thereby controlling the voltage value of the output voltage of the first conversion circuit 200 .
  • the driving signal generating circuit 405 mainly generates the driving signal through the comparison signal, and the generation of the comparison signal is mainly through the error signal and the slope compensation signal.
  • the voltage value of the first voltage can be used for slope compensation, and the amplitude of the slope compensation signal after slope compensation changes, resulting in the slope compensation signal and the error signal
  • the time when the difference is zero is shifted, thereby changing the level inversion time of the comparison signal, and the transmission time of the driving signal generated by the corresponding signal generation circuit 405 is also changed, so as to realize timely response to the change of the output voltage, And adjust the driving signal accordingly.
  • control device 400 may be connected to the input power source connected to the input terminal of the first conversion circuit 200 , and the input power source may provide power for the control device 400 .
  • a DC converter may also be connected between the input power supply and the control device 400.
  • the DC converter performs voltage conversion processing on the voltage output by the input power supply, so as to output a power supply voltage available to the control device 400 .
  • the specific structures of the detection circuit 401 , the amplification circuit 402 , the slope compensation circuit 403 , the comparison circuit 404 and the signal generation circuit 405 in the control device 400 will be introduced.
  • the input end of detection circuit 401 can be connected with the output end of voltage divider circuit, and the output end of detection circuit 401 is connected with amplifying circuit 402 and slope compensation circuit 403 respectively, and the output end of voltage divider circuit constitutes the point to be detected, and the point output to be detected is The voltage value is output to the slope compensation circuit 403 and the amplification circuit 402 .
  • the detection circuit 401 may be a data transmission line, which directly outputs the voltage value of the point to be detected to the connected device.
  • the above description of the structure of the detection circuit 401 is only an example. In actual use, the detection circuit 401 provided in the present application may also include other structures, such as voltage sensors, which are not introduced here.
  • the input end of the amplifying circuit 402 is connected to the detection circuit 401, the output end of the amplifying circuit 402 is connected to the input end of the comparison circuit 404, and the amplifying circuit 402 can compare the voltage value of the first voltage output by the detection circuit 401 with the voltage of the reference voltage The error between the values is amplified to obtain an error signal, and the error signal is output to the comparison circuit 404 .
  • the amplifying circuit 402 may include an operational amplifier, the non-inverting input terminal of the operational amplifier receives a reference voltage, the inverting input terminal of the operational amplifier is connected to the detection circuit 401 for receiving the second voltage output by the detection circuit 401, and the operational amplifier The output terminal of is connected to the comparison circuit 404 and the slope compensation circuit 403 for outputting an error signal.
  • the slope compensation circuit 403 is respectively connected to the output end of the detection circuit 401 and the input end of the comparison circuit 404, and the slope compensation circuit 403 can compensate the slope signal according to the voltage value of the first voltage output by the detection circuit 301 , to obtain a slope compensation signal, and output the slope compensation signal to the comparison circuit 404 .
  • the slope compensation circuit 403 includes: a slope signal compensation module 4031 and a control module 4032 .
  • the slope signal compensation module 4031 is respectively connected to the output terminal of the detection circuit 401 and the control module, and the slope signal compensation module 4031 is used to generate the slope compensation signal according to the second voltage;
  • the The control module 4032 is connected to the comparison circuit 404, and the control module 4032 controls the working state of the slope signal compensation module 4032 according to the comparison signal.
  • the slope signal compensation module in the embodiment of the present application has two circuit structures, and the slope compensation processes under the two circuit structures in the embodiment are introduced respectively below.
  • the slope signal compensation module 4031 includes: a first switch S1, a second switch S2, a third switch S3, a first current source I1, a second current source I2 and a first capacitor C1.
  • the first electrode of the first switch S1 is used to connect to the first power supply VCC1, and the second electrode of the first switch S1 is connected to the first end of the first current source I1.
  • the second end of the first power supply I1 is connected to the first end of the first capacitor C1, the first electrode of the second switch S2 and the first electrode of the third switch S3; the second switch S2
  • the second electrode of the second switch S3 is connected to the second end of the first capacitor C1;
  • the second electrode of the third switch S3 is connected to the first end of the second current source I2;
  • the first end of the second current source I2 The two terminals are connected to the second end of the first capacitor C1; the second end of the first capacitor C1 is connected to the output end of the detection circuit 401, and the first end of the first capacitor C1 is connected to the comparison
  • the circuit 404 is connected; the control electrode of the first switch S1, the control electrode of the second switch S2 and the control electrode of the third switch S3 are all connected to the control module.
  • a voltage follower is connected between the second end of the first capacitor C1 and the detection circuit.
  • the first voltage can be controlled by controlling the charging and discharging speed of the first capacitor C1.
  • the output voltage of the conversion circuit 200 reaches the target value, the sum of the discharge voltage value of the first capacitor C1 and the target value is equal to the magnitude of the error signal, then the magnitude of the slope compensation signal output by the first capacitor C1 is equal to the magnitude of the error signal
  • the comparison circuit 404 outputs a comparison signal, and generates a corresponding driving signal to control the working state of the first conversion circuit 200 .
  • the period of the slope compensation signal may be consistent with the period of the driving signal of the switches in the first converting circuit 200 .
  • control electrode of the first switch S1 the control electrode of the second switch S2 and the control electrode of the third switch S3 are all connected to the control module 4032, and the control module 4032 controls the above three switches In the working state, the slope signal compensation module 4031 is controlled to generate a slope compensation signal.
  • the slope signal compensation module outputs the slope compensation signal mainly through charging and discharging of the first capacitor C1.
  • the charging and discharging state of the first capacitor C1 can be realized by adjusting the working state of the switch in the slope signal compensation module.
  • control module 4032 can control the slope signal compensation module 4031 to perform slope compensation by adjusting the working states of multiple switches to obtain a slope compensation signal.
  • control module 4032 The specific structure of the control module 4032 and the process of controlling the slope signal compensation module 4031 to perform slope compensation will be described in detail below with reference to FIG. 6 .
  • FIG. 7 it is a schematic structural diagram of a control module 4032 provided in the embodiment of the present application.
  • the control module 4032 includes: a first RS flip-flop RS1, a second RS flip-flop RS2, a first timer TD1, a second timer TD2 and a first inverter Z1.
  • the connection relationship of the components in the control module 4032 shown in FIG. 7 may be: the first end of the first RS flip-flop RS1 is connected to the output end of the comparison circuit 404, and the first end of the first RS flip-flop RS1 The two terminals are connected to the first terminal of the first timer TD1, the output terminal of the first RS flip-flop RS1 is connected to the control electrode of the first switch S1, the input terminal of the first inverter Z1 and The second end of the first timer TD1 is connected; the first end of the second RS flip-flop RS2 is connected to the comparison circuit, and the second end of the second RS flip-flop RS2 is connected to the second timing connected to the first end of TD2, the output end of the second RS flip-flop RS2 is connected to the control electrode of the second switch S2 and the second end of the second timer TD2; the first inverter Z1 The output terminal is connected to the control electrode of the third switch S3.
  • both the setting terminal S of the flip-flop RS1 and the setting terminal S of the flip-flop RS2 receive High-level signal, at this time, the output terminals of trigger RS1 and trigger RS2 output a high-level signal, at this time, the switch S1 and switch S2 will be turned on because the control electrode receives the high-level signal, at this time, the first capacitor C1 passes Switch S2 discharges. Simultaneously, the timer TD1 and the timer TD2 start counting.
  • the duration for which the comparison circuit 404 outputs a high-level signal is shorter, and the setting terminal of the flip-flop RS1
  • the signal received by S and the setting terminal S of flip-flop RS2 will quickly change from a high level state to a low level state. Since the timing time of timer TD1 and timer TD2 has not arrived, TD1 and TD2 output low level signal, the states of the output terminals of the flip-flop RS1 and the flip-flop RS1 remain unchanged, and the switch S1 and the switch S2 maintain a conduction state.
  • the output of the trigger RS2 outputs a low-level signal, and the switch S2 is disconnected because the control electrode receives the low-level signal, the switch S1 remains on, and the current source I1 charges the first capacitor C1 with a constant current through the switch S1.
  • the timing time of the timer TD1 arrives, TD1 outputs a high level signal, and the signal output by the output terminal of the trigger RS1 turns from high level to Low level, the switch S1 is turned off because the control electrode receives a low level signal, the output terminal of Z1 outputs a high level signal, and the first capacitor C1 performs constant current discharge through the switch S3 and the current source I2.
  • the comparison circuit 404 can compare the output voltage of the first conversion circuit 200 A corresponding driving signal is generated at a time corresponding to the voltage being the target value, so that the output voltage of the first conversion circuit 200 meets the voltage requirement of the load.
  • the ramp signal is generated by controlling the first capacitor C1 to charge and discharge, and the ramp signal generated by the first capacitor C1 is compensated by superimposing the voltage value of the first voltage on the second end of the first capacitor C1 to obtain slope compensation Signal.
  • FIG. 8 it is a schematic structural diagram of another control module 4032 provided in the embodiment of the present application.
  • the control module 4032 includes: a third RS flip-flop RS3 , a fourth RS flip-flop RS4 , a fifth RS flip-flop RS5 , a third timer TD3 , a fourth timer TD4 and a fifth timer TD5 .
  • connection relationship of the devices in the control module 4031 shown in Figure 8 may be: the first end of the third RS flip-flop RS3 is connected to the output end of the comparison circuit, the second end of the third RS flip-flop RS3 terminal is connected with the first terminal of the third timer TD3 and the first terminal of the fourth timer TD4, the output terminal of the third RS flip-flop RS3 is connected with the control electrode of the first switch S1 and the The second end of the third timer TD3 is connected; the first end of the fourth RS flip-flop RS4 is connected to the second end of the fourth timer TD4, and the second end of the fourth RS flip-flop RS4 connected to the comparison circuit, the output end of the fourth RS flip-flop RS4 is connected to the control electrode of the third switch S3; the first end of the fifth RS flip-flop RS5 is connected to the comparison circuit, so The second end of the fifth RS flip-flop RS5 is connected to the first end of the fifth timer TD5, and the
  • control module 4032 When the above-mentioned control module 4032 is used to control the working states of multiple switches in the slope signal compensation module 4031, if the comparison circuit 404 outputs a high level signal, both the setting terminal S of the flip-flop RS3 and the setting terminal S of the flip-flop RS5 receive High-level signal, at this time, the output terminals of trigger RS3 and trigger RS5 output a high-level signal, the switch S1 and switch S2 will be turned on because the control electrode receives the high-level signal, and the capacitor C1 is discharged through the switch S2 at this time .
  • timer TD3, timer TD4 and timer TD5 start counting, because the signals received by the two input ports of comparison circuit 404 are always in a changing state, the duration of the output level signal of comparison circuit 404 is shorter, and the setting of RS3 is started.
  • the signal received by the bit terminal S and the set terminal S of the flip-flop RS5 will quickly change from a high level to a low level state.
  • timer TD3 Since the timing time of the timer TD3, timer TD4 and timer TD5 has not arrived, the timer TD3 , Timer TD4 and timer TD5 output low-level signals, at this time switch S1 and switch S2 maintain the conduction state, switch S3 is turned off, when the capacitor C1 is fully discharged, the timing time of TD5 arrives, and trigger RS5 outputs a low-level signal at this time When the signal is flat, the switch S2 is cut off, the switch S1 remains on, and the current source I1 charges the capacitor C1 with a constant current through the switch S1. When the capacitor C1 is fully charged, the timer TD3 and timer TD4 have reached the timing, and the output of TD3 is high.
  • Level signal the signal output by the output terminal of RS3 flip-flop turns from high level to low level, switch S1 is cut off because the control electrode receives a low level signal, RS4 outputs a high level signal, and the control terminal of switch S3 is subjected to high level
  • the level signal is turned on, and at this time, the capacitor C1 is discharged with a constant current through the switch S3 and the current source I2.
  • the timing duration of TD4 is higher than that of TD3.
  • TD3 When the timing duration of TD3 is reached, TD3 outputs a high-level signal, and the signal output from the output terminal of the RS3 flip-flop turns from a high-level state to Low-level filling, switch S1 is cut off due to the control electrode receiving the signal, at this time the first capacitor C1 maintains the current state, when the timing time of TD4 is reached, RS4 outputs a high-level signal, and the control terminal of the switch S3 is closed due to receiving the high-level signal is turned on, at this time, the capacitor C1 is discharged with a constant current through the switch S3 and the current source I2.
  • the first capacitor C1 The amplitude of the slope compensation signal output by the first end will also change, and the corresponding time point when the difference between the slope compensation signal and the error signal is zero is shifted, so as to respond quickly to the change of the output voltage.
  • control module provided by this application may also include other structures.
  • a delayer may be used to replace the timer in the control module. I will not introduce them one by one.
  • the slope signal compensation module 4031 includes: a fourth switch S4, a fifth switch S5, a sixth switch S6, a second capacitor C2, a third current source I3, a fourth current source I4 and an adder ⁇ .
  • the second electrode of the fifth switch S5 is connected to the second electrode of the sixth switch S6; the second electrode of the sixth switch S6 is connected to the fourth current source I4 connected to the first end of the fourth current source I4; the second end of the fourth current source I4 is connected to the second end of the second capacitor C2; the second end of the second capacitor C2 is used to receive the reference voltage, the The first end of the second capacitor C2 is connected to the first input end of the adder ⁇ ; the second end of the adder ⁇ is connected to the detection circuit, and the output end of the adder ⁇ is connected to the comparison circuit Connection; the control electrode of the fourth switch S4, the control electrode of the fifth switch S5 and the control electrode of the sixth switch S6 are all connected to the first control module.
  • the amplitude of the slope compensation signal can be adjusted by controlling the charging and discharging time of the second capacitor C2. Since the first input end of the adder ⁇ is connected to the first end of the second capacitor C2, receiving the first The second input terminal of the adder ⁇ is connected to the detection circuit 401 for the slope signal output by the second capacitor C2, and receives the second voltage output by the detection circuit 401. The adder ⁇ superimposes the second signal and the slope signal to output a slope compensation signal.
  • control electrode of the fourth switch S4, the control electrode of the fifth switch S5 and the control electrode of the sixth switch S6 are all connected to the control module 4032, and the control module 4032 controls the working states of the above three switches,
  • the slope signal compensation module 4031 is controlled to generate a slope compensation signal.
  • control module 4032 The specific structure of the control module 4032 will be described in detail below with reference to FIG. 9 .
  • FIG. 10 it is a schematic structural diagram of a control module 4032 provided in the embodiment of the present application.
  • the control module includes: a first RS flip-flop RS1, a second RS flip-flop RS2, a first timer TD1, a second timer TD2 and a first inverter Z1.
  • connection relationship of the components in the control module shown in Figure 10 may be: the first end of the first RS flip-flop RS1 is connected to the output end of the comparison circuit, and the second end of the first RS flip-flop RS1 connected to the first terminal of the first timer TD1, the output terminal of the first RS flip-flop RS1 is connected to the control electrode of the fourth switch S4, the input terminal of the first inverter Z1 and the The second end of the first timer TD1 is connected; the first end of the second RS flip-flop RS2 is connected to the comparison circuit, and the second end of the second RS flip-flop RS2 is connected to the second timer TD2 The first terminal of the second RS flip-flop RS2 is connected to the control electrode of the first switch S1 and the second terminal of the second timer TD2; the output terminal of the first inverter Z1 It is connected with the control electrode of the second switch S2.
  • the control circuit includes: a third RS flip-flop RS3 , a fourth RS flip-flop RS4 , a fifth RS flip-flop RS5 , a third timer TD3 , a fourth timer TD4 and a fifth timer TD5 .
  • the connection relationship between the devices in the control module shown in Figure 11 may be: the first end of the third RS flip-flop RS3 is connected to the output end of the comparison circuit, and the second end of the third RS flip-flop RS3 It is connected with the first terminal of the third timer TD3 and the first terminal of the fourth timer TD4, and the output terminal of the third RS flip-flop RS3 is connected with the control electrode of the fourth switch S4 and the The second end of the third timer TD3 is connected; the first end of the fourth RS flip-flop RS4 is connected to the second end of the fourth timer TD4, and the second end of the fourth RS flip-flop RS4 is connected to The comparison circuit is connected, the output end of the fourth RS flip-flop RS4 is connected to the control electrode of the second switch S2; the first end of the fifth RS flip-flop RS5 is connected to the comparison circuit, the The second end of the fifth RS flip-flop RS5 is connected to the first end of the fifth timer
  • the slope compensation circuit shown in FIG. 9 performs slope compensation mainly by superimposing the second voltage output by the detection circuit 401 by the adder ⁇ .
  • the adder ⁇ may specifically include: a first resistor R1, a second resistor R2, a fifth current source I5, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch The switch S11, the twelfth switch S12, and the thirteenth switch S13.
  • the first electrode of the seventh switch S7 is connected to the third power supply VCC3, the second electrode of the eleventh switch S11 is connected to the first electrode of the tenth switch S10 and The first electrode of the eleventh switch S11 is connected, the control electrode of the seventh switch S7 is connected with the control electrode of the eighth switch S8 and the control electrode of the ninth switch S9;
  • One electrode is connected to the third power supply VCC3, the second electrode of S12 of the twelfth switch is connected to the first electrode of the twelfth switch S12 and the first electrode of the thirteenth switch S13;
  • the ninth switch The first electrode of S9 is connected to the third power supply VCC3, the second electrode of S13 of the thirteenth switch is connected to the first end of the fifth current source I5; the second end of the fifth current source I5 is connected to ground connection;
  • the second electrode of the tenth switch S10 is connected to the comparison circuit and the first end of the first resistor R1, and the control electrode of the tenth switch S10 is connected to
  • the specific implementation is that a reference voltage is superimposed on the second terminal of the second capacitor C2 of the slope signal compensation module, and the switch S15 receives the reference voltage to eliminate the reference voltage superimposed in the slope compensation signal output by the second capacitor C2 from the comparison signal output by the comparison circuit The influence of time, and use the switch S16 to superimpose the voltage value of the first voltage output by the detection circuit 401 .
  • the comparison circuit 404 is respectively connected with the amplifier circuit 402, the slope compensation circuit 403 and the signal generation circuit 405, and the comparison circuit 404 can compare the error signal output by the amplifier circuit 402 with the slope compensation signal output by the slope compensation circuit 403, and use the comparison result as The comparison signal is output to the signal generating circuit 405 .
  • the comparison circuit 404 may directly use a comparator.
  • the inverting input terminal of the comparator may be connected to the first terminal of the first capacitor C1 to receive the slope compensation signal output by the first capacitor C1
  • the non-inverting input terminal of the comparator may be connected to the output terminal of the amplifier circuit 302 , to receive the error signal output by the amplifying circuit 302 , and the output end of the comparator is connected to the signal generating circuit 405 .
  • the comparator compares the slope compensation signal received at the input end with the error signal, and outputs the comparison result to the signal generating circuit 405 .
  • slope signal compensation module 4031 uses the slope signal compensation module shown in FIG. switch S16 and the first comparator COMP1.
  • the first electrode of the fourteenth switch S14 is connected to the third power supply VCC3, and the second electrode of the fourteenth switch S14 is respectively connected to the first electrode of the fifteenth switch S15. connected to the first electrode of the sixteenth switch S16, and the control electrode of the fourteenth switch S14 is connected to the control electrode of the seventh switch S7;
  • the second electrode of the fifteenth switch S15 is connected to the first input terminal of the first comparator COPM1, and the control electrode of the fifteenth switch S15 is used to receive the reference signal; the sixteenth switch The second electrode of S16 is connected to the second input terminal of the first comparator COMP1, and the control electrode of the sixteenth switch S16 is connected to the amplification circuit; the first input terminal of the first comparator COMP1 is connected to the first input terminal of the first comparator COMP1.
  • the second electrode of the tenth switch S10 is connected to the second electrode of the twelfth switch S12, and the second input terminal of the first comparator COMP1 is connected to the second electrode of the eleventh switch S11 and the second electrode of the twelfth switch S12.
  • the second electrode of the thirteenth switch S13 is connected, and the output terminal of the first comparator COMP1 is connected with the signal generating circuit.
  • the difference between the first voltage and the reference voltage is superimposed in the switch S16 and the switch S17, and the control electrode of the switch S19 can be used to receive the reference voltage for compensation voltage compensation, so as to satisfy Ensure that the signal inversion moment of the comparator COMP1 meets the requirements of the output voltage.
  • the signal generation circuit 405 is connected to the comparison circuit 404 , and the signal generation circuit 405 is also connected to the switch of the first transformation circuit 200 , and the signal generation circuit 405 can generate a driving signal of the first transformation circuit 200 according to the comparison signal output by the comparison circuit 404 .
  • the signal generation circuit 405 may include: a frequency division module 4051 , a first signal generation module 4052 and a second signal generation module 4053 .
  • the input end of the frequency division module 4051 is connected to the comparison circuit 404, and the output end of the frequency division module 4051 is connected to the first signal generation module 4052 and the second signal generation module 4052.
  • the generation module 4053 is connected, and the frequency division module 4051 is used for performing frequency division processing on the comparison signal output by the comparison circuit 404 to obtain a first frequency division signal and a second frequency division signal, and divide the first frequency division signal output to the first signal generation module 4052, and output the second frequency division module to the second signal generation module 4053;
  • the first signal generation module 4052 can be based on the first frequency division signal and the
  • the voltage conversion ratio of the first conversion circuit 200 generates a first driving signal;
  • the second signal generating module 4053 can generate a second driving signal according to the second frequency division signal and the voltage conversion ratio of the first conversion circuit 200 Signal.
  • the first conversion circuit 200 is a two-level conversion circuit
  • the first conversion circuit 200 includes a first group of switches and a second group of switches, wherein when the first group of switches is closed, the input power An output inductance in the first conversion circuit may be charged.
  • the driving signal of the first conversion circuit 200 includes a first driving signal and a second driving signal.
  • the first signal generation module 4052 may be connected to the first group of switches, and output the first driving signal to the first group of switches.
  • the second signal generating module 4053 may be connected to the second group of switches, and output the second driving signal to the second group of switches.
  • the first conversion circuit 200 is a three-level conversion circuit
  • the first conversion circuit 200 includes a first group of switches, a second group of switches, a third group of switches and a fourth group of switches.
  • the structure of the first conversion circuit 200 can be referred to as shown in FIG. 1
  • the driving signals of the first conversion circuit 200 include a first driving signal, a second driving signal, a third driving signal and a fourth driving signal.
  • the first signal generating module 4052 can be connected with the first group of switches and the third group of switches, the first signal generating module 4052 can generate the first driving signal and the third driving signal, and output the first driving signal to the first group of switches, and output the third driving signal to the second group of switches.
  • the second signal generating module 4053 can be connected with the second group of switches and the fourth group of switches, the second signal generating module 4053 can generate the second driving signal and the fourth driving signal, and output the second driving signal to the second group of switches, and outputting the fourth driving signal to the fourth group of switches.
  • the specific structures of the frequency dividing module 4051 , the first signal generating module 4052 and the second signal generating module 4053 are given below.
  • the first signal generating module 4052 includes: a first on-time control module and a first logic module.
  • the second signal generation module 4053 includes: a second on-time control module and a second logic module.
  • the first on-time control module is connected to the input terminal of the first conversion circuit 200, the output terminal of the first conversion circuit 200 and the frequency division module, and the first on-time control module After receiving the first frequency division signal, according to the comparison result of the input voltage of the first conversion circuit 200 and the output voltage of the first conversion circuit 200, generate the first on-time control signal;
  • the first logic module is respectively connected to the first on-time control module and the frequency division module, and generates the first driving signal according to the first on-time control signal and the first frequency division signal.
  • the second on-time control module is connected with the input end of the first conversion circuit 200, the output end of the first conversion circuit 200 and the frequency division module, and the second on-time control module is used After receiving the second frequency division signal, according to the comparison result of the input voltage of the first conversion circuit 200 and the output voltage of the first conversion circuit 200, generate a second on-time control signal;
  • the second logic module is connected to the second on-time control module and the frequency dividing module respectively, and generates the second driving signal
  • the first logic module may also be used to generate a third driving signal
  • the second logic module may also be used to generate a fourth driving signal
  • the function of setting the first on-time control module is to determine the on-time length of the first driving signal.
  • the role of setting the first logic module is to: determine the period of the first driving signal according to the first frequency division signal, and generate the first driving signal according to the conduction duration of the first driving signal.
  • the function of setting the second on-time control module is to determine the on-time length of the second driving signal.
  • the role of setting the second logic module is to determine the period of the second driving signal according to the second frequency division signal, and generate the second driving signal according to the conduction duration of the second driving signal.
  • FIG. 15 is a schematic structural diagram of the frequency dividing module 4051 provided by the embodiment of the present application.
  • the frequency dividing module 4051 may include a D flip-flop, an inverter D1, a first AND gate circuit D2 and a second AND gate circuit D3.
  • the clock input terminal of the D flip-flop is used as the input terminal of the frequency division module, and is connected with the input terminal of the comparison circuit
  • the output terminal of the first AND gate circuit D2 is used as the first output terminal of the frequency division module, and is connected with the first signal generation module
  • the output end of the second AND gate circuit D3 is used as the second output end of the frequency dividing module, and is connected to the second signal generating module.
  • each device in the frequency division module shown in Figure 15 is: the clock port of the D flip-flop is connected to the comparison circuit 404, the D input end of the D flip-flop is connected to the second input end of the D flip-flop and the second AND gate circuit The second input end of D3 is connected, the data output end of the D flip-flop is connected with the second input end of the first AND gate circuit D2, the first input end of the first AND gate circuit D2 is connected with the output end of the comparison circuit, and the second The first input end of the AND gate circuit D3 is connected to the output end of the comparison circuit.
  • the D flip-flop acts on the rising edge of the comparison signal, and when the comparison signal output by the comparison circuit 404 presents a high level state, The signal output by the D flip-flop is reversed once, and the initial state of the D flip-flop is a low-level signal, then the output signal of the D flip-flop is reversed from a low-level signal to a high-level signal, and the AND gate circuit &1 satisfies the output high-level signal flat condition, the first frequency division signal output by &1 turns from a low level state to a high level signal, &2 receives a low level signal and the second frequency division signal maintains a low level state, when the comparison circuit shows a high level next time In the level state, the signal output by the D flip-flop turns from a high level state to a low level signal.
  • the input terminal of &1 receives a low level signal
  • both input terminals of &2 receive a high level signal
  • &1 The output of the first frequency division signal is inverted from high level to low level
  • the second frequency division signal output by &2 is inverted from low level to high level.
  • the waveform schematic diagram of the first frequency division signal, the second frequency division signal and the comparison signal can be referred to as shown in FIG. 16 .
  • the periods of the first frequency-divided signal and the second frequency-divided signal are the same, and are out of phase with each other by half a period.
  • FIG. 17 is a schematic structural diagram of a first signal generating module provided by an embodiment of the present application.
  • the third resistor R3, the fourth resistor R4, the fifth resistor R5, the seventeenth switch S17, the third capacitor C3, the second comparator COMP2, the eighth RS flip-flop RS8 and the eighth timer TD8 It constitutes a first on-time control module
  • the ninth RS flip-flop RS9 constitutes a first logic module.
  • each device in the first signal generating module 4052 shown in FIG. 17 is: the first end of the third resistor R3 is connected to the output end of the first conversion circuit 200, and the first end of the third resistor R3 Two ends are connected with the first end of the fourth resistance R4; the first end of the fourth resistance R4 is connected with the first input end of the second comparator COMP2, and the second end of the fourth resistance R4 connected to the ground wire; the first end of the fifth resistor R5 is connected to the input end of the first conversion circuit 200, and the second end of the fifth resistor R5 is connected to the first end of the seventeenth switch S17.
  • One electrode is connected to the first end of the third capacitor C3; the first end of the third capacitor C3 is connected to the second input end of the second comparator COMP2, and the second end of the third capacitor C3 connected to the ground wire; the second electrode of the seventeenth switch S17 is connected to the ground wire, and the control circuit of the seventeenth switch S17 is connected to the output terminal of the eighth RS flip-flop RS8; the The output terminal of the second comparator COMP2 is connected with the first logic module and the first terminal of the eighth timer TD8; the first input terminal of the eighth RS flip-flop RS8 is connected with the frequency dividing module The output end is connected, the second input end of the eighth RS flip-flop RS8 is connected with the second end of the eighth timer TD8; the first input end of the ninth RS flip-flop RS9 is connected with the frequency division module The output end of the ninth RS flip-flop RS9 is connected to the first on-time control module, and the output end of the ninth RS flip-flop RS9 is used
  • the first logic module further includes a third inverter Z3.
  • the input terminal of the third inverter Z3 is connected to the output terminal of the ninth RS flip-flop RS9, and the output terminal of the third inverter Z3 is connected to the switch S4.
  • the flip-flop RS8 When the first driving signal and the fourth driving signal are generated by the first signal generation module shown in Figure 17, when the first frequency division signal is in a high level state, the flip-flop RS8 is The control electrode of the switch S17 provides a low-level signal, the switch S17 is turned off, the input voltage Vin of the first conversion circuit 200 charges the capacitor C3, and when the potential of the second terminal of the capacitor C3 is higher than the potential of the second terminal of the resistor R3, the comparison The output signal of COMP2 is turned from low level to high level. If the first frequency division signal output by the frequency division module is in high level state, trigger RS9 outputs high level to switch S1, and inverter Z3 converts the output signal of RS4 to The high level inverts to get a low level signal to the switch S4. Wherein, the flip-flop RS9 outputs the first driving signal, and the inverted Z3 outputs the fourth driving signal.
  • FIG. 18 is a schematic structural diagram of the second signal generation module 4053 .
  • the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the twenty-first switch S22, the fourth capacitor C4, the third comparator COMP3, the tenth RS flip-flop RS10 and the ninth timer TD9 constitutes a first on-time control module, and the eleventh RS flip-flop RS11 constitutes a second logic module.
  • each device in the first signal generating module 4052 shown in FIG. 18 is: the first end of the sixth resistor R6 is connected to the output end of the first conversion circuit 200, and the first end of the sixth resistor R6 The two terminals are connected to the first end of the seventh resistor R7; the first end of the seventh resistor R7 is connected to the first input end of the third comparator COMP3, and the second end of the seventh resistor R7 connected to the ground wire; the first end of the eighth resistor R8 is connected to the input end of the first conversion circuit 200, the second end of the eighth resistor R8 is connected to the first end of the eighteenth switch S18 One electrode is connected to the first end of the fourth capacitor C4; the first end of the fourth capacitor C4 is connected to the second input end of the third comparator COMP3, and the second end of the fourth capacitor C4 connected to the ground wire; the second electrode of the eighteenth switch S18 is connected to the ground wire, and the control circuit of the eighteenth switch S18 is connected to the output terminal
  • the second logic module further includes a fourth inverter Z4.
  • the input end of the fourth inverter Z4 is connected to the output end of the eleventh RS flip-flop RS11, and the output end of the fourth inverter Z4 is connected to the switch S3.
  • the working principle of the second signal generating module 4053 is the same as that of the first signal generating module 4052, since the first frequency-divided signal and the second frequency-divided signal are out of phase with each other by half a period, therefore, the second The first driving signal and the second driving signal are also out of phase by half a period.
  • a power converter provided by the embodiment of the present application may be shown in FIG. 19 .
  • the first conversion circuit includes switches Q1/Q2/Q3/Q4, an output inductor Lm and a flying capacitor Cf.
  • resistors R1 and R2 are included in the voltage divider circuit. Wherein, the first end of the resistor R1 is connected to the output end of the first conversion circuit 200, the second end of the resistor R1 is connected to the first end of the resistor R2, the second end of the resistor R2 is grounded, and the second end of the resistor R1 outputs the first a voltage. Wherein, the second end of the resistor R1 constitutes a point to be detected and is connected to the detection circuit.
  • the detection circuit includes a data transmission line, the output transmission line is connected to the point to be detected, and outputs the voltage value of the first voltage output by the point to be detected to the amplifier circuit and the slope compensation circuit.
  • the operational amplifier U1 is included. Wherein, the first input end of U1 is connected to the second end of the resistor R1, the second input end of U1 receives a reference voltage, and the output end of U1 outputs an error signal.
  • the slope compensation circuit includes switch S1, switch S2, switch S3, capacitor C1, follower U2, RS flip-flop RS1, RS flip-flop RS2, timer TD1, timer TD2, current source I1, current source I2 and inverter Phase device Z1.
  • the first electrode of the switch S1 is connected to the power supply VCC1, the second electrode of the switch S1 is connected to the first end of the current source I1; the second end of the current source I1 is respectively connected to the first end of the capacitor C1, the switch The first electrode of S3 is connected to the first electrode of switch S3; the second electrode of the switch S2 is connected to the second end of C1; the second electrode of the switch S3 is connected to the first end of the current source I2; the current The second end of the source I2 is connected to the second end of the capacitor C1; the second end of the capacitor C1 is connected to the output end of the follower U2; the input end of the follower U2 is connected to the second end of the resistor R1; the capacitor The second end of C1 outputs the slope compensation signal; the first end of RS flip-flop RS1 receives the comparison signal, the second end of RS flip-flop RS1 is connected to the first end of timer TD1, and the output end of RS flip-flop RS1
  • a comparator COMP1 is included in the comparison circuit.
  • the first input terminal of the comparator COMP1 is connected to the output terminal of U1
  • the second input terminal of the comparator COMP1 is connected to the first terminal of the capacitor C1
  • the output terminal of the comparator COMP1 outputs a comparison signal.
  • the signal generation circuit includes frequency divider, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, switch S4, switch S5, capacitor C2, capacitor C3, comparator COMP2, comparator COMP3, RS flip-flop RS3, RS flip-flop RS4, RS flip-flop RS5, RS flip-flop RS6, timer TD3, timer TD4, inverter Z2 and inverter Z3.
  • the first end of the resistor R3 is connected to the output end of the first conversion circuit, the second end of the resistor R3 is connected to the first end of the resistor R4; the first end of the resistor R4 is connected to the first input end of the comparator COMP2 connected, the second end of the resistor R4 is connected to the ground wire; the first end of the resistor R5 is connected to the input end of the first conversion circuit, and the second end of the fifth resistor R5 is connected to the first electrode of the switch S4 connected to the first end of the capacitor C2; the first end of the capacitor C2 is connected to the second input end of the second comparator COMP2, and the second end of the capacitor C2 is connected to the ground; the second electrode of the switch S4 is connected to the The ground wire is connected, the control electrode of the switch S4 is connected with the output terminal of the trigger RS3; the output terminal of the second comparator COMP2 is connected with the R terminal of the RS trigger RS4 and the input terminal of the timer TD3; the trigger The
  • the first end of the resistor R6 is connected to the output end of the first conversion circuit, the second end of the resistor R6 is connected to the first end of the resistor R7; the first end of the resistor R7 is connected to the first input end of the comparator COMP3, The second end of the resistor R4 is connected to the ground wire; the first end of the resistor R8 is connected to the input end of the first conversion circuit, and the second end of the fifth resistor R8 is connected to the first electrode of the switch S5 and the capacitor
  • the first end of C3 is connected; the first end of the capacitor C3 is connected with the second input end of the comparator COMP3, and the second end of the capacitor C3 is connected with the ground wire; the second electrode of the switch S5 is connected with the ground wire Connection, the control electrode of the switch S5 is connected with the output terminal of the trigger RS5; the output terminal of the comparator COMP5 is connected with the R terminal of the RS trigger RS6 and the input terminal of the timer TD4; the S terminal of the trigger
  • the resistors R1 and R2 in the detection circuit step down the output voltage to obtain the first voltage, and output the voltage values of the first voltage to the
  • the capacitor C1 outputs a slope signal according to a fixed period
  • the second terminal of the capacitor C1 superimposes the voltage value of the first voltage, that is, the amplitude of the slope compensation signal output by the first terminal of the capacitor C1 is equal to the charging value of the capacitor C1 and the first voltage The sum of the voltage values of a voltage.
  • the output voltage When the output voltage reaches the target value, the sum of the voltage value of the first voltage and the charging value of capacitor C1 is the magnitude of the error signal of U1, and the time when the COMP1 output comparison signal is high level is shifted forward, and the output of COMP1 Connect the two frequency dividers, and the two frequency dividers are respectively connected to the setting terminals S of the flip-flops RS4 and RS6.
  • the S terminal When the S terminal is 1, the drive signal is output once, so as to realize the change of the drive signal of the switch, and the first conversion circuit Adjust the working state of the circuit, thus effectively avoiding the driving delay problem caused by the slow output signal of U1, so that the output voltage can meet the demand of the load.
  • the inverting input terminal of COMP1 receives the sum of the discharge voltage of capacitor C1 and the voltage value of the first voltage
  • the non-inverting input terminal of COMP1 receives the voltage output by U1.
  • the comparison signal is turned from low level to high level
  • the comparison signal is divided by the frequency divider to output the first frequency division signal and the second frequency-division signal
  • the first frequency-division signal and the second frequency-division signal pass through the triggers RS4 and RS6, and output a high-level drive signal to the switches Q1 and Q4, the switches Q1 and Q4 are turned on, and the input power is converted to the first
  • the output inductance of the circuit is charged, the output current rises, and when the output voltage reaches the minimum allowable value, the output voltage rises. Since the waveform of the driving signal is fixed, the output voltage can
  • control device can adjust the period of the driving signal by controlling the slope compensation signal to compensate the output waveform of the output inductor Lm, and the COMP2 and COMP3 in the signal generating circuit are respectively connected to the R terminals of the flip-flops RS4 and RS6, which can be passed Adjust COMP2 and COMP3 to adjust the time that the driving signal maintains a high level, so as to achieve the purpose of adjusting the duty cycle of the driving signal.
  • the above-mentioned introduction to the structure of the power converter is only an example.
  • the power converter provided in this application may also include other structures. The following working principles are the same, and this application will not introduce them one by one here.
  • the power converter in order to increase the conversion power of the power converter, should include at least one second converter circuit, and the output terminal of the first conversion circuit is connected in parallel with the output terminal of each second conversion circuit.
  • the output voltages of the converter circuits are the same.
  • the signal generation circuit in the control device provided in the embodiment of the present application further includes: a third signal generation circuit corresponding to each of the second conversion circuits module and a fourth signal generation module.
  • the frequency division module is connected to each of the third signal generation modules and each of the fourth signal generation modules, and the frequency division module is also used to divide the comparison signal. frequency processing to obtain a third frequency-divided signal corresponding to each of the third signal generating modules and a fourth frequency-divided signal corresponding to each of the fourth signal generating modules; each of the third The signal generation module is connected to the frequency division module, and the third signal generation module is used to receive the corresponding third frequency division signal, and convert according to the received third frequency division signal and the voltage of the corresponding second conversion circuit Ratio, generate the fifth drive signal; the fourth signal generation module is connected to the frequency division module, the fourth signal generation module is used to receive the corresponding fourth frequency division signal, and according to the received fourth frequency division signal and the corresponding voltage conversion ratio of the second conversion circuit to generate a sixth drive signal; and output the fifth drive signal and the sixth drive signal to the corresponding second conversion circuit.
  • the fifth driving signal and the sixth driving signal constitute a corresponding driving signal of the second converting circuit.
  • the third signal generating module can also generate the seventh driving signal
  • the fourth signal generating module can also generate the eighth driving signal, and combine the seventh driving signal and The eighth phase read signal is output to the corresponding second conversion circuit.
  • the frequency division circuit is a frequency divider by four.
  • an embodiment of the present application also provides a power conversion method, which is applied to a power converter, and the power converter may include a conversion circuit and a control device connected to the conversion circuit.
  • the method specifically includes the following steps:
  • Step 2201. Detect the output voltage of the conversion circuit to obtain the voltage value of the first voltage.
  • Step 2202 Generate a slope compensation signal by using the voltage value of the first voltage.
  • Step 2203 Obtain an error signal according to the error between the voltage value of the first voltage and the voltage value of the reference voltage.
  • Step 2204 compare the slope compensation signal with the error signal to obtain a comparison signal.
  • Step 2205 Generate a drive signal for the transformation circuit according to the comparison signal.
  • the structure of the power converter can be seen from FIG. 4 to FIG. 22 , which will not be repeated here in this application.
  • the generating the slope compensation signal by using the voltage value of the first voltage includes: superimposing the voltage value of the first voltage and the slope signal to obtain the slope compensation signal.
  • generating the driving signal of the conversion circuit according to the comparison signal includes: dividing the frequency of the comparison signal to obtain The first frequency division signal and the second frequency division signal; according to the first frequency division signal and the voltage conversion ratio of the conversion circuit, a first drive signal is generated; according to the second frequency division signal and the voltage conversion ratio of the conversion circuit The voltage conversion ratio is used to generate a second driving signal; the driving signal of the conversion circuit includes the first driving signal and the second driving signal.
  • generating the driving signal of the conversion circuit according to the comparison signal includes: dividing the frequency of the comparison signal to obtain The first frequency-division signal and the second frequency-division signal; according to the first frequency-division signal and the voltage conversion ratio of the conversion circuit, generate a first drive signal and a third drive signal; according to the second frequency-division signal and The voltage conversion by the conversion circuit generates the second driving signal and the fourth driving signal.
  • an embodiment of the present application further provides a power adapter.
  • the power adapter includes a casing, a connection port and the aforementioned power converter.
  • an embodiment of the present application further provides an electronic device, which may include a power supply, a load, and the aforementioned power converter.
  • the power converter is connected with the battery, and the power converter can convert the output voltage of the battery to obtain a target voltage, and output the target voltage to the load.

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Abstract

一种功率变换器、电源适配器、电子设备和功率变换方法,使变换电路的输出电压满足负载需求。该功率变换器包括第一变换电路和与第一变换电路连接的控制装置,该控制装置可以检测第一变换电路的输出电压,得到第一电压的电压值;利用第一电压的电压值生成斜坡补偿信号;根据第一电压的电压值与参考电压的电压值之间的误差,得到误差信号;将斜坡补偿信号和误差信号进行比较,得到比较信号;根据比较信号,生成第一变换电路的驱动信号。

Description

一种功率变换器、电源适配器、电子设备和功率变换方法 技术领域
本申请涉及电力电子领域,尤其涉及一种功率变换器、电源适配器、电子设备和功率变换方法。
背景技术
Buck转换电路是常见的变化电路拓扑结构之一,以其可以实现减小无源器件的数量和体积而被用于多种类型的电力系统中。例如,电动/混合动力汽车的电源管理系统、光伏发电系统、通信电源供电系统、数据中心等电力系统内的电压转换电路,常需要使用三电平Buck转换实现电压转换。
目前,Buck转换电路多采用电压控制方式,即根据Buck转换电路的输出电压确定Buck转换电路中开关的驱动信号,从而实现控制Buck电路的工作状态。但是上述电压控制方式,用于产生开关驱动信号的控制装置的时钟周期固定,导致驱动信号的周期固定,当负载发生变化,无法及时对开关的状态进行调整,输出电压不发满足负载的需求。
发明内容
本申请提供一种功率变换器、电源适配器、电子设备和功率变换方法,可以根据负载情况进行及时调整变换电路的工作状态,使输出电压满足负载的需求。
第一方面,本申请提供一种功率变换器,该功率变换器包括第一变换电路和与第一变换电路连接的控制装置。该控制装置可以对第一变换电路的工作状态进行控制。
具体地,该控制装置可以检测所述第一变换电路的输出电压,得到第一电压的电压值;利用所述第一电压的电压值生成斜坡补偿信号;将所述第一电压的电压值与参考电压的电压值之间的误差进行放大处理,得到误差信号;将所述斜坡补偿信号和所述误差信号进行比较,得到比较信号;根据所述比较信号,生成所述第一变换电路的驱动信号。
采用上述功率变换器,可以利用第一电压的电压值进行斜坡补偿,得到斜坡补偿信号,进行斜坡补偿后的斜坡补偿信号幅值发生了改变,导致与误差信号的差值为零的时刻发生偏移,从而改变了比较信号的电平翻转时刻,相应的生成驱动信号的时刻也发生改变,从而实现及时根据负载情况对驱动信号进行调整的目的。
实际使用时,该控制装置可以包括:检测电路、放大电路、斜坡补偿电路、比较电路和信号生成电路。
其中,所述检测电路的输入端与所述第一变换电路的输出端连接,所述检测电路的输出端与所述斜坡补偿电路和所述放大电路连接,所述检测电路用于检测所述第一变换电路输出电压,得到所述第一电压的电压值,并将所述第一电压的电压值输出给所述斜坡补偿电路和所述放大电路;所述放大电路与所述比较电路连接,所述放大电路用于对所述第一电压的电压值与参考电压的电压值的误差进行放大处理,得到所述误差信号,并将所述误差信号输出给所述比较电路;所述斜坡补偿电路与所述比较电路连接,所述斜坡补偿电路用于根据所述第一电压的电压值,生成所述斜坡补偿信号;所述比较电路与所述信号生成电路连接,所述比较电路用于将所述斜坡补偿信号和所述误差信号进行比较,得到所述比 较信号,并将所述比较信号输出给所述信号生成电路;所述信号生成电路用于根据所述比较信号,生成所述第一变换电路的驱动信号。
本申请提供的功率变换器,斜坡补偿电路可以与检测电路连接,并根据检测电路输出的表征第一变换电路输出情况的第一电压值的电压值,并利用第一电压的电压值进行斜坡补偿,进行斜坡补偿后的斜坡补偿信号幅值发生变化,导致与误差信号的差值为零的时刻发生偏移,从而改变了比较信号的电平翻转时刻,相应的信号生成电路发送驱动信号的时刻也发生改变,从而实现及时根据负载情况对驱动信号进行调整的目的。
在一种可能的实现方式中,所述斜坡补偿电路包括:斜坡信号补偿模块和控制模块。
其中,所述斜坡信号补偿模块分别与所述检测电路和控制模块连接,所述斜坡信号生成模块用于根据所述第一电压的电压值,生成所述斜坡补偿信号;所述控制模块与所述比较电路连接,所述控制模块根据所述比较信号控制所述斜坡信号补偿模块的工作状态。
采用上述控制装置,斜坡信号补偿装置可以利用第一电压的电压值进行斜坡补偿,得到斜率和幅值满足需求的斜坡补偿信号。
在一种可能的实现方式,所述斜坡信号补偿模块包括:第一开关S1、第二开关S2、第三开关S3、第一电流源I1、第二电流源I2和第一电容C1。
其中,所述第一开关S1的第一电极用于与第一电源VCC1连接,所述第一开关S1的第二电极所述第一电流源I1的第一端连接;所述第一电源I1的第二端与所述第一电容C1的第一端、所述第二开关S2的第一电极和第三开关S3的第一电极连接;所述第二开关S2的第二电极与所述第一电容C1的第二端连接;所述第三开关S3的第二电极与所述第二电流源I2的第一端连接;所述第二电流源I2的第二端与所述第一电容C1的第二端连接;所述第一电容C1的第二端与所述检测电路的输出端连接,所述第一电容C1的第一端与所述比较电路连接;所述第一开关S1的控制电极、所述第二开关S2的控制电极和所述第三开关S3的控制电极均与所述第一控制模块连接。
采用上述通过第一控制第一电容C1的充放电输出斜坡补偿信号,由于斜坡补偿信号叠加了表征第一变换电路输出情况的第一电压的电压值,斜坡补偿信号的幅值发生了变换,则斜坡补偿信号与误差信号之差为零的时刻向前偏移,相应的驱动信号的发送时刻向前偏移,采用该驱动信号后第一变换电路输出电压可以满足负载的需求。
在一种可能的实现方式中,所述控制模块包括:第一RS触发器RS1、第二RS触发器RS2、第一定时器TD1、第二定时器TD2和第一反相器Z1。
其中,所述第一RS触发器RS1的第一端与所述比较电路连接,所述第一RS触发器RS1的第二端与所述第一定时器TD1的第一端连接,所述第一RS触发器RS1的输出端与所述第一开关S1的控制电极、所述第一反相器Z1的输入端和所述第一定时器TD1的第二端连接;所述第二RS触发器RS2的第一端与所述比较电路连接,所述第二RS触发器RS2的第二端与所述第二定时器TD2的第一端连接,所述第二RS触发器RS2的输出端与所述第二开关S2的控制电极和第二定时器TD2的第二端连接;所述第一反相器Z1的输出端与所述第三开关S3的控制电极连接。
采用上述控制装置,可以通过控制斜坡信号补偿模块中开关的工作状态,从而控制第一电容C1进行充放电,生成斜坡补偿信号。
在一种可能的实现方式中,所述控制模块包括:第三RS触发器RS3、第四RS触发器RS4、第五RS触发器RS5、第三定时器TD3、第四定时器TD4和第五定时器TD5。
其中,所述第三RS触发器RS3的第一端与所述比较电路连接,所述第三RS触发器RS3的第二端与所述第三定时器TD3的第一端和所述第四定时器TD4的第一端连接,所述第三RS触发器RS3的输出端与所述第一开关S1的控制电极和所述第三定时器TD3的第二端连接;所述第四RS触发器RS4的第一端与所述第四定时器TD4的第二端连接,所述第四RS触发器RS4的第二端与所述比较电路连接,所述第四RS触发器RS4的输出端与所述第三开关S3的控制电极连接;所述第五RS触发器RS5的第一端与所述比较电路连接,所述第五RS触发器RS5的第二端与所述第五定时器TD5的第一端连接,所述第五RS触发器RS5的输出端与所述第二开关S2的控制电极和所述第五定时器TD5的第二端连接。
采用上述控制装置,可以通过控制斜坡信号补偿模块中开关的工作状态,从而控制第一电容C1进行充放电。
在一种可能的实现方式中,所述斜波信号补偿模块包括:第四开关S4、第五开关S5、第六开关S6、第二电容C2、第三电流源I3、第四电流源I4和加法器∑。
其中,所述第四开关S4的第一电极用于与第二电源VCC2连接,所述第四开关S4的第二电极与所述第三电流源I3的第一端连接;所述第三电流源I3的第二端分别与所述第二电容C2的第一端、所述第九开关S5、9的第一电极和第六开关S6的第一电极连接;所述第五开关S5的第二电极与所述第六开关S6的第二电极连接;所述第六开关S6的第二电极与所述第四电流源I4的第一端连接;所述第四电流源I4的第二端与所述第二电容C2的第二端连接;所述第二电容C2的第二端用于接收所述参考电压,所述第二电容C2的第一端与所述加法器的第一输入端连接;所述加法器的第二端与所述检测电路连接,所述加法器的输出端与所述比较电路连接;所述第四开关S4的控制电极、所述第五开关S5的控制电极和所述第六开关S6的控制电极均与所述第一控制模块连接。
采用上述控制装置,可以利用加法器叠加第二电压,进行斜坡补偿。
在一种可能的实现方式中,所述加法器包括:第五电流源I5、第七开关S7、第八开关S8、第九开关S9、第十开关S10、第十一开关S11、第十二开关S12、第十三开关S13、第一电阻R1和第二电阻R2。
其中,所述第七开关S7的第一电极与第三电源VCC3连接,所述第十一开关的S11的第二电极与所述第十开关S10的第一电极和第十一开关S11的第一电极连接,所述第七开关S7的控制电极与所述第十二开关12的控制电极和所述第九开关S9的控制电极连接;所述第八开关S8的第一电极与第三电源VCC3连接,所述第十二开关的S12的第二电极与所述第十二开关S12的第一电极和第十三开关S13的第一电极连接;所述第九开关S9的第一电极与第三电源VCC3连接,所述第十三开关的S13的第二电极与所述第五电流源I5的第一端连接;所述第五电流源I5的第二端与地线连接;所述第十开关S10的第二电极与所述比较电路和所述第一电阻R1的第一端连接,所述第十开关S10的控制电极与所述第二电容C2的第一端连接;所述第十一开关S11的第二电极与所述比较电路和所述第二电阻R2的第一端连接,所述第十一开关S11的控制电极用于接收所述参考电压;所述第十二开关S12的第二电极与所述比较电路和所述第一电阻R1的第一端连接,所述第十二开关S12的控制电极与所述检测电路连接;所述第十三开关S13的第二电极与所述比较电路和所述第二电阻R2的第一端连接,所述第十三开关S13的控制电极用于接收所述参考电压;所述第一电阻R1的第二端与所述地线连接;所述第二电阻R2的第二端与所述地线 连接。
在一种可能的实现方式中,所述比较电路包括:第十四开关S14、第十五开关S15、第十六开关S16和第一比较器COMP1。
其中,所述第十四开关S14第一电极与第三电源VCC3连接,所述第十四开关S14的第二电极分别与所述第十五开关S15的第一电极和第十六开关S16的第一电极连接,所述第十四开关S14的控制电极与所述第七开关S7的控制电极连接;所述第十五开关S15的第二电极与所述第一比较器COPM1的第一输入端连接,所述第十五开关S15的控制电极用于接收所述参考信号;所述第十六开关S16的第二电极与所述第一比较器COMP1的第二输入端连接,所述第十六开关S16的控制电极与所述放大电路连接;所述第一比较器COMP1的第一输入端与所述第十开关S10的第二电极和所述第十二开关S12的第二电极连接,所述第一比较器COMP1的第二输入端与所述第十一开关S11的第二电极和所述第十三开关S13的第二电极连接,所述第一比较器COMP1的输出端与所述信号生成电路连接。
在一种可能的实现方式中,所述信号生成电路包括:分频模块、第一信号生成模块和第二信号生成模块。
其中,所述分频模块的输入端与所述比较电路连接,所述分频模块的输出端与所述第一信号生成模块和所述第二信号生成模块连接,所述分频模块用于对所述比较信号进行分频处理,得到第一分频信号和第二分频信号,并将所述第一分频信号输出给所述第一信号生成模块,将所述第二分频模块输出给所述第二信号生成模块;所述第一信号生成模块用于根据所述第一分频信号和所述第一变换电路的电压转换比,生成第一驱动信号;所述第二信号生成模块用于根据所述第二分频信号和所述第一变换电路的电压转换比,生成第二驱动信号。其中,所述第一变换电路的驱动信号包括所述第一驱动信号和所述第二驱动信号。
采用上述控制装置,第一变换电路由多个开关组成,可以利用第一信号生成模块生成第一驱动信号,以及利用第二信号生成模块生成第二驱动信号。
在一种可能的实现方式中,所述第一信号生成模块包括:第一导通时间控制模块和第一逻辑模块。
其中,所述第一导通时间控制模块与所述第一变换电路的输入端、所述第一变换电路的输出端和所述分频模块连接,所述第一导通时间控制模块用于在接收到所述第一分频信号后,根据所述第一变换电路的输入电压和所述第一变换电路的输出电压的比较结果,生成第一导通时间控制信号;所述第一逻辑模块分别与所述第一导通时间控制模块和所述分频模块连接,根据所述第一导通时间控制信号和所述第一分频信号,生成所述第一驱动信号;所述第二信号生成模块包括:第二导通时间控制模块和第二逻辑模块;所述第二导通时间控制模块与所述第一变换电路的输入端、所述第一变换电路的输出端和所述分频模块连接,所述第二导通时间控制模块用于在接收到所述第二分频信号后,根据所述第一变换电路的输入电压和所述第一变换电路的输出电压的比较结果,生成第二导通时间控制信号;所述第二逻辑模块分别与所述第二导通时间控制模块和所述分频模块连接,根据所述第二导通时间控制信号和所述第二分频信号,生成所述第二驱动信号。
采用上述控制装置,可以利用第一导通时间控制模块控制第一驱动信号和第四驱动信号的占空比,可以利用第二导通时间控制模块控制第二驱动信号和第三驱动信号的占空比。
在一种可能的实现方式中,所述第一导通时间控制模块包括:第三电阻R3、第四电阻R4、第五电阻R5、第十七开关S17、第三电容C3、第二比较器COMP2、第八RS触发器RS8和第八定时器TD8。
其中,所述第三电阻R3的第一端与所述第一变换电路的输出端连接,所述第三电阻R3的第二端与所述第四电阻R4的第一端连接;所述第四电阻R4的第一端与所述第二比较器COMP2的第一输入端连接,所述第四电阻R4的第二端与所述地线连接;所述第五电阻R5的第一端与所述第一变换电路的输入端连接,所述第五电阻R5的第二端与所述第十七开关S17的第一电极和所述第三电容C3的第一端连接;所述第三电容C3的第一端与所述第二比较器COMP2的第二输入端连接,所述第三电容C3的第二端与所述地线连接;所述第十七开关S17的第二电极与所述地线连接,所述第十七开关S17的控制电路与所述第八RS触发器RS8的输出端连接;所述第二比较器COMP2的输出端与所述第一逻辑模块和所述第八定时器TD8的第一端连接;所述第八RS触发器RS8的第一输入端与所述分频模块的输出端连接,所述第八RS触发器RS8的第二输入端与所述第八定时器TD8的第二端连接。
在一种可能的实现方式中,若所述第一变换电路为二电平变换电路,所述第一逻辑模块包括:第九RS触发器RS9。
其中,所述第九RS触发器RS9的第一输入端与所述分频模块的输出端连接,所述第九RS触发器RS9的第二输入端与所述第一导通时间控制模块连接,所述第九RS触发器RS9的输出端用于与所述第一变换电路的第一组开关连接,并向所述第一组开关输出所述第一驱动信号。其中,所述第一组开关用于控制所述第一变换电路中电感充电。
在一种可能的实现方式中,若所述第一变换电路为三电平变换电路,所述第一逻辑模块包括第十RS触发器RS10和第三反相器Z3。
具体地,所述第十RS触发器RS10的第一输入端与所述分频模块的输出端连接,所述第十RS触发器RS10的第二输入端与所述第一导通时间控制模块连接,所述第十RS触发器RS10的输出端用于与所述第一变换电路的第一组开关连接,并向所述第一组开关输出所述第一驱动信号;所述第三反相器Z3的输入端与所述第十RS触发器RS10的输出端连接,所述第三反相器Z3的输出端与所述第三组开关连接,并向所述第三组开关输出第三驱动信号。
其中,所述第一组开关、第二组开关、所述第三组开关和第四组开关串联连接,所述第一开关的第一端为所述第一变换电路的第一输入端,所述第四组开关的第二端为所述第一变换电路的第二输出端。所述第一组开关接收的所述第一驱动信号、所述第二组开关接收的所述第二驱动信号、所述第三组开关接收的所述第三驱动信号和所述第四组开关接收的第四驱动信号构成所述第一变换电路的驱动信号。在一种可能的设计中,所述转换电路控制装置还与至少一个第二变换电路连接,每个所述第二变换电路的输出端与所述第一变换电路的输出端并联,所述信号生成电路还包括:与每个所述第二变换电路对应的第三信号生成模块和第四信号生成模块。
其中,所述分频模块与每个所述第三信号生成模块和每个所述第四信号生成模块连接,所述分频模块还用于对所述比较信号进行分频处理,得到与每个所述第三信号生成模块一一对应的第三分频信号和与每个所述第四信号生成模块一一对应的第四分频信号;每个所述第三信号生成模块与所述分频模块连接,所述第三信号生成模块用于接收对应的第三分 频信号,并根据接收的所述第三分频信号和对应的第二变换电路的电压转换比,生成第五驱动信号;所述第四信号生成模块与所述分频模块连接,所述第四信号生成模块用于接收对应的第四分频信号,并根据接收的第四分频信号和对应的所述第二变换电路的电压转换比,生成第六驱动信号;将所述五驱动信号和所述第六驱动信号输出给对应的第二变换电路。
采用上述控制装置,在多个变换电路输出端并联的场景中,多个变换电路的输出电压相等,为了减少变换电路的控制装置,可以利用控制装置控制多个变换电路的工作状态。
在一种可能的实现方式中,本申请实施例提供的控制装置还包括:分压电路。
其中,分压电路的输入端与第一变换电路的输出端连接,分压电路的输出端与所述检测电路的输入端连接,分压电路用于将第一变换电路输出的电压进行降压处理,得到所述第一电压,并将第一电压输出给检测电路。
采用上述控制装置,由于控制装置中的多个器件的处理电压值越大,器件的处理难度和处理成本越高,为了控制装置中的器件成本,可以先将待检测的电压进行降压处理,来减少控制装置后续数据处理难度。
第二方面,本申请提供一种功率变换方法,该功率变换方法可以应用于功率变换装置中,具体地,该功率变换方法包括以下步骤:检测变换电路的输出电压,得到第一电压的电压值;利用所述第一电压的电压值生成斜坡补偿信号;根据将所述第一电压的电压值与参考电压的电压值之间的误差,得到误差信号;将所述斜坡补偿信号和所述误差信号进行比较,得到比较信号;根据所述比较信号,生成所述变换电路的驱动信号。
采用上述方法,可以利用表征负载供电情况的第一电压的电压值生成斜坡补偿信号,斜坡补偿信号与误差信号之间差值的误差信号的电平状态转换时刻发送变换,相应的生成的驱动信号的时刻发送变换,从而使变换电路的状态发送变化,从而时变换电路的输出电压满足负载的需求。
在一种可能的实现方式中,所述利用所述第一电压的电压值生成斜坡补偿信号,包括:将所述第一电压的电压值与斜坡信号进行叠加,得到所述斜坡补偿信号。
采用上述方法,将表征负载供电情况的第一电压的电压值与斜坡信号进行叠加,得到斜坡补偿信号,斜坡补偿信号的幅值发生了改变,则斜坡补偿信号与误差信号的差值发生了改变,相应驱动信号的发送时刻发送了改变。
在一种可能的实现方式中,若所述变换电路为二电平变换电路,所述根据所述比较信号,生成所述变换电路的驱动信号,包括:对所述比较信号进行分频,得到第一分频信号和第二分频信号;根据所述第一分频信号和所述变换电路的电压转换比,生成第一驱动信号;根据所述第二分频信号和所述变换电路的电压转换比,生成第二驱动信号;所述变换电路的驱动信号包括所述第一驱动信号和所述第二驱动信号。
在一种可能的实现方式中,若所述变换电路为三电平变换电路,所述根据所述比较信号,生成所述变换电路的驱动信号,包括:对所述比较信号进行分频,得到第一分频信号和第二分频信号;根据所述第一分频信号和所述变换电路的电压转换比,生成第一驱动信号和第三驱动信号;根据所述第二分频信号和所述变换电路的电压转换,生成第二驱动信号和第四驱动信号。
第三方面,本申请提供一种电源适配器,该电源适配器包括壳体、连接端口以及本申请上述第一方面中任一项所提供的功率变换器。
其中,该电源适配器可以连接在电子设备与供电电源之间,该电源适配器可以将供电电源输出的电压转换为电子设备的充电电压,并将充电电压输出给电子设备,来为电子设备充电。
第四方面,本申请提供电子设备,该电子设备包括:电池、负载和本申请上述第一方面中任一项所提供的功率变换器。
其中,所述功率变换器与所述电池连接,所述功率变换器用于对所述电池输出电压进行转换,得到目标电压,并将所述目标电压输出给所述负载。
附图说明
图1为本申请实施例提供的一种三电平Buck电路的结构示意图;
图2为本申请实施例提供的一种三电平Buck电路的驱动信号的波动示意图;
图3为本申请实施例提供的一种三电平Buck电路控制装置的结构示意图;
图4为本申请实施例提供的一种功率变换器的结构示意图一;
图5为本申请实施例提供的一种功率变换器的结构示意图二;
图6为本申请实施例提供的一种斜坡信号补偿模块的结构示意图一;
图7为本申请实施例提供的一种控制模块的结构示意图一;
图8为本申请实施例提供的一种控制模块的结构示意图二;
图9为本申请实施例提供的一种斜坡信号补偿模块的结构示意图二;
图10为本申请实施例提供的一种控制模块的结构示意图三;
图11为本申请实施例提供的一种控制模块的结构示意图四;
图12为本申请实施例提供的一种加法器的结构示意图;
图13为本申请实施例提供的一种比较电路的结构示意图;
图14为本申请实施例提供的一种信号生成电路的结构示意图;
图15为本申请实施例提供的一种分频模块的结构示意图;
图16为本申请实施例提供的一种二分频器的输出波形示意图;
图17为本申请实施例提供的一种第一信号生成模块的结构示意图;
图18为本申请实施例提供的一种第二信号生成模块的结构示意图;
图19为本申请实施例提供的一种功率变换器的结构示意图三;
图20为本申请实施例提供的一种比较信号波形示意图;
图21为本申请实施例提供的一种功率变换器的结构示意图四;
图22为本申请实施例提供的一种功率变换方法的流程示意图。
具体实施方式
下面将结合附图,对本申请实施例进行详细描述。
方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是,在本申请的描述中“至少一个”是指一个或多个,其中,多个是指两个或两个以上。鉴于此,本发明实施例中也可以将“多个”理解为“至少两个”。“和/或”,描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B这三种情况。另外,字符“/”,如无特殊说明,一般表示前后关联 对象是一种“或”的关系。另外,需要理解的是,在本申请的描述中,“第一”、“第二”等词汇,仅用于区分描述的目的,而不能理解为指示或暗示相对重要性,也不能理解为指示或暗示顺序。
需要指出的是,本申请实施例中“连接”指的是电连接,两个电学元件连接可以是两个电学元件之间的直接或间接连接。例如,A与B连接,既可以是A与B直接连接,也可以是A与B之间通过一个或多个其它电学元件间接连接,例如A与B连接,也可以是A与C直接连接,C与B直接连接,A与B之间通过C实现了连接。
需要指出的是,本申请实施例中“电压转换比”指的是电压转换电路的输入电压和输出电压之间的比值,若电压转换电路执行降压转换,则电压转换电路的输出电压小于输入电压,即电压转换电路的电压转换比小于1。若电压转换电路执行升压转换,则电压转换电路的输出电压大于输入电压,即电压转换电路的电压转换比大于1。
需要指出的是,本申请实施例中的开关可以是继电器、金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor,MOSFET),双极结型管(bipolar junction transistor,BJT),绝缘栅双极型晶体管(insulated gate bipolar transistor,IGBT),氮化镓场效应晶体管(GaN),碳化硅(SiC)功率管等多种类型的开关器件中的一种或多种,本申请实施例对此不再一一列举。每个开关器件皆可以包括第一电极、第二电极和控制电极,其中,控制电极用于控制开关器件的导通或断开。当开关器件导通时,开关器件的第一电极和第二电极之间可以传输电流,当开关器件断开时,开关器件的第一电极和第二电极之间无法传输电流。以MOSFET为例,开关器件的控制电极为栅极,开关器件的第一电极可以是开关器件的源极,第二电极可以是开关器件的漏极,或者,第一电极可以是开关器件的漏极,第二电极可以是开关器件的源极。
目前,大多数的电子设备中都安装有功率变换器或者电子设备与功率变换器连接,电子设备内的功率变换器可以用于实现电子设备内部的电压(或电流)变换,以满足电子设备对电压或者电流的需求。例如,直流-直流(DC/DC)电压转换电路、直流-交流(DC/AC)电压转换电路、交流-直流(AC/DC)电压转换装置等,可以分别实现不同形式的电压(或电流)转换。与电子设备连接的功率变换器,用于实现供电电源的电压(或电流)变换,以满足电子设备对供电电压或者供电电流的需求。例如,电压转换电路可以是适配器。其中,电子设备可以是智能手机、平板电脑、智能手表等电子设备,可以支持5G、折叠屏等前沿技术。
一般来说,任一功能的功率变换器皆可以采用升压斩波Boost电路和降压式变换Buck电路实现。例如,采用Buck电路作为DC/DC电压转换电路时,该电压转换电路可以称之为降压转换电路。具体来说,Buck电路是一种降压式电压转换电路拓扑结构,由于电子设备的传输功率逐渐增大,Buck电路以其可以实现大功率转换而被广泛应用。其中,Buck电路主要分为二电平Buck电路和三电平Buck电路,下面以三电平Buck电路为例对Buck电路的工作原理进行说明。
如图1所示,为一种三电平Buck电路的结构示意图。参见图1所示,该三电平Bcuk电路主要包括:第一组开关Q1、第二组开关Q2、第三组开关Q3、第四组开关Q4、输出电感Lm、飞跨电容Cf和输出电容CL。
其中,第一组开关Q1的第一电极构成三电平Buck电路输入端的第一端口,第一组开关Q1的第二电极与第二组开关Q2的第一电极连接;第二组开关Q2的第一电极与飞跨电 容Cf的第一端连接,第二组开关Q2的第二电极与第三组开关Q3的第一电极连接;第三组开关Q3的第一电极与飞跨电容Cf的第二端连接,第三组开关Q3的第二电极与第四组开关Q4的第一电极连接;第四组开关Q4的第二电极构成三电平Buck电路输入端的第二端口;输出电感Lm的第一端与第二组开关Q2的第二电极连接,输出电感Lm的第二端与输出电容CL的第一端连接,输出电感CL的第二端接地。其中,输出电感CL的第一端构成三电平Buck电路输出端的第一端口,输出电感CL的第二端构成三电平Buck电路输出端的第二端口。
其中,输入端的第一端口可以是三电平Buck电路接收高电位的端点,输入端的第二端口可以是三电平Buck电路接收低电平的端点,输入端的第一端口和第二端口构成三电平Buck电路的输入端。输出端的第一端口可以是三电平Buck电路输出高电位的端点,输出端的第二端口可以是三电平Buck电路输出低电平的端口,输出端的第一端口和第二端口构成三电平Buck电路的输出端。
实际使用时,三电平Buck电路中第一组开关Q1至第四组开关Q4的驱动信号的占空比可以大于05,驱动信号的占空比也可以大于0.5,当驱动信号占空比小于0.5和驱动信号大于0.5时,三电平Buck电路的工作方式不同。
下面结合图1,以开关驱动信号的占空比小于0.5为例对三电平Buck的工作过程进行详细介绍。
具体地,当三电平Buck电路中开关的占空比小于0.5时,三电平Buck电路的工作过程主要包括以下四个阶段。
阶段一、控制第一组开关Q1和第三组开关Q3导通,输入电源输出的输入电压Vin通过第一组开关Q1和第三组开关Q3为飞跨电容Cf和输出电感Lm充电,飞跨电容Cf和输出电感Lm进行储能,输出电流Lm的电流值逐渐上升。阶段二、在确定三电平Buck电路的输出电压Vout达到目标值时,控制第一组开关Q1和第三组开关Q3截止,输出电感Lm可以通过第三组开关Q3和第四组开关Q4的寄生二极管进行续流,随着输出电感Lm存储电能的减少,流过输出电感Lm的电流值逐渐减小。阶段三、在确定输出电感Lm放电完毕,控制第二组开关Q2和第四组开关Q4导通,此时飞跨电容Cf通过第二组开关Q2和第四组开关Q4为输出电感Lm充电,输出电感Lm进行储能。阶段四、在确定三电平Buck电路的输出电压Vout达到目标值时,控制第二组开关Q2和第四组开关Q4截止,输出电感Lm可以通过第三组开关Q3和第四组开关Q4的寄生二极管进行续流,随着输出电感Lm存储的电能逐渐减少,流过输出电感Lm的电流逐渐减小。
需要说明的是,由于输出电容CL与输出电感Lm经过的信号存在相位差,导致输出电压Vout的电压值的变化落后输出电流Lm的电流值的变化。即当三电平Buck电路处于第二阶段,且输出电流Lm的电流值到达允许的最小值后,控制开关进行切换使三电平Buck电路进入第三阶段时,输出电压Vout的电压值持续下降状态,并经过一定时间后达到允许的最小值后逐渐上升,需要在开关在输出电流Lm的电流值处于最低值时输出电压输出的目标值处进行开关状态切换。
实际使用时,当开关驱动信号的占空比小于0.5时,四个开关的一个驱动信号周期可以控制三电平Buck电路重复执行一次上述四个阶段。其中,当三电平Buck电路重复在上述四个阶段工作时,输出电感Lm电流波形可参见图2所示。
由此可知,当第一组开关Q1和第三组开关Q3同时导通时,则输入电压为飞跨电容 Cf和输出电感Lm充电,飞跨电容Cf处于充电状态。当第二组开关Q2和第四组开关Q4同时导通时,飞跨电容Cf为输出电感Lm充电,飞跨电容Cf处于放电状态。
由上述三电平Buck电路工作原理可知,可以通过控制电路中四个开关的导通时刻实现控制三电平Buck电路进入相应的阶段,使三电平Buck电路进入不同的阶段,第一三电平Buck电路在不同阶段内的输出电流Lm的电流值不同,相应的经过时延后的三电平Buck电路的输出电压也不同。实际使用时,第一组开关Q1的控制电极、第二组开关Q2的控制电极、第三组开关Q3的控制电极和第四组开关Q4的控制电极均与三电平Buck电路的控制装置连接,该控制装置可以为四个开关的控制电路提供合适驱动信号,开关在驱动信号的作用下进行工作状态的调节。
如图3所示,为三电平Buck电路控制装置的结构示意图。参见3所示,控制装置检测三电平Buck电路输出端的电压,并将输出端的电压通过电阻R1和R2进行降压处理,得到待检测电压,运行放大器U1将待检测电压与参考电压之间的误差进行放大,得到误差电压,比较器U2和U3将U1输出的误差电压与斜坡生成器输出的斜坡信号进行比较,并将比较结果输出给后端连接的RS触发器,RS触发器给对应的开关提供驱动信号。
在一种可能的实现方式中,参考电压可以是目标电压经过电阻R1和R2进行降压处理后的电压值。其中,目标电压可以是三电平Buck电路后端连接用电设备的额定工作电压。
采用上述控制装置控制三电平Buck电路中开关的工作状态时,当输出电压Vout的电压值处于目标值时,输出相应的驱动信号进行开关状态切换。由于U1输出误差信号的时延较长,且斜坡生成器输出的斜坡信号周期固定,当输出电压达到目标值时,不能及时输出对应的驱动信号,输出电压Vout的电压值到达允许的最低值之后继续降低,三电平Buck输出电压不能满足负载需求。
为解决上述问题,本申请实施例提供了一种功率变换器、电源适配器、电子设备和工功率变换方法,该功率变换器可以包括第一变换电路和与第一变换电路连接的控制装置,控制装置可以根据负载情况进行及时调整为第一变换电路提供的驱动信号,从而第一变换器电路输出的电压满足负载的需求。
实际使用时,图1所示的三电平Buck电路为第一变换电路一种可能的结构示例。在实际应用中,第一变换电路具有多种可能的实现结构,例如二电平Buck电路,本申请对此并不一一列举,但这些降压式Buck电路皆可以适用于本申请。
参见图4所示,为本申请实施例提供的一种功率变换器,该功率变换器可以包括第一变换电路200和与第一变换电路连接的控制装置400。其中,控制装置400可以检测所述第一变换电路200的输出电压,得到第一电压的电压值;利用所述第一电压的电压值生成斜坡补偿信号;根据所述第一电压的电压值与参考电压的电压值之间的误差,得到误差信号;将所述斜坡补偿信号和所述误差信号进行比较,得到比较信号;根据所述比较信号,生成所述第一变换电路200的驱动信号。
实际使用时,参见图5所示,该控制装置400可以包括:检测电路401、放大电路402、斜坡补偿电路403、比较电路404和信号生成电路405。
具体地,所述检测电路401的输入端与所述第一变换电路的输出端连接,所述检测电路401的输出端与所述斜坡补偿电路403和放大电路402连接;所述放大电路402与所述比较电路404连接;所述斜坡补偿电路403与所述比较电路404连接;所述比较电路404与所述信号生成电路405连接;所述信号生成电路405用于与第一变换电路200的连接, 并为第一变换电路200中的开关提供驱动信号。
其中,所述检测电路401可以检测所述第一变换电路200输出的电压,得到第一电压的电压值,并将所述第一电压的电压值输出给所述斜坡补偿电路403和所述放大电路402;所述放大电路402可以对所述第一电压的电压值与参考电压的电压值的误差进行放大处理,得到误差信号,并将所述误差信号输出给所述比较电路404;所述斜坡补偿电路403可以根据所述第一电压的电压值,生成斜坡补偿信号,并将所述斜坡补偿信号输出给所述比较电路404;所述比较电路404可以将所述斜坡补偿信号和所述误差信号进行比较,得到比较信号,并将所述比较信号输出给所述信号生成电路405;所述信号生成电路405可以根据所述比较信号,生成第一变换电路200的驱动信号。
实际使用时,为了降低检测电路401的检测成本以及与检测电路401连接的器件的数据处理成本,本申请实施例提供的控制装置400还可以包括分压电路。其中,分压支路可以由多个串联的分压电阻构成。
具体地,分压电路的输入端与第一变换电路200的输出端连接,分压电路的输出端与检测电路401的输入端连接,分压电路可以将第一变换电路200的输出电压进行降压处理,得到第一电压,并将第一电压输出给检测电路。
实际应用中,控制装置400可以固定在第一变换电路200上。在另一种实现方式中,控制装置400也可以设置成灵活可拆卸的形式,即第一变换电路200上设有固定接口,以实现控制装置400与第一变换电路200的连接,在这种情况下,控制装置400可以视为独立于第一变换电路200的装置。
本申请中,控制装置400可以通过为第一变换电路200中开关提供相应的驱动信号,来调整开关的工作状态,从而控制第一变换电路200的输出电压的电压值。
采用本申请实施例提供的控制装置400生成第一变换电路200中开关的驱动信号时,驱动信号生成电路405主要通过比较信号生成驱动信号,而比较信号的生成主要通过误差信号和斜坡补偿信号的比较结果生成的,由于放大电路402输出误差信号的速度较慢,可以利用第一电压的电压值进行斜坡补偿,进行斜坡补偿后的斜坡补偿信号的幅值发生变化,导致斜坡补偿信号与误差信号的差值为零的时刻发生偏移,从而改变了比较信号的电平翻转时刻,相应的信号生成电路405生成的驱动信号的发送时刻也发生改变,从而实现及时对输出电压的变化进行响应,并对驱动信号进行相应的调整。
具体地,控制装置400可以与第一变换电路200的输入端连接的输入端电源连接,该输入电源可以为控制装置400供电。
应理解,若直接通过输入电源对控制装置400供电,输入电源输出的电压可能难以满足控制装置400对供电电压的需要,因此,输入电源与控制装置400之间还可以连接有直流转换器,该直流转换器将输入电源输出的电压进行电压转换处理,从而输出控制装置400可用的供电电压。
下面,对控制装置400中的检测电路401、放大电路402、斜坡补偿电路403、比较电路404和信号生成电路405的具体结构进行介绍。
一、检测电路401
检测电路401的输入端可以分压电路的输出端连接,检测电路401的输出端分别与放大电路402和斜坡补偿电路403连接,分压电路的输出端构成待检测点,将待检测点输出的电压值输出给所述斜坡补偿电路403和所述放大电路402。
具体地,检测电路401可以为数据传输线,直接将待检测点的电压值直接输出给连接的器件。
需要说明的是,上述对检测电路401结构的介绍仅为示例,实际使用时,本申请提供的检测电路401还可以包括其它结构,例如,电压传感器,本申请这里不一一介绍。
二、放大电路402
放大电路402的输入端与检测电路401连接,放大电路402的输出端与比较电路404的输入端连接,放大电路402可以将检测电路401输出的所述第一电压的电压值与参考电压的电压值之间的误差进行放大处理,得到误差信号,并将所述误差信号输出给所述比较电路404。
在一示例中,放大电路402可以包括运行放大器,运算放大器的同相输入端接收参考电压,运算放大器的反相输入端与检测电路401连接,用于接收检测电路401输出的第二电压,运算放大器的输出端与所述比较电路404和斜坡补偿电路403连接,用于输出误差信号。
三、斜坡补偿电路403
斜坡补偿电路403分别与检测电路401的输出端和比较电路404的输入端连接,所述斜坡补偿电路403可以根据所述检测电路301输出的所述第一电压的电压值,对斜坡信号进行补偿,得到斜坡补偿信号,并将所述斜坡补偿信号输出给所述比较电路404。
其中,斜坡补偿电路403包括:斜坡信号补偿模块4031和控制模块4032。
具体地,所述斜坡信号补偿模块4031分别与所述检测电路401的输出端和控制模块连接,所述斜坡信号补偿模块4031用于根据所述第二电压,生成所述斜坡补偿信号;所述控制模块4032与所述比较电路404连接,所述控制模块4032根据所述比较信号控制所述斜坡信号补偿模块4032的工作状态。
具体地,根据斜坡信号补偿模块4031的补偿位置的不同,本申请实施例中的斜坡信号补偿模块具有两种电路结构,下面结合实施例两种电路结构下的斜坡补偿过程分别进行介绍。
实施例一、
斜坡信号补偿模块4031包括:第一开关S1、第二开关S2、第三开关S3、第一电流源I1、第二电流源I2和第一电容C1。
具体地,参见图6所示,所述第一开关S1的第一电极用于与第一电源VCC1连接,所述第一开关S1的第二电极所述第一电流源I1的第一端连接;所述第一电源I1的第二端与所述第一电容C1的第一端、所述第二开关S2的第一电极和第三开关S3的第一电极连接;所述第二开关S2的第二电极与所述第一电容C1的第二端连接;所述第三开关S3的第二电极与所述第二电流源I2的第一端连接;所述第二电流源I2的第二端与所述第一电容C1的第二端连接;所述第一电容C1的第二端与所述检测电路401的输出端连接,所述第一电容C1的第一端与所述比较电路404连接;所述第一开关S1的控制电极、所述第二开关S2的控制电极和所述第三开关S3的控制电极均与所述控制模块连接。
实际使用时,为了实现斜坡补偿信号与第一变换电路200输出端之间的隔离,第一电容C1的第二端与检测电路之间还连接有电压跟随器。
采用上述斜坡信号补偿模块,由于第一电容C1的第二端与检测电路401连接,接收 检测电路401输出的第一电压的电压值,可以通过控制第一电容C1的充放电速度,使第一变换电路200的输出电压到达目标值时,第一电容C1的放电电压值与目标值之和与误差信号的幅值相等,则第一电容C1的输出的斜坡补偿信号的幅值与误差信号的差值为零,比较电路404输出比较信号,并生成相应的驱动信号对第一变换电路200的工作状态进行控制。其中,斜坡补偿信号的周期可以与第一变换电路200中开关的驱动信号周期一致。
具体地,所述第一开关S1的控制电极、所述第二开关S2的控制电极和所述第三开关S3的控制电极均与所述控制模块4032连接,控制模块4032通过控制上述三个开关的工作状态,控制斜坡信号补偿模块4031生成斜坡补偿信号。
具体实现时,斜坡信号补偿模块主要通过第一电容C1的充放电实现输出斜坡补偿信号。第一电容C1的充放电状态可以通过调节斜坡信号补偿模块中开关的工作状态来实现。
本申请实施例,控制模块4032可以通过调整多个开关工作状态实现控制斜坡信号补偿模块4031进行斜坡补偿,得到斜坡补偿信号。
下面结合图6,对控制模块4032的具体结构以及控制斜坡信号补偿模块4031进行斜坡补偿的过程进行详细说明。
如图7所示,为本申请实施例提供的一种控制模块4032的结构示意图。参见图7所示,控制模块4032包括:第一RS触发器RS1、第二RS触发器RS2、第一定时器TD1、第二定时器TD2和第一反相器Z1。
图7所示的控制模块4032中个器件的连接关系可以是:所述第一RS触发器RS1的第一端与所述比较电路404的输出端连接,所述第一RS触发器RS1的第二端与所述第一定时器TD1的第一端连接,所述第一RS触发器RS1的输出端与所述第一开关S1的控制电极、所述第一反相器Z1的输入端和所述第一定时器TD1的第二端连接;所述第二RS触发器RS2的第一端与所述比较电路连接,所述第二RS触发器RS2的第二端与所述第二定时器TD2的第一端连接,所述第二RS触发器RS2的输出端与所述第二开关S2的控制电极和第二定时器TD2的第二端连接;所述第一反相器Z1的输出端与所述第三开关S3的控制电极连接。
采用上述控制模块4032控制斜坡信号补偿模块4031中多个开关的工作状态时,若比较电路404输出高电平信号,触发器RS1的置位端S和触发器RS2的置位端S均接收到高电平信号,此时触发器RS1和触发器RS2的输出端输出高电平信号,此时开关S1和开关S2会因控制电极接收高电平信号而导通,此时第一电容C1通过开关S2进行放电。同时,定时器TD1和定时器TD2开始计时,由于比较电路404的两个输入端口接收的信号一直处于变化状态,则比较电路404输出高电平信号的时长较短,触发器RS1的置位端S和触发器RS2的置位端S接收的信号会很快由高电平状态转换为低电平状态,由于定时器TD1和定时器TD2的定时时间未到达,则TD1和TD2输出低电平信号,触发器RS1和触发器RS1的输出端状态保持不变,开关S1和开关S2维持导通状态。当第一电容C1放电完毕,TD2的定时时间到达,此时触发器RS2输出端出低电平信号,开关S2因控制电极接收低电平信号而断开,开关S1维持导通状态,电流源I1通过开关S1向第一电容C1恒流充电,当电容C1充电完毕,此时定时器TD1的定时时间到达,TD1输出高电平信号,触发器RS1输出端输出的信号由高电平翻转为低电平,开关S1因控制电极接收低电平信号而截止,Z1的输出端输出高电平信号,第一电容C1通过开关S3和电流源I2进行恒流放电。
实际使用时,当第一变换电路200的输出电压达到目标值时,第一电容C1的放电电压值和目标值之和为误差信号的幅值,比较电路404可以在第一变换电路200的输出电压为目标值对应的时刻生成相应的驱动信号,从而实现第一变换电路200的输出电压满足负载对电压的需求。
实际使用时,通过控制第一电容C1进行充放电生成斜坡信号,通过在第一电容C1的第二端叠加第一电压的电压值实现对第一电容C1生成的斜坡信号进行补偿,得到斜坡补偿信号。
采用上述斜坡补偿方式,虽然第一电容C1的充放电过程以及充放电时间未发生变化,但是由于第一电容C1的第二端叠加了第一电压的电压值,在该情况下,第一电容C1第一端输出的斜坡补偿信号的幅值也会发生变化,相应的斜坡补偿信号与误差信号之差为零的时刻点向前偏移,从而有效的消除由于放大电路输出信号缓慢造成的响应慢的问题,使输出电压满足负载的需求。
如图8所示,为本申请实施例提供的另一种控制模块4032的结构示意图。参见图8所示,控制模块4032包括:第三RS触发器RS3、第四RS触发器RS4、第五RS触发器RS5、第三定时器TD3、第四定时器TD4和第五定时器TD5。
图8所示的控制模块4031中个器件的连接关系可以是:所述第三RS触发器RS3的第一端与所述比较电路的输出端连接,所述第三RS触发器RS3的第二端与所述第三定时器TD3的第一端和所述第四定时器TD4的第一端连接,所述第三RS触发器RS3的输出端与所述第一开关S1的控制电极和所述第三定时器TD3的第二端连接;所述第四RS触发器RS4的第一端与所述第四定时器TD4的第二端连接,所述第四RS触发器RS4的第二端与所述比较电路连接,所述第四RS触发器RS4的输出端与所述第三开关S3的控制电极连接;所述第五RS触发器RS5的第一端与所述比较电路连接,所述第五RS触发器RS5的第二端与所述第五定时器TD5的第一端连接,所述第五RS触发器RS5的输出端与所述第二开关S2的控制电极和所述第五定时器TD5的第二端连接。
采用上述控制模块4032控制斜坡信号补偿模块4031中多个开关的工作状态时,若比较电路404输出高电平信号,触发器RS3的置位端S和触发器RS5的置位端S均接收到高电平信号,此时触发器RS3和触发器RS5的输出端输出高电平信号,开关S1和开关S2会因控制电极接收高电平信号而导通,此时电容C1通过开关S2进行放电。同时,定时器TD3、定时器TD4和定时器TD5开始计时,由于比较电路404的两个输入端口接收的信号一直处于变化状态,则比较电路404输出电平信号的时长较短,出发RS3的置位端S和触发器RS5的置位端S接收的信号会很快由高电平转换为低电平状态,由于定时器TD3、定时器TD4和定时器TD5的定时时间未到达,定时器TD3、定时器TD4和定时器TD5输出低电平信号,此时开关S1和开关S2维持导通状态,开关S3截止,当电容C1放电完毕,TD5的定时时间到达,此时触发器RS5输出低电平信号,开关S2截止,开关S1维持导通状态,电流源I1通过开关S1向电容C1恒流充电,当电容C1充电完毕,此时定时器TD3和定时器TD4的定时时间到达,TD3输出高电平信号,RS3触发器输出端输出的信号由高电平翻转为低电平,开关S1因控制电极接收低电平信号而截止,RS4输出高电平信号,开关S3的控制端因承受高电平信号而导通,此时电容C1通过开关S3和电流源I2恒流放电。
在一种可能的实现方式中,TD4的定时时长高于TD3的定时时长,当TD3的定时时 间达到时,TD3输出高电平信号,RS3触发器输出端输出的信号由高电平状态翻转为低电平装填,开关S1因控制电极接收信号而截止,此时第一电容C1维持当前状态,待TD4定时时间达到,RS4输出高电平信号,开关S3的控制端因承受高电平信号而导通,此时电容C1通过开关S3和电流源I2恒流放电。
需要说明的是,虽然第一电容C1的充放电过程以及充放电时间未发生变化,但是由于第一电容C1的第二端叠加了第一电压的电压值,在该情况下,第一电容C1第一端输出的斜坡补偿信号的幅值也会发生变化,相应的斜坡补偿信号与误差信号之差为零的时刻点发生偏移,从而对输出电压的变化快速响应。
需要说明的是,上述对控制模块结构的介绍仅为示例,实际使用时,本申请提供的控制模块还可以包括其它结构,例如,可以采用延时器替代控制模块中的定时器,本申请这里不一一介绍。
实施例二、
其中,斜坡信号补偿模块4031包括:第四开关S4、第五开关S5、第六开关S6、第二电容C2、第三电流源I3、第四电流源I4和加法器∑。
具体地,参见图9所示,所述第五开关S5的第二电极与所述第六开关S6的第二电极连接;所述第六开关S6的第二电极与所述第四电流源I4的第一端连接;所述第四电流源I4的第二端与所述第二电容C2的第二端连接;所述第二电容C2的第二端用于接收所述参考电压,所述第二电容C2的第一端与所述加法器∑的第一输入端连接;所述加法器∑的第二端与所述检测电路连接,所述加法器∑的输出端与所述比较电路连接;所述第四开关S4的控制电极、所述第五开关S5的控制电极和所述第六开关S6的控制电极均与所述第一控制模块连接。
采用上述斜坡信号补偿模块4031,可以通过控制第二电容C2的充放电时间,调整斜坡补偿信号的幅值,由于加法器∑的第一输入端与第二电容C2的第一端连接,接收第二电容C2输出的斜坡信号,加法器∑的第二输入端与检测电路401连接,接收检测电路401输出的第二电压,加法器∑将第二信号和斜坡信号进行叠加输出斜坡补偿信号。
具体地,所述第四开关S4的控制电极、第五开关S5的控制电极和第六开关S6的控制电极均与所述控制模块4032连接,控制模块4032通过控制上述三个开关的工作状态,控制斜坡信号补偿模块4031生成斜坡补偿信号。
下面结合图9,对控制模块4032的具体结构进行详细说明。
如图10所示,为本申请实施例提供的一种控制模块4032的结构示意图。参见图10所示,控制模块包括:第一RS触发器RS1、第二RS触发器RS2、第一定时器TD1、第二定时器TD2和第一反相器Z1。
图10所示的控制模块中个器件的连接关系可以是:所述第一RS触发器RS1的第一端与所述比较电路的输出端连接,所述第一RS触发器RS1的第二端与所述第一定时器TD1的第一端连接,所述第一RS触发器RS1的输出端与所述第四开关S4的控制电极、所述第一反相器Z1的输入端和所述第一定时器TD1的第二端连接;所述第二RS触发器RS2的第一端与所述比较电路连接,所述第二RS触发器RS2的第二端与所述第二定时器TD2的第一端连接,所述第二RS触发器RS2的输出端与所述第一开关S1的控制电极和第二定时器TD2的第二端连接;所述第一反相器Z1的输出端与所述第二开关S2的控制电极连接。
应理解,图10所示的控制模块4031控制第二电容C2充放电的过程,与上述控制模块4032控制第一电容C1充放电的过程相同,本申请这里不做重复介绍。
如图11所示,为本申请实施例提供的另一种控制模块的结构示意图。参见图11所示,控制电路包括:第三RS触发器RS3、第四RS触发器RS4、第五RS触发器RS5、第三定时器TD3、第四定时器TD4和第五定时器TD5。
图11所示的控制模块中个器件的连接关系可以是:所述第三RS触发器RS3的第一端与所述比较电路的输出端连接,所述第三RS触发器RS3的第二端与所述第三定时器TD3的第一端和所述第四定时器TD4的第一端连接,所述第三RS触发器RS3的输出端与所述第四开关S4的控制电极和所述第三定时器TD3的第二端连接;所述第四RS触发器RS4的第一端与所述第四定时器TD4的第二端连接,所述第四RS触发器RS4的第二端与所述比较电路连接,所述第四RS触发器RS4的输出端与所述第二开关S2的控制电极连接;所述第五RS触发器RS5的第一端与所述比较电路连接,所述第五RS触发器RS5的第二端与所述第五定时器TD5的第一端连接,所述第五RS触发器RS5的输出端与所述第一开关S1的控制电极和所述第五定时器TD5的第二端连接。
应理解,图11所示的控制模块4031控制第二电容C2充放电的过程,与上述控制模块4032控制第一电容C1充放电的过程相同,本申请这里不做重复介绍。
应理解,图9所示的斜坡补偿电路主要通过加法器∑叠加检测电路401输出的第二电压进行斜坡补偿,下面结合对法器∑的具体进行说明。
具体实现时,加法器∑具体可以包括:第一电阻R1、第二电阻R2、第五电流源I5、第七开关S7、第八开关S8、第九开关S9、第十开关S10、第十一开关S11、第十二开关S12、第十三开关S13。
具体地,参见图12所示,所述第七开关S7的第一电极与第三电源VCC3连接,所述第十一开关的S11的第二电极与所述第十开关S10的第一电极和第十一开关S11的第一电极连接,所述第七开关S7的控制电极与所述第八开关S8的控制电极和所述第九开关S9的控制电极连接;所述第八开关S8的第一电极与第三电源VCC3连接,所述第十二开关的S12的第二电极与所述第十二开关S12的第一电极和第十三开关S13的第一电极连接;所述第九开关S9的第一电极与第三电源VCC3连接,所述第十三开关的S13的第二电极与所述第五电流源I5的第一端连接;所述第五电流源I5的第二端与地线连接;所述第十开关S10的第二电极与所述比较电路和第一电阻R1的第一端连接,所述第十开关S10的控制电极与所述第二电容C2的第一端连接;所述第十一开关S11的第二电极与所述比较电路和所述第二电阻R2的第一端连接,所述第十一开关S11的控制电极用于接收所述参考电压;所述第十二开关S12的第二电极与所述比较电路和所述第一电阻R1的第一端连接,所述第十二开关S12的控制电极与所述检测电路连接;所述第十三开关S13的第二电极与所述比较电路和所述第二电阻R2的第一端连接,所述第十三开关S13的控制电极用于接收所述参考电压;所述第一电阻R1的第二端与所述地线连接;所述第二电阻R2的第二端与所述地线连接。其中,所述第七开关S7的控制电极与所述第八开关S8的控制电极、所述第九开关S9的控制电极和第九开关S9的第二电极连接。
具体实现是,斜坡信号补偿模块第二电容C2的第二端叠加了参考电压,开关S15接收参考电压,来消除第二电容C2输出的斜坡补偿信号中叠加的参考电压对比较电路输出的比较信号时间的影响,并利用开关S16叠加检测电路401输出的第一电压的电压值。
四、比较电路404
比较电路404分别与放大电路402、斜坡补偿电路403和信号生成电路405连接,比较电路404可以将放大电路402输出的误差信号和斜坡补偿电路403输出的斜坡补偿信号进行比较,并将比较结果作为比较信号,将比较信号输出给信号生成电路405。
实际使用时,根据斜坡补偿电路403中斜坡信号补偿模块4031补偿方式的不同,本申请实施例中的比较电路中存在两种电路结构。
在一种可能的实现方式,若斜坡信号补偿模块4031采用图6所示斜坡信号补偿模块进行斜坡信号补偿时,比较电路404可以直接采用比较器。
具体地,该比较器的反相输入端可以与第一电容C1的第一端连接,接收第一电容C1输出的斜坡补偿信号,比较器的正相输入端可以与放大电路302的输出端连接,接收放大电路302输出的误差信号,比较器的输出端与信号生成电路405连接。该比较器将输入端接收的斜坡补偿信号和误差信号进行比较,并将比较结果输出给信号生成电路405。
在一种可能的实现方式,若斜坡信号补偿模块4031采用图10所示的斜坡信号补偿模块进行斜坡补偿时,比较电路404可以包括:第十四开关S14、第十五开关S15、第十六开关S16和第一比较器COMP1。
具体地,参见图13所示,所述第十四开关S14第一电极与第三电源VCC3连接,所述第十四开关S14的第二电极分别与所述第十五开关S15的第一电极和第十六开关S16的第一电极连接,所述第十四开关S14的控制电极与所述第七开关S7的控制电极连接;
所述第十五开关S15的第二电极与所述第一比较器COPM1的第一输入端连接,所述第十五开关S15的控制电极用于接收所述参考信号;所述第十六开关S16的第二电极与所述第一比较器COMP1的第二输入端连接,所述第十六开关S16的控制电极与所述放大电路连接;所述第一比较器COMP1的第一输入端与所述第十开关S10的第二电极和所述第十二开关S12的第二电极连接,所述第一比较器COMP1的第二输入端与所述第十一开关S11的第二电极和所述第十三开关S13的第二电极连接,所述第一比较器COMP1的输出端与所述信号生成电路连接。
需要说明的是,图12所示的加法器中,利用开关S16和开关S17中叠加了一个第一电压与参考电压之差,可以利用开关S19的控制电极接收参考电压进行补偿电压补偿,以满足保证比较器COMP1的信号翻转时刻满足输出电压的要求。
五、信号生成电路405
信号生成电路405与比较电路404连接,信号生成电路405还与第一变换电路200的开关连接,信号生成电路405可以根据比较电路404输出的比较信号生成第一变换电路200的驱动信号。
其中,所述信号生成电路405可以包括:分频模块4051、第一信号生成模块4052和第二信号生成模块4053。
具体地,参见图14所示,所述分频模块4051的输入端与所述比较电路404连接,所述分频模块4051的输出端与所述第一信号生成模块4052和所述第二信号生成模块4053连接,所述分频模块4051用于对所述比较电路404输出的比较信号进行分频处理,得到第一分频信号和第二分频信号,并将所述第一分频信号输出给所述第一信号生成模块4052,将所述第二分频模块输出给所述第二信号生成模块4053;所述第一信号生成模块4052可以根据所述第一分频信号和所述第一变换电路200的电压转换比,生成第一驱动信号;所 述第二信号生成模块4053可以根据所述第二分频信号和所述第一变换电路200的电压转换比,生成第二驱动信号。
在一种可能的实现方式中,若第一变换电路200为二电平变换电路,第一变换电路200中包括第一组开关和第二组开关,其中,第一组开关闭合时,输入电源可以向第一变换电路中的输出电感充电。当第一组开关断开、且第二组开关闭合时,输出电感通过第二组开关进行续流。此时,第一变换电路200的驱动信号包括第一驱动信号和第二驱动信号。
具体地,第一信号生成模块4052可以与第一组开关连接,并向第一组开关输出第一驱动信号。第二信号生成模块4053可以与第二组开关连接,并向第二组开关输出第二驱动信号。
在一种可能的实现方式中,若第一变换电路200为三电平变换电路,第一变换电路200中包括第一组开关、第二组开关、第三组开关和第四组开关。其中,第一变换电路200的结构可参见图1所示,第一变换电路200的驱动信号包括第一驱动信号、第二驱动信号、第三驱动信号和第四驱动信号。
具体地,第一信号生成模块4052可以与第一组开关和第三组开关连接,第一信号生成模块4052可以生成第一驱动信号和第三驱动信号,并将第一驱动信号输出给第一组开关,以及将第三驱动信号输出给第二组开关。第二信号生成模块4053可以与第二组开关和第四组开关连接,第二信号生成模块4053可以生成第二驱动信号和第四驱动信号,并将第二驱动信号输出给第二组开关,以及将第四驱动信号输出给第四组开关。
下面给出分频模块4051、第一信号生成模块4052和第二信号生成模块4053的具体结构。
具体的,所述第一信号生成模块4052包括:第一导通时间控制模块和第一逻辑模块。所述第二信号生成模块4053包括:第二导通时间控制模块和第二逻辑模块。
其中,所述第一导通时间控制模块与所述第一变换电路200的输入端、所述第一变换电路200的输出端和所述分频模块连接,所述第一导通时间控制模块用于在接收到所述第一分频信号后,根据所述第一变换电路200的输入电压和所述第一变换电路200的输出电压的比较结果,生成第一导通时间控制信号;所述第一逻辑模块分别与所述第一导通时间控制模块和所述分频模块连接,根据所述第一导通时间控制信号和所述第一分频信号,生成所述第一驱动信号;所述第二导通时间控制模块与所述第一变换电路200的输入端、所述第一变换电路200的输出端和所述分频模块连接,所述第二导通时间控制模块用于在接收到所述第二分频信号后,根据所述第一变换电路200的输入电压和所述第一变换电路200的输出电压的比较结果,生成第二导通时间控制信号;所述第二逻辑模块分别与所述第二导通时间控制模块和所述分频模块连接,根据所述第二导通时间控制信号和所述第二分频信号,生成所述第二驱动信号。
在一种可能的实现方式中,第一逻辑模块还可以用于生成第三驱动信号,第二逻辑模块还可以用于生成第四驱动信号。
其中,设置第一导通时间控制模块的作用为:确定第一驱动信号的导通时长。设置第一逻辑模块的作用为:根据第一分频信号,确定第一驱动信号的周期,并根据第一驱动信号的导通时长,生成第一驱动信号。设置第二导通时间控制模块的作用为:确定第二驱动信号的导通时长。设置第二逻辑模块的作用是:根据第二分频信号,确定第二驱动信号的周期,并根据第二驱动信号的导通时长,生成第二驱动信号。
为了便于理解,下面给出分频模块4051、第一信号生成模块4052和第二信号生成模块4053的具体示例。
图15为本申请实施例提供的分频模块4051的结构示意图。在图15中,分频模块4051可以包括D触发器,反相器D1、第一与门电路D2和第二与门电路D3。其中,D触发器的时钟输入端作为分频模块的输入端,与比较电路的输入端连接,第一与门电路D2的输出端作为分频模块的第一输出端,与第一信号生成模块连接,第二与门电路D3的输出端作为分频模块的第二输出端,与第二信号生成模块连接。
图15所示的分频模块中各器件的连接关系为:D触发器的时钟端口与比较电路404连接,D触发器的D输入端与D触发器的第二输入端和第二与门电路D3的第二输入端连接,D触发器的数据输出端与第一与门电路D2的第二输入端连接,第一与门电路D2的第一输入端与比较电路的输出端连接,第二与门电路D3的第一输入端与比较电路的输出端连接。
通过图15所示的分频模块4051对比较电路404输出的比较电路进行分频处理时,D触发器在比较信号的上升沿动作,当比较电路404输出的比较信号呈现高电平状态时,D触发器输出的信号进行一次翻转,以D触发器的初始状态为低电平信号,则D触发器的输出信号由低电平信号翻转为高电平信号,与门电路&1满足输出高电平的条件,&1的输出第一分频信号由低电平状态翻转为高电平信号,&2因接收到低电平信号第二分频信号维持低电平状态,当比较电路下次呈现高电平状态时,D触发器输出的信号由高电平状态翻转为低电平信号,此时&1的输入端接收到低电平信号,&2的两个输入端均接收高电平信号,&1输出的第一分频信号由高电平翻转为低电平,&2输出的第二分频信号由低电平翻转为高电平。其中,第一分频信号,第二分频信号和比较信号的波形示意图可参见图16所示。
应理解,第一分频信号和第二分频信号的周期相同,且彼此错相半个周期。
图17为本申请实施例提供的第一信号生成模块的结构示意图。参见图17所示,第三电阻R3、第四电阻R4、第五电阻R5、第十七开关S17、第三电容C3、第二比较器COMP2、第八RS触发器RS8和第八定时器TD8构成第一导通时间控制模块,第九RS触发器RS9构成第一逻辑模块。
图17所示的第一信号生成模块4052中各器件的连接关系为:所述第三电阻R3的第一端与所述第一变换电路200的输出端连接,所述第三电阻R3的第二端与所述第四电阻R4的第一端连接;所述第四电阻R4的第一端与所述第二比较器COMP2的第一输入端连接,所述第四电阻R4的第二端与所述地线连接;所述第五电阻R5的第一端与所述第一变换电路200的输入端连接,所述第五电阻R5的第二端与所述第十七开关S17的第一电极和所述第三电容C3的第一端连接;所述第三电容C3的第一端与所述第二比较器COMP2的第二输入端连接,所述第三电容C3的第二端与所述地线连接;所述第十七开关S17的第二电极与所述地线连接,所述第十七开关S17的控制电路与所述第八RS触发器RS8的输出端连接;所述第二比较器COMP2的输出端与所述第一逻辑模块和所述第八定时器TD8的第一端连接;所述第八RS触发器RS8的第一输入端与所述分频模块的输出端连接,所述第八RS触发器RS8的第二输入端与所述第八定时器TD8的第二端连接;所述第九RS触发器RS9的第一输入端与所述分频模块的输出端连接,所述第九RS触发器RS9的第二输入端与所述第一导通时间控制模块连接,所述第九RS触发器RS9的输出端用于与 开关S1连接。
实际使用时,若第一变换电路200为三电平变换电路,第一逻辑模块还包括第三反相器Z3。其中,所述第三反相器Z3的输入端与所述第九RS触发器RS9的输出端连接,所述第三反相器Z3的输出端与开关S4连接。
通过图17所示的第一信号生成模块生成第一驱动信号和第四驱动信号时,当第一分频信号为高电平状态时,触发器RS8因置位端S接收高电平信号为开关S17的控制电极提供低电平信号,开关S17断开,第一变换电路200的输入电压Vin为电容C3充电,当电容C3的第二端的电位高于电阻R3的第二端电位时,比较器COMP2输出信号由低电平翻转为高电平,若分频模块输出的第一分频信号为高电平状态,触发器RS9输出高电平给开关S1,反相器Z3将RS4输出的高电平反相得到低电平信号给开关S4。其中,触发器RS9输出第一驱动信号,反相Z3输出第四驱动信号。
同理,参见图18所示,为第二信号生成模块4053的结构示意图。参见图18所示,第六电阻R6、第七电阻R7、第八电阻R8、第二十一开关S22、第四电容C4、第三比较器COMP3、第十RS触发器RS10和第九定时器TD9构成第一导通时间控制模块,第十一RS触发器RS11构成第二逻辑模块。
图18所示的第一信号生成模块4052中各器件的连接关系为:所述第六电阻R6的第一端与所述第一变换电路200的输出端连接,所述第六电阻R6的第二端与所述第七电阻R7的第一端连接;所述第七电阻R7的第一端与所述第三比较器COMP3的第一输入端连接,所述第七电阻R7的第二端与所述地线连接;所述第八电阻R8的第一端与所述第一变换电路200的输入端连接,所述第八电阻R8的第二端与所述第十八开关S18的第一电极和所述第四电容C4的第一端连接;所述第四电容C4的第一端与所述第三比较器COMP3的第二输入端连接,所述第四电容C4的第二端与所述地线连接;所述第十八开关S18的第二电极与所述地线连接,所述第十八开关S18的控制电路与所述第十RS触发器RS10的输出端连接;所述第三比较器COMP3的输出端与所述第二逻辑模块和所述第九定时器TD9的第一端连接;所述第十RS触发器RS10的第一输入端与所述分频模块的输出端连接,所述第十RS触发器RS10的第二输入端与所述第九定时器TD9的第二端连接;所述第十一RS触发器RS11的第一输入端与所述分频模块的输出端连接,所述第十一RS触发器RS11的第二输入端与所述第二导通时间控制模块连接,所述第十一RS触发器RS11的输出端用于与所述开关S2连接。
实际使用时,若第一变换电路200为三电平变换电路,第二逻辑模块还包括第四反相器Z4。其中,所述第四反相器Z4的输入端与所述第十一RS触发器RS11的输出端连接,所述第四反相器Z4的输出端与所述开关S3连接。
需要说明的是,第二信号生成模块4053的工作原理与第一信号生成模块4052的工作原理相同,由于第一分频信号和第二分频信号彼此之间错相半个周期,因此,第一驱动信号和第二驱动信号之间也错相半个周期。
结合以上描述,示例地,本申请实施例提供的一种功率变换器,可以如图19所示。
在第一变换电路中,包括开关Q1/Q2/Q3/Q4,输出电感Lm和飞跨电容Cf。
在分压电路中,包括电阻R1和电阻R2。其中,电阻R1的第一端与第一变换电路200的输出端连接,电阻R1的第二端与电阻R2的第一端连接,电阻R2的第二端接地,电阻R1的第二端输出第一电压。其中,电阻R1的第二端构成待检测点与检测电路连接。
在检测电路中,包括数据传输线,该输出传输线与待检测点连接,将待检测点输出的第一电压的电压值输出给放大电路与斜坡补偿电路中。
在放大电路中,包括运算放大器U1。其中,U1的第一输入端与电阻R1的第二端连接,U1的第二输入端接收参考电压,U1的输出端输出误差信号。
在斜坡补偿电路中,包括开关S1、开关S2、开关S3、电容C1、跟随器U2、RS触发器RS1、RS触发器RS2、定时器TD1、定时器TD2、电流源I1、电流源I2和反相器Z1。其中,开关S1的第一电极与电源VCC1连接,所述开关S1的第二电极与电流源I1的第一端连接;电流源I1的第二端分别与所述电容C1的第一端、开关S3的第一电极和开关S3的第一电极连接;所述开关S2的第二电极与所述C1第二端连接;所述开关S3的第二电极与电流源I2的第一端连接;电流源I2的第二端与所述电容C1的第二端连接;所述电容C1的第二端与跟随器U2的输出端连接;跟随器U2的输入端与电阻R1的第二端连接;电容C1的第二端输出斜坡补偿信号;RS触发器RS1的第一端接收比较信号,RS触发器RS1的第二端与定时器TD1的第一端连接,RS触发器RS1的输出端与所述开关S1的控制电极、反相器Z1的输入端和定时器TD1的第二端连接;RS触发器RS2的第一端接收比较信号,RS触发器RS2的第二端与所述定时器TD2的第一端连接,RS触发器RS2的输出端与所述开关S2的控制电极和定时器TD2的第二端连接;反相器Z1的输出端与所述开关S3的控制电极连接。
在比较电路中,包括比较器COMP1。其中,比较器COMP1的第一输入端与U1的输出端连接,比较器COMP1的第二输入端与电容C1的第一端连接,比较器COMP1的输出端输出比较信号。
在信号生成电路中,包括二分频器、电阻R3、电阻R4、电阻R5、电阻R6、电阻R7、电阻R8、开关S4、开关S5、电容C2、电容C3、比较器COMP2、比较器COMP3、RS触发器RS3、RS触发器RS4、RS触发器RS5、RS触发器RS6、定时器TD3、定时器TD4、反相器Z2和反相器Z3。其中,电阻R3的第一端与所述第一变换电路的输出端连接,电阻R3的第二端与电阻R4的第一端连接;电阻R4的第一端与比较器COMP2的第一输入端连接,电阻R4的第二端与所述地线连接;电阻R5的第一端与所述第一变换电路的输入端连接,所述第五电阻R5的第二端与开关S4的第一电极和电容C2的第一端连接;电容C2的第一端与所述第二比较器COMP2的第二输入端连接,电容C2的第二端与所述地线连接;开关S4的第二电极与所述地线连接,开关S4的控制电极与触发器RS3的输出端连接;所述第二比较器COMP2的输出端与RS触发器RS4的R端连接和定时器TD3的输入端连接;触发器RS3的S端与二分频器的第一输入端连接,触发器RS3的R端与定时器TD3的输出端连接;触发器RS4的S端与二分频器的第一输出端连接,触发器RS4的输出端与开关Q1的控制电极和反相器Z2的输入端连接;反相器Z2的输出端与开关Q4的输出端连接。电阻R6的第一端与所述第一变换电路的输出端连接,电阻R6的第二端与电阻R7的第一端连接;电阻R7的第一端与比较器COMP3的第一输入端连接,电阻R4的第二端与所述地线连接;电阻R8的第一端与所述第一变换电路的输入端连接,所述第五电阻R8的第二端与开关S5的第一电极和电容C3的第一端连接;电容C3的第一端与所述比较器COMP3的第二输入端连接,电容C3的第二端与所述地线连接;开关S5的第二电极与所述地线连接,开关S5的控制电极与触发器RS5的输出端连接;比较器COMP5的输出端与RS触发器RS6的R端连接和定时器TD4的输入端连接;触发器RS5的S端 与二分频器的第二输入端连接,触发器RS5的R端与定时器TD4的输出端连接;触发器RS6的S端与二分频器的第二输出端连接,触发器RS6的输出端与开关Q2的控制电极和反相器Z3的输入端连接;反相器Z3的输出端与开关Q3的输出端连接。
采用上述功率变换器,当第一变换电路的输出电压发生变化时,检测电路中的电阻R1和R2对输出电压进行降压处理,得到第一电压,并将第一电压的电压值分别输出给斜坡补偿电路和放大电路,电容C1按照固定周期输出斜坡信号,电容C1的第二端叠加第一电压的电压值,即电容C1第一端输出斜坡补偿信号的幅值为电容C1充电值与第一电压的电压值之和。当输出电压达到目标值时,第一电压的电压值与电容C1的充电值之和为U1的误差信号的幅值,COMP1输出比较信号为高电平的时间向前偏移,而COMP1输出端连接二分频器,而二分频器分别连接触发器RS4和RS6的置位端S,当S端为1时,则输出一次驱动信号,从而实现改变开关的驱动信号,对第一变换电路的工作状态进行调整,从而有效的避免了由于U1输出信号缓慢导致的驱动延迟问题,使输出电压满足负载的需求。
具体地,参见图20所示,COMP1的反相输入端接收电容C1的放电电压与第一电压的电压值之和,COMP1的正相输入端接收U1输出的电压,当第一变换电路的输出电压达到目标值时,COMP1正相输入端与反相输入端接收的电位相等,比较信号由低电平翻转为高电平,该比较信号经过二分频器分频后输出第一分频信号和第二分频信号,第一分频信号和第二分频信号经过触发器RS4和RS6后,向开关Q1和Q4输出高电平驱动信号,开关Q1和Q4开启,输入电源向第一变换电路的输出电感充电,输出电流上升,输出电压达到允许的最低值后,输出电压上升,由于驱动信号的波形固定,输出电压可以按照固定规律在特定范围内波形,保证输出电压稳定,满足负载的需求。
应理解,上述控制装置可以通过控制斜坡补偿信号对输出电感Lm的输出波形补偿,从而调整驱动信号的周期,而信号生成电路中的COMP2和COMP3分别连接触发器RS4和RS6的R端,可以通过调整COMP2和COMP3调整驱动信号维持高电平的时间,从而实现调整驱动信号占空比的目的。
需要说明的是,上述对功率变换器结构的介绍仅为示例,实际使用时,根据第一变换电路结构以及斜坡补偿电路的不同,本申请提供的功率变换器还可以包括其它结构,由于其它结构下的工作原理相同,本申请这里不一一介绍。
实际使用时,为了提升功率变换器的转换功率,功率变换器中该包括至少一个第二变换器电路,第一变换电路的输出端与每个第二变换电路的输出端并联,则多个变换器电路的输出电压相同,为了降低多个变换电路的控制成本,本申请实施例提供的控制装置中的所述信号生成电路还包括:与每个所述第二变换电路对应的第三信号生成模块和第四信号生成模块。
其中,参见图21所示,所述分频模块与每个所述第三信号生成模块和每个所述第四信号生成模块连接,所述分频模块还用于对所述比较信号进行分频处理,得到与每个所述第三信号生成模块一一对应的第三分频信号和与每个所述第四信号生成模块一一对应的第四分频信号;每个所述第三信号生成模块与所述分频模块连接,所述第三信号生成模块用于接收对应的第三分频信号,并根据接收的所述第三分频信号和对应的第二变换电路的电压转换比,生成第五驱动信号;所述第四信号生成模块与所述分频模块连接,所述第四信号生成模块用于接收对应的第四分频信号,并根据接收的第四分频信号和对应的所述第二变换电路的电压转换比,生成第六驱动信号;将所述五驱动信号和所述第六驱动信号输出 给对应的第二变换电路。其中,所述五驱动信号和所述第六驱动信号构成对应的第二变换电路的驱动信号。需要说明的是,当第二变换电路为三电平变换电路,第三信号生成模块还可以生成第七驱动信号,第四信号生成模块还可以生成第八驱动信号,并将第七驱动信号和第八期读懂信号输出给对应的第二变换电路。
具体实现时,若第二变换电路的数量为1,则分频电路为四分频器。
基于同一发明构思,本申请实施例还提供了一种功率变换方法,该方法应用于功率变换器上,该功率变换器可以包括变换电路以及与变换电路连接的控制装置。参见图22,该方法具体包括以下步骤:
步骤2201、检测变换电路的输出电压,得到第一电压的电压值。
步骤2202、利用第一电压的电压值生成斜坡补偿信号。
步骤2203、根据将第一电压的电压值与参考电压的电压值之间的误差,得到误差信号。
步骤2204、将斜坡补偿信号和误差信号进行比较,得到比较信号。
步骤2205、根据比较信号,生成变换电路的驱动信号。
具体地,功率变换器的结构如图可参见图4至图22所示,本申请这里不做重复介绍。
在一种可能的实现方式中,所述利用所述第一电压的电压值生成斜坡补偿信号,包括:将所述第一电压的电压值与斜坡信号进行叠加,得到所述斜坡补偿信号。
在一种可能的实现方式中,若所述变换电路为二电平变换电路,所述根据所述比较信号,生成所述变换电路的驱动信号,包括:对所述比较信号进行分频,得到第一分频信号和第二分频信号;根据所述第一分频信号和所述变换电路的电压转换比,生成第一驱动信号;根据所述第二分频信号和所述变换电路的电压转换比,生成第二驱动信号;所述变换电路的驱动信号包括所述第一驱动信号和所述第二驱动信号。
在一种可能的实现方式中,若所述变换电路为三电平变换电路,所述根据所述比较信号,生成所述变换电路的驱动信号,包括:对所述比较信号进行分频,得到第一分频信号和第二分频信号;根据所述第一分频信号和所述变换电路的电压转换比,生成第一驱动信号和第三驱动信号;根据所述第二分频信号和所述变换电路的电压转换,生成第二驱动信号和第四驱动信号。
基于同一发明构思,本申请实施例还提供一种电源适配器。该电源适配器包括壳体、连接端口和前述功率变换器。
需要说明的是,电源适配器中未详尽描述的实现方式及其技术效果可以参见功率变换器中的相关描述,此处不再赘述。
基于相同的技术构思,本申请实施例还提供一种电子设备,该电子设备可以包括电源、负载和前述功率变换器。
其中,功率变换器与电池连接,功率变换器可以对电池的输出电压进行变换,得到目标电压,并将目标电压输出给负载。
需要说明的是,电子设备中未详尽描述的实现方式及其技术效果可以参见功率变换器中的相关描述,此处不再赘述。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。

Claims (22)

  1. 一种功率变换器,其特征在于,包括第一变换电路以及与第一变换电路连接的控制装置,所述控制装置用于:
    检测所述第一变换电路的输出电压,得到第一电压的电压值;
    利用所述第一电压的电压值生成斜坡补偿信号;
    根据所述第一电压的电压值与参考电压的电压值之间的误差,得到误差信号;
    将所述斜坡补偿信号和所述误差信号进行比较,得到比较信号;
    根据所述比较信号,生成所述第一变换电路的驱动信号。
  2. 如权利要求1所述的功率变换器,其特征在于,所述控制装置包括检测电路、放大电路、斜坡补偿电路、比较电路和信号生成电路;
    所述检测电路的输入端与所述第一变换电路的输出端连接,所述检测电路的输出端与所述斜坡补偿电路和所述放大电路连接,所述检测电路用于检测所述第一变换电路输出电压,得到所述第一电压的电压值,并将所述第一电压的电压值输出给所述斜坡补偿电路和所述放大电路;
    所述放大电路与所述比较电路连接,所述放大电路用于对所述第一电压的电压值与所述参考电压的电压值的误差进行放大处理,得到误差信号,并将所述误差信号输出给所述比较电路;
    所述斜坡补偿电路与所述比较电路连接,所述斜坡补偿电路用于根据所述第一电压的电压值,生成所述斜坡补偿信号;
    所述比较电路与所述信号生成电路连接,所述比较电路用于将所述斜坡补偿信号和所述误差信号进行比较,得到所述比较信号,并将所述比较信号输出给所述信号生成电路;
    所述信号生成电路用于根据所述比较信号,生成所述第一变换电路的驱动信号。
  3. 如权利要求2所述的功率变换器,其特征在于,所述斜坡补偿电路包括:斜坡信号补偿模块和控制模块;
    所述斜坡信号补偿模块分别与所述检测电路和控制模块连接,所述斜坡信号生成模块用于根据所述第一电压的电压值,生成所述斜坡补偿信号;
    所述控制模块与所述比较电路连接,所述控制模块根据所述比较信号控制所述斜坡信号补偿模块的工作状态。
  4. 如权利要求3所述的功率变换器,其特征在于,所述斜坡信号补偿模块包括:第一开关S1、第二开关S2、第三开关S3、第一电流源I1、第二电流源I2和第一电容C1;
    所述第一开关S1的第一电极用于与第一电源VCC1连接,所述第一开关S1的第二电极所述第一电流源I1的第一端连接;
    所述第一电源I1的第二端与所述第一电容C1的第一端、所述第二开关S2的第一电极和第三开关S3的第一电极连接;
    所述第二开关S2的第二电极与所述第一电容C1的第二端连接;
    所述第三开关S3的第二电极与所述第二电流源I2的第一端连接;
    所述第二电流源I2的第二端与所述第一电容C1的第二端连接;
    所述第一电容C1的第二端与所述检测电路的输出端连接,所述第一电容C1的第一端与所述比较电路连接;
    所述第一开关S1的控制电极、所述第二开关S2的控制电极和所述第三开关S3的控制电极均与所述第一控制模块连接。
  5. 如权利要求4所述的功率变换器,其特征在于,所述控制模块包括:第一RS触发器RS1、第二RS触发器RS2、第一定时器TD1、第二定时器TD2和第一反相器Z1;
    所述第一RS触发器RS1的第一端与所述比较电路连接,所述第一RS触发器RS1的第二端与所述第一定时器TD1的第一端连接,所述第一RS触发器RS1的输出端与所述第一开关S1的控制电极、所述第一反相器Z1的输入端和所述第一定时器TD1的第二端连接;
    所述第二RS触发器RS2的第一端与所述比较电路连接,所述第二RS触发器RS2的第二端与所述第二定时器TD2的第一端连接,所述第二RS触发器RS2的输出端与所述第二开关S2的控制电极和第二定时器TD2的第二端连接;
    所述第一反相器Z1的输出端与所述第三开关S3的控制电极连接。
  6. 如权利要求4所述的功率变换器,其特征在于,所述控制模块包括:第三RS触发器RS3、第四RS触发器RS4、第五RS触发器RS5、第三定时器TD3、第四定时器TD4和第五定时器TD5;
    所述第三RS触发器RS3的第一端与所述比较电路连接,所述第三RS触发器RS3的第二端与所述第三定时器TD3的第一端和所述第四定时器TD4的第一端连接,所述第三RS触发器RS3的输出端与所述第一开关S1的控制电极和所述第三定时器TD3的第二端连接;
    所述第四RS触发器RS4的第一端与所述第四定时器TD4的第二端连接,所述第四RS触发器RS4的第二端与所述比较电路连接,所述第四RS触发器RS4的输出端与所述第三开关S3的控制电极连接;
    所述第五RS触发器RS5的第一端与所述比较电路连接,所述第五RS触发器RS5的第二端与所述第五定时器TD5的第一端连接,所述第五RS触发器RS5的输出端与所述第二开关S2的控制电极和所述第五定时器TD5的第二端连接。
  7. 如权利要求3所述的功率变换器,其特征在于,所述斜波信号补偿模块包括:第四开关S4、第五开关S5、第六开关S6、第二电容C2、第三电流源I3、第四电流源I4和加法器;
    所述第四开关S4的第一电极用于与第二电源VCC2连接,所述第四开关S4的第二电极与所述第三电流源I3的第一端连接;
    所述第三电流源I3的第二端分别与所述第二电容C2的第一端、所述第五开关S5的第一电极和第六开关S6的第一电极连接;
    所述第五开关S5的第二电极与所述第六开关S6的第二电极连接;
    所述第六开关S6的第二电极与所述第四电流源I4的第一端连接;
    所述第四电流源I4的第二端与所述第二电容C2的第二端连接;
    所述第二电容C2的第二端用于接收所述参考电压,所述第二电容C2的第一端与所述加法器的第一输入端连接;
    所述加法器的第二端与所述检测电路连接,所述加法器的输出端与所述比较电路连接;
    所述第四开关S4的控制电极、所述第五开关S5的控制电极和所述第六开关S6的控制电极均与所述第一控制模块连接。
  8. 如权利要求7所述的功率变换器,其特征在于,所述加法器包括:第五电流源I5、第七开关S7、第八开关S8、第九开关S9、第十开关S10、第十一开关S11、第十二开关S12、第十三开关S13、第一电阻R1和第二电阻R2;
    所述第七开关S7的第一电极与第三电源VCC3连接,所述第七开关的S7的第二电极与所述第十开关S10的第一电极和第十一开关S11的第一电极连接,所述第七开关S7的控制电极与所述第八开关S8的控制电极、所述第九开关S9的控制电极和所述第九开关S9的第二电极连接;
    所述第八开关S8的第一电极与第三电源VCC3连接,所述第八开关的S8的第二电极与所述第十二开关S12的第一电极和第十三开关S13的第一电极连接;
    所述第九开关S9的第一电极与第三电源VCC3连接,所述第九开关的S9的第二电极与所述第五电流源I5的第一端连接;
    所述第五电流源I5的第二端与地线连接;
    所述第十开关S10的第二电极与所述比较电路和所述第一电阻R1的第一端连接,所述第十开关S10的控制电极与所述第二电容C2的第一端连接;
    所述第十一开关S11的第二电极与所述比较电路和所述第二电阻R2的第一端连接,所述第十一开关S11的控制电极用于接收所述参考电压;
    所述第十二开关S12的第二电极与所述比较电路和所述第一电阻R1的第一端连接,所述第十二开关S12的控制电极与所述检测电路连接;
    所述第十三开关S13的第二电极与所述比较电路和所述第二电阻R2的第一端连接,所述第十三开关S13的控制电极用于接收所述参考电压;
    所述第一电阻R1的第二端与所述地线连接;
    所述第二电阻R2的第二端与所述地线连接。
  9. 如权利要求8所述的功率变换器,其特征在于,所述比较电路包括:第十四开关S14、第十五开关S15、第十六开关S16和第一比较器COMP1;
    所述第十四开关S14第一电极与所述第三电源VCC3连接,所述第十四开关S14的第二电极分别与所述第十五开关S15的第一电极和第十六开关S16的第一电极连接,所述第十四开关S14的控制电极与所述第七开关S7的控制电极连接;
    所述第十五开关S15的第二电极与所述第一比较器COPM1的第一输入端连接,所述第十五开关S15的控制电极用于接收所述参考信号;
    所述第十六开关S16的第二电极与所述第一比较器COMP1的第二输入端连接,所述第十六开关S16的控制电极与所述放大电路连接;
    所述第一比较器COMP1的第一输入端与所述第十开关S10的第二电极和所述第十二开关S12的第二电极连接,所述第一比较器COMP1的第二输入端与所述第十一开关S11的第二电极和所述第十三开关S13的第二电极连接,所述第一比较器COMP1的输出端与所述信号生成电路连接。
  10. 如权利要求2所述的功率变换器,其特征在于,所述信号生成电路包括:分频模块、第一信号生成模块和第二信号生成模块;
    所述分频模块的输入端与所述比较电路连接,所述分频模块的输出端与所述第一信号生成模块和所述第二信号生成模块连接,所述分频模块用于对所述比较信号进行分频处理,得到第一分频信号和第二分频信号,并将所述第一分频信号输出给所述第一信号生成模块, 将所述第二分频模块输出给所述第二信号生成模块;
    若所述第一变换电路为二电平变换电路,所述第一信号生成模块用于根据所述第一分频信号和所述第一变换电路的电压转换比,生成第一驱动信号;
    所述第二信号生成模块用于根据所述第二分频信号和所述第一变换电路的电压转换比,生成第二驱动信号;
    所述第一变换电路的驱动信号包括所述第一驱动信号和所述第二驱动信号。
  11. 如权利要求10所述的功率变换器,其特征在于,所述第一信号生成模块包括:第一导通时间控制模块和第一逻辑模块;
    所述第一导通时间控制模块与所述第一变换电路的输入端、所述第一变换电路的输出端和所述分频模块连接,所述第一导通时间控制模块用于在接收到所述第一分频信号后,根据所述第一变换电路的输入电压和所述第一变换电路的输出电压的比较结果,生成第一导通时间控制信号;
    所述第一逻辑模块分别与所述第一导通时间控制模块和所述分频模块连接,根据所述第一导通时间控制信号和所述第一分频信号,生成所述第一驱动信号;
    所述第二信号生成模块包括:第二导通时间控制模块和第二逻辑模块;
    所述第二导通时间控制模块与所述第一变换电路的输入端、所述第一变换电路的输出端和所述分频模块连接,所述第二导通时间控制模块用于在接收到所述第二分频信号后,根据所述第一变换电路的输入电压和所述第一变换电路的输出电压的比较结果,生成第二导通时间控制信号;
    所述第二逻辑模块分别与所述第二导通时间控制模块和所述分频模块连接,根据所述第二导通时间控制信号和所述第二分频信号,生成所述第二驱动信号。
  12. 如权利要求11所述的功率变换器,其特征在于,所述第一导通时间控制模块包括:第三电阻R3、第四电阻R4、第五电阻R5、第十七开关S17、第三电容C3、第二比较器COMP2、第八RS触发器RS8和第八定时器TD8;
    所述第三电阻R3的第一端与所述第一变换电路的输出端连接,所述第三电阻R3的第二端与所述第四电阻R4的第一端连接;
    所述第四电阻R4的第一端与所述第二比较器COMP2的第一输入端连接,所述第四电阻R4的第二端与所述地线连接;
    所述第五电阻R5的第一端与所述第一变换电路的输入端连接,所述第五电阻R5的第二端与所述第十七开关S17的第一电极和所述第三电容C3的第一端连接;
    所述第三电容C3的第一端与所述第二比较器COMP2的第二输入端连接,所述第三电容C3的第二端与所述地线连接;
    所述第十七开关S17的第二电极与所述地线连接,所述第十七开关S17的控制电路与所述第八RS触发器RS8的输出端连接;
    所述第二比较器COMP2的输出端与所述第一逻辑模块和所述第八定时器TD8的第一端连接;
    所述第八RS触发器RS8的第一输入端与所述分频模块的输出端连接,所述第八RS触发器RS8的第二输入端与所述第八定时器TD8的第二端连接。
  13. 如权利要求11或12所述的功率变换器,其特征在于,若所述第一变换电路为二电平变换电路,所述第一逻辑模块包括:第九RS触发器RS5;
    所述第九RS触发器RS5的第一输入端与所述分频模块的输出端连接,所述第九RS触发器RS5的第二输入端与所述第一导通时间控制模块连接,所述第九RS触发器RS5的输出端用于与所述第一变换电路的第一组开关连接,并向所述第一组开关输出所述第一驱动信号;所述第一组开关用于控制所述第一变换电路中电感充电。
  14. 如权利要求13所述的功率变换器,其特征在于,所述若所述第一变换电路为三电平变换电路,所述第一逻辑模块包括:第十RS触发器RS10和第三反相器Z3;
    所述第十RS触发器RS10的第一输入端与所述分频模块的输出端连接,所述第十RS触发器RS10的第二输入端与所述第一导通时间控制模块连接,所述第十RS触发器RS10的输出端用于与所述第一变换电路的第一组开关连接,并向所述第一组开关输出所述第一驱动信号;
    所述第三反相器Z3的输入端与所述第十RS触发器RS10的输出端连接,所述第三反相器Z3的输出端与所述第三组开关连接,并向所述第三组开关输出第三驱动信号;
    所述第一组开关、第二组开关、所述第三组开关和第四组开关串联连接,所述第一开关的第一端为所述第一变换电路的第一输入端,所述第四组开关的第二端为所述第一变换电路的第二输出端;
    所述第一组开关接收的所述第一驱动信号、所述第二组开关接收的所述第二驱动信号、所述第三组开关接收的所述第三驱动信号和所述第四组开关接收的第四驱动信号构成所述第一变换电路的驱动信号。
  15. 如权利要求8所述的功率变换器,其特征在于,所述控制装置还与至少一个第二变换电路连接,每个所述第二变换电路的输出端与所述第一变换电路的输出端并联,所述信号生成电路还包括:与每个所述第二变换电路对应的第三信号生成模块和第四信号生成模块;
    所述分频模块与每个所述第三信号生成模块和每个所述第四信号生成模块连接,所述分频模块还用于对所述比较信号进行分频处理,得到与每个所述第三信号生成模块一一对应的第三分频信号和与每个所述第四信号生成模块一一对应的第四分频信号;
    每个所述第三信号生成模块与所述分频模块连接,所述第三信号生成模块用于接收对应的第三分频信号,并根据接收的所述第三分频信号和对应的第二变换电路的电压转换比,生成第五驱动信号;
    所述第四信号生成模块与所述分频模块连接,所述第四信号生成模块用于接收对应的第四分频信号,并根据接收的第四分频信号和对应的所述第二变换电路的电压转换比,生成第六驱动信号;
    将所述五驱动信号和所述第六驱动信号输出给对应的第二变换电路。
  16. 如权利要求1-15中任一项所述的功率变换器,其特征在于,所述控制装置还包括:分压电路;
    所述分压电路的输入端与所述第一变换电路的输出端连接,所述分压电路的输出端与所述检测电路的输入端连接,所述分压电路用于将所述第一变换电路的输出电压进行降压处理,得到所述第一电压,并将所述第一电压输出给所述检测电路。
  17. 一种功率变换方法,其特征在于,包括:
    检测变换电路的输出电压,得到第一电压的电压值;
    利用所述第一电压的电压值生成斜坡补偿信号;
    根据将所述第一电压的电压值与参考电压的电压值之间的误差,得到误差信号;
    将所述斜坡补偿信号和所述误差信号进行比较,得到比较信号;
    根据所述比较信号,生成所述变换电路的驱动信号。
  18. 如权利要求17所述的方法,其特征在于,所述利用所述第一电压的电压值生成斜坡补偿信号,包括:
    将所述第一电压的电压值与斜坡信号进行叠加,得到所述斜坡补偿信号。
  19. 如权利要求17或18所述的方法,其特征在于,若所述变换电路为二电平变换电路,所述根据所述比较信号,生成所述变换电路的驱动信号,包括:
    对所述比较信号进行分频,得到第一分频信号和第二分频信号;
    根据所述第一分频信号和所述变换电路的电压转换比,生成第一驱动信号;
    根据所述第二分频信号和所述变换电路的电压转换比,生成第二驱动信号;
    所述变换电路的驱动信号包括所述第一驱动信号和所述第二驱动信号。
  20. 如权利要求19所述的方法,其特征在于,若所述变换电路为三电平变换电路,所述根据所述比较信号,生成所述变换电路的驱动信号,包括:
    对所述比较信号进行分频,得到第一分频信号和第二分频信号;
    根据所述第一分频信号和所述变换电路的电压转换比,生成第一驱动信号和第三驱动信号;
    根据所述第二分频信号和所述变换电路的电压转换,生成第二驱动信号和第四驱动信号。
  21. 一种电源适配器,其特征在于,包括壳体、连接端口以及如权利要求1-16任一项所述的功率变换器。
  22. 一种电子设备,其特征在于,包括:电池、负载和如权利要求1-16任一项所述的功率变换器;
    所述功率变换器与所述电池连接,所述功率变换器用于对所述电池的输出电压进行变换,得到目标电压,并将所述目标电压输出给所述负载。
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CN101924469A (zh) * 2010-08-06 2010-12-22 东南大学 具有快速瞬态响应的开关电源
US20160351146A1 (en) * 2015-05-25 2016-12-01 Rohm Co., Ltd. Switching power supply circuit, liquid crystal driving device, and liquid crystal display device
CN107104595A (zh) * 2017-05-16 2017-08-29 电子科技大学 适用于峰值电流模控制降压变换器的自适应斜坡补偿电路
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