WO2023065522A1 - 四阶前馈补偿运算放大器及其设计方法 - Google Patents

四阶前馈补偿运算放大器及其设计方法 Download PDF

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WO2023065522A1
WO2023065522A1 PCT/CN2021/140254 CN2021140254W WO2023065522A1 WO 2023065522 A1 WO2023065522 A1 WO 2023065522A1 CN 2021140254 W CN2021140254 W CN 2021140254W WO 2023065522 A1 WO2023065522 A1 WO 2023065522A1
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Prior art keywords
drain
pmos transistor
transistor
nmos transistor
operational amplifier
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PCT/CN2021/140254
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English (en)
French (fr)
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罗永双
陈凯让
王友华
万贤杰
董吉
冉波
朱璨
付东兵
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重庆吉芯科技有限公司
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Publication of WO2023065522A1 publication Critical patent/WO2023065522A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • H03F3/45201—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/38—Positive-feedback circuit arrangements without negative feedback

Definitions

  • the invention relates to the technical field of integrated circuits, in particular to a fourth-order feedforward compensation operational amplifier and a design method thereof.
  • the gain of the operational amplifier in its loop filter needs to meet two performance requirements: (1), a gain of at least 40dB is required within the signal bandwidth; (2) There needs to be a gain of 10-20dB at the Nyquist frequency of the modulator.
  • Traditional second-order Miller-compensated operational amplifiers are difficult to meet such performance requirements, and high-order multi-channel feedforward compensation operational amplifiers are suitable for such application scenarios.
  • X.Yang et al. calculated the transfer function of the fourth-order feedforward compensation operational amplifier, and obtained the positions of the four poles and three zeros of the operational amplifier, and then obtained the positions of the main circuit transconductance and the front transconductance of the operational amplifier.
  • the transconductance of the feed branch is constrained so that the three zeros are approximately equal and are all within the unity gain bandwidth of the amplifier, so that the designed feedforward operational amplifier maintains a gain of at least 40dB within a bandwidth of several hundred MHz, and at the same time it satisfies the condition Stability; but such a design method requires cumbersome mathematical operations when deriving the system transfer function of a high-order multi-channel feedforward operational amplifier. degree also increased.
  • the purpose of the present invention is to provide a technical solution of a fourth-order feedforward compensation operational amplifier for solving the above-mentioned technical problems.
  • a fourth-order feedforward compensation operational amplifier comprising a first transconductance amplifying unit, a second transconductance amplifying unit, a third transconductance amplifying unit, a fourth transconductance amplifying unit, a fifth transconductance amplifying unit, and a sixth transconductance amplifying unit an amplification unit and a seventh transconductance amplification unit;
  • the first transconductance amplifying unit, the second transconductance amplifying unit, the third transconductance amplifying unit and the fourth transconductance amplifying unit are cascaded in sequence, the first transconductance amplifying unit, the The second transconductance amplifying unit, the third transconductance amplifying unit and the fourth transconductance amplifying unit constitute a fourth-order operational amplifier path;
  • the input terminal of the fifth transconductance amplifying unit is connected to the output terminal of the first transconductance amplifying unit, the output terminal of the fifth transconductance amplifying unit is connected to the input terminal of the fourth transconductance amplifying unit, and the The first transconductance amplifying unit, the fifth transconductance amplifying unit and the fourth transconductance amplifying unit constitute a third-order operational amplifier path;
  • the input terminal of the sixth transconductance amplifying unit is connected to the output terminal of the first transconductance amplifying unit, the output terminal of the sixth transconductance amplifying unit is connected to the output terminal of the fourth transconductance amplifying unit, and the The first transconductance amplifying unit and the sixth transconductance amplifying unit form a second-order operational amplifier path;
  • the input terminal of the seventh transconductance amplifying unit is connected to the input terminal of the first transconductance amplifying unit, the output terminal of the seventh transconductance amplifying unit is connected to the output terminal of the fourth transconductance amplifying unit, and the The seventh transconductance amplifying unit constitutes a first-order operational amplifier path;
  • the first-order operational amplifier path performs feedforward compensation on the second-order operational amplifier path
  • the second-order operational amplifier path performs feed-forward compensation on the third-order operational amplifier path
  • the third-order operational amplifier path performs feed-forward compensation on the third-order operational amplifier path.
  • the fourth-order operational amplifier path performs feed-forward compensation.
  • the first transconductance amplifying unit adopts a cascode differential amplification structure
  • the first transconductance amplifying unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor , the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor, the source of the first PMOS transistor is connected to the operating voltage, and the gate of the first PMOS transistor is connected to the The drain of the first PMOS transistor, the source of the second PMOS transistor is connected to the operating voltage, the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor, and the second PMOS transistor is connected to the drain of the third PMOS transistor.
  • the drain of the second PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the second PMOS transistor is also connected to the drain of the first PMOS transistor, and the source of the third PMOS transistor is connected to the operating voltage,
  • the drain of the third PMOS transistor is also connected to the drain of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the operating voltage, and the gate of the fourth PMOS transistor is connected to the fourth PMOS transistor.
  • the drain of the PMOS transistor, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the first NMOS transistor is used as a differential output negative terminal, and the gate of the first NMOS transistor
  • the pole is connected to the first bias voltage
  • the source of the first NMOS transistor is connected to the drain of the second NMOS transistor
  • the gate of the second NMOS transistor is used as a positive differential input terminal
  • the gate of the second NMOS transistor is used as a positive differential input terminal.
  • the source is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the second bias voltage, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the second bias voltage.
  • the gate of the fourth NMOS transistor is used as a differential input negative terminal
  • the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor
  • the fifth NMOS transistor is connected to the source of the fifth NMOS transistor.
  • the gate of the NMOS transistor is connected to the first bias voltage
  • the drain of the fifth NMOS transistor is connected to the drain of the third PMOS transistor
  • the drain of the fifth NMOS transistor is used as a differential output positive terminal.
  • the second transconductance amplification unit adopts a differential amplification structure
  • the second transconductance amplification unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a sixth NMOS transistor , the seventh NMOS transistor and the eighth NMOS transistor, the source of the fifth PMOS transistor is connected to the operating voltage, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, and the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor.
  • the source of the PMOS transistor is connected to the operating voltage, the gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor , the drain of the sixth PMOS transistor is also connected to the drain of the fifth PMOS transistor, the source of the seventh PMOS transistor is connected to the operating voltage, and the drain of the seventh PMOS transistor is also connected to the The drain of the eighth PMOS transistor, the source of the eighth PMOS transistor is connected to the operating voltage, the gate of the eighth PMOS transistor is connected to the drain of the eighth PMOS transistor, and the drain of the sixth NMOS transistor.
  • the drain is connected to the drain of the fifth PMOS transistor, and the drain of the sixth NMOS transistor is used as a differential output negative terminal, the gate of the sixth NMOS transistor is used as a differential input positive terminal, and the sixth NMOS transistor
  • the source of the seventh NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NM
  • the third transconductance amplifying unit adopts a differential amplification structure with common-mode feedback
  • the third transconductance amplifying unit includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, A PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first operational amplifier, a first resistor and a second resistor, the source of the ninth PMOS transistor is connected to the operating voltage, and the first The gates of the nine PMOS transistors are used as the first differential input positive terminal, the drain of the ninth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the source of the tenth PMOS transistor is connected to the operating voltage, so The grid of the tenth PMOS transistor is connected to the grid of the eleventh PMOS transistor, the source of the eleventh PMOS transistor is connected to the operating voltage, and the drain of the eleventh PMOS transistor is connected to the first
  • the drains of the twelve PMOS transistors, the source of the twelfth PMOS transistor is connected to the operating voltage, the gate of the twelfth PMOS transistor is used as the first differential input negative terminal, and the drain of the ninth NMOS transistor connected to the drain of the ninth PMOS transistor, and the drain of the ninth NMOS transistor is used as a differential output negative terminal, the gate of the ninth NMOS transistor is used as a second differential input positive terminal, and the ninth NMOS transistor
  • the source of the transistor is connected to the drain of the tenth NMOS transistor, the gate of the tenth NMOS transistor is connected to the fourth bias voltage, the source of the tenth NMOS transistor is grounded, and the drain of the tenth NMOS transistor pole is also connected to the source of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor is used as the second differential input negative terminal, and the drain of the eleventh NMOS transistor is connected to the eleventh PMOS transistor
  • the fourth transconductance amplifying unit adopts a complementary differential amplification structure with common-mode feedback
  • the fourth transconductance amplifying unit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, The sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the second operational amplifier, the third resistor and the fourth resistor, all
  • the source of the thirteenth PMOS transistor is connected to the operating voltage
  • the gate of the thirteenth PMOS transistor is used as the first differential input positive terminal
  • the drain of the thirteenth PMOS transistor is connected to the fourteenth PMOS transistor.
  • the drain of the tube, the source of the fourteenth PMOS tube is connected to the operating voltage
  • the gate of the fourteenth PMOS tube is connected to the gate of the fifteenth PMOS tube
  • the fifteenth PMOS tube The source of the fifteenth PMOS transistor is connected to the operating voltage
  • the drain of the fifteenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor
  • the source of the sixteenth PMOS transistor is connected to the operating voltage
  • the drain of the sixteenth PMOS transistor is connected to the operating voltage.
  • the gate of the sixteenth PMOS transistor is used as the first differential input negative terminal
  • the source of the seventeenth PMOS transistor is connected to the operating voltage
  • the drain of the seventeenth PMOS transistor is connected to the fourteenth PMOS transistor.
  • the source of the eighteenth PMOS transistor is connected to the operating voltage
  • the drain of the eighteenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor
  • the drain of the twelfth NMOS transistor The pole is connected to the drain of the fourteenth PMOS transistor, and the drain of the twelfth NMOS transistor is used as a differential output negative terminal, and the gate of the twelfth NMOS transistor is connected to the gate of the seventeenth PMOS transistor.
  • the source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, and the gate of the thirteenth NMOS transistor is connected to the fifth bias voltage, so The source of the thirteenth NMOS transistor is grounded, the drain of the thirteenth NMOS transistor is also connected to the source of the fourteenth NMOS transistor, and the gate of the fourteenth NMOS transistor is connected to the eighteenth NMOS transistor.
  • the gate of the PMOS transistor is used as the second differential input negative terminal
  • the drain of the fourteenth NMOS transistor is connected to the drain of the fifteenth PMOS transistor
  • the drain of the fourteenth NMOS transistor is used as a differential output
  • the positive terminal, the non-inverting input terminal of the second operational amplifier is connected to the drain of the twelfth NMOS tube after the third resistor connected in series, and the non-inverting input terminal of the second operational amplifier is also connected through the series connected
  • the fourth resistor is connected to the drain of the fourteenth NMOS transistor, the inverting input terminal of the second operational amplifier is connected to the second reference signal, and the output terminal of the second operational amplifier is connected to the fourteenth PMOS transistor the grid.
  • the fifth transconductance amplifying unit adopts a differential amplification structure with common-mode feedback
  • the fifth transconductance amplifying unit includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, The twenty-second PMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, the third operational amplifier, the fifth resistor and the sixth resistor, the source of the nineteenth PMOS transistor is connected to the The working voltage, the gate of the nineteenth PMOS transistor is used as the first differential input positive terminal, the drain of the nineteenth PMOS transistor is connected to the drain of the twentieth PMOS transistor, and the twentieth PMOS transistor The source of the transistor is connected to the operating voltage, the gate of the twenty-first PMOS transistor is connected to the gate of the twenty-first PMOS transistor, and the source of the twenty-first PMOS transistor is connected to the operating voltage, The drain of the twenty-first PMOS transistor is connected to the drain of the twenty-second PMOS transistor, the source of the twenty-second PMOS
  • the gate is used as a first differential input negative terminal, the drain of the fifteenth NMOS transistor is connected to the drain of the nineteenth PMOS transistor, and the drain of the fifteenth NMOS transistor is used as a differential output negative terminal, so
  • the gate of the fifteenth NMOS transistor is used as the second differential input positive terminal, the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the gate of the sixteenth NMOS transistor is connected to The sixth bias voltage, the source of the sixteenth NMOS transistor is grounded, the drain of the sixteenth NMOS transistor is also connected to the source of the seventeenth NMOS transistor, and the gate of the seventeenth NMOS transistor Pole is used as the second differential input negative terminal, the drain of the seventeenth NMOS transistor is connected to the drain of the twenty-first PMOS transistor, and the drain of the seventeenth NMOS transistor is used as the differential output positive terminal, so
  • the non-inverting input terminal of the third operational amplifier is connected to the drain of the fifteenth NMOS
  • the sixth transconductance amplifying unit adopts a complementary differential amplification structure with common-mode feedback, and the sixth transconductance amplifying unit includes a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, and a twenty-fifth PMOS transistor.
  • the source of the twenty-third PMOS transistor is connected to the operating voltage
  • the gate of the twenty-third PMOS transistor is used as the first differential input positive terminal
  • the gate of the twenty-third PMOS transistor is The drain is connected to the drain of the twenty-fourth PMOS transistor
  • the source of the twenty-fourth PMOS transistor is connected to the operating voltage
  • the gate of the twenty-fourth PMOS transistor is connected to the twenty-fifth PMOS transistor.
  • the gate of the PMOS transistor, the source of the twenty-fifth PMOS transistor is connected to the operating voltage
  • the drain of the twenty-fifth PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor
  • the drain of the twenty-fifth PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor.
  • the source of the twenty-sixth PMOS transistor is connected to the operating voltage
  • the gate of the twenty-sixth PMOS transistor is used as the first differential input negative terminal
  • the source of the twenty-seventh PMOS transistor is connected to the operating voltage
  • the drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-fourth PMOS transistor
  • the source of the twenty-eighth PMOS transistor is connected to the operating voltage
  • the source of the twenty-eighth PMOS transistor is connected to the operating voltage.
  • the drain is connected to the drain of the twenty-fifth PMOS transistor, the drain of the eighteenth NMOS transistor is connected to the drain of the twenty-fourth PMOS transistor, and the drain of the eighteenth NMOS transistor is used as The negative terminal of the differential output, the gate of the eighteenth NMOS transistor is connected to the gate of the twenty-seventh PMOS transistor as the second differential input positive terminal, and the source of the eighteenth NMOS transistor is connected to the gate of the twenty-seventh PMOS transistor.
  • the drain of the nineteenth NMOS transistor, the gate of the nineteenth NMOS transistor is connected to the seventh bias voltage, the source of the nineteenth NMOS transistor is grounded, and the drain of the nineteenth NMOS transistor is also connected to the The source of the twentieth NMOS transistor, the gate of the twentieth NMOS transistor is connected to the gate of the twenty-eighth PMOS transistor and used as the second differential input negative terminal, the drain of the twentieth NMOS transistor
  • the pole is connected to the drain of the twenty-fifth PMOS transistor, and the drain of the twenty-fifth NMOS transistor is used as a positive differential output terminal, and the non-inverting input terminal of the fourth operational amplifier passes through the seventh resistor connected in series connected to the drain of the eighteenth NMOS transistor, the non-inverting input terminal of the fourth operational amplifier is also connected to the drain of the twentieth NMOS transistor through the eighth resistor connected in series, and the fourth operational amplifier The inverting input terminal of the fourth operational amplifier is connected to the fourth reference signal, and the output terminal of the
  • the seventh transconductance amplifying unit adopts a complementary differential amplification structure, and the seventh transconductance amplifying unit includes a twenty-ninth PMOS transistor, a thirty-first PMOS transistor, a thirty-first PMOS transistor, a thirty-first PMOS transistor, and a thirty-first PMOS transistor.
  • the source of the twenty-ninth PMOS transistor is connected to the operating voltage
  • the gate of the twenty-ninth PMOS transistor is connected to the drain of the twenty-ninth PMOS transistor
  • the drain of the twenty-ninth PMOS transistor is connected to the The drain of the 30th PMOS transistor
  • the source of the 30th PMOS transistor is connected to the operating voltage
  • the gate of the 30th PMOS transistor is connected to the drain of the 31st PMOS transistor
  • the source of the thirty-first PMOS transistor is connected to the operating voltage
  • the gate of the thirty-first PMOS transistor is connected to the drain of the thirty-first PMOS transistor
  • the drain of the thirty-first PMOS transistor The pole is connected to the drain of the thirty-second PMOS transistor
  • the drain of the thirty-third PMOS transistor is connected to the operating voltage, the drain of the thirty-third PMOS transistor is connected to the drain of the thirty-third PMOS transistor, and the thirty-third PMOS transistor is connected to the drain of the thirty-third PMOS transistor.
  • the sources of the four PMOS transistors are connected to the operating voltage, the drains of the thirty-fourth PMOS transistors are connected to the drains of the thirty-first PMOS transistors, and the drains of the twenty-first NMOS transistors are connected to the The drain of the thirtieth PMOS transistor, and the drain of the twenty-first NMOS transistor is used as a differential output negative terminal after being connected in series with the first capacitor, and the gate of the twenty-first NMOS transistor is connected to the The gate of the thirty-third PMOS transistor is used as a positive differential input terminal, the source of the twenty-first NMOS transistor is connected to the drain of the twenty-second NMOS transistor, and the drain of the twenty-second NMOS transistor is The gate is connected to the eighth bias
  • the gate of the twenty-third NMOS transistor is connected to the gate of the thirty-fourth PMOS transistor and used as a differential input negative terminal, and the drain of the twenty-third NMOS transistor is connected to the drain of the thirty-first PMOS transistor , and the drain of the twenty-third NMOS transistor is used as a differential output positive terminal after being connected in series with the second capacitor.
  • the fourth-order feedforward compensation operational amplifier is designed and completed based on a 65nm CMOS process.
  • a design method for a fourth-order feedforward compensation operational amplifier comprising the steps of:
  • first transconductance amplification unit a first transconductance amplification unit, a second transconductance amplification unit, a third transconductance amplification unit, a fourth transconductance amplification unit, a fifth transconductance amplification unit, a sixth transconductance amplification unit, and a seventh transconductance amplification unit;
  • first transconductance amplifying unit Using the first transconductance amplifying unit, the second transconductance amplifying unit, the third transconductance amplifying unit and the fourth transconductance amplifying unit to form a fourth-order operational amplifier path;
  • the fifth transconductance amplifying unit and the fourth transconductance amplifying unit to form a third-order operational amplifier path, and through the third-order operational amplifier path to the fourth-order operational amplifier path for feed-forward compensation;
  • a first-order operational amplifier path is formed by using the seventh transconductance amplification unit, and feedforward compensation is performed on the second-order operational amplifier path through the first-order operational amplifier path.
  • the first transconductance amplification unit is formed based on cascode differential amplification technology
  • the second transconductance amplification unit is formed based on differential amplification technology
  • the third transconductance amplification unit is formed based on common-mode feedback differential amplification technology.
  • the transconductance amplifying unit and the fifth transconductance amplifying unit, the fourth transconductance amplifying unit and the sixth transconductance amplifying unit are formed based on a complementary differential amplification technology of common mode feedback
  • the fourth transconductance amplifying unit is formed based on a complementary differential amplification technology
  • the seventh transconductance amplification unit is formed based on cascode differential amplification technology
  • the second transconductance amplification unit is formed based on differential amplification technology
  • the third transconductance amplification unit is formed based on common-mode feedback differential amplification technology.
  • the fourth-order feedforward compensation operational amplifier and its design method of the present invention have at least the following beneficial effects:
  • the highest-order path of the fourth-order feedforward compensation operational amplifier is the fourth-order operational amplifier path, and the gain of the operational amplifier increases with the increase of the cascaded order, and the DC gain of the fourth-order feedforward compensation operational amplifier can be approximately equal to its
  • the DC gain of the fourth-order op-amp path is based on "the first-order op-amp path feed-forward compensates the second-order op-amp path, the second-order op-amp path feed-forward compensates the third-order op-amp path, and the third-order op-amp path compensates the fourth-order op-amp path.”
  • the structural design of the first-order operational amplifier path for feed-forward compensation the zero point generated by the adjacent two-order operational amplifier path is equal to the zero point of the equivalent second-order feedforward operational amplifier except the common part, so it is easy to design according to this structure.
  • the poles of the transfer function are determined by each node, according to the parasitic capacitance of each node and the output Impedance can get the corresponding pole. According to the obtained DC gain, three zeros and four poles, the transfer function of the fourth-order feedforward compensation operational amplifier can be obtained.
  • the fourth-order feedforward compensation operational amplifier Based on the circuit structure design of the fourth-order feedforward compensation operational amplifier , its transfer function can be easily obtained; in addition, based on the obtained transfer function and the gain requirement of the continuous-time bandpass sigma-delta modulator, the transconductance of each transconductance in the fourth-order feedforward compensation operational amplifier can be deduced inversely According to the transconductance constraint relationship between amplifying units, each transconductance amplifying unit is selected and designed according to the corresponding transconductance constraint relationship, and the formed fourth-order feedforward compensation operational amplifier can effectively meet the use of continuous time bandpass sigma-delta modulator need.
  • FIG. 1 is a schematic diagram showing the steps of the design method of the fourth-order feed-forward compensation operational amplifier in the present invention.
  • FIG. 2 is a schematic structural diagram of a fourth-order feedforward compensation operational amplifier in the present invention.
  • FIG. 3 is a circuit structure diagram of the first transconductance amplifying unit g m1 in an embodiment of the present invention.
  • FIG. 4 is a circuit structure diagram of the second transconductance amplifying unit g m2 in an embodiment of the present invention.
  • FIG. 5 is a circuit structure diagram of the third transconductance amplifying unit g m3 in an embodiment of the present invention.
  • FIG. 6 is a circuit structure diagram of the fourth transconductance amplifying unit g m4 in an embodiment of the present invention.
  • FIG. 7 is a circuit structure diagram of the fifth transconductance amplifying unit g m5 in an embodiment of the present invention.
  • FIG. 8 is a circuit structure diagram of the sixth transconductance amplifying unit g m6 in an embodiment of the present invention.
  • FIG. 9 is a circuit structure diagram of the seventh transconductance amplifying unit g m7 in an embodiment of the present invention.
  • FIG. 10 is a structural equivalent schematic diagram of a fourth-order feedforward compensation operational amplifier in the present invention.
  • Figure 11 shows a structural equivalent schematic diagram of a second-order feedforward compensation operational amplifier.
  • FIG. 12 is a schematic diagram of the amplitude-frequency response curve and the phase-frequency response curve of the fourth-order feedforward compensation operational amplifier in an embodiment of the present invention.
  • the inventor found that: for the continuous time bandpass sigma-delta modulator used for hundreds of MHz intermediate frequency, the traditional second-order Miller compensation operational amplifier is difficult to meet its gain performance requirements, and can only use High-order multi-channel feed-forward compensation operational amplifier, but with the increase in the order of high-order multi-channel feed-forward compensation operational amplifier and the increase in the complexity of its structure, it is difficult for designers to design a high-order multi-channel feed-forward that meets specific needs Compensation operational amplifier; in the prior art, either the system transfer function of the high-order multi-channel feedforward operational amplifier is derived based on cumbersome mathematical operations, and as the order of the amplifier increases or the structure of the amplifier system becomes more complicated, the calculation of its transfer function
  • the complexity also increases, either based on the code writing algorithm that completely abandons the physical structure, through the performance requirements of the feedforward operational amplifier to be designed and the physical constraints of the device process and based on the g m / ID method of operational amplifier design. The code is written to design the amplifier,
  • the present invention proposes a kind of design method of fourth-order feed-forward compensation operational amplifier, and it comprises steps:
  • the first transconductance amplification unit g m1 is formed based on cascode differential amplification technology
  • the second transconductance amplification unit g m2 is formed based on differential amplification technology
  • the differential amplification technology based on common mode feedback form the third transconductance amplifying unit g m3 and the fifth transconductance amplifying unit g m5
  • the amplification technique forms the seventh transconductance amplification unit g m7 .
  • steps S2 to S5 are executed to obtain a fourth-order feedforward compensation operational amplifier as shown in Figure 2, which includes a first transconductance amplifying unit g m1 , a second transconductance amplifying unit g m2 , and a third transconductance amplifying unit g m3 , the fourth transconductance amplifying unit g m4 , the fifth transconductance amplifying unit g m5 , the sixth transconductance amplifying unit g m6 and the seventh transconductance amplifying unit g m7 ; the first transconductance amplifying unit g m1 , the second The transconductance amplifying unit g m2 , the third transconductance amplifying unit g m3 and the fourth transconductance amplifying unit g m4 are sequentially cascaded to form a fourth-order operational amplifier path; the input terminal of the fifth transconductance amplifying unit g m5 is
  • the fourth-order feedforward compensation operational amplifier of the present invention is designed and completed based on a 65nm CMOS process.
  • the first transconductance amplifying unit g m1 adopts a cascode differential amplification structure
  • the first transconductance amplifying unit g m1 includes a first PMOS transistor P1, The second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4 and the fifth NMOS transistor N5, the first The source of the PMOS transistor P1 is connected to the working voltage VDD, the gate of the first PMOS transistor P1 is connected to the drain of the first PMOS transistor P1, the source of the second PMOS transistor P2 is connected to the working voltage VDD, and the gate of the second PMOS transistor P2 The drain of the third PMOS transistor P3 is connected, the drain of the second PMOS transistor P2 is connected to the gate of the third PMOS transistor P3, the drain of the second PMOS transistor P2 is also connected to the first PMOS transistor P1, The second PMOS transistor P2, the third PM
  • the source of the transistor P3 is connected to the working voltage VDD
  • the drain of the third PMOS transistor P3 is also connected to the drain of the fourth PMOS transistor P4
  • the source of the fourth PMOS transistor P4 is connected to the working voltage VDD
  • the gate of the fourth PMOS transistor P4 The drain of the fourth PMOS transistor P4 is connected, the drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and the drain of the first NMOS transistor N1 is used as the differential output negative terminal V A- , the first NMOS transistor
  • the gate of N1 is connected to the first bias voltage V B1
  • the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2
  • the gate of the second NMOS transistor N2 is used as a differential input positive terminal V IN+
  • the source of the transistor N2 is connected to the drain of the third NMOS transistor N3, the gate of the third NMOS transistor N3 is connected to the
  • the second transconductance amplifying unit gm2 adopts a differential amplification structure
  • the second transconductance amplifying unit gm2 includes a fifth PMOS transistor P5 and a sixth PMOS transistor P6 , the seventh PMOS transistor P7, the eighth PMOS transistor P8, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8, the source of the fifth PMOS transistor P5 is connected to the working voltage VDD, and the source of the fifth PMOS transistor P5
  • the gate is connected to the drain of the fifth PMOS transistor P5, the source of the sixth PMOS transistor P6 is connected to the working voltage VDD, the gate of the sixth PMOS transistor P6 is connected to the drain of the seventh PMOS transistor P7, and the drain of the sixth PMOS transistor P6
  • the pole is connected to the gate of the seventh PMOS transistor P7, the drain of the sixth PMOS transistor P6 is also connected to the drain of the fifth PMOS transistor P5,
  • the third transconductance amplifying unit gm3 adopts a differential amplification structure with common-mode feedback
  • the third transconductance amplifying unit gm3 includes a ninth PMOS transistor P9, The tenth PMOS transistor P10, the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the first operational amplifier A1, the first resistor R1 and The second resistor R2, the source of the ninth PMOS transistor P9 is connected to the working voltage VDD, the gate of the ninth PMOS transistor P9 is used as the first differential input positive terminal V B+ , and the drain of the ninth PMOS transistor P9 is connected to the tenth PMOS transistor P10 The drain of the tenth PMOS transistor P10 is connected to the working voltage VDD, the gate of the tenth PMOS transistor P10 is connected to the gate of the
  • the drain of the nine NMOS transistor N9, the non-inverting input terminal of the first operational amplifier A1 is also connected to the drain of the eleventh NMOS transistor N11 after the second resistor R2 connected in series, and the inverting input terminal of the first operational amplifier A1 is connected to the first Referring to the signal V ref1 , the output terminal of the first operational amplifier A1 is connected to the gate of the tenth PMOS transistor P10 .
  • the fourth transconductance amplifying unit gm4 adopts a complementary differential amplification structure with common-mode feedback
  • the fourth transconductance amplifying unit gm4 includes a thirteenth PMOS transistor P13, fourteenth PMOS transistor P14, fifteenth PMOS transistor P15, sixteenth PMOS transistor P16, seventeenth PMOS transistor P17, eighteenth PMOS transistor P18, twelfth NMOS transistor N12, thirteenth NMOS transistor N13 , the fourteenth NMOS transistor N14, the second operational amplifier A2, the third resistor R3 and the fourth resistor R4, the source of the thirteenth PMOS transistor P13 is connected to the working voltage VDD, and the gate of the thirteenth PMOS transistor P13 serves as the first Differential input positive terminal V C+ , the drain of the thirteenth PMOS transistor P13 is connected to the drain of the fourteenth PMOS transistor P14, the source of the fourteenth PMOS transistor P14 is connected to the operating voltage V
  • the fifth transconductance amplifying unit gm5 adopts a differential amplification structure with common-mode feedback
  • the fifth transconductance amplifying unit gm5 includes a nineteenth PMOS transistor P19 , 20th PMOS transistor P20, 21st PMOS transistor P21, 22nd PMOS transistor P22, 15th NMOS transistor N15, 16th NMOS transistor N16, 17th NMOS transistor N17, 3rd operational amplifier A3 , the fifth resistor R5 and the sixth resistor R6, the source of the nineteenth PMOS transistor P19 is connected to the working voltage VDD, the gate of the nineteenth PMOS transistor P19 is used as the first differential input positive terminal V B+ , the nineteenth PMOS transistor P19
  • the drain of the twentieth PMOS transistor P20 is connected to the drain of the twentieth PMOS transistor P20, the source of the twentieth PMOS transistor P20 is connected to the operating voltage VDD, the gate of the twentieth PMOS transistor P20 is connected to the gate of the twenty
  • the sixth transconductance amplifying unit gm6 adopts a complementary differential amplification structure with common-mode feedback
  • the sixth transconductance amplifying unit gm6 includes a twenty-third PMOS Tube P23, twenty-fourth PMOS tube P24, twenty-fifth PMOS tube P25, twenty-sixth PMOS tube P26, twenty-seventh PMOS tube P27, twenty-eighth PMOS tube P28, eighteenth NMOS tube N18,
  • the gate of the transistor P23 is used as the first differential input positive terminal V C+
  • the drain of the twenty-third PMOS transistor P23 is connected to the drain of the twenty-fourth PMOS transistor P24
  • R7 is connected to the drain of the eighteenth NMOS transistor N18
  • the non-inverting input terminal of the fourth operational amplifier A4 is also connected to the drain of the twentieth NMOS transistor N20 after the eighth resistor R8 connected in series
  • the inverting input of the fourth operational amplifier A4 The input terminal is connected to the fourth reference signal V ref4
  • the output terminal of the fourth operational amplifier A4 is connected to the gate of the twenty-fourth PMOS transistor P24 .
  • the seventh transconductance amplifying unit gm7 adopts a complementary differential amplification structure
  • the seventh transconductance amplifying unit gm7 includes a twenty-ninth PMOS transistor P29, a third Tenth PMOS transistor P30, thirty-first PMOS transistor P31, thirty-second PMOS transistor P32, thirty-third PMOS transistor P33, thirty-fourth PMOS transistor P34, twenty-first NMOS transistor N21, twenty-second NMOS
  • the drain of the ninth PMOS transistor P29, the drain of the twenty-ninth PMOS transistor P29 is connected to the drain of the thirtieth PMOS transistor P30, the source of the thi
  • the source of the tube P34 is connected to the working voltage VDD
  • the drain of the thirty-fourth PMOS tube P34 is connected to the drain of the thirty-first PMOS tube P31
  • the drain of the twenty-first NMOS tube N21 is connected to the drain of the thirty-first PMOS tube P30
  • the drain of the twenty-first NMOS transistor is used as the differential output negative terminal V OUT- after being connected in series with the first capacitor C1
  • the gate of the twenty-first NMOS transistor N21 is connected to the gate of the thirty-third PMOS transistor P33
  • the gate is used as the differential input positive terminal V IN+
  • the source of the twenty-first NMOS transistor N21 is connected to the drain of the twenty-second NMOS transistor N22
  • the gate of the twenty-second NMOS transistor N22 is connected to the eighth bias voltage V B8
  • the source of the twenty-second NMOS transistor N22 is grounded
  • the drain of the twenty-second NMOS transistor N22 is also connected to the source of the twenty-
  • the conductance amplifying unit g m3 and the fourth transconductance amplifying unit g m4 constitute the fourth-order operational amplifier path, which is the main amplification path; the remaining fifth transconductance amplifying unit g m5 , the sixth transconductance amplifying unit g m6 and the seventh transconductance amplifying unit
  • the amplifying unit g m7 is three feedforward stages, the first transconductance amplifying unit g m1 , the fifth transconductance amplifying unit g m5 and the fourth transconductance amplifying unit g m4 form a third-order operational amplifier path, the first transconductance amplifying unit
  • the highest-order path of this fourth-order feedforward compensation operational amplifier is the first transconductance amplification unit g m1 , the second transconductance amplification unit g m2 , and the third transconductance amplification unit g m3 and the fourth transconductance amplifying unit g m4 form the fourth-order operational amplifier path, and the gain of the operational amplifier increases with the increase of the cascaded order, so the DC gain of the fourth-order feedforward compensation operational amplifier can be approximately equal to its
  • the DC gain of the fourth-order op amp path which is:
  • a 0 is the gain of the fourth-order feedforward compensation operational amplifier
  • a 1 -A 4 are respectively the first transconductance amplifying unit g m1 , the second transconductance amplifying unit g m2 , the third transconductance amplifying unit g m3 and Gain of the fourth transconductance amplifying unit g m4 .
  • capacitors C 1 -C 3 are the parasitic capacitances of nodes A, B, and C, respectively
  • capacitor C 4 is the sum of parasitic capacitances of output nodes and the load capacitance of the operational amplifier
  • resistors r 1 -r 3 are the parasitic capacitances of nodes A, B, and C, respectively.
  • the output impedance of the resistance r 4 is the parallel impedance of the output node output impedance and the load impedance.
  • transconductance amplification unit gma and transconductance amplification unit gmb
  • the feedforward branch is composed of transconductance amplification unit gmc
  • capacitors C a -C b are the parasitic capacitances of the nodes
  • resistors r a -r b are the output impedances of the nodes.
  • This feedforward op amp system transfer function has a zero and can be expressed as:
  • ⁇ Z is the frequency zero point
  • G ma ⁇ G mc are the transconductance values of the transconductance amplification units g ma ⁇ g mc respectively.
  • the fourth-order op-amp path is compensated by the third-order op-amp path
  • the third-order op-amp path is compensated by the second-order op-amp path
  • the second-order op-amp path is compensated by the second-order op-amp path.
  • path is compensated by a first-order op amp path. In this way, three times of compensation will cause the operational amplifier to generate three zero points.
  • the zero points generated by the fourth-order operational amplifier path and the third-order operational amplifier path since the first transconductance amplification unit g m1 and the second transconductance amplification unit g m2 are shared by these two paths, the zero points generated by these two paths It is equal to the zero point generated by the second transconductance amplifying unit gm2 , the third transconductance amplifying unit gm3 and the fifth transconductance amplifying unit gm5 , and the zero point can be obtained by using formula (3):
  • ⁇ Z1 is the first frequency zero point
  • G m2 is the transconductance value of the second transconductance amplifying unit g m2
  • G m3 is the transconductance value of the third transconductance amplifying unit g m3
  • G m5 is the fifth transconductance Zoom in on the transconductance value of cell g m5 .
  • the zero point is related to the fourth transconductance amplification unit g m4 , the fifth transconductance amplification unit g m5 and the first transconductance amplification unit
  • the zero points generated by the six transconductance amplification units g m6 are equal, and can be expressed as:
  • ⁇ Z2 is the second frequency zero point
  • G m4 is the transconductance value of the fourth transconductance amplifying unit g m4
  • G m6 is the transconductance value of the sixth transconductance amplifying unit g m6 .
  • the zero point is related to the first transconductance amplification unit g m1 , the sixth transconductance amplification unit g m6 and the first transconductance amplification unit g m6
  • the zero points generated by the seven transconductance amplifying units g m7 are equal, and the zero point can be obtained by using formula (3):
  • ⁇ Z3 is the third frequency zero point
  • G m1 is the transconductance value of the first transconductance amplifying unit g m1
  • G m7 is the transconductance value of the seventh transconductance amplifying unit g m7 .
  • the present invention proposes a method for obtaining its system transfer function through an intuitive understanding of the system structure of the high-order multi-channel feedforward operational amplifier without complex mathematical derivation calculations, and the fourth-order feedforward compensation operational amplifier of the present invention Based on 65nm CMOS process design and implementation.
  • the implementation of the fourth-order feedforward compensation operational amplifier circuit stage utilizes such as current multiplexing technology, cascode structure, parallel structure of diode-connected transistor pairs and cross-coupled transistor pairs of the same size, and complementary differential class AB operation. Optimization techniques such as amplifier performance.
  • the first NMOS transistor N1 and the second NMOS transistor N2 in the first transconductance amplifying unit g m1 adopt a cascode structure to achieve high gain and reduce the noise contribution of the subsequent stage.
  • the first transconductance amplifying unit g m1 , the second transconductance amplifying unit g m2 and the seventh transconductance amplifying unit g m7 adopt diode-connected PMOS transistors and cross-coupled PMOS transistor pairs of the same size to simultaneously realize High gain and definite output DC voltage, however, in order to ensure sufficient output voltage swing of the operational amplifier, the third transconductance amplifying unit g m3 , the fourth transconductance amplifying unit g m4 , and the fifth transconductance amplifying unit Such technology is not adopted in g m5 and the sixth transconductance amplifying unit g m6 .
  • the transconductance of the feedforward branch of the operational amplifier is relatively large, so the third transconductance amplifying unit gm3 and the fourth transconductance amplifying unit gm4 can be realized by using a differential pair of PMOS transistors , while the feedforward branch transconductance fifth transconductance amplifying unit g m5 , sixth transconductance amplifying unit g m6 and seventh transconductance amplifying unit g m7 must be realized by using a differential pair of NMOS transistors with higher carrier mobility.
  • the current multiplexing technology is adopted in the fourth transconductance amplifying unit g m4 , the sixth transconductance amplifying unit g m6 and the seventh transconductance amplifying unit g m7 to reduce power consumption.
  • a corresponding fourth-order feedforward compensation operational amplifier is designed and implemented based on a 65nm CMOS process, and its amplitude-frequency response and phase-frequency response curves when driving a 400fF capacitive load are shown in Figure 12, As shown in Figure 12, the abscissa is uniformly Frequency (frequency), and the corresponding unit is Hertz (Hz), and the ordinate Magnitude and Phase are amplitude and phase, respectively, and the corresponding units are decibel (dB) and degree (deg).
  • the fourth-order feedforward compensation operational amplifier proposed by the present invention can meet the gain requirement of the operational amplifier in a continuous-time band-pass sigma-delta modulator with an intermediate frequency up to 340 MHz and a sampling frequency up to 2 GHz.
  • the highest-order path is the fourth-order operational amplifier path.
  • the gain of the operational amplifier increases with the increase of the cascaded order, and its DC gain can be approximately equal to the DC gain of its fourth-order op-amp path.
  • the structural design of the first-order sequential feed-forward compensation the zero point generated by the adjacent two-stage operational amplifier path is equal to the zero point equivalent to the second-order feedforward operational amplifier except for the common part, so it is easy to be based on this structure
  • the design obtains three zeros corresponding to the transfer function, and there is only a feedforward branch in the fourth-order feedforward compensation operational amplifier, and there is no feedback branch, so the poles of the transfer function are determined by each node, according to the parasitic capacitance of each node And the output impedance can get the corresponding pole, according to the obtained DC gain, three zeros and four poles, the transfer function of the fourth-order feedforward compensation operational amplifier can be obtained, based on the circuit of the fourth-order feedforward compensation operational amplifier structure design, it is easy to obtain its transfer function; in addition, based on the obtained transfer function and the gain requirement of the continuous-time band-pass sigma-delta modulator, it is possible to inversely deduce each of the fourth-order feedforward compensation operational amplifiers According

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Abstract

本发明提供一种四阶前馈补偿运算放大器及其设计方法，基于"以四阶运放路径为主，相邻两阶运放路径中较低的一阶对较高的一阶递次进行前馈补偿"的结构设计，很容易得到传递函数的增益和三个零点，且只有前馈支路、不存在反馈支路，可由节点参数得到四个极点，根据得到的直流增益、三个零点和四个极点，即可得到该四阶前馈补偿运算放大器的传递函数，也就是说基于该电路结构设计，很容易就能得出传递函数；基于得出的传递函数及连续时间带通sigma-delta调制器的增益需求，能推导出各跨导放大单元之间的跨导约束关系，按照对应的跨导约束关系对各跨导放大单元进行选择设计，形成的四阶前馈补偿运算放大器能有效满足连续时间带通sigma-delta调制器的使用需求。

Description

四阶前馈补偿运算放大器及其设计方法 技术领域
本发明涉及集成电路技术领域，特别是涉及一种四阶前馈补偿运算放大器及其设计方法。
背景技术
对于用于数百MHz中频的连续时间带通sigma-delta调制器，其环路滤波器中的运算放大器的增益需要满足两个性能要求：(1)、在信号带宽内需要至少40dB的增益；(2)、在调制器的奈奎斯特频率处需要有10-20dB的增益。传统的二阶Miller补偿的运算放大器难以满足这样的性能需求，高阶多路前馈补偿运算放大器正适用于这样的应用场景。
然而，由于随着其阶数的增加以及结构的复杂度增加使得设计者难以设计满足特定需求的高阶多路前馈补偿运算放大器。基于此，X.Yang等人通过计算四阶前馈补偿运算放大器的传递函数，得到了其运算放大器的四个极点和三个零点的位置，然后通过将运放放大器中主路跨导和前馈支路跨导进行约束使得三个零点大致相等，并且均处在放大器的单位增益带宽内，从而使得其设计的前馈运算放大器高达几百MHz带宽内保持至少40dB的增益，同时其满足条件稳定性；但是这样的设计方法在推导高阶多路前馈运算放大器的系统传递函数时需要进行繁琐的数学运算，随着放大器阶数的增加或者放大器系统结构变复杂的其传递函数计算的复杂度也随之增加。此外，F.T.Gebreyohannes等人提出了一种基于g m/I D方法设计用于连续时间带通sigma-delta调制器中运算放大器的算法，该算法将运算放大器中的每一个器件都设计成算法中的代码，通过对所需要设计的前馈运算放大器的性能的要求以及器件工艺物理约束且基于运放设计的g m/I D方法对代码进行编写来设计放大器。然而，利用这样的算法实现的运算放大器并没有对放大器电路本身进行分析和理解，失去了对高阶多路前馈运算放大器电路级的深入理解。
有鉴于此，目前亟需一种无需复杂的数学推导计算就能得出其系统传递函数且能有效深入分析其电路级结构的高阶多路前馈运算放大器。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种四阶前馈补偿运算放大器的技术方案，用于解决上述技术问题。
为实现上述目的及其他相关目的，本发明提供的技术方案如下。
一种四阶前馈补偿运算放大器，包括第一跨导放大单元、第二跨导放大单元、第三跨导 放大单元、第四跨导放大单元、第五跨导放大单元、第六跨导放大单元及第七跨导放大单元；
所述第一跨导放大单元、所述第二跨导放大单元、所述第三跨导放大单元及所述第四跨导放大单元依次级联，所述第一跨导放大单元、所述第二跨导放大单元、所述第三跨导放大单元及所述第四跨导放大单元构成四阶运放路径；
所述第五跨导放大单元的输入端接所述第一跨导放大单元的输出端，所述第五跨导放大单元的输出端接所述第四跨导放大单元的输入端，所述第一跨导放大单元、所述第五跨导放大单元及所述第四跨导放大单元构成三阶运放路径；
所述第六跨导放大单元的输入端接所述第一跨导放大单元的输出端，所述第六跨导放大单元的输出端接所述第四跨导放大单元的输出端，所述第一跨导放大单元及所述第六跨导放大单元构成二阶运放路径；
所述第七跨导放大单元的输入端接所述第一跨导放大单元的输入端，所述第七跨导放大单元的输出端接所述第四跨导放大单元的输出端，所述第七跨导放大单元构成一阶运放路径；
其中，所述一阶运放路径对所述二阶运放路径进行前馈补偿，所述二阶运放路径对所述三阶运放路径进行前馈补偿，所述三阶运放路径对所述四阶运放路径进行前馈补偿。
可选地，所述第一跨导放大单元采用共源共栅的差分放大结构，所述第一跨导放大单元包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管及第五NMOS管，所述第一PMOS管的源极接工作电压，所述第一PMOS管的栅极接所述第一PMOS管的漏极，所述第二PMOS管的源极接所述工作电压，所述第二PMOS管的栅极接所述第三PMOS管的漏极，所述第二PMOS管的漏极接所述第三PMOS管的栅极，所述第二PMOS管的漏极还接所述第一PMOS管的漏极，所述第三PMOS管的源极接所述工作电压，所述第三PMOS管的漏极还接所述第四PMOS管的漏极，所述第四PMOS管的源极接所述工作电压，所述第四PMOS管的栅极接所述第四PMOS管的漏极，所述第一NMOS管的漏极接所述第一PMOS管的漏极，且所述第一NMOS管的漏极作为差分输出负端，所述第一NMOS管的栅极接第一偏置电压，所述第一NMOS管的源极接所述第二NMOS管的漏极，所述第二NMOS管的栅极作为差分输入正端，所述第二NMOS管的源极接所述第三NMOS管的漏极，所述第三NMOS管的栅极接第二偏置电压，所述第三NMOS管的源极接地，所述第三NMOS管的漏极还接所述第四NMOS管的源极，所述第四NMOS管的栅极作为差分输入负端，所述第四NMOS管的漏极接所述第五NMOS管的源极，所述第五NMOS管的栅极接所述第一偏置电压，所述第五NMOS管的漏极接所述第三PMOS管的漏极，且所述第五NMOS管的漏极作为差分输出正端。
可选地，所述第二跨导放大单元采用差分放大结构，所述第二跨导放大单元包括第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第六NMOS管、第七NMOS管及第八NMOS管，所述第五PMOS管的源极接所述工作电压，所述第五PMOS管的栅极接所述第五PMOS管的漏极，所述第六PMOS管的源极接所述工作电压，所述第六PMOS管的栅极接所述第七PMOS管的漏极，所述第六PMOS管的漏极接所述第七PMOS管的栅极，所述第六PMOS管的漏极还接所述第五PMOS管的漏极，所述第七PMOS管的源极接所述工作电压，所述第七PMOS管的漏极还接所述第八PMOS管的漏极，所述第八PMOS管的源极接所述工作电压，所述第八PMOS管的栅极接所述第八PMOS管的漏极，所述第六NMOS管的漏极接所述第五PMOS管的漏极，且所述第六NMOS管的漏极作为差分输出负端，所述第六NMOS管的栅极作为差分输入正端，所述第六NMOS管的源极接所述第七NMOS管的漏极，所述第七NMOS管的栅极接第三偏置电压，所述第七NMOS管的源极接地，所述第七NMOS管的漏极还接所述第八NMOS管的源极，所述第八NMOS管的栅极作为差分输入负端，所述第八NMOS管的漏极接所述第七PMOS管的漏极，且所述第八NMOS管的漏极作为差分输出正端。
可选地，所述第三跨导放大单元采用具有共模反馈的差分放大结构，所述第三跨导放大单元包括第九PMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管、第一运算放大器、第一电阻及第二电阻，所述第九PMOS管的源极接所述工作电压，所述第九PMOS管的栅极作为第一差分输入正端，所述第九PMOS管的漏极接所述第十PMOS管的漏极，所述第十PMOS管的源极接所述工作电压，所述第十PMOS管的栅极接所述第十一PMOS管的栅极，所述第十一PMOS管的源极接所述工作电压，所述第十一PMOS管的漏极接所述第十二PMOS管的漏极，所述第十二PMOS管的源极接所述工作电压，所述第十二PMOS管的栅极作为第一差分输入负端，所述第九NMOS管的漏极接所述第九PMOS管的漏极，且所述第九NMOS管的漏极作为差分输出负端，所述第九NMOS管的栅极作为第二差分输入正端，所述第九NMOS管的源极接所述第十NMOS管的漏极，所述第十NMOS管的栅极接第四偏置电压，所述第十NMOS管的源极接地，所述第十NMOS管的漏极还接所述第十一NMOS管的源极，所述第十一NMOS管的栅极作为第二差分输入负端，所述第十一NMOS管的漏极接所述第十一PMOS管的漏极，且所述第十一NMOS管的漏极作为差分输出正端，所述第一运算放大器的同相输入端经串联的所述第一电阻后接所述第九NMOS管的漏极，所述第一运算放大器的同相输入端还经串联的所述第二电阻后接所述第十一NMOS管的漏极，所述第一运算放大器的反相输入端接第一参 考信号，所述第一运算放大器的输出端接所述第十PMOS管的栅极。
可选地，所述第四跨导放大单元采用具有共模反馈的互补差分放大结构，所述第四跨导放大单元包括第十三PMOS管、第十四PMOS管、第十五PMOS管、第十六PMOS管、第十七PMOS管、第十八PMOS管、第十二NMOS管、第十三NMOS管、第十四NMOS管、第二运算放大器、第三电阻及第四电阻，所述第十三PMOS管的源极接所述工作电压，所述第十三PMOS管的栅极作为第一差分输入正端，所述第十三PMOS管的漏极接所述第十四PMOS管的漏极，所述第十四PMOS管的源极接所述工作电压，所述第十四PMOS管的栅极接所述第十五PMOS管的栅极，所述第十五PMOS管的源极接所述工作电压，所述第十五PMOS管的漏极接所述第十六PMOS管的漏极，所述第十六PMOS管的源极接所述工作电压，所述第十六PMOS管的栅极作为第一差分输入负端，所述第十七PMOS管的源极接所述工作电压，所述第十七PMOS管的漏极接所述第十四PMOS管的漏极，所述第十八PMOS管的源极接所述工作电压，所述第十八PMOS管的漏极接所述第十五PMOS管的漏极，所述第十二NMOS管的漏极接所述第十四PMOS管的漏极，且所述第十二NMOS管的漏极作为差分输出负端，所述第十二NMOS管的栅极接所述第十七PMOS管的栅极并作为第二差分输入正端，所述第十二NMOS管的源极接所述第十三NMOS管的漏极，所述第十三NMOS管的栅极接第五偏置电压，所述第十三NMOS管的源极接地，所述第十三NMOS管的漏极还接所述第十四NMOS管的源极，所述第十四NMOS管的栅极接所述第十八PMOS管的栅极并作为第二差分输入负端，所述第十四NMOS管的漏极接所述第十五PMOS管的漏极，且所述第十四NMOS管的漏极作为差分输出正端，所述第二运算放大器的同相输入端经串联的所述第三电阻后接所述第十二NMOS管的漏极，所述第二运算放大器的同相输入端还经串联的所述第四电阻后接所述第十四NMOS管的漏极，所述第二运算放大器的反相输入端接第二参考信号，所述第二运算放大器的输出端接所述第十四PMOS管的栅极。
可选地，所述第五跨导放大单元采用具有共模反馈的差分放大结构，所述第五跨导放大单元包括第十九PMOS管、第二十PMOS管、第二十一PMOS管、第二十二PMOS管、第十五NMOS管、第十六NMOS管、第十七NMOS管、第三运算放大器、第五电阻及第六电阻，所述第十九PMOS管的源极接所述工作电压，所述第十九PMOS管的栅极作为第一差分输入正端，所述第十九PMOS管的漏极接所述第二十PMOS管的漏极，所述第二十PMOS管的源极接所述工作电压，所述第二十PMOS管的栅极接所述第二十一PMOS管的栅极，所述第二十一PMOS管的源极接所述工作电压，所述第二十一PMOS管的漏极接所述第二十二PMOS管的漏极，所述第二十二PMOS管的源极接所述工作电压，所述第二十二PMOS管的 栅极作为第一差分输入负端，所述第十五NMOS管的漏极接所述第十九PMOS管的漏极，且所述第十五NMOS管的漏极作为差分输出负端，所述第十五NMOS管的栅极作为第二差分输入正端，所述第十五NMOS管的源极接所述第十六NMOS管的漏极，所述第十六NMOS管的栅极接第六偏置电压，所述第十六NMOS管的源极接地，所述第十六NMOS管的漏极还接所述第十七NMOS管的源极，所述第十七NMOS管的栅极作为第二差分输入负端，所述第十七NMOS管的漏极接所述第二十一PMOS管的漏极，且所述第十七NMOS管的漏极作为差分输出正端，所述第三运算放大器的同相输入端经串联的所述第五电阻后接所述第十五NMOS管的漏极，所述第三运算放大器的同相输入端还经串联的所述第六电阻后接所述第十七NMOS管的漏极，所述第三运算放大器的反相输入端接第三参考信号，所述第三运算放大器的输出端接所述第二十PMOS管的栅极。
可选地，所述第六跨导放大单元采用具有共模反馈的互补差分放大结构，所述第六跨导放大单元包括第二十三PMOS管、第二十四PMOS管、第二十五PMOS管、第二十六PMOS管、第二十七PMOS管、第二十八PMOS管、第十八NMOS管、第十九NMOS管、第二十NMOS管、第四运算放大器、第七电阻及第八电阻，所述第二十三PMOS管的源极接所述工作电压，所述第二十三PMOS管的栅极作为第一差分输入正端，所述第二十三PMOS管的漏极接所述第二十四PMOS管的漏极，所述第二十四PMOS管的源极接所述工作电压，所述第二十四PMOS管的栅极接所述第二十五PMOS管的栅极，所述第二十五PMOS管的源极接所述工作电压，所述第二十五PMOS管的漏极接所述第二十六PMOS管的漏极，所述第二十六PMOS管的源极接所述工作电压，所述第二十六PMOS管的栅极作为第一差分输入负端，所述第二十七PMOS管的源极接所述工作电压，所述第二十七PMOS管的漏极接所述第二十四PMOS管的漏极，所述第二十八PMOS管的源极接所述工作电压，所述第二十八PMOS管的漏极接所述第二十五PMOS管的漏极，所述第十八NMOS管的漏极接所述第二十四PMOS管的漏极，且所述第十八NMOS管的漏极作为差分输出负端，所述第十八NMOS管的栅极接所述第二十七PMOS管的栅极并作为第二差分输入正端，所述第十八NMOS管的源极接所述第十九NMOS管的漏极，所述第十九NMOS管的栅极接第七偏置电压，所述第十九NMOS管的源极接地，所述第十九NMOS管的漏极还接所述第二十NMOS管的源极，所述第二十NMOS管的栅极接所述第二十八PMOS管的栅极并作为第二差分输入负端，所述第二十NMOS管的漏极接所述第二十五PMOS管的漏极，且所述第二十NMOS管的漏极作为差分输出正端，所述第四运算放大器的同相输入端经串联的所述第七电阻后接所述第十八NMOS管的漏极，所述第四运算放大器的同相输入端还经串联的所述第八电阻后接所述第二 十NMOS管的漏极，所述第四运算放大器的反相输入端接第四参考信号，所述第四运算放大器的输出端接所述第二十四PMOS管的栅极。
可选地，所述第七跨导放大单元采用互补差分放大结构，所述第七跨导放大单元包括第二十九PMOS管、第三十PMOS管、第三十一PMOS管、第三十二PMOS管、第三十三PMOS管、第三十四PMOS管、第二十一NMOS管、第二十二NMOS管、第二十三NMOS管、第一电容及第二电容，所述第二十九PMOS管的源极接所述工作电压，所述第二十九PMOS管的栅极接所述第二十九PMOS管的漏极，所述第二十九PMOS管的漏极接所述第三十PMOS管的漏极，所述第三十PMOS管的源极接所述工作电压，所述第三十PMOS管的栅极接所述第三十一PMOS管的漏极，所述第三十一PMOS管的源极接所述工作电压，所述第三十一PMOS管的栅极接所述第三十PMOS管的漏极，所述第三十一PMOS管的漏极接所述第三十二PMOS管的漏极，所述第三十二PMOS管的源极接所述工作电压，所述第三十二PMOS管的栅极接所述第三十二PMOS管的漏极，所述第三十三PMOS管的源极接所述工作电压，所述第三十三PMOS管的漏极接所述第三十PMOS管的漏极，所述第三十四PMOS管的源极接所述工作电压，所述第三十四PMOS管的漏极接所述第三十一PMOS管的漏极，所述第二十一NMOS管的漏极接所述第三十PMOS管的漏极，且所述第二十一NMOS管的漏极经串接的所述第一电容后作为差分输出负端，所述第二十一NMOS管的栅极接所述第三十三PMOS管的栅极并作为差分输入正端，所述第二十一NMOS管的源极接所述第二十二NMOS管的漏极，所述第二十二NMOS管的栅极接第八偏置电压，所述第二十二NMOS管的源极接地，所述第二十二NMOS管的漏极还接所述第二十三NMOS管的源极，所述第二十三NMOS管的栅极接所述第三十四PMOS管的栅极并作为差分输入负端，所述第二十三NMOS管的漏极接所述第三十一PMOS管的漏极，且所述第二十三NMOS管的漏极经串接的所述第二电容后作为差分输出正端。
可选地，所述四阶前馈补偿运算放大器基于65nm CMOS工艺设计完成。
一种四阶前馈补偿运算放大器的设计方法，包括步骤：
提供第一跨导放大单元、第二跨导放大单元、第三跨导放大单元、第四跨导放大单元、第五跨导放大单元、第六跨导放大单元及第七跨导放大单元；
利用所述第一跨导放大单元、所述第二跨导放大单元、所述第三跨导放大单元及所述第四跨导放大单元构成四阶运放路径；
利用所述第一跨导放大单元、所述第五跨导放大单元及所述第四跨导放大单元构成三阶运放路径，并通过所述三阶运放路径对所述四阶运放路径进行前馈补偿；
利用所述第一跨导放大单元及所述第六跨导放大单元构成二阶运放路径，并通过所述二阶运放路径对所述三阶运放路径进行前馈补偿；
利用所述第七跨导放大单元构成一阶运放路径，并通过所述一阶运放路径对所述二阶运放路径进行前馈补偿。
可选地，基于共源共栅的差分放大技术形成所述第一跨导放大单元，基于差分放大技术形成所述第二跨导放大单元，基于共模反馈的差分放大技术形成所述第三跨导放大单元和所述第五跨导放大单元，基于共模反馈的互补差分放大技术形成所述第四跨导放大单元和所述第六跨导放大单元，基于互补差分放大技术形成所述第七跨导放大单元。
如上所述，本发明的四阶前馈补偿运算放大器及其设计方法至少具有以下有益效果：
该四阶前馈补偿运算放大器的最高阶路径为四阶运放路径，而运算放大器的增益随着级联阶数的增加而增加，该四阶前馈补偿运算放大器的直流增益可以近似等于其四阶运放路径的直流增益，基于“一阶运放路径对二阶运放路径进行前馈补偿，二阶运放路径对三阶运放路径进行前馈补偿，三阶运放路径对四阶运放路径进行前馈补偿”的结构设计，相邻两阶运放路径产生的零点等于除开公用部分外的等效二阶前馈运算放大器的零点，从而很容易就能根据该结构设计得到对应传递函数的三个零点，并且该四阶前馈补偿运算放大器中只有前馈支路，不存在反馈支路，所以其传递函数的极点由其各个节点决定，根据各个节点的寄生电容和输出阻抗即可得到对应的极点，根据得到的直流增益、三个零点和四个极点，即可得到该四阶前馈补偿运算放大器的传递函数，基于该四阶前馈补偿运算放大器的电路结构设计，很容易就能得出其传递函数；此外，基于得出的传递函数及连续时间带通sigma-delta调制器的增益需求，能反向推导出该四阶前馈补偿运算放大器中各跨导放大单元之间的跨导约束关系，按照对应的跨导约束关系对各跨导放大单元进行选择设计，形成的四阶前馈补偿运算放大器能有效满足连续时间带通sigma-delta调制器的使用需求。
附图说明
图1显示为本发明中四阶前馈补偿运算放大器的设计方法的步骤示意图。
图2显示为本发明中四阶前馈补偿运算放大器的的结构示意图。
图3显示为本发明一实施例中第一跨导放大单元g m1的电路结构图。
图4显示为本发明一实施例中第二跨导放大单元g m2的电路结构图。
图5显示为本发明一实施例中第三跨导放大单元g m3的电路结构图。
图6显示为本发明一实施例中第四跨导放大单元g m4的电路结构图。
图7显示为本发明一实施例中第五跨导放大单元g m5的电路结构图。
图8显示为本发明一实施例中第六跨导放大单元g m6的电路结构图。
图9显示为本发明一实施例中第七跨导放大单元g m7的电路结构图。
图10显示为本发明中四阶前馈补偿运算放大器的的结构等效示意图。
图11显示为二阶前馈补偿运算放大器的的结构等效示意图。
图12显示为本发明一实施例中四阶前馈补偿运算放大器的幅频响应曲线和相频响应曲线示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图12。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
如前述在背景技术中所述，发明人研究发现：对于用于数百MHz中频的连续时间带通sigma-delta调制器，传统的二阶Miller补偿运算放大器难以满足其增益性能需求，只能采用高阶多路前馈补偿运算放大器，但随着高阶多路前馈补偿运算放大器阶数的增加以及其结构的复杂度增加，设计者很难设计出满足特定需求的高阶多路前馈补偿运算放大器；现有技术中，要么是基于繁琐的数学运算推导高阶多路前馈运算放大器的系统传递函数，而随着放大器阶数的增加或者放大器系统结构变复杂的其传递函数计算的复杂度也随之增加，要么是基于完全摒弃物理结构的代码编写算法，通过对所需要设计的前馈运算放大器的性能要求以及器件工艺物理约束且基于运放设计的g m/I D方法对代码进行编写来设计放大器，但该代码编写算法并没有对放大器电路本身进行分析和理解，失去了对高阶多路前馈运算放大器电路级的深入理解。
基于此，如图1-图2所示，本发明提出一种四阶前馈补偿运算放大器的设计方法，其包 括步骤：
S1、提供第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3、第四跨导放大单元g m4、第五跨导放大单元g m5、第六跨导放大单元g m6及第七跨导放大单元g m7；
S2、利用第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3及第四跨导放大单元g m4构成四阶运放路径；
S3、利用第一跨导放大单元g m1、第五跨导放大单元g m5及第四跨导放大单元g m4构成三阶运放路径，并通过三阶运放路径对四阶运放路径进行前馈补偿；
S4、利用第一跨导放大单元g m1及第六跨导放大单元g m6构成二阶运放路径，并通过二阶运放路径对三阶运放路径进行前馈补偿；
S5、利用第七跨导放大单元g m7构成一阶运放路径，并通过一阶运放路径对二阶运放路径进行前馈补偿。
可选地，在步骤S1中，基于共源共栅的差分放大技术形成第一跨导放大单元g m1，基于差分放大技术形成第二跨导放大单元g m2，基于共模反馈的差分放大技术形成第三跨导放大单元g m3和第五跨导放大单元g m5，基于共模反馈的互补差分放大技术形成第四跨导放大单元g m4和第六跨导放大单元g m6，基于互补差分放大技术形成第七跨导放大单元g m7。
详细地，执行步骤S2～S5，得到如图2所示的四阶前馈补偿运算放大器，其包括第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3、第四跨导放大单元g m4、第五跨导放大单元g m5、第六跨导放大单元g m6及第七跨导放大单元g m7；第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3及第四跨导放大单元g m4依次级联，构成四阶运放路径；第五跨导放大单元g m5的输入端接第一跨导放大单元g m1的输出端，第五跨导放大单元g m5的输出端接第四跨导放大单元g m4的输入端，第一跨导放大单元g m1、第五跨导放大单元g m5及第四跨导放大单元g m4构成三阶运放路径；第六跨导放大单元g m6的输入端接第一跨导放大单元g m1的输出端，第六跨导放大单g m6元的输出端接第四跨导放大单元g m4的输出端，第一跨导放大单元g m1及第六跨导放大单元g m6构成二阶运放路径；第七跨导放大单元g m7的输入端接第一跨导放大单元g m1的输入端，第七跨导放大单元g m7的输出端接第四跨导放大单元g m4的输出端，第七跨导放大单元g m7构成一阶运放路径；其中，一阶运放路径对二阶运放路径进行前馈补偿，二阶运放路径对三阶运放路径进行前馈补偿，三阶运放路径对四阶运放路径进行前馈补偿，即相邻两阶运放路径中较低的一阶对较高的一阶递次进行前馈补偿。
其中，本发明的四阶前馈补偿运算放大器基于65nm CMOS工艺设计完成。
在本发明的一可选实施例中，如图3所示，第一跨导放大单元g m1采用共源共栅的差分放大结构，第一跨导放大单元g m1包括第一PMOS管P1、第二PMOS管P2、第三PMOS管P3、第四PMOS管P4、第一NMOS管N1、第二NMOS管N2、第三NMOS管N3、第四NMOS管N4及第五NMOS管N5，第一PMOS管P1的源极接工作电压VDD，第一PMOS管P1的栅极接第一PMOS管P1的漏极，第二PMOS管P2的源极接工作电压VDD，第二PMOS管P2的栅极接第三PMOS管P3的漏极，第二PMOS管P2的漏极接第三PMOS管P3的栅极，第二PMOS管P2的漏极还接第一PMOS管P1的漏极，第三PMOS管P3的源极接工作电压VDD，第三PMOS管P3的漏极还接第四PMOS管P4的漏极，第四PMOS管P4的源极接工作电压VDD，第四PMOS管P4的栅极接第四PMOS管P4的漏极，第一NMOS管N1的漏极接第一PMOS管P1的漏极，且第一NMOS管N1的漏极作为差分输出负端V A-，第一NMOS管N1的栅极接第一偏置电压V B1，第一NMOS管N1的源极接第二NMOS管N2的漏极，第二NMOS管N2的栅极作为差分输入正端V IN+，第二NMOS管N2的源极接第三NMOS管N3的漏极，第三NMOS管N3的栅极接第二偏置电压V B2，第三NMOS管N3的源极接地，第三NMOS管N3的漏极还接第四NMOS管N4的源极，第四NMOS管N4的栅极作为差分输入负端V IN-，第四NMOS管N4的漏极接第五NMOS管N5的源极，第五NMOS管N5的栅极接第一偏置电压V B1，第五NMOS管N5的漏极接第三PMOS管P3的漏极，且第五NMOS管N5的漏极作为差分输出正端V A+。
在本发明的一可选实施例中，如图4所示，第二跨导放大单元g m2采用差分放大结构，第二跨导放大单元g m2包括第五PMOS管P5、第六PMOS管P6、第七PMOS管P7、第八PMOS管P8、第六NMOS管N6、第七NMOS管N7及第八NMOS管N8，第五PMOS管P5的源极接工作电压VDD，第五PMOS管P5的栅极接第五PMOS管P5的漏极，第六PMOS管P6的源极接工作电压VDD，第六PMOS管P6的栅极接第七PMOS管P7的漏极，第六PMOS管P6的漏极接第七PMOS管P7的栅极，第六PMOS管P6的漏极还接第五PMOS管P5的漏极，第七PMOS管P7的源极接工作电压VDD，第七PMOS管P7的漏极还接第八PMOS管P8的漏极，第八PMOS管P8的源极接工作电压VDD，第八PMOS管P8的栅极接第八PMOS管P8的漏极，第六NMOS管N6的漏极接第五PMOS管P5的漏极，且第六NMOS管P6的漏极作为差分输出负端V B-，第六NMOS管N6的栅极作为差分输入正端V A+，第六NMOS管N6的源极接第七NMOS管N7的漏极，第七NMOS管N7的栅极接第三偏置电压V B3，第七NMOS管N7的源极接地，第七NMOS管N7的漏极还接第八NMOS管N8的源极，第八NMOS管N8的栅极作为差分输入负端V A-，第八NMOS管N8的漏极接第七PMOS 管P7的漏极，且第八NMOS管N8的漏极作为差分输出正端V B+。
在本发明的一可选实施例中，如图5所示，第三跨导放大单元g m3采用具有共模反馈的差分放大结构，第三跨导放大单元g m3包括第九PMOS管P9、第十PMOS管P10、第十一PMOS管P11、第十二PMOS管P12、第九NMOS管N9、第十NMOS管N10、第十一NMOS管N11、第一运算放大器A1、第一电阻R1及第二电阻R2，第九PMOS管P9的源极接工作电压VDD，第九PMOS管P9的栅极作为第一差分输入正端V B+，第九PMOS管P9的漏极接第十PMOS管P10的漏极，第十PMOS管P10的源极接工作电压VDD，第十PMOS管P10的栅极接第十一PMOS管P11的栅极，第十一PMOS管P11的源极接工作电压VDD，第十一PMOS管P11的漏极接第十二PMOS管P12的漏极，第十二PMOS管P12的源极接工作电压VDD，第十二PMOS管P12的栅极作为第一差分输入负端V B-，第九NMOS管N9的漏极接第九PMOS管P9的漏极，且第九NMOS管N9的漏极作为差分输出负端V C-，第九NMOS管N9的栅极作为第二差分输入正端V A+，第九NMOS管N9的源极接第十NMOS管N10的漏极，第十NMOS管N10的栅极接第四偏置电压V B4，第十NMOS管N10的源极接地，第十NMOS管N10的漏极还接第十一NMOS管N11的源极，第十一NMOS管N11的栅极作为第二差分输入负端V A-，第十一NMOS管N11的漏极接第十一PMOS管P11的漏极，且第十一NMOS管N11的漏极作为差分输出正端V C+，第一运算放大器A1的同相输入端经串联的第一电阻R1后接第九NMOS管N9的漏极，第一运算放大器A1的同相输入端还经串联的第二电阻R2后接第十一NMOS管N11的漏极，第一运算放大器A1的反相输入端接第一参考信号V ref1，第一运算放大器A1的输出端接第十PMOS管P10的栅极。
在本发明的一可选实施例中，如图6所示，第四跨导放大单元g m4采用具有共模反馈的互补差分放大结构，第四跨导放大单元g m4包括第十三PMOS管P13、第十四PMOS管P14、第十五PMOS管P15、第十六PMOS管P16、第十七PMOS管P17、第十八PMOS管P18、第十二NMOS管N12、第十三NMOS管N13、第十四NMOS管N14、第二运算放大器A2、第三电阻R3及第四电阻R4，第十三PMOS管P13的源极接工作电压VDD，第十三PMOS管P13的栅极作为第一差分输入正端V C+，第十三PMOS管P13的漏极接第十四PMOS管P14的漏极，第十四PMOS管P14的源极接工作电压VDD，第十四PMOS管P14的栅极接第十五PMOS管P15的栅极，第十五PMOS管P15的源极接工作电压VDD，第十五PMOS管P15的漏极接第十六PMOS管P16的漏极，第十六PMOS管P16的源极接工作电压VDD，第十六PMOS管P16的栅极作为第一差分输入负端V C-，第十七PMOS管P17的源极接工作电压VDD，第十七PMOS管P17的漏极接第十四PMOS管P14的漏极，第十八PMOS管P18 的源极接工作电压VDD，第十八PMOS管P18的漏极接第十五PMOS管P15的漏极，第十二NMOS管N12的漏极接第十四PMOS管P14的漏极，且第十二NMOS管N12的漏极作为差分输出负端V OUT-，第十二NMOS管N12的栅极接第十七PMOS管P12的栅极并作为第二差分输入正端V A+，第十二NMOS管N12的源极接第十三NMOS管N13的漏极，第十三NMOS管N13的栅极接第五偏置电压V B5，第十三NMOS管N13的源极接地，第十三NMOS管N13的漏极还接第十四NMOS管N14的源极，第十四NMOS管N14的栅极接第十八PMOS管P18的栅极并作为第二差分输入负端V A+，第十四NMOS管N14的漏极接第十五PMOS管P15的漏极，且第十四NMOS管N14的漏极作为差分输出正端V OUT+，第二运算放大器A2的同相输入端经串联的第三电阻R3后接第十二NMOS管N12的漏极，第二运算放大器A2的同相输入端还经串联的第四电阻R4后接第十四NMOS管N14的漏极，A2第二运算放大器的反相输入端接第二参考信号V ref2，第二运算放大器A2的输出端接第十四PMOS管P14的栅极。
在本发明的一可选实施例中，如图7所示，第五跨导放大单元g m5采用具有共模反馈的差分放大结构，第五跨导放大单元g m5包括第十九PMOS管P19、第二十PMOS管P20、第二十一PMOS管P21、第二十二PMOS管P22、第十五NMOS管N15、第十六NMOS管N16、第十七NMOS管N17、第三运算放大器A3、第五电阻R5及第六电阻R6，第十九PMOS管P19的源极接工作电压VDD，第十九PMOS管P19的栅极作为第一差分输入正端V B+，第十九PMOS管P19的漏极接第二十PMOS管P20的漏极，第二十PMOS管P20的源极接工作电压VDD，第二十PMOS管P20的栅极接第二十一PMOS管P21的栅极，第二十一PMOS管P21的源极接工作电压VDD，第二十一PMOS管P21的漏极接第二十二PMOS管P22的漏极，第二十二PMOS管P22的源极接工作电压VDD，第二十二PMOS管P20的栅极作为第一差分输入负端V B-，第十五NMOS管N15的漏极接第十九PMOS管P19的漏极，且第十五NMOS管N15的漏极作为差分输出负端V C-，第十五NMOS管N15的栅极作为第二差分输入正端V A+，第十五NMOS管N15的源极接第十六NMOS管N16的漏极，第十六NMOS管N16的栅极接第六偏置电压V B6，第十六NMOS管N16的源极接地，第十六NMOS管N16的漏极还接第十七NMOS管N17的源极，第十七NMOS管N17的栅极作为第二差分输入负端V A-，第十七NMOS管N17的漏极接第二十一PMOS管P21的漏极，且第十七NMOS管N17的漏极作为差分输出正端V C-，第三运算放大器A3的同相输入端经串联的第五电阻R5后接第十五NMOS管N15的漏极，第三运算放大器A3的同相输入端还经串联的第六电阻R6后接第十七NMOS管N17的漏极，第三运算放大器A3的反相输入端接第三参考信号V ref3， 第三运算放大器A3的输出端接第二十PMOS管P20的栅极。
在本发明的一可选实施例中，如图8所示，第六跨导放大单元g m6采用具有共模反馈的互补差分放大结构，第六跨导放大单元g m6包括第二十三PMOS管P23、第二十四PMOS管P24、第二十五PMOS管P25、第二十六PMOS管P26、第二十七PMOS管P27、第二十八PMOS管P28、第十八NMOS管N18、第十九NMOS管N19、第二十NMOS管N20、第四运算放大器A4、第七电阻R7及第八电阻R8，第二十三PMOS管P23的源极接工作电压VDD，第二十三PMOS管P23的栅极作为第一差分输入正端V C+，第二十三PMOS管P23的漏极接第二十四PMOS管P24的漏极，第二十四PMOS管P24的源极接工作电压VDD，第二十四PMOS管P24的栅极接第二十五PMOS管P25的栅极，第二十五PMOS管P25的源极接工作电压VDD，第二十五PMOS管P25的漏极接第二十六PMOS管P26的漏极，第二十六PMOS管P26的源极接工作电压VDD，第二十六PMOS管P26的栅极作为第一差分输入负端V C-，第二十七PMOS管P27的源极接工作电压VDD，第二十七PMOS管P27的漏极接第二十四PMOS管P24的漏极，第二十八PMOS管P28的源极接工作电压VDD，所述第二十八PMOS管的漏极接所述第二十五PMOS管的漏极，所述第十八NMOS管的漏极接所述第二十四PMOS管的漏极，且所述第十八NMOS管的漏极作为差分输出负端，第十八NMOS管N18的栅极接第二十七PMOS管P27的栅极并作为第二差分输入正端V A+，第十八NMOS管N18的源极接第十九NMOS管N19的漏极，第十九NMOS管N19的栅极接第七偏置电压V B7，第十九NMOS管N19的源极接地，第十九NMOS管N19的漏极还接第二十NMOS管N20的源极，第二十NMOS管N20的栅极接第二十八PMOS管P28的栅极并作为第二差分输入负端V A-，第二十NMOS管N20的漏极接第二十五PMOS管P25的漏极，且第二十NMOS管N20的漏极作为差分输出正端V OUT+，第四运算放大器A4的同相输入端经串联的第七电阻R7后接第十八NMOS管N18的漏极，第四运算放大器A4的同相输入端还经串联的第八电阻R8后接第二十NMOS管N20的漏极，第四运算放大器A4的反相输入端接第四参考信号V ref4，第四运算放大器A4的输出端接第二十四PMOS管P24的栅极。
在本发明的一可选实施例中，如图9所示，第七跨导放大单元g m7采用互补差分放大结构，第七跨导放大单元g m7包括第二十九PMOS管P29、第三十PMOS管P30、第三十一PMOS管P31、第三十二PMOS管P32、第三十三PMOS管P33、第三十四PMOS管P34、第二十一NMOS管N21、第二十二NMOS管N22、第二十三NMOS管N23、第一电容C1及第二电容C2，第二十九PMOS管P29的源极接工作电压VDD，第二十九PMOS管P29的栅极接第二十九PMOS管P29的漏极，第二十九PMOS管P29的漏极接第三十PMOS管P30的漏 极，第三十PMOS管P30的源极接工作电压VDD，第三十PMOS管P30的栅极接第三十一PMOS管P31的漏极，第三十一PMOS管P31的源极接工作电压VDD，第三十一PMOS管P31的栅极接第三十PMOS管P30的漏极，第三十一PMOS管P31的漏极接第三十二PMOS管P32的漏极，第三十二PMOS管P32的源极接工作电压VDD，第三十二PMOS管P32的栅极接第三十二PMOS管P32的漏极，第三十三PMOS管P33的源极接工作电压VDD，第三十三PMOS管P33的漏极接第三十PMOS管P30的漏极，第三十四PMOS管P34的源极接工作电压VDD，第三十四PMOS管P34的漏极接第三十一PMOS管P31的漏极，第二十一NMOS管N21的漏极接第三十PMOS管P30的漏极，且第二十一NMOS管的漏极经串接的第一电容C1后作为差分输出负端V OUT-，第二十一NMOS管N21的栅极接第三十三PMOS管P33的栅极并作为差分输入正端V IN+，第二十一NMOS管N21的源极接第二十二NMOS管N22的漏极，第二十二NMOS管N22的栅极接第八偏置电压V B8，第二十二NMOS管N22的源极接地，第二十二NMOS管N22的漏极还接第二十三NMOS管N23的源极，第二十三NMOS管N23的栅极接第三十四PMOS管P34的栅极并作为差分输入负端V IN-，第二十三NMOS管N23的漏极接第三十一PMOS管P33的漏极，且第二十三NMOS管N23的漏极经串接的第二电容C2后作为差分输出正端V OUT+。
详细地，执行完步骤S1～S5，得到如图2或如图10所示的四阶前馈补偿运算放大器，第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3及第四跨导放大单元g m4构成四阶运放路径，为主放大路径；余下的第五跨导放大单元g m5、第六跨导放大单元g m6及第七跨导放大单元g m7为三个前馈级，第一跨导放大单元g m1、第五跨导放大单元g m5及第四跨导放大单元g m4构成三阶运放路径，第一跨导放大单元g m1及第六跨导放大单元g m6构成二阶运放路径，第七跨导放大单元g m7构成一阶运放路径；且一阶运放路径对二阶运放路径进行前馈补偿，二阶运放路径对三阶运放路径进行前馈补偿，三阶运放路径对四阶运放路径进行前馈补偿。
更详细地，如图10所示，由于工艺问题，四阶前馈补偿运算放大器中各级跨导放大单元之间的连接节点不可避免地存在寄生电容，同时由于多级级联，对应节点输出阻抗的影响也不可不察。由于决定一个运算放大器的传递函数的主要参数为增益、极点以及零点，所以依次求解这三个参数便可以得到高阶多路前馈补偿运算放大器的传递函数。
首先，从图2和图10可以看出，此四阶前馈补偿运算放大器的最高阶路径为第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3及第四跨导放大单元g m4构成的四阶运放路径，而运算放大器的增益随着级联阶数的增加而增加，所以此四阶前馈补偿运算 放大器的直流增益可以近似等于其四阶运放路径的直流增益，即：
A 0≈A 1A 2A 3A 4            (1)
其中，A 0为此四阶前馈补偿运算放大器的增益，A 1-A 4分别为第一跨导放大单元g m1、第二跨导放大单元g m2、第三跨导放大单元g m3及第四跨导放大单元g m4的增益。
其次，由于该四阶前馈运算放大器中只有前馈支路，而不存在反馈支路，所以其传递函数的极点由其各个节点决定，即：
Figure PCTCN2021140254-appb-000001
其中，电容C 1-C 3分别为节点A、B、C的寄生电容，电容C 4为输出节点寄生电容与运算放大器负载电容之和，电阻r 1-r 3分别为节点A、B、C的输出阻抗，电阻r 4为输出节点输出阻抗与负载阻抗的并联阻抗。
最后，对于一个最简单的二阶前馈补偿运算放大器，如图11所示，其主路由跨导放大单元g ma和跨导放大单元g mb组成，前馈支路由跨导放大单元g mc组成，电容C a-C b分别为节点的寄生电容，电阻r a-r b分别为节点的输出阻抗。该前馈运算放大器系统传递函数存在一个零点，并且可以表示为：
Figure PCTCN2021140254-appb-000002
其中，ω Z为频率零点，G ma～G mc分别为跨导放大单元g ma～g mc的跨导值。
在图2或图10所示的四阶前馈补偿运算放大器中，四阶运放路径由三阶运放路径进行补偿，三阶运放路径由二阶运放路径进行补偿，二阶运放路径由一阶运放路径进行补偿。这样经过三次补偿就会使得该运算放大器产生三个零点。
对于由四阶运放路径和三阶运放路径产生的零点，由于第一跨导放大单元g m1、第二跨导放大单元g m2被这两条路径公用，所以这两条路径产生的零点与第二跨导放大单元g m2、第三跨导放大单元g m3及第五跨导放大单元g m5产生的零点相等，利用式(3)可以得到该零点为：
Figure PCTCN2021140254-appb-000003
其中，ω Z1为第一个频率零点，G m2为第二跨导放大单元g m2的跨导值，G m3为第三跨导放大单元g m3的跨导值，G m5为第五跨导放大单元g m5的跨导值。
同理，对于三阶运放路径和二阶运放路径产生的零点，利用和ω Z1求解相同的方法，该零点与第四跨导放大单元g m4、第五跨导放大单元g m5及第六跨导放大单元g m6产生的零点相等，并且可以表示为：
Figure PCTCN2021140254-appb-000004
其中，ω Z2为第二个频率零点，G m4为第四跨导放大单元g m4的跨导值，G m6为第六跨导放大单元g m6的跨导值。
同理，对于二阶运放路径和一阶运放路径产生的零点，利用和ω Z1求解相同的方法，该零点与第一跨导放大单元g m1、第六跨导放大单元g m6及第七跨导放大单元g m7产生的零点相等，利用式(3)可以得到该零点为：
Figure PCTCN2021140254-appb-000005
其中，ω Z3为第三个频率零点，G m1为第一跨导放大单元g m1的跨导值，G m7为第七跨导放大单元g m7的跨导值。
需要注意的是，上面式(4)-(6)所表示的三个零点是忽略了前馈运算放大器另外两条运放路径下的零点，而不是整个四阶前馈运算放大器系统传递函数的真正的零点。根据式(1)-(2)，(4)-(6)，可以得到该四阶前馈运算放大器整体的系统传递函数为：
Figure PCTCN2021140254-appb-000006
最后，通过对该四阶前馈补偿运算放大器中各级跨导的约束可以使得其满足增益和稳定性要求。本发明一可选实施例中采用的约束关系如下所示：
Figure PCTCN2021140254-appb-000007
因此，本发明提出了一种无需复杂的数学推导计算而是通过对于高阶多路前馈运算放大器系统结构直观的理解得到其系统传递函数的方法，且本发明的四阶前馈补偿运算放大器基于65nm CMOS工艺设计实现。此外，该四阶前馈补偿运算放大器电路级实现上利用了如电流复用技术、共源共栅结构、相同尺寸的二极管连接的晶体管对与交叉耦合晶体管对并联结 构以及互补差分AB类工作方式等放大器性能的优化技术。
详细地，为了提升运算放大器的性能，采用了多种优化技术。其一，第一跨导放大单元g m1中第一NMOS管N1和第二NMOS管N2采用了共源共栅结构来实现高的增益以减小后级的噪声贡献。其二，第一跨导放大单元g m1、第二跨导放大单元g m2及第七跨导放大单元g m7中采用了相同尺寸的二极管连接的PMOS管和交叉耦合的PMOS管对来同时实现高增益和确定的输出直流电压，尽管如此，为了保证该运算放大器足够的输出电压摆幅，所以在第三跨导放大单元g m3、第四跨导放大单元g m4、第五跨导放大单元g m5及第六跨导放大单元g m6中并没有采用这样的技术。其三，从式(8)可以看出，运算放大器的前馈支路的跨导较大，所以第三跨导放大单元g m3及第四跨导放大单元g m4可以采用PMOS管差分对实现，而前馈支路跨导第五跨导放大单元g m5、第六跨导放大单元g m6及第七跨导放大单元g m7必须采用载流子迁移率更高的NMOS管差分对实现。其四，在第四跨导放大单元g m4、第六跨导放大单元g m6及第七跨导放大单元g m7中采用了电流复用技术来减小功耗。其五，由于输出级在第四跨导放大单元g m4、第六跨导放大单元g m6及第七跨导放大单元g m7中的跨导最高，所以这两级运算放大器采用了互补差分AB类工作模式。
在本发明的一可选实施例中，基于65nm CMOS工艺设计实现对应的四阶前馈补偿运算放大器，并且其在驱动400fF电容负载时的幅频响应和相频响应曲线如图12所示，如图12所示，横坐标统一为Frequency(频率)，对应单位为赫兹(Hz)，纵坐标Magnitude、Phase分别为幅度和相位，对应单位为分贝(dB)和度(deg)。由图12可知，其在直流、250MHz、340MHz以及1GHz下的增益分别为64.6dB，44.0dB，40.1dB以及11.5dB，且其相位裕度和功耗分别为72.1°，12.96mW。因此，本发明提出的四阶前馈补偿运算放大器能满足中频高达340MHz、采样频率达2GHz的连续时间带通sigma-delta调制器中运算放大器的增益需求。
综上所述，在本发明所提供的四阶前馈补偿运算放大器及其设计方法中，基于“以四阶运放路径为主”的结构设计，其最高阶路径为四阶运放路径，而运算放大器的增益随着级联阶数的增加而增加，其直流增益可以近似等于其四阶运放路径的直流增益，基于“相邻两阶运放路径中较低的一阶对较高的一阶递次进行前馈补偿”的结构设计，相邻两阶运放路径产生的零点等于除开公用部分外的等效于二阶前馈运算放大器的零点，从而很容易就能根据该结构设计得到对应传递函数的三个零点，并且该四阶前馈补偿运算放大器中只有前馈支路，不存在反馈支路，所以其传递函数的极点由其各个节点决定，根据各个节点的寄生电容和输出阻抗即可得到对应的极点，根据得到的直流增益、三个零点和四个极点，即可得到该四阶 前馈补偿运算放大器的传递函数，基于该四阶前馈补偿运算放大器的电路结构设计，很容易就能得出其传递函数；此外，基于得出的传递函数及连续时间带通sigma-delta调制器的增益需求，能反向推导出该四阶前馈补偿运算放大器中各跨导放大单元之间的跨导约束关系，按照对应的跨导约束关系对各跨导放大单元进行选择设计，形成的四阶前馈补偿运算放大器能有效满足连续时间带通sigma-delta调制器的使用需求。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (11)

  1. 一种四阶前馈补偿运算放大器，其特征在于，包括第一跨导放大单元、第二跨导放大单元、第三跨导放大单元、第四跨导放大单元、第五跨导放大单元、第六跨导放大单元及第七跨导放大单元；
    所述第一跨导放大单元、所述第二跨导放大单元、所述第三跨导放大单元及所述第四跨导放大单元依次级联，所述第一跨导放大单元、所述第二跨导放大单元、所述第三跨导放大单元及所述第四跨导放大单元构成四阶运放路径；
    所述第五跨导放大单元的输入端接所述第一跨导放大单元的输出端，所述第五跨导放大单元的输出端接所述第四跨导放大单元的输入端，所述第一跨导放大单元、所述第五跨导放大单元及所述第四跨导放大单元构成三阶运放路径；
    所述第六跨导放大单元的输入端接所述第一跨导放大单元的输出端，所述第六跨导放大单元的输出端接所述第四跨导放大单元的输出端，所述第一跨导放大单元及所述第六跨导放大单元构成二阶运放路径；
    所述第七跨导放大单元的输入端接所述第一跨导放大单元的输入端，所述第七跨导放大单元的输出端接所述第四跨导放大单元的输出端，所述第七跨导放大单元构成一阶运放路径；
    其中，所述一阶运放路径对所述二阶运放路径进行前馈补偿，所述二阶运放路径对所述三阶运放路径进行前馈补偿，所述三阶运放路径对所述四阶运放路径进行前馈补偿。
  2. 根据权利要求1所述的四阶前馈补偿运算放大器，其特征在于，所述第一跨导放大单元采用共源共栅的差分放大结构，所述第一跨导放大单元包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管及第五NMOS管，所述第一PMOS管的源极接工作电压，所述第一PMOS管的栅极接所述第一PMOS管的漏极，所述第二PMOS管的源极接所述工作电压，所述第二PMOS管的栅极接所述第三PMOS管的漏极，所述第二PMOS管的漏极接所述第三PMOS管的栅极，所述第二PMOS管的漏极还接所述第一PMOS管的漏极，所述第三PMOS管的源极接所述工作电压，所述第三PMOS管的漏极还接所述第四PMOS管的漏极，所述第四PMOS管的源极接所述工作电压，所述第四PMOS管的栅极接所述第四PMOS管的漏极，所述第一NMOS管的漏极接所述第一PMOS管的漏极，且所述第一NMOS管的漏极作为差分输出负端，所述第一NMOS管的栅极接第一偏置电压，所述第一NMOS管的源极接所述第二NMOS管的漏极，所述第二NMOS管的栅极作为差分输入正端，所述第二NMOS管的源极接所述第三NMOS管的漏极，所述第三NMOS管的栅极接第二偏置电压，所述第三NMOS管的源极接地，所述第三NMOS管的漏极还接所述第四NMOS管的源极，所述第四NMOS管的栅极作 为差分输入负端，所述第四NMOS管的漏极接所述第五NMOS管的源极，所述第五NMOS管的栅极接所述第一偏置电压，所述第五NMOS管的漏极接所述第三PMOS管的漏极，且所述第五NMOS管的漏极作为差分输出正端。
  3. 根据权利要求2所述的四阶前馈补偿运算放大器，其特征在于，所述第二跨导放大单元采用差分放大结构，所述第二跨导放大单元包括第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第六NMOS管、第七NMOS管及第八NMOS管，所述第五PMOS管的源极接所述工作电压，所述第五PMOS管的栅极接所述第五PMOS管的漏极，所述第六PMOS管的源极接所述工作电压，所述第六PMOS管的栅极接所述第七PMOS管的漏极，所述第六PMOS管的漏极接所述第七PMOS管的栅极，所述第六PMOS管的漏极还接所述第五PMOS管的漏极，所述第七PMOS管的源极接所述工作电压，所述第七PMOS管的漏极还接所述第八PMOS管的漏极，所述第八PMOS管的源极接所述工作电压，所述第八PMOS管的栅极接所述第八PMOS管的漏极，所述第六NMOS管的漏极接所述第五PMOS管的漏极，且所述第六NMOS管的漏极作为差分输出负端，所述第六NMOS管的栅极作为差分输入正端，所述第六NMOS管的源极接所述第七NMOS管的漏极，所述第七NMOS管的栅极接第三偏置电压，所述第七NMOS管的源极接地，所述第七NMOS管的漏极还接所述第八NMOS管的源极，所述第八NMOS管的栅极作为差分输入负端，所述第八NMOS管的漏极接所述第七PMOS管的漏极，且所述第八NMOS管的漏极作为差分输出正端。
  4. 根据权利要求3所述的四阶前馈补偿运算放大器，其特征在于，所述第三跨导放大单元采用具有共模反馈的差分放大结构，所述第三跨导放大单元包括第九PMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管、第一运算放大器、第一电阻及第二电阻，所述第九PMOS管的源极接所述工作电压，所述第九PMOS管的栅极作为第一差分输入正端，所述第九PMOS管的漏极接所述第十PMOS管的漏极，所述第十PMOS管的源极接所述工作电压，所述第十PMOS管的栅极接所述第十一PMOS管的栅极，所述第十一PMOS管的源极接所述工作电压，所述第十一PMOS管的漏极接所述第十二PMOS管的漏极，所述第十二PMOS管的源极接所述工作电压，所述第十二PMOS管的栅极作为第一差分输入负端，所述第九NMOS管的漏极接所述第九PMOS管的漏极，且所述第九NMOS管的漏极作为差分输出负端，所述第九NMOS管的栅极作为第二差分输入正端，所述第九NMOS管的源极接所述第十NMOS管的漏极，所述第十NMOS管的栅极接第四偏置电压，所述第十NMOS管的源极接地，所述第十NMOS管的漏极还接 所述第十一NMOS管的源极，所述第十一NMOS管的栅极作为第二差分输入负端，所述第十一NMOS管的漏极接所述第十一PMOS管的漏极，且所述第十一NMOS管的漏极作为差分输出正端，所述第一运算放大器的同相输入端经串联的所述第一电阻后接所述第九NMOS管的漏极，所述第一运算放大器的同相输入端还经串联的所述第二电阻后接所述第十一NMOS管的漏极，所述第一运算放大器的反相输入端接第一参考信号，所述第一运算放大器的输出端接所述第十PMOS管的栅极。
  5. 根据权利要求4所述的四阶前馈补偿运算放大器，其特征在于，所述第四跨导放大单元采用具有共模反馈的互补差分放大结构，所述第四跨导放大单元包括第十三PMOS管、第十四PMOS管、第十五PMOS管、第十六PMOS管、第十七PMOS管、第十八PMOS管、第十二NMOS管、第十三NMOS管、第十四NMOS管、第二运算放大器、第三电阻及第四电阻，所述第十三PMOS管的源极接所述工作电压，所述第十三PMOS管的栅极作为第一差分输入正端，所述第十三PMOS管的漏极接所述第十四PMOS管的漏极，所述第十四PMOS管的源极接所述工作电压，所述第十四PMOS管的栅极接所述第十五PMOS管的栅极，所述第十五PMOS管的源极接所述工作电压，所述第十五PMOS管的漏极接所述第十六PMOS管的漏极，所述第十六PMOS管的源极接所述工作电压，所述第十六PMOS管的栅极作为第一差分输入负端，所述第十七PMOS管的源极接所述工作电压，所述第十七PMOS管的漏极接所述第十四PMOS管的漏极，所述第十八PMOS管的源极接所述工作电压，所述第十八PMOS管的漏极接所述第十五PMOS管的漏极，所述第十二NMOS管的漏极接所述第十四PMOS管的漏极，且所述第十二NMOS管的漏极作为差分输出负端，所述第十二NMOS管的栅极接所述第十七PMOS管的栅极并作为第二差分输入正端，所述第十二NMOS管的源极接所述第十三NMOS管的漏极，所述第十三NMOS管的栅极接第五偏置电压，所述第十三NMOS管的源极接地，所述第十三NMOS管的漏极还接所述第十四NMOS管的源极，所述第十四NMOS管的栅极接所述第十八PMOS管的栅极并作为第二差分输入负端，所述第十四NMOS管的漏极接所述第十五PMOS管的漏极，且所述第十四NMOS管的漏极作为差分输出正端，所述第二运算放大器的同相输入端经串联的所述第三电阻后接所述第十二NMOS管的漏极，所述第二运算放大器的同相输入端还经串联的所述第四电阻后接所述第十四NMOS管的漏极，所述第二运算放大器的反相输入端接第二参考信号，所述第二运算放大器的输出端接所述第十四PMOS管的栅极。
  6. 根据权利要求5所述的四阶前馈补偿运算放大器，其特征在于，所述第五跨导放大单 元采用具有共模反馈的差分放大结构，所述第五跨导放大单元包括第十九PMOS管、第二十PMOS管、第二十一PMOS管、第二十二PMOS管、第十五NMOS管、第十六NMOS管、第十七NMOS管、第三运算放大器、第五电阻及第六电阻，所述第十九PMOS管的源极接所述工作电压，所述第十九PMOS管的栅极作为第一差分输入正端，所述第十九PMOS管的漏极接所述第二十PMOS管的漏极，所述第二十PMOS管的源极接所述工作电压，所述第二十PMOS管的栅极接所述第二十一PMOS管的栅极，所述第二十一PMOS管的源极接所述工作电压，所述第二十一PMOS管的漏极接所述第二十二PMOS管的漏极，所述第二十二PMOS管的源极接所述工作电压，所述第二十二PMOS管的栅极作为第一差分输入负端，所述第十五NMOS管的漏极接所述第十九PMOS管的漏极，且所述第十五NMOS管的漏极作为差分输出负端，所述第十五NMOS管的栅极作为第二差分输入正端，所述第十五NMOS管的源极接所述第十六NMOS管的漏极，所述第十六NMOS管的栅极接第六偏置电压，所述第十六NMOS管的源极接地，所述第十六NMOS管的漏极还接所述第十七NMOS管的源极，所述第十七NMOS管的栅极作为第二差分输入负端，所述第十七NMOS管的漏极接所述第二十一PMOS管的漏极，且所述第十七NMOS管的漏极作为差分输出正端，所述第三运算放大器的同相输入端经串联的所述第五电阻后接所述第十五NMOS管的漏极，所述第三运算放大器的同相输入端还经串联的所述第六电阻后接所述第十七NMOS管的漏极，所述第三运算放大器的反相输入端接第三参考信号，所述第三运算放大器的输出端接所述第二十PMOS管的栅极。
  7. 根据权利要求6所述的四阶前馈补偿运算放大器，其特征在于，所述第六跨导放大单元采用具有共模反馈的互补差分放大结构，所述第六跨导放大单元包括第二十三PMOS管、第二十四PMOS管、第二十五PMOS管、第二十六PMOS管、第二十七PMOS管、第二十八PMOS管、第十八NMOS管、第十九NMOS管、第二十NMOS管、第四运算放大器、第七电阻及第八电阻，所述第二十三PMOS管的源极接所述工作电压，所述第二十三PMOS管的栅极作为第一差分输入正端，所述第二十三PMOS管的漏极接所述第二十四PMOS管的漏极，所述第二十四PMOS管的源极接所述工作电压，所述第二十四PMOS管的栅极接所述第二十五PMOS管的栅极，所述第二十五PMOS管的源极接所述工作电压，所述第二十五PMOS管的漏极接所述第二十六PMOS管的漏极，所述第二十六PMOS管的源极接所述工作电压，所述第二十六PMOS管的栅极作为第一差分输入负端，所述第二十七PMOS管的源极接所述工作电压，所述第二十七PMOS管的漏极接所述第二十四PMOS管的漏极，所述第二十八PMOS管的源极接所述工作电压，所述第二十八PMOS管的漏极接所述第二十五PMOS管的 漏极，所述第十八NMOS管的漏极接所述第二十四PMOS管的漏极，且所述第十八NMOS管的漏极作为差分输出负端，所述第十八NMOS管的栅极接所述第二十七PMOS管的栅极并作为第二差分输入正端，所述第十八NMOS管的源极接所述第十九NMOS管的漏极，所述第十九NMOS管的栅极接第七偏置电压，所述第十九NMOS管的源极接地，所述第十九NMOS管的漏极还接所述第二十NMOS管的源极，所述第二十NMOS管的栅极接所述第二十八PMOS管的栅极并作为第二差分输入负端，所述第二十NMOS管的漏极接所述第二十五PMOS管的漏极，且所述第二十NMOS管的漏极作为差分输出正端，所述第四运算放大器的同相输入端经串联的所述第七电阻后接所述第十八NMOS管的漏极，所述第四运算放大器的同相输入端还经串联的所述第八电阻后接所述第二十NMOS管的漏极，所述第四运算放大器的反相输入端接第四参考信号，所述第四运算放大器的输出端接所述第二十四PMOS管的栅极。
  8. 根据权利要求7所述的四阶前馈补偿运算放大器，其特征在于，所述第七跨导放大单元采用互补差分放大结构，所述第七跨导放大单元包括第二十九PMOS管、第三十PMOS管、第三十一PMOS管、第三十二PMOS管、第三十三PMOS管、第三十四PMOS管、第二十一NMOS管、第二十二NMOS管、第二十三NMOS管、第一电容及第二电容，所述第二十九PMOS管的源极接所述工作电压，所述第二十九PMOS管的栅极接所述第二十九PMOS管的漏极，所述第二十九PMOS管的漏极接所述第三十PMOS管的漏极，所述第三十PMOS管的源极接所述工作电压，所述第三十PMOS管的栅极接所述第三十一PMOS管的漏极，所述第三十一PMOS管的源极接所述工作电压，所述第三十一PMOS管的栅极接所述第三十PMOS管的漏极，所述第三十一PMOS管的漏极接所述第三十二PMOS管的漏极，所述第三十二PMOS管的源极接所述工作电压，所述第三十二PMOS管的栅极接所述第三十二PMOS管的漏极，所述第三十三PMOS管的源极接所述工作电压，所述第三十三PMOS管的漏极接所述第三十PMOS管的漏极，所述第三十四PMOS管的源极接所述工作电压，所述第三十四PMOS管的漏极接所述第三十一PMOS管的漏极，所述第二十一NMOS管的漏极接所述第三十PMOS管的漏极，且所述第二十一NMOS管的漏极经串接的所述第一电容后作为差分输出负端，所述第二十一NMOS管的栅极接所述第三十三PMOS管的栅极并作为差分输入正端，所述第二十一NMOS管的源极接所述第二十二NMOS管的漏极，所述第二十二NMOS管的栅极接第八偏置电压，所述第二十二NMOS管的源极接地，所述第二十二NMOS管的漏极还接所述第二十三NMOS管的源极，所述第二十三NMOS管的栅极接所述第三十四PMOS管的栅极并作为差分输入负端，所述第二十三NMOS管的漏极接所述第三十一PMOS管的漏 极，且所述第二十三NMOS管的漏极经串接的所述第二电容后作为差分输出正端。
  9. 根据权利要求1-8中任一项所述的四阶前馈补偿运算放大器，其特征在于，所述四阶前馈补偿运算放大器基于65nm CMOS工艺设计完成。
  10. 一种四阶前馈补偿运算放大器的设计方法，其特征在于，包括步骤：
    提供第一跨导放大单元、第二跨导放大单元、第三跨导放大单元、第四跨导放大单元、第五跨导放大单元、第六跨导放大单元及第七跨导放大单元；
    利用所述第一跨导放大单元、所述第二跨导放大单元、所述第三跨导放大单元及所述第四跨导放大单元构成四阶运放路径；
    利用所述第一跨导放大单元、所述第五跨导放大单元及所述第四跨导放大单元构成三阶运放路径，并通过所述三阶运放路径对所述四阶运放路径进行前馈补偿；
    利用所述第一跨导放大单元及所述第六跨导放大单元构成二阶运放路径，并通过所述二阶运放路径对所述三阶运放路径进行前馈补偿；
    利用所述第七跨导放大单元构成一阶运放路径，并通过所述一阶运放路径对所述二阶运放路径进行前馈补偿。
  11. 根据权利要求10所述的四阶前馈补偿运算放大器的设计方法，其特征在于，基于共源共栅的差分放大技术形成所述第一跨导放大单元，基于差分放大技术形成所述第二跨导放大单元，基于共模反馈的差分放大技术形成所述第三跨导放大单元和所述第五跨导放大单元，基于共模反馈的互补差分放大技术形成所述第四跨导放大单元和所述第六跨导放大单元，基于互补差分放大技术形成所述第七跨导放大单元。
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