WO2023065410A1 - Semiconductor structure bonding method, and semiconductor device - Google Patents

Semiconductor structure bonding method, and semiconductor device Download PDF

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Publication number
WO2023065410A1
WO2023065410A1 PCT/CN2021/129242 CN2021129242W WO2023065410A1 WO 2023065410 A1 WO2023065410 A1 WO 2023065410A1 CN 2021129242 W CN2021129242 W CN 2021129242W WO 2023065410 A1 WO2023065410 A1 WO 2023065410A1
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semiconductor structure
monomer
bonding
bonding surface
marking
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PCT/CN2021/129242
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French (fr)
Chinese (zh)
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任小亮
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长鑫存储技术有限公司
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Publication of WO2023065410A1 publication Critical patent/WO2023065410A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67121Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/03011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03015Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for aligning the bonding area, e.g. marks, spacers

Definitions

  • the present disclosure relates to, but is not limited to, a bonding method of a semiconductor structure and a semiconductor device.
  • the semiconductor structure with the bonding surface will be turned over many times, which will inevitably cause the bonding surface of the semiconductor structure to be polluted, reducing the bonding efficiency and bonding quality of the semiconductor structure.
  • the present disclosure provides a bonding method of a semiconductor structure and a semiconductor device.
  • a first aspect of an embodiment of the present disclosure provides a method for bonding a semiconductor structure, including:
  • the first bonding surface is bonded to the second bonding surface.
  • turning the first semiconductor structure over so that the first bonding surface is opposite to the second bonding surface includes:
  • the first semiconductor structure is rotated by a first preset angle so that the first bonding surface is opposite to the second bonding surface;
  • the first semiconductor structure has a curved edge, and any edge tangent of the first semiconductor structure, or a parallel line parallel to the edge tangent is used as a flip axis, and the first semiconductor structure is completely flipped over the second preset. An angle is set so that the first bonding surface is opposite to the second bonding surface.
  • performing the alignment process on the first semiconductor structure and the second semiconductor structure includes:
  • the first center point coincides with the second center point, and the first mark coincides with the second mark.
  • obtaining the first center point and the first mark of the first monomer includes:
  • the first marking process includes adding a first marking point and a second marking point on the first bonding surface, the first marking point The shape of the second marking point is different from that of the second marking point, and the first marking point and the second marking point are arranged diagonally;
  • Obtaining the second center point and the second mark of the second monomer includes:
  • the second marking process includes adding a third marking point and a fourth marking point on the second bonding surface, the third marking point The shape of is different from that of the fourth marking point, and the third marking point and the fourth marking point are arranged diagonally.
  • the first monomer is square, the number of the first marking point is one, and the number of the second marking point is an odd number greater than or equal to 1;
  • Performing the first marking process on the first bonding surface includes:
  • a first virtual connection line is formed between the first marking point and the second marking point at the corner opposite to it, and a second virtual connection line is formed between the remaining second marking points , the intersection of the first virtual connection and the second virtual connection forms the first central point;
  • the second monomer is square, and the number of the third marking point and the number of the fourth marking point are both one;
  • Performing the second marking process on the second bonding surface includes:
  • the third marking point is arranged at a vertex among the plurality of vertex corners of the second bonding surface, and the fourth marking point is arranged at a vertex opposite to the third marking point place;
  • a third virtual connection line is formed between the third marking point and the fourth marking point, and the midpoint of the third virtual connection line is the second center point.
  • processing the first surface or the second surface includes:
  • the bonding method of the semiconductor structure further includes:
  • the bonding connection between the first bonding surface and the second bonding surface includes:
  • a mixed bonding connection is performed on the first bonding surface of the first monomer and the second bonding surface of the second monomer.
  • a second aspect of the embodiments of the present disclosure provides a semiconductor device, including:
  • the bearing platform, the fixing component is arranged on the bearing platform, and the fixing component is used to fix the first semiconductor structure on the bearing platform, and the second semiconductor structure is fixed on the side of the bearing platform, wherein the
  • the first semiconductor structure has a first face and a second face disposed opposite to each other;
  • a processing component configured to process the first surface or the second surface of the first semiconductor structure, so that at least one first monomer is formed on the first surface or the second surface;
  • An overturning component connected to the carrying platform, is used to turn over the carrying platform as a whole, so as to turn over the first semiconductor structure as a whole;
  • an alignment component for aligning the first bonding surface of the at least one first monomer with the second bonding surface of the at least one second monomer of the second semiconductor structure
  • the probe assembly is used to realize the bonding connection between the first bonding surface and the second bonding surface.
  • the fixing assembly includes a fixing ring and a fixing film, the fixing ring is detachably connected to the carrying platform, and the fixing film is attached to the fixing ring for The first semiconductor structure is fixed on the fixing ring.
  • the first surface or the second surface of the first semiconductor structure is provided with a plurality of criss-crossing dicing lines
  • the processing assembly includes a dicing machine that saws the first semiconductor structure along the dicing lane to form the at least one first monomer on the first face or the second face .
  • the turning assembly includes a first manipulator, and the first manipulator is connected to the carrying platform.
  • the alignment assembly includes a second manipulator and an observation device, the second manipulator is disposed at the edge of the carrying platform, and the observation device is disposed at the working end of the second manipulator .
  • the probe assembly includes a probe base and a probe, the probe base is disposed at the working end of the second manipulator, the probe base is disposed close to the observation device, wherein , there are a plurality of probes, and the probes are arranged inside the probe seat, and the probes can move along the axial direction of the probe seat to push the first monomer to move for a predetermined time. distance, so that the first bonding surface is attached to the second bonding surface.
  • the probe base includes an electrostatic chuck, a plurality of the probes are located in the electrostatic chuck, and one end of the probes can protrude to the outside of the electrostatic chuck.
  • the probe base includes a probe base body, the probe base body has a working surface, the working surface is provided with an adsorption area, and the adsorption area communicates with the negative pressure device;
  • a plurality of the probes are located inside the probe holder body, and one end of the probes can pass through the adsorption area.
  • Fig. 1 is a flow chart of a bonding method for a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a schematic diagram of a bonding method for a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a schematic diagram of a fixing manner of a first semiconductor structure in a method for bonding semiconductor structures according to an exemplary embodiment.
  • Fig. 4 is a schematic diagram of irradiating a sawn first semiconductor structure with UV rays in a bonding method of semiconductor structures according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of performing wafer expansion on a first semiconductor structure in a bonding method for semiconductor structures according to an exemplary embodiment.
  • FIG. 6 is a schematic view of FIG. 5 in a plan view direction.
  • Fig. 7 is a schematic diagram of performing a first marking process on a first semiconductor structure in a bonding method of semiconductor structures according to an exemplary embodiment.
  • Fig. 8 is a schematic diagram showing an alignment process in a bonding method of a semiconductor structure according to an exemplary embodiment.
  • Fig. 9 is a schematic diagram showing a bonding connection in a bonding method of a semiconductor structure according to an exemplary embodiment.
  • Fig. 10 is a schematic diagram of a probe assembly in a semiconductor device according to an exemplary embodiment.
  • Fig. 11 is a schematic diagram of a probe assembly in a semiconductor device according to an exemplary embodiment.
  • a first semiconductor structure 20. A second semiconductor structure;
  • L1 the first virtual connection
  • L2 the second virtual connection
  • M the first marking point
  • N the second marking point
  • the whole wafer is usually cut into a plurality of chips arranged at intervals, and then is adsorbed on the bonding surface of the chip by a transfer device such as a manipulator, so that the chip is separated from the wafer, and then passed through
  • the transfer equipment is turned over many times and then bonded to the semiconductor structure to be bonded. After the semiconductor structure is turned over many times, the bonding surface of the semiconductor structure will inevitably be polluted.
  • the surface of the bonding surface of the semiconductor structures needs to be cleaned before the bonding of the two semiconductor structures, and each chip needs to be cleaned.
  • the bonding process is very cumbersome, which reduces the bonding efficiency and bonding quality of the semiconductor structure.
  • Embodiments of the present disclosure provide a semiconductor structure bonding method and a semiconductor device.
  • the bonding process of the semiconductor structure is greatly reduced.
  • the number of flips in the process avoids the surface contamination of the semiconductor structure caused by multiple flips, thereby effectively improving the bonding quality and bonding efficiency of the semiconductor structure.
  • FIG. 1 shows a flow chart of a bonding method for a semiconductor structure provided in an exemplary embodiment according to the present disclosure.
  • the bonding method of the semiconductor structure will be introduced below with reference to FIGS. 1 to 9 .
  • This embodiment does not limit the semiconductor structure.
  • the following will introduce the semiconductor structure as a wafer as an example, but this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures, such as dynamic random Memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • an exemplary embodiment of the present disclosure provides a bonding method for a semiconductor structure, including:
  • Step S100 providing a first semiconductor structure, the first semiconductor structure has a first surface and a second surface opposite to each other.
  • Step S200 Processing the first surface or the second surface to form at least one first monomer on the first surface or the second surface, wherein the first monomer has a first bonding surface.
  • Step S300 Perform wafer expansion on the first semiconductor structure.
  • Step S400 providing a second semiconductor structure having at least one second monomer, the second monomer has a second bonding surface, and the second semiconductor structure is fixed.
  • Step S500 Flip over the first semiconductor structure as a whole, so that the first bonding surface of at least one first monomer is opposite to the second bonding surface of at least one second monomer.
  • Step S600 performing an alignment process on at least one first monomer and at least one second monomer to align the first bonding surface with the second bonding surface.
  • Step S700 bonding the first bonding surface and the second bonding surface.
  • a first semiconductor structure 10 is provided, and the first semiconductor structure 10 has a first surface 101 and a second surface 102 disposed opposite to each other.
  • the first semiconductor structure 10 includes but is not limited to a wafer, wherein the first semiconductor structure 10 may also be a chip or a substrate of semiconductor material. In this embodiment, description is made by taking the first semiconductor structure 10 and the second semiconductor structure 20 as wafers as an example.
  • the wafer may be made of semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compound, and silicon-oxygen compound.
  • step S200 the first surface 101 of the first semiconductor structure 10 is processed so that at least one first monomer 110 is formed on the first surface 101 .
  • the top surface of the first monomer 110 forms a first bonding surface 1101 .
  • the second surface 102 of the first semiconductor structure 10 is processed so that at least one first monomer 110 is formed on the second surface 102 .
  • the top surface of the first monomer 110 forms a first bonding surface 1101 .
  • the first surface 101 or the second surface 102 can be sawed to form at least one first unit 110 on the first surface 101 or the second surface 102, wherein the first unit 110 The top surface forms a first bonding surface 1101 .
  • the formation process of the first monomer 110 can adopt the following method:
  • a plurality of cutting lines 103 arranged alternately in the transverse direction and the vertical direction are designed.
  • the distance between adjacent cutting lines 103 can be the same or Not the same, the distance can be flexibly set according to the design size of the first unit 110 .
  • the first semiconductor structure 10 can be placed on the carrier platform 40 of the semiconductor device, and the first semiconductor structure 10 can be fixed on the carrier platform 40 through the fixing ring 601 and the fixing film 602 .
  • the fixing ring 604 can be an edge ring in a semiconductor device, and the fixing film 602 is made of glue material with adhesiveness, so as to fix the first semiconductor structure 10 on the edge ring.
  • step S200 after at least one first monomer 110 is formed on the first surface 101 or the second surface 102 of the first semiconductor structure 10, the following steps are further included:
  • UV rays are irradiated on the side of the first semiconductor structure 10 away from the first bonding surface 1101 to reduce the adhesion between the first monomer 110 and the fixing film, so as to facilitate subsequent expansion of the first semiconductor structure 10 .
  • a wafer expansion process is performed on the side of the first semiconductor structure 10 having at least one first monomer 110 .
  • the surface of the first semiconductor structure 10 having at least one first monomer 110 may be expanded by a wafer expander.
  • the expansion ring 30 in the wafer expansion machine can be press-attached to the edge position on the first semiconductor structure 10 , and the diameter of the expansion ring 30 is smaller than the inner diameter of the fixing ring 601 .
  • the first semiconductor structure with multiple first monomers can be expanded first, and then turned over as a whole; it can also be turned over with respect to the first semiconductor structure with multiple first monomers. Afterwards, expand the film.
  • the first monomer 110 is pushed out by the probe assembly 50 by a predetermined position. The distance is such that the first monomer 110 is separated from the fixed film 602 and then attached to the second bonding surface 2101 of the second monomer 210 .
  • a second semiconductor structure 20 having at least one second monomer 210 is provided.
  • the second semiconductor structure 20 includes but is not limited to a wafer, wherein the second semiconductor structure 20 can also be a chip or a substrate of semiconductor material. In this embodiment, it is described by taking the second semiconductor structure 20 as a wafer as an example. Wherein, the wafer may be made of semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compound, and silicon-oxygen compound.
  • the second semiconductor structure 20 may be fixed in the semiconductor device, so as to be bonded to the flipped first semiconductor structure 10 in a subsequent packaging process.
  • step S500 the first semiconductor structure 10 formed with at least one first monomer 110 is turned over as a whole, wherein the edge ring can be turned over as a whole by a manipulator or other equipment in the semiconductor equipment, so as to The first bonding surface 1101 of at least one first monomer 110 on the first semiconductor structure 10 is opposite to the second bonding surface 2101 of at least one second monomer 210 .
  • the first semiconductor structure 10 is rotated by a first preset angle so that the first bonding surface 1101 is opposite to the second bonding surface 2101 .
  • the rotation range of the first preset angle is 0-180°, and the rotation degree of the first preset angle can be flexibly selected according to the fixed position of the second semiconductor structure 20 in the semiconductor device.
  • the first semiconductor structure 10 can also be turned over as a whole by using the following method:
  • the first semiconductor structure 10 has a curved edge, and the entire first semiconductor structure 10 is flipped at a second preset angle by taking any edge tangent of the first semiconductor structure 10 as a flip axis. Or, take the parallel line on the first semiconductor structure 10 that is parallel to the edge tangent line as the flip axis, flip the first semiconductor structure as a whole by a second preset angle, so that the first bonding surface 1101 of at least one first monomer 110 It is opposite to the second bonding surface 2101 of the at least one second monomer 210 .
  • the rotation range of the second preset angle is 0-180°, and the rotation degree of the second preset angle can be flexibly selected according to the fixed position of the second semiconductor structure 20 in the semiconductor device.
  • step S600 an alignment process is performed on at least one first monomer 110 and at least one second monomer 210 disposed opposite to each other.
  • first monomers 110 in the first semiconductor structure 10 are the same as the dimensions of the plurality of second monomers 210 in the second semiconductor structure 20, only the first semiconductor The structure 10 and the second semiconductor structure 20 undergo an alignment process.
  • the standard size of the first monomer 110 is different from the standard size of the second monomer 210, each first monomer 110 and the corresponding second monomer 210 need to be aligned before being bonded. deal with.
  • the first center point A and the first mark of the first unit 110 are obtained.
  • the first marking process is performed on the first bonding surface 1101 of the first monomer 110 .
  • the first marking process includes adding a first marking point M and a second marking point N on the first bonding surface 1101 .
  • the shapes of the first marking point M and the second marking point N are different, and the first marking point M and the second marking point N are diagonally arranged.
  • each first unit 110 is square, for example, the shape of the first unit 110 is square or rectangular.
  • the number of the first marking point M is one, and the number of the second marking point N is an odd number greater than or equal to 1.
  • the number of the second marking point may be 1 or 3.
  • the number of the first marking point M is 1, and the shape of the first marking point M is T-shaped; the number of the second marking point N is 3, and the shape of the second marking point N is marked It is cross-shaped.
  • the first marking point M is arranged at one of the multiple vertex corners of the first bonding surface 1101 on the first monomer 110, and an odd number of second marking points N are arranged on multiple corners of the first bonding surface 1101. the rest of the corners. That is to say, the first marking point M and one of the second marking points N are arranged diagonally at both ends of one of the diagonal lines of the square first unit 110, and a second marking point is formed between the two marking points.
  • a virtual connection line L1 the other two second marking points N are set at the two ends of another diagonal line, and a second virtual connection line L2 is formed between the two marking points, so that on the first cell 110 A first center point A is formed on the surface of the bonding surface 1101 , that is, the first center point A is formed by the intersection of the first virtual line L1 and the second virtual line L2 .
  • first marking point M and the second marking point N on the first bonding surface 1101 on the first monomer 110 are both one, wherein the first marking point M and the The second marking points N are arranged symmetrically along the same straight line, and the straight line passes through the central point of the square first unit 110 .
  • a fourth virtual link L4 is formed between the first marking point M and the second marking point N, and the center of the fourth virtual link L4 is the first central point A.
  • the first marking process on the first unit 110 and the second marking process on the second unit 210 use a high-speed camera to obtain and record the first center point A, and obtain the first virtual line L1 and the second The virtual connection L2, wherein the first symbol includes the first virtual connection L1 and the second virtual connection L2, or the first symbol includes the fourth virtual connection L4.
  • a second center point and a second mark of the second monomer 210 are acquired.
  • the second marking process is performed on the second bonding surface 2101 of the second monomer 210 first.
  • the second marking process includes adding a third marking point P and a fourth marking point Q on the second bonding surface 2101 .
  • the shapes of the third marking point P and the fourth marking point Q are different, and the third marking point P and the fourth marking point Q are diagonally arranged.
  • each second unit 210 is square, for example, the second unit 210 is square or rectangular.
  • the number of the third marking point P and the number of the fourth marking point Q are both one, wherein, the shape marking the third marking point P is T-shaped, and the shape marking the fourth marking point Q is cross-shaped.
  • the third marking point P is arranged at one of the apex corners of the second bonding surface 2101 of the second monomer 210, and the fourth marking point Q is arranged on the second bonding surface 2101 with the third marking point Point P is at the top corner of the diagonal.
  • a third virtual link L3 is formed between the third marking point P and the fourth marking point Q. At this time, the midpoint of the third virtual line L3 is the second center point B.
  • the arrangement of the third marking point P and the fourth marking point Q After the position is also determined, the length of the third virtual connection L3 and its center point can be quickly determined.
  • the positions of the third virtual connection L3 and its center point can be pre-stored in the control system of the semiconductor device, or can be It was captured and recorded by a high-speed camera.
  • the second mark includes a third virtual line L3.
  • the second flag includes a third virtual line L3.
  • the first The position of the monomer 110 is such that the first central point A on the first bonding surface 1101 of the first monomer 110 coincides with the second central point B on the second bonding surface 2101 of the second monomer 210, and at the same time, The rotation angle of the first unit 110 is adjusted, so that the alignment between the first unit 110 and the second unit 210 is completed quickly.
  • the first unit 110 and the second unit 210 by setting marking points in the first unit 110 and the second unit 210, and using the coincidence of the center point and the coincidence of the virtual line, the first unit 110 and the second unit can be quickly realized.
  • the precise alignment between 210 improves the bonding quality in subsequent processes.
  • step S700 when at least one first monomer 110 and at least one second monomer 210 are aligned, one of the first monomers 110 is pushed out a predetermined distance, so that the second A unit 110 is detached from the fixing film 602, and the first unit 110 is brought into abutment with the second unit 210 aligned therewith.
  • hybrid bonding is performed on the first bonding surface 1101 of the first monomer 110 and the second bonding surface 2101 of the second monomer 210 aligned therewith.
  • hybrid bonding is a direct bonding technique, e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive), and can simultaneously achieve metal-metal bonding and Dielectric-dielectric bonding.
  • a separate metal-metal bonding between the first monomer 110 and the second monomer 210 may also be performed; or, it may also be the first monomer 110 and the second monomer A separate dielectric-dielectric bonding is performed between the two monomers 210 .
  • the first semiconductor structure having at least one first monomer is turned over as a whole, and then the first monomer is directly bonded to the second semiconductor structure, eliminating the need to The process of separately separating and transporting the first monomer from the first semiconductor structure avoids the surface contamination of the bonding surface of the semiconductor structure caused by multiple flips, thereby effectively improving the bonding quality and bonding efficiency of the semiconductor structure .
  • An exemplary embodiment of the present disclosure also provides a semiconductor device.
  • the semiconductor device includes a carrier 40 , a processing component 70 , a turning component (not shown in the figure), an alignment component (not shown in the figure) and a probe component 50 .
  • a fixing component 60 is disposed on the carrier platform 40 , and the fixing component 60 is used for fixing the first semiconductor structure 10 on the carrier platform 40 .
  • the second semiconductor structure 20 to be bonded is fixed on the side of the carrying platform 40 .
  • the first semiconductor structure 10 has a first surface 101 and a second surface 102 oppositely disposed.
  • the processing component 70 is used to process the first surface 101 or the second surface 102 of the first semiconductor structure 10, so as to form at least one first unit 110 on the first surface 101 or the second surface 102, wherein the first unit The top surface of the body 110 forms a first bonding surface 1101 .
  • the overturning component is connected with the carrying platform 40 and is used for turning over the carrying platform 40 as a whole, so as to turn over the first semiconductor structure 10 as a whole.
  • the alignment component is used for aligning the first bonding surface 1101 of the at least one first monomer 110 and the second bonding surface 2101 of the at least one second monomer 210 of the second semiconductor structure 20 .
  • the alignment processing process performed by the alignment component may refer to the alignment processing process in step S600 above.
  • the probe assembly 50 is used to realize the bonding connection between the first bonding surface 1101 and the second bonding surface 1201 .
  • the bonding connection methods include hybrid bonding, metal-metal bonding and dielectric-dielectric bonding.
  • the fixing component 60 includes a fixing ring 601 and a fixing film 602 .
  • the fixing ring 601 is detachably connected to the carrying platform 40 .
  • the fixing film 602 is pasted on the fixing ring 601 for fixing the first semiconductor structure 10 on the fixing ring.
  • the fixing ring 601 may adopt an edge ring in a semiconductor device.
  • the fixing film 602 is made of glue material, such as chip tape.
  • the first surface 101 or the second surface 102 of the first semiconductor structure 10 is adhered to the fixing film 602 .
  • Using the fixing ring 601 and the fixing film 602 can quickly and accurately fix the first semiconductor structure 10, improve the stability of the subsequent sawing process of the first semiconductor structure 10, and effectively ensure the sawing of the first semiconductor structure 10 precision.
  • the processing component 70 includes a cutting machine, then the formation process of at least one first monomer 110 on the first semiconductor structure 10 can adopt the following method:
  • first surface 101 or the second surface 102 of the first semiconductor structure 10 are provided a plurality of criss-crossing dicing lines 103 .
  • the first semiconductor structure 10 is sawed along the cutting line 103 by a cutting machine, so as to form at least one first monomer 110 on the first surface 101 or the second surface 102 .
  • a cutting machine By pre-designing the cutting line 103 on the first surface 101 or the second surface 102 and cutting with a cutting machine to form the first unit 110 , the operation is simple and the cutting size of each first unit 110 can be effectively guaranteed.
  • the turning assembly includes a first manipulator connected to the carrying platform 40 .
  • the first manipulator turns over the carrying platform 40 as a whole, so as to realize the whole turning over of the first semiconductor structure 10 .
  • the flipping accuracy of the first semiconductor structure 10 can be effectively guaranteed, and the accuracy in the subsequent alignment process can be improved, thereby improving the bonding quality of the semiconductor structure.
  • the alignment assembly includes a second manipulator and a viewing device.
  • the second manipulator is arranged at the edge of the carrying platform 40, and is used to align the first bonding surface 1101 of at least one first monomer 110 with the second bonding surface 2101 of at least one second monomer 210 of the second semiconductor structure 20. Alignment processing is performed.
  • the observation device is arranged at the working end of the second manipulator, wherein the observation device may include a high-speed camera for acquiring the first center point A of the first semiconductor structure 10, the first virtual line L1 and the second virtual line L2, and The second central point B and the third virtual connection line L3 of the second semiconductor structure 20 are obtained.
  • the first center point A coincides with the second center point B
  • the third virtual line L3 coincides with the first virtual line L1 or the second virtual line L2. Therefore, the alignment between the first monomer 110 and the second monomer 210 can be quickly realized, the alignment accuracy of the semiconductor structure can be improved, and the bonding quality and bonding efficiency of the semiconductor structure can be improved.
  • the probe assembly 50 includes a probe base 501 and a probe 502 .
  • the probe base 501 is set at the working end of the second manipulator and is set close to the observation device.
  • There are multiple probes 502 and they are arranged inside the probe holder 501 .
  • the probe 502 can move along the axial direction of the probe base 501 to push the first monomer 110 to move a predetermined distance, so that the first bonding surface 1101 of the first monomer 110 is attached to the surface of the second monomer 210. on the second bonding surface 2101 .
  • the probe base 501 includes an electrostatic chuck, and a plurality of probes 502 are located in the electrostatic chuck, wherein one end of the probes 502 can protrude to the outside of the electrostatic chuck.
  • the electrostatic chuck has an adsorption function, and can absorb the side of the first monomer 110 facing away from the first bonding surface 1101, so as to prevent the position shift of the first monomer 110 after the alignment process, and then, multiple probes
  • the needle 502 is slowly ejected from the electrostatic chuck, and along the ejection direction of the first monomer 110, the position difference between the first monomer 110 and the surrounding first monomers is formed, so that the first monomer 110 of the first monomer 110 A bonding surface 1101 is attached to a second bonding surface 2101 opposite to it. Then, a mixed bonding treatment is performed to bond the first monomer 110 and the second monomer 210 .
  • the probe base 501 includes a probe base body 5011, the probe base body 5011 has a working surface 5012, an adsorption region 5013 is arranged on the working surface 5012, the adsorption region 5013 and the negative pressure device connected.
  • the adsorption region 5013 By setting the adsorption region 5013 on the probe base body 5011 , the side of the first monomer 110 away from the first bonding surface 1101 can be adsorbed, preventing the position displacement of the first monomer 110 after the alignment process.
  • a plurality of probes 502 are located inside the probe holder body 5011, and one end of the probes 502 can pass through the adsorption area 5013, along the ejection direction of the first monomer 110, make the first monomer 110 and its surroundings
  • the first monomer forms a position difference, so that the first bonding surface 1101 of the first monomer 110 is bonded to the second bonding surface 2101 opposite thereto.
  • a mixed bonding treatment is performed to bond the first monomer 110 and the second monomer 210 .
  • the first semiconductor structure forming at least one first unit is turned over as a whole, and then the first unit and the second unit are aligned, and then the probe assembly is used to make the first unit One bonding surface and the second bonding surface opposite to it are mixed and bonded, which saves the process of separately separating and transporting the first monomer from the first semiconductor structure, and avoids the semiconductor structure caused by multiple flipping.
  • the surface contamination of the bonding surface can effectively improve the bonding quality and bonding efficiency of the semiconductor structure.
  • the first semiconductor structure with at least one first monomer is turned over as a whole, and then the bonding process is performed, which greatly reduces the bonding of the semiconductor structure.
  • the number of flips in the process avoids the surface contamination of the semiconductor structure caused by multiple flips, thereby effectively improving the bonding quality and bonding efficiency of the semiconductor structure.

Abstract

Disclosed are a semiconductor structure bonding method, and a semiconductor device, which relate to the technical field of semiconductors. The semiconductor structure bonding method comprises: providing a first semiconductor structure with a first surface and a second surface that are opposite to each other; processing the first surface or the second surface to form at least one first element having a first bonding surface; expanding the first semiconductor structure; providing a second semiconductor structure with a second bonding surface; overturning the entire first semiconductor structure; aligning the first bonding surface and the second bonding surface; and completing the bonding process.

Description

半导体结构的键合方法和半导体设备Bonding method of semiconductor structure and semiconductor device
本公开基于申请号为202111210755.0,申请日为2021年10月18日,申请名称为“半导体结构的键合方法和半导体设备”的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本公开作为参考。This disclosure is based on the Chinese patent application with the application number 202111210755.0, the application date is October 18, 2021, and the application name is "bonding method of semiconductor structure and semiconductor equipment", and claims the priority of the Chinese patent application. The entire content of the patent application is hereby incorporated by reference into this disclosure.
技术领域technical field
本公开涉及但不限于一种半导体结构的键合方法和半导体设备。The present disclosure relates to, but is not limited to, a bonding method of a semiconductor structure and a semiconductor device.
背景技术Background technique
在半导体制造过程中,通常需要对半导体结构的各个表面进行各种工艺处理。随着半导体行业的发展,对半导体结构的集成度和功能的要求越来越高封装技术在半导体产品中扮演着越来越重要的角色。在电子设备的内部结构中,半导体结构例如芯片、功能元器件等的密集度不断增加,而器件关键尺寸不断较小,这给半导体封装行业带来极大挑战。During the semiconductor manufacturing process, it is usually necessary to perform various processes on each surface of the semiconductor structure. With the development of the semiconductor industry, the requirements for the integration and function of the semiconductor structure are getting higher and higher. Packaging technology plays an increasingly important role in semiconductor products. In the internal structure of electronic equipment, the density of semiconductor structures such as chips and functional components continues to increase, while the critical dimensions of devices continue to decrease, which brings great challenges to the semiconductor packaging industry.
半导体结构的封装工艺制程中,具有键合面的半导体结构会被多次翻转,从而不可避免的造成半导体结构的键合面被污染,降低了半导体结构的键合效率和键合质量。During the packaging process of the semiconductor structure, the semiconductor structure with the bonding surface will be turned over many times, which will inevitably cause the bonding surface of the semiconductor structure to be polluted, reducing the bonding efficiency and bonding quality of the semiconductor structure.
发明内容Contents of the invention
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
本公开提供一种半导体结构的键合方法和半导体设备。The present disclosure provides a bonding method of a semiconductor structure and a semiconductor device.
本公开实施例的第一方面提供了一种半导体结构的键合方法,包括:A first aspect of an embodiment of the present disclosure provides a method for bonding a semiconductor structure, including:
提供第一半导体结构,所述第一半导体结构具有相对设置的第一面和第二面;providing a first semiconductor structure having oppositely disposed first and second sides;
对所述第一面或所述第二面进行处理,使所述第一面或所述第二面上形 成至少一个第一单体,其中,所述第一单体具有第一键合面;processing the first surface or the second surface so that at least one first monomer is formed on the first surface or the second surface, wherein the first monomer has a first bonding surface ;
对所述第一半导体结构进行扩片处理;performing wafer expansion on the first semiconductor structure;
提供具有至少一个第二单体的第二半导体结构,所述第二单体具有第二键合面,所述第二半导体结构固定;providing a second semiconductor structure having at least one second monomer having a second bonding surface, the second semiconductor structure being immobilized;
整体翻转所述第一半导体结构,使所述至少一个第一单体的第一键合面与所述至少一个第二单体的第二键合面相对;Flipping the first semiconductor structure as a whole, so that the first bonding surface of the at least one first monomer is opposite to the second bonding surface of the at least one second monomer;
对所述至少一个第一单体和所述至少一个第二单体进行对准处理,使所述第一键合面与所述第二键合面对准;performing an alignment process on the at least one first monomer and the at least one second monomer to align the first bonding surface with the second bonding surface;
所述第一键合面和所述第二键合面键合连接。The first bonding surface is bonded to the second bonding surface.
根据本公开的一些实施例,在整体翻转所述第一半导体结构,使所述第一键合面与所述第二键合面相对中,包括:According to some embodiments of the present disclosure, turning the first semiconductor structure over so that the first bonding surface is opposite to the second bonding surface includes:
以所述第一半导体结构的任意一条中轴线为旋转轴,所述第一半导体结构旋转第一预设角度,以使所述第一键合面与所述第二键合面相对;Taking any central axis of the first semiconductor structure as a rotation axis, the first semiconductor structure is rotated by a first preset angle so that the first bonding surface is opposite to the second bonding surface;
或者,or,
所述第一半导体结构具有曲线边缘,以所述第一半导体结构的任意一条边缘切线,或者,与所述边缘切线相互平行的平行线为翻转轴,所述第一半导体结构整体翻转第二预设角度,以使所述第一键合面与所述第二键合面相对。The first semiconductor structure has a curved edge, and any edge tangent of the first semiconductor structure, or a parallel line parallel to the edge tangent is used as a flip axis, and the first semiconductor structure is completely flipped over the second preset. An angle is set so that the first bonding surface is opposite to the second bonding surface.
根据本公开的一些实施例,在对所述第一半导体结构和所述第二半导体结构进行对准处理中,包括:According to some embodiments of the present disclosure, performing the alignment process on the first semiconductor structure and the second semiconductor structure includes:
获取所述第一单体的第一中心点和第一标志;Acquiring a first center point and a first mark of the first monomer;
获取所述第二单体的第二中心点和第二标志;obtaining a second center point and a second mark of the second monomer;
使所述第一中心点与所述第二中心点重合、所述第一标志与所述第二标志重合。The first center point coincides with the second center point, and the first mark coincides with the second mark.
根据本公开的一些实施例,在获取所述第一单体的第一中心点和第一标志中,包括:According to some embodiments of the present disclosure, obtaining the first center point and the first mark of the first monomer includes:
在所述第一键合面上进行第一标记处理,其中,所述第一标记处理包括在所述第一键合面上添加第一标记点和第二标记点,所述第一标记点的形状与所述第二标记点的形状不同,且所述第一标记点与所述第二标记点斜对角 设置;Perform a first marking process on the first bonding surface, wherein the first marking process includes adding a first marking point and a second marking point on the first bonding surface, the first marking point The shape of the second marking point is different from that of the second marking point, and the first marking point and the second marking point are arranged diagonally;
在获取所述第二单体的第二中心点和第二标志中,包括:Obtaining the second center point and the second mark of the second monomer includes:
在所述第二键合面上进行第二标记处理,其中,所述第二标记处理包括在所述第二键合面上添加第三标记点和第四标记点,所述第三标记点的形状与所述第四标记点的形状不同,且所述第三标记点与所述第四标记点斜对角设置。Perform a second marking process on the second bonding surface, wherein the second marking process includes adding a third marking point and a fourth marking point on the second bonding surface, the third marking point The shape of is different from that of the fourth marking point, and the third marking point and the fourth marking point are arranged diagonally.
根据本公开的一些实施例,所述第一单体为方形,所述第一标记点的个数为一个,所述第二标记点的个数为大于等于1的奇数个;According to some embodiments of the present disclosure, the first monomer is square, the number of the first marking point is one, and the number of the second marking point is an odd number greater than or equal to 1;
在所述第一键合面上进行第一标记处理中,包括:Performing the first marking process on the first bonding surface includes:
将所述第一标记点布置于所述第一键合面的多个顶角中的一个顶角处,将奇数个所述第二标记点布置于所述第一键合面的多个顶角中的其余顶角处;arranging the first marking point at one of the apex corners of the first bonding surface, and arranging an odd number of the second marking points at a plurality of apexes of the first bonding surface at the remaining top corners of the corner;
其中,所述第一标记点同与其呈对对角的顶角处的所述第二标记点之间形成第一虚拟连线,剩余的所述第二标记点之间形成第二虚拟连线,所述第一虚拟连线与所述第二虚拟连线的交点形成所述第一中心点;Wherein, a first virtual connection line is formed between the first marking point and the second marking point at the corner opposite to it, and a second virtual connection line is formed between the remaining second marking points , the intersection of the first virtual connection and the second virtual connection forms the first central point;
所述第二单体为方形,所述第三标记点和所述第四标记点的个数均为一个;The second monomer is square, and the number of the third marking point and the number of the fourth marking point are both one;
在所述第二键合面上进行第二标记处理中,包括:Performing the second marking process on the second bonding surface includes:
将所述第三标记点布置于所述第二键合面的多个顶角中的一个顶角处,所述第四标记点布置于与所述第三标记点呈对对角的顶角处;arranging the third marking point at a vertex among the plurality of vertex corners of the second bonding surface, and the fourth marking point is arranged at a vertex opposite to the third marking point place;
其中,所述第三标记点和所述第四标记点之间形成第三虚拟连线,所述第三虚拟连线的中点为所述第二中心点。Wherein, a third virtual connection line is formed between the third marking point and the fourth marking point, and the midpoint of the third virtual connection line is the second center point.
根据本公开的一些实施例,对所述第一面或所述第二面进行处理中,包括:According to some embodiments of the present disclosure, processing the first surface or the second surface includes:
对所述第一面或所述第二面进行锯切,以在所述第一面或所述第二面上形成所述至少一个第一单体,其中,所述第一单体的顶面形成所述第一键合面。performing sawing on the first surface or the second surface to form the at least one first monomer on the first surface or the second surface, wherein the top of the first monomer A surface forms the first bonding surface.
根据本公开的一些实施例,所述半导体结构的键合方法还包括:According to some embodiments of the present disclosure, the bonding method of the semiconductor structure further includes:
对所述第一半导体结构中背离所述第一键合面的一侧照射UV射线。Irradiating UV rays to the side of the first semiconductor structure away from the first bonding plane.
根据本公开的一些实施例,在所述第一键合面和所述第二键合面键合连接中,包括:According to some embodiments of the present disclosure, the bonding connection between the first bonding surface and the second bonding surface includes:
将所述至少一个第一单体推出预定距离,并与与其相对准的所述第二单体抵接;pushing out the at least one first unit by a predetermined distance, and abutting against the second unit aligned therewith;
对所述第一单体的所述第一键合面和所述第二单体的第二键合面进行混合键合连接。A mixed bonding connection is performed on the first bonding surface of the first monomer and the second bonding surface of the second monomer.
本公开实施例的第二方面提供了一种半导体设备,包括:A second aspect of the embodiments of the present disclosure provides a semiconductor device, including:
承载台,所述承载台上设有固定组件,所述固定组件用于将第一半导体结构固定于所述承载台上,第二半导体结构固定于所述承载台的旁侧,其中,所述第一半导体结构具有相对设置的第一面和第二面;The bearing platform, the fixing component is arranged on the bearing platform, and the fixing component is used to fix the first semiconductor structure on the bearing platform, and the second semiconductor structure is fixed on the side of the bearing platform, wherein the The first semiconductor structure has a first face and a second face disposed opposite to each other;
处理组件,用于对所述第一半导体结构的所述第一面或所述第二面进行处理,使所述第一面或所述第二面上形成至少一个第一单体;a processing component, configured to process the first surface or the second surface of the first semiconductor structure, so that at least one first monomer is formed on the first surface or the second surface;
翻转组件,与所述承载台连接,用于整体翻转所述承载台,以整体翻转所述第一半导体结构;An overturning component, connected to the carrying platform, is used to turn over the carrying platform as a whole, so as to turn over the first semiconductor structure as a whole;
对准组件,用于对所述至少一个第一单体的第一键合面与所述第二半导体结构的至少一个第二单体的第二键合面进行对准处理;an alignment component for aligning the first bonding surface of the at least one first monomer with the second bonding surface of the at least one second monomer of the second semiconductor structure;
探针组件,用于实现所述第一键合面和所述第二键合面键合连接。The probe assembly is used to realize the bonding connection between the first bonding surface and the second bonding surface.
根据本公开的一些实施例,所述固定组件包括固定环和固定薄膜,所述固定环可拆卸地连接在所述承载台上,所述固定薄膜贴附于所述固定环上,用于将所述第一半导体结构固定在所述固定环上。According to some embodiments of the present disclosure, the fixing assembly includes a fixing ring and a fixing film, the fixing ring is detachably connected to the carrying platform, and the fixing film is attached to the fixing ring for The first semiconductor structure is fixed on the fixing ring.
根据本公开的一些实施例,所述第一半导体结构的所述第一面或所述第二面上设有多个横纵交错的切割道;According to some embodiments of the present disclosure, the first surface or the second surface of the first semiconductor structure is provided with a plurality of criss-crossing dicing lines;
所述处理组件包括切割机,所述切割机沿所述切割道对所述第一半导体结构锯切,以使所述第一面或所述第二面上形成所述至少一个第一单体。The processing assembly includes a dicing machine that saws the first semiconductor structure along the dicing lane to form the at least one first monomer on the first face or the second face .
根据本公开的一些实施例,所述翻转组件包括第一机械手,所述第一机械手与所述承载台连接。According to some embodiments of the present disclosure, the turning assembly includes a first manipulator, and the first manipulator is connected to the carrying platform.
根据本公开的一些实施例,所述对准组件包括第二机械手和观察装置,所述第二机械手设置在所述承载台的边缘处,所述观察装置设置在所述第二机械手的工作端。According to some embodiments of the present disclosure, the alignment assembly includes a second manipulator and an observation device, the second manipulator is disposed at the edge of the carrying platform, and the observation device is disposed at the working end of the second manipulator .
根据本公开的一些实施例,所述探针组件包括探针座和探针,所述探针座设置在所述第二机械手的工作端,所述探针座靠近所述观察装置设置,其中,所述探针为多个,且所述探针设在所述探针座内部,所述探针可沿所述探针座的轴向方向移动,以推动所述第一单体运动预定距离,使所述第一键合面贴合于所述第二键合面上。According to some embodiments of the present disclosure, the probe assembly includes a probe base and a probe, the probe base is disposed at the working end of the second manipulator, the probe base is disposed close to the observation device, wherein , there are a plurality of probes, and the probes are arranged inside the probe seat, and the probes can move along the axial direction of the probe seat to push the first monomer to move for a predetermined time. distance, so that the first bonding surface is attached to the second bonding surface.
根据本公开的一些实施例,所述探针座包括静电卡盘,多个所述探针位于所述静电卡盘内,所述探针的一端可伸出至所述静电卡盘的外侧。According to some embodiments of the present disclosure, the probe base includes an electrostatic chuck, a plurality of the probes are located in the electrostatic chuck, and one end of the probes can protrude to the outside of the electrostatic chuck.
根据本公开的一些实施例,所述探针座包括探针座本体,所述探针座本体具有工作面,所述工作面上设置有吸附区域,所述吸附区域与负压装置连通;According to some embodiments of the present disclosure, the probe base includes a probe base body, the probe base body has a working surface, the working surface is provided with an adsorption area, and the adsorption area communicates with the negative pressure device;
其中,多个所述探针位于所述探针座本体内部,且所述探针的一端可由所述吸附区域中穿出。Wherein, a plurality of the probes are located inside the probe holder body, and one end of the probes can pass through the adsorption area.
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书,附图以及权利要求书变得明显。The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description, drawings, and claims.
附图说明Description of drawings
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例,并且与描述一起用于解释本公开实施例的原理。在这些附图中,类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例,而不是全部实施例。对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,可以根据这些附图获得其他的附图。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some, but not all, embodiments of the present disclosure. Those skilled in the art can obtain other drawings based on these drawings without creative efforts.
图1是根据一示例性实施例示出的半导体结构的键合方法的流程图。Fig. 1 is a flow chart of a bonding method for a semiconductor structure according to an exemplary embodiment.
图2是根据一示例性实施例示出的半导体结构的键合方法的示意图。Fig. 2 is a schematic diagram of a bonding method for a semiconductor structure according to an exemplary embodiment.
图3是根据一示例性实施例示出的半导体结构的键合方法中第一半导体结构的固定方式的示意图。Fig. 3 is a schematic diagram of a fixing manner of a first semiconductor structure in a method for bonding semiconductor structures according to an exemplary embodiment.
图4是根据一示例性实施例示出的半导体结构的键合方法中对锯切后的第一半导体结构的照射UV射线的示意图。Fig. 4 is a schematic diagram of irradiating a sawn first semiconductor structure with UV rays in a bonding method of semiconductor structures according to an exemplary embodiment.
图5是根据一示例性实施例示出的半导体结构的键合方法中对第一半导体结构进行扩片处理的示意图。Fig. 5 is a schematic diagram of performing wafer expansion on a first semiconductor structure in a bonding method for semiconductor structures according to an exemplary embodiment.
图6是图5的俯视方向的示意图。FIG. 6 is a schematic view of FIG. 5 in a plan view direction.
图7是根据一示例性实施例示出的半导体结构的键合方法中对第一半导体结构进行第一标记处理的示意图。Fig. 7 is a schematic diagram of performing a first marking process on a first semiconductor structure in a bonding method of semiconductor structures according to an exemplary embodiment.
图8是根据一示例性实施例示出的半导体结构的键合方法中进行对准处理的示意图。Fig. 8 is a schematic diagram showing an alignment process in a bonding method of a semiconductor structure according to an exemplary embodiment.
图9是根据一示例性实施例示出的半导体结构的键合方法中进行键合连接的示意图。Fig. 9 is a schematic diagram showing a bonding connection in a bonding method of a semiconductor structure according to an exemplary embodiment.
图10是根据一示例性实施例示出的半导体设备中探针组件的示意图。Fig. 10 is a schematic diagram of a probe assembly in a semiconductor device according to an exemplary embodiment.
图11是根据一示例性实施例示出的半导体设备中探针组件的示意图。Fig. 11 is a schematic diagram of a probe assembly in a semiconductor device according to an exemplary embodiment.
附图标记:Reference signs:
10、第一半导体结构;20、第二半导体结构;10. A first semiconductor structure; 20. A second semiconductor structure;
30、扩片环;40、承载台;30. Expansion ring; 40. Carrying platform;
50、探针组件;60、固定组件;50. Probe assembly; 60. Fixed assembly;
70、处理组件;101、第一面;70. Processing components; 101. The first side;
102、第二面;103、切割道;102, the second side; 103, the cutting road;
110、第一单体;210、第二单体;110, the first monomer; 210, the second monomer;
501、探针座;502、探针;501, probe seat; 502, probe;
601、固定环;602、固定薄膜;601, fixed ring; 602, fixed film;
1101、第一键合面;2101、第二键合面;1101, the first bonding surface; 2101, the second bonding surface;
5011、探针座本体;5012、工作面;5011, probe base body; 5012, working surface;
5013、吸附区域;5013. Adsorption area;
A、第一中心点;B第二中心点;A. The first center point; B The second center point;
L1、第一虚拟连线;L2、第二虚拟连线;L1, the first virtual connection; L2, the second virtual connection;
L3、第三虚拟连线;L4、第四虚拟连线;L3, the third virtual connection; L4, the fourth virtual connection;
M、第一标记点;N、第二标记点;M, the first marking point; N, the second marking point;
P、第三标记点;Q、第四标记点。P, the third marking point; Q, the fourth marking point.
具体实施方式Detailed ways
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公 开实施例中的附图,对公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。需要说明的是,在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互任意组合。In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments It is a part of the embodiments of the present disclosure, but not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
半导体结构在封装过程中,通常是将整片晶圆切割成多个间隔开设置的芯片,而后通过机械手等转运设备吸附在该芯片的键合面上,使该芯片与晶圆分离,而后经过转运设备的多次翻转再与待键合的半导体结构进行键合,而半导体结构在经过多次翻转后,会不可避免的造成半导体结构的键合面被污染。During the packaging process of the semiconductor structure, the whole wafer is usually cut into a plurality of chips arranged at intervals, and then is adsorbed on the bonding surface of the chip by a transfer device such as a manipulator, so that the chip is separated from the wafer, and then passed through The transfer equipment is turned over many times and then bonded to the semiconductor structure to be bonded. After the semiconductor structure is turned over many times, the bonding surface of the semiconductor structure will inevitably be polluted.
在半导体结构中,为了保证半导体结构键合的可靠性和安装性,在两个半导体结构键合之前,需要对半导体结构的键合面的表面进行清洗,并且每个芯片都需要进行清洗。导致后续封装过程中,尤其是采用混合键合方式的封装制程中,键合制程十分繁琐,降低了半导体结构的键合效率和键合质量。In the semiconductor structure, in order to ensure the reliability and mountability of the bonding of the semiconductor structures, the surface of the bonding surface of the semiconductor structures needs to be cleaned before the bonding of the two semiconductor structures, and each chip needs to be cleaned. As a result, in the subsequent packaging process, especially in the packaging process using a hybrid bonding method, the bonding process is very cumbersome, which reduces the bonding efficiency and bonding quality of the semiconductor structure.
本公开实施例提供了一种半导体结构的键合方法和半导体设备,通过将具有至少一个第一单体的第一半导体结构进行整体翻转,而后再进行键合过程,大大减少了半导体结构键合过程中的翻转次数,避免了因多次翻转而导致的半导体结构的表面污染问题,从而有效提高了半导体结构的键合质量和键合效率。Embodiments of the present disclosure provide a semiconductor structure bonding method and a semiconductor device. By turning over the first semiconductor structure with at least one first monomer as a whole, and then performing the bonding process, the bonding process of the semiconductor structure is greatly reduced. The number of flips in the process avoids the surface contamination of the semiconductor structure caused by multiple flips, thereby effectively improving the bonding quality and bonding efficiency of the semiconductor structure.
本公开示例性的实施例中提供了一种半导体结构的键合方法,如图1所示,图1示出了根据本公开以示例性的实施例提供的半导体结构的键合方法的流程图,下面结合图1至图9对半导体结构的键合方法进行介绍。An exemplary embodiment of the present disclosure provides a bonding method for a semiconductor structure, as shown in FIG. 1 , and FIG. 1 shows a flow chart of a bonding method for a semiconductor structure provided in an exemplary embodiment according to the present disclosure. , the bonding method of the semiconductor structure will be introduced below with reference to FIGS. 1 to 9 .
本实施例对半导体结构不作限制,下面将以半导体结构为晶圆为例进行介绍,但本实施例并不以此为限,本实施例中的半导体结构还可以为其他的结构,例如动态随机存储器(Dynamic Random Access Memory,DRAM)。This embodiment does not limit the semiconductor structure. The following will introduce the semiconductor structure as a wafer as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures, such as dynamic random Memory (Dynamic Random Access Memory, DRAM).
如图1所述,本公开一示例性的实施例提供了一种半导体结构的键合方法,包括:As shown in FIG. 1 , an exemplary embodiment of the present disclosure provides a bonding method for a semiconductor structure, including:
步骤S100:提供第一半导体结构,第一半导体结构具有相对设置的第一面和第二面。Step S100 : providing a first semiconductor structure, the first semiconductor structure has a first surface and a second surface opposite to each other.
步骤S200:对第一面或第二面进行处理,使第一面或第二面上形成至少一个第一单体,其中,第一单体具有第一键合面。Step S200: Processing the first surface or the second surface to form at least one first monomer on the first surface or the second surface, wherein the first monomer has a first bonding surface.
步骤S300:对第一半导体结构进行扩片处理。Step S300: Perform wafer expansion on the first semiconductor structure.
步骤S400:提供具有至少一个第二单体的第二半导体结构,第二单体具有第二键合面,第二半导体结构固定。Step S400 : providing a second semiconductor structure having at least one second monomer, the second monomer has a second bonding surface, and the second semiconductor structure is fixed.
步骤S500:整体翻转第一半导体结构,使至少一个第一单体的第一键合面与至少一个第二单体的第二键合面相对。Step S500: Flip over the first semiconductor structure as a whole, so that the first bonding surface of at least one first monomer is opposite to the second bonding surface of at least one second monomer.
步骤S600:对至少一个第一单体和至少一个第二单体进行对准处理,使第一键合面与第二键合面对准。Step S600: performing an alignment process on at least one first monomer and at least one second monomer to align the first bonding surface with the second bonding surface.
步骤S700:第一键合面和第二键合面键合连接。Step S700: bonding the first bonding surface and the second bonding surface.
示例性地,如图1和图7所示,在步骤S100中,提供第一半导体结构10,第一半导体结构10具有相对设置的第一面101和第二面102。第一半导体结构10包括但不限于晶圆,其中,第一半导体结构10也可以是芯片或者是半导体材料的基底。在本实施例中,以第一半导体结构10和第二半导体结构20均为晶圆为例进行说明。Exemplarily, as shown in FIG. 1 and FIG. 7 , in step S100 , a first semiconductor structure 10 is provided, and the first semiconductor structure 10 has a first surface 101 and a second surface 102 disposed opposite to each other. The first semiconductor structure 10 includes but is not limited to a wafer, wherein the first semiconductor structure 10 may also be a chip or a substrate of semiconductor material. In this embodiment, description is made by taking the first semiconductor structure 10 and the second semiconductor structure 20 as wafers as an example.
其中,晶圆可以由半导体材质制成,半导体材料可以为硅、锗、硅锗化合物以及硅氧化合物中的一种或者多种。Wherein, the wafer may be made of semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compound, and silicon-oxygen compound.
参照图3所示,在步骤S200中,对第一半导体结构10的第一面101进行处理,使得第一面101上形成至少一个第一单体110。第一单体110的顶面形成第一键合面1101。Referring to FIG. 3 , in step S200 , the first surface 101 of the first semiconductor structure 10 is processed so that at least one first monomer 110 is formed on the first surface 101 . The top surface of the first monomer 110 forms a first bonding surface 1101 .
或者,对第一半导体结构10的第二面102进行处理,使得第二面102上形成至少一个第一单体110。第一单体110的顶面形成第一键合面1101。在一些实施例中,可以对第一面101或第二面102进行锯切,以在第一面101或第二面102上形成至少一个第一单体110,其中,第一单体110的顶面形成第一键合面1101。Alternatively, the second surface 102 of the first semiconductor structure 10 is processed so that at least one first monomer 110 is formed on the second surface 102 . The top surface of the first monomer 110 forms a first bonding surface 1101 . In some embodiments, the first surface 101 or the second surface 102 can be sawed to form at least one first unit 110 on the first surface 101 or the second surface 102, wherein the first unit 110 The top surface forms a first bonding surface 1101 .
其中,第一单体110的形成过程可以采用如下方法:Wherein, the formation process of the first monomer 110 can adopt the following method:
在第一半导体结构10的第一面101或者第二面102上设计多个沿横向和纵向交错设置的切割道103,沿同一延伸方向,相邻切割道103之间的间距可以相同,也可以不相同,该间距可以根据第一单体110的设计尺寸进行灵 活设定。然后,可以将第一半导体结构10放置在半导体设备的承载台40上,并通过固定环601和固定薄膜602将第一半导体结构10固定在承载台40上。需要说明的是,固定环604可以采用半导体设备中的边缘环,固定薄膜602为胶制材料,具有粘性,从而将第一半导体结构10固定在边缘环上。而后利用半导体切割机沿切割道103进行锯切,以快速在第一半导体结构10的第一面101或者第二面102形成至少一个第一单体110,沿切割道103进行切割,能有效保证每个第一单体110的切割尺寸。On the first surface 101 or the second surface 102 of the first semiconductor structure 10, a plurality of cutting lines 103 arranged alternately in the transverse direction and the vertical direction are designed. Along the same extension direction, the distance between adjacent cutting lines 103 can be the same or Not the same, the distance can be flexibly set according to the design size of the first unit 110 . Then, the first semiconductor structure 10 can be placed on the carrier platform 40 of the semiconductor device, and the first semiconductor structure 10 can be fixed on the carrier platform 40 through the fixing ring 601 and the fixing film 602 . It should be noted that the fixing ring 604 can be an edge ring in a semiconductor device, and the fixing film 602 is made of glue material with adhesiveness, so as to fix the first semiconductor structure 10 on the edge ring. Then use a semiconductor cutting machine to saw along the dicing road 103 to quickly form at least one first monomer 110 on the first surface 101 or the second surface 102 of the first semiconductor structure 10, and cut along the dicing road 103, which can effectively ensure The cutting size of each first monomer 110 .
需要说明的是,参照图4,在步骤S200中,当第一半导体结构10的第一面101或者第二面102上形成至少一个第一单体110之后,还包括以下步骤:It should be noted that, referring to FIG. 4, in step S200, after at least one first monomer 110 is formed on the first surface 101 or the second surface 102 of the first semiconductor structure 10, the following steps are further included:
对第一半导体结构10中背离第一键合面1101的一侧照射UV射线,以降低第一单体110与固定薄膜之间粘性,便于后续对第一半导体结构10进行扩片处理。UV rays are irradiated on the side of the first semiconductor structure 10 away from the first bonding surface 1101 to reduce the adhesion between the first monomer 110 and the fixing film, so as to facilitate subsequent expansion of the first semiconductor structure 10 .
示例性地,在步骤S300中,对第一半导体结构10上具有至少一个第一单体110的那一面进行扩片处理。参照图5和图6,可以通过晶圆扩片机对第一半导体结构10上具有至少一个第一单体110的那一面进行扩片处理。其中,可以通过晶圆扩片机中的扩片环30压附在第一半导体结构10上的边缘位置处,扩片环30的直径小于固定环601的内径。而后,提升固定环601,使固定环601相对于扩片环30向上移动,使第一半导体结构10上相邻的第一单体100的间距增大,便于后续对第一单体110的对准处理。需要说明的是,可以先对具有多个第一单体的第一半导体结构进行扩片处理后,然后再整体翻转;也可以是相对具有多个第一单体的第一半导体结构进行整体翻转后,再进行扩片处理。Exemplarily, in step S300 , a wafer expansion process is performed on the side of the first semiconductor structure 10 having at least one first monomer 110 . Referring to FIG. 5 and FIG. 6 , the surface of the first semiconductor structure 10 having at least one first monomer 110 may be expanded by a wafer expander. Wherein, the expansion ring 30 in the wafer expansion machine can be press-attached to the edge position on the first semiconductor structure 10 , and the diameter of the expansion ring 30 is smaller than the inner diameter of the fixing ring 601 . Then, lift the fixing ring 601, so that the fixing ring 601 moves upward relative to the expansion ring 30, so that the distance between the adjacent first cells 100 on the first semiconductor structure 10 is increased, which is convenient for the subsequent pairing of the first cells 110. Quasi processing. It should be noted that the first semiconductor structure with multiple first monomers can be expanded first, and then turned over as a whole; it can also be turned over with respect to the first semiconductor structure with multiple first monomers. Afterwards, expand the film.
其中,对于经过扩片处理后的第一单体110,由于固定薄膜602上还依然具有粘附效果,因此,在进行对准处理后,通过探针组件50将第一单体110顶出预定距离,使该第一单体110与固定薄膜602分离后,再与第二单体210的第二键合面2101进行贴合。Wherein, for the first monomer 110 after the expansion process, since the fixing film 602 still has an adhesive effect, after the alignment process, the first monomer 110 is pushed out by the probe assembly 50 by a predetermined position. The distance is such that the first monomer 110 is separated from the fixed film 602 and then attached to the second bonding surface 2101 of the second monomer 210 .
示例性地,如图2所示,在步骤S400中,提供具有至少一个第二单体210的第二半导体结构20。第二半导体结构20包括但不限于晶圆,其中,第 二半导体结构20也可以是芯片或者是半导体材料的基底。在本实施例中,以第二半导体结构20为晶圆为例进行说明。其中,晶圆可以由半导体材质制成,半导体材料可以为硅、锗、硅锗化合物以及硅氧化合物中的一种或者多种。Exemplarily, as shown in FIG. 2 , in step S400 , a second semiconductor structure 20 having at least one second monomer 210 is provided. The second semiconductor structure 20 includes but is not limited to a wafer, wherein the second semiconductor structure 20 can also be a chip or a substrate of semiconductor material. In this embodiment, it is described by taking the second semiconductor structure 20 as a wafer as an example. Wherein, the wafer may be made of semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compound, and silicon-oxygen compound.
在第二单体210上具有第二键合面2101,该第二键合面2101可以是第二单体210的顶面。第二半导体结构20可以是固定在半导体设备中的,以便于后续封装制程中与翻转后的第一半导体结构10进行键合连接。There is a second bonding surface 2101 on the second monomer 210 , and the second bonding surface 2101 may be the top surface of the second monomer 210 . The second semiconductor structure 20 may be fixed in the semiconductor device, so as to be bonded to the flipped first semiconductor structure 10 in a subsequent packaging process.
参照图2所示,在步骤S500中,对形成有至少一个第一单体110的第一半导体结构10进行整体翻转,其中,可以通过半导体设备中的机械手等设备对边缘环进行整体翻转,以使第一半导体结构10上的至少一个第一单体110的第一键合面1101与至少一个第二单体210的第二键合面2101相对。Referring to FIG. 2 , in step S500, the first semiconductor structure 10 formed with at least one first monomer 110 is turned over as a whole, wherein the edge ring can be turned over as a whole by a manipulator or other equipment in the semiconductor equipment, so as to The first bonding surface 1101 of at least one first monomer 110 on the first semiconductor structure 10 is opposite to the second bonding surface 2101 of at least one second monomer 210 .
需要说明的是,在对第一半导体结构10进行整体翻转过程中,可以采用以下方法进行翻转:It should be noted that, during the overall flipping process of the first semiconductor structure 10, the following methods can be used for flipping:
以第一半导体结构10的任意一条中轴线为旋转轴,将第一半导体结构10旋转第一预设角度,以使第一键合面1101与第二键合面2101相对。其中,第一预设角度的旋转范围为0-180°,该第一预设角度的旋转度数可以根据第二半导体结构20在半导体设备中的固定位置进行灵活选择的。Taking any central axis of the first semiconductor structure 10 as a rotation axis, the first semiconductor structure 10 is rotated by a first preset angle so that the first bonding surface 1101 is opposite to the second bonding surface 2101 . Wherein, the rotation range of the first preset angle is 0-180°, and the rotation degree of the first preset angle can be flexibly selected according to the fixed position of the second semiconductor structure 20 in the semiconductor device.
或者,还可以采用以下方法对第一半导体结构10进行整体翻转:Alternatively, the first semiconductor structure 10 can also be turned over as a whole by using the following method:
第一半导体结构10具有曲线边缘,以第一半导体结构10的任意一条边缘切线为翻转轴,对第一半导体结构10进行整体翻转第二预设角度。或者,以第一半导体结构10上与边缘切线相互平行的平行线为翻转轴,对第一半导体结构整体翻转第二预设角度,以使至少一个第一单体110的第一键合面1101与至少一个第二单体210的第二键合面2101相对。其中,第二预设角度的旋转范围为0-180°,该第二预设角度的旋转度数可以根据第二半导体结构20在半导体设备中的固定位置进行灵活选择的。The first semiconductor structure 10 has a curved edge, and the entire first semiconductor structure 10 is flipped at a second preset angle by taking any edge tangent of the first semiconductor structure 10 as a flip axis. Or, take the parallel line on the first semiconductor structure 10 that is parallel to the edge tangent line as the flip axis, flip the first semiconductor structure as a whole by a second preset angle, so that the first bonding surface 1101 of at least one first monomer 110 It is opposite to the second bonding surface 2101 of the at least one second monomer 210 . Wherein, the rotation range of the second preset angle is 0-180°, and the rotation degree of the second preset angle can be flexibly selected according to the fixed position of the second semiconductor structure 20 in the semiconductor device.
示例性地,如图8所示,在步骤S600中,对相对设置的至少一个第一单体110和至少一个第二单体210进行对准处理。需要说明的是,当第一半导体结构10中的多个第一单体110的规格尺寸与第二半导体结构20中的多个第二单体210的规格尺寸相同时,可以只对第一半导体结构10与第二半导体 结构20进行一次对准处理。而当第一单体110的规格尺寸与第二单体210的规格尺寸不相同时,每个第一单体110与相对应的第二单体210进行键合之间,均需要执行对准处理。Exemplarily, as shown in FIG. 8 , in step S600 , an alignment process is performed on at least one first monomer 110 and at least one second monomer 210 disposed opposite to each other. It should be noted that when the dimensions of the plurality of first monomers 110 in the first semiconductor structure 10 are the same as the dimensions of the plurality of second monomers 210 in the second semiconductor structure 20, only the first semiconductor The structure 10 and the second semiconductor structure 20 undergo an alignment process. And when the standard size of the first monomer 110 is different from the standard size of the second monomer 210, each first monomer 110 and the corresponding second monomer 210 need to be aligned before being bonded. deal with.
其中,第一单体110和第二单体210之间可以采用以下方法进行对准处理:Wherein, the following method can be used for alignment between the first monomer 110 and the second monomer 210:
获取第一单体110的第一中心点A和第一标志。其中,在获取第一单体110的第一中心点A和第一标志之前,先对第一单体110的第一键合面1101进行第一标记处理。在本实施例中,第一标记处理包括在第一键合面1101上添加第一标记点M和第二标记点N。其中,第一标记点M和第二标记点N的形状不相同,并且第一标记点M和第二标记点N斜对角设置。The first center point A and the first mark of the first unit 110 are obtained. Wherein, before obtaining the first center point A and the first mark of the first monomer 110 , the first marking process is performed on the first bonding surface 1101 of the first monomer 110 . In this embodiment, the first marking process includes adding a first marking point M and a second marking point N on the first bonding surface 1101 . Wherein, the shapes of the first marking point M and the second marking point N are different, and the first marking point M and the second marking point N are diagonally arranged.
在一些实施例中,每个第一单体110为方形,比如第一单体110的形状为正方形或者为长方形。In some embodiments, each first unit 110 is square, for example, the shape of the first unit 110 is square or rectangular.
第一标记点M的个数为一个,第二标记点N的个数为大于等于1的奇数个,比如第二标记点的个数可以是1个,也可以是3个。在一个实施例中,第一标记点M的个数为1个,标记第一标记点M的形状为T型;第二标记点N的个数为3个,标记第二标记点N的形状为十字型。The number of the first marking point M is one, and the number of the second marking point N is an odd number greater than or equal to 1. For example, the number of the second marking point may be 1 or 3. In one embodiment, the number of the first marking point M is 1, and the shape of the first marking point M is T-shaped; the number of the second marking point N is 3, and the shape of the second marking point N is marked It is cross-shaped.
将第一标记点M布置于第一单体110上第一键合面1101的多个顶角中的一个顶角处,将奇数个第二标记点N布置于第一键合面1101的多个顶角中的其余顶角处。也就是说,第一标记点M与其中一个第二标记点N呈斜对角设置在方形的第一单体110的其中一条对角线的两端,且该两个标记点之间形成第一虚拟连线L1,另外两个第二标记点N设置在另一条对角线的两端,该两个标记点之间形成第二虚拟连线L2,这样在第一单体110的第一键合面1101的表面上就会形成第一中心点A,即,第一虚拟连线L1和第二虚拟连线L2的交点形成第一中心点A。The first marking point M is arranged at one of the multiple vertex corners of the first bonding surface 1101 on the first monomer 110, and an odd number of second marking points N are arranged on multiple corners of the first bonding surface 1101. the rest of the corners. That is to say, the first marking point M and one of the second marking points N are arranged diagonally at both ends of one of the diagonal lines of the square first unit 110, and a second marking point is formed between the two marking points. A virtual connection line L1, the other two second marking points N are set at the two ends of another diagonal line, and a second virtual connection line L2 is formed between the two marking points, so that on the first cell 110 A first center point A is formed on the surface of the bonding surface 1101 , that is, the first center point A is formed by the intersection of the first virtual line L1 and the second virtual line L2 .
需要说明的是,在又一个实施例中,第一单体110上的第一键合面1101上的第一标记点M和第二标记点N均为一个,其中,第一标记点M和第二标记点N沿同一直线对称设置,且该直线穿过方形的第一单体110的中心点。此时,第一标记点M和第二标记点N之间形成第四虚拟连线L4,第四虚拟连线L4的中心即为第一中心点A。It should be noted that, in yet another embodiment, the first marking point M and the second marking point N on the first bonding surface 1101 on the first monomer 110 are both one, wherein the first marking point M and the The second marking points N are arranged symmetrically along the same straight line, and the straight line passes through the central point of the square first unit 110 . At this time, a fourth virtual link L4 is formed between the first marking point M and the second marking point N, and the center of the fourth virtual link L4 is the first central point A.
在完成对第一单体110的第一标记处理,和第二单体210的第二标记处理之后,利用高速摄像机获取并记录第一中心点A,以及获取第一虚拟连线L1和第二虚拟连线L2,其中,第一标志包括第一虚拟连线L1和第二虚拟连线L2,或者,第一标志包括第四虚拟连线L4。After completing the first marking process on the first unit 110 and the second marking process on the second unit 210, use a high-speed camera to obtain and record the first center point A, and obtain the first virtual line L1 and the second The virtual connection L2, wherein the first symbol includes the first virtual connection L1 and the second virtual connection L2, or the first symbol includes the fourth virtual connection L4.
获取第二单体210的第二中心点和第二标志。其中,在获取第二单体210的第二中心点B和第二标志之前,先对第二单体210的第二键合面2101进行第二标记处理。在本实施例中,第二标记处理包括在第二键合面2101上添加第三标记点P和第四标记点Q。其中,第三标记点P和第四标记点Q的形状不相同,并且第三标记点P和第四标记点Q斜对角设置。A second center point and a second mark of the second monomer 210 are acquired. Wherein, before obtaining the second center point B and the second mark of the second monomer 210, the second marking process is performed on the second bonding surface 2101 of the second monomer 210 first. In this embodiment, the second marking process includes adding a third marking point P and a fourth marking point Q on the second bonding surface 2101 . Wherein, the shapes of the third marking point P and the fourth marking point Q are different, and the third marking point P and the fourth marking point Q are diagonally arranged.
在一些实施例中,每个第二单体210为方形,比如第二单体210的形状为正方形或者为长方形。In some embodiments, each second unit 210 is square, for example, the second unit 210 is square or rectangular.
第三标记点P和第四标记点Q的个数均为一个,其中,标记第三标记点P的形状为T型,标记第四标记点Q的形状为十字形。将第三标记点P布置于第二单体210的第二键合面2101的多个顶角中的一个顶角处,第四标记点Q布置于第二键合面2101上与第三标记点P呈对角的顶角处。第三标记点P和第四标记点Q之间形成第三虚拟连线L3。此时,第三虚拟连线L3的中点为第二中心点B,需要说明的是,当第二单体210的尺寸确定之后,并且将第三标记点P和第四标记点Q的布置位置也确定以后,第三虚拟连线L3的长度及其中心点均能快速确定,该第三虚拟连线L3及其中心点的位置可以是预先储存在半导体设备的控制系统中的,也可以是利用高速摄像机捕获并记录储存的。其中,第二标记包括第三虚拟连线L3。The number of the third marking point P and the number of the fourth marking point Q are both one, wherein, the shape marking the third marking point P is T-shaped, and the shape marking the fourth marking point Q is cross-shaped. The third marking point P is arranged at one of the apex corners of the second bonding surface 2101 of the second monomer 210, and the fourth marking point Q is arranged on the second bonding surface 2101 with the third marking point Point P is at the top corner of the diagonal. A third virtual link L3 is formed between the third marking point P and the fourth marking point Q. At this time, the midpoint of the third virtual line L3 is the second center point B. It should be noted that after the size of the second unit 210 is determined, the arrangement of the third marking point P and the fourth marking point Q After the position is also determined, the length of the third virtual connection L3 and its center point can be quickly determined. The positions of the third virtual connection L3 and its center point can be pre-stored in the control system of the semiconductor device, or can be It was captured and recorded by a high-speed camera. Wherein, the second mark includes a third virtual line L3.
在获取了第一中心点A和第二中心点B,以及第一标志和第二标志之后,通过半导体设备中的机械手等设备调节第一半导体结构10与第二半导体结构20之间的相对位置,使第一中心点A与第二中心点B重合,以及使第三虚拟连线L3与第一虚拟连线L1重合,或者,使第三虚拟连线L3与第二虚拟连线L2重合,从而快速完成第一单体110与第二单体210之间的对准。After obtaining the first center point A and the second center point B, as well as the first mark and the second mark, adjust the relative position between the first semiconductor structure 10 and the second semiconductor structure 20 through a device such as a manipulator in the semiconductor device , make the first center point A coincide with the second center point B, and make the third virtual line L3 coincide with the first virtual line L1, or make the third virtual line L3 coincide with the second virtual line L2, Thus, the alignment between the first monomer 110 and the second monomer 210 is quickly completed.
其中,第二标志包括第三虚拟连线L3。Wherein, the second flag includes a third virtual line L3.
在一些实施例中,当第一单体110的第一键合面1101上具有第四虚拟连 线L4时,在第一单体110和第二单体210进行对准处理中,调整第一单体110的位置,使第一单体110的第一键合面1101上的第一中心点A与第二单体210的第二键合面2101上的第二中心点B重合,同时,调整第一单体110的旋转角度,从而快速完成第一单体110与第二单体210之间的对准。In some embodiments, when there is a fourth dummy line L4 on the first bonding surface 1101 of the first monomer 110, during the alignment process of the first monomer 110 and the second monomer 210, the first The position of the monomer 110 is such that the first central point A on the first bonding surface 1101 of the first monomer 110 coincides with the second central point B on the second bonding surface 2101 of the second monomer 210, and at the same time, The rotation angle of the first unit 110 is adjusted, so that the alignment between the first unit 110 and the second unit 210 is completed quickly.
在本实施例中,通过在第一单体110和第二单体210中设置标记点,并利用中心点重合以及虚拟连线重合的方式,可快速实现第一单体110和第二单体210之间的精确对准,提高后续制程中的键合质量。In this embodiment, by setting marking points in the first unit 110 and the second unit 210, and using the coincidence of the center point and the coincidence of the virtual line, the first unit 110 and the second unit can be quickly realized. The precise alignment between 210 improves the bonding quality in subsequent processes.
示例性地,如图9所示,在步骤S700中,当至少一个第一单体110和至少一个第二单体210对准后,将其中一个第一单体110推出预定距离,使该第一单体110从固定薄膜602上脱离,并使该第一单体110与与其相对准的第二单体210抵接。Exemplarily, as shown in FIG. 9, in step S700, when at least one first monomer 110 and at least one second monomer 210 are aligned, one of the first monomers 110 is pushed out a predetermined distance, so that the second A unit 110 is detached from the fixing film 602, and the first unit 110 is brought into abutment with the second unit 210 aligned therewith.
而后,对第一单体110的第一键合面1101与与其相对准的第二单体210的第二键合面2101进行混合键合连接。其中,混合键合是一种直接键合技术,例如,在不使用中间层(例如,焊料或粘合剂)的情况下在表面之间形成键合,并且可以同时获得金属-金属键合和电介质-电介质键合。Then, hybrid bonding is performed on the first bonding surface 1101 of the first monomer 110 and the second bonding surface 2101 of the second monomer 210 aligned therewith. Among them, hybrid bonding is a direct bonding technique, e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive), and can simultaneously achieve metal-metal bonding and Dielectric-dielectric bonding.
需要说明的是,在一些实施例中,也可以是对第一单体110和第二单体210之间进行单独的金属-金属键合;或者,也可以是对第一单体110和第二单体210之间进行单独的电介质-电介质键合。It should be noted that, in some embodiments, a separate metal-metal bonding between the first monomer 110 and the second monomer 210 may also be performed; or, it may also be the first monomer 110 and the second monomer A separate dielectric-dielectric bonding is performed between the two monomers 210 .
在本实施例半导体结构的键合方法中,通过将具有至少一个第一单体的第一半导体结构进行整体翻转,而后将第一单体直接键合在第二半导体结构上,省去了将第一单体从第一半导体结构中单独分离转运的过程,避免了因多次翻转而导致的半导体结构的键合面的表面污染问题,从而有效提高了半导体结构的键合质量和键合效率。In the bonding method of the semiconductor structure in this embodiment, the first semiconductor structure having at least one first monomer is turned over as a whole, and then the first monomer is directly bonded to the second semiconductor structure, eliminating the need to The process of separately separating and transporting the first monomer from the first semiconductor structure avoids the surface contamination of the bonding surface of the semiconductor structure caused by multiple flips, thereby effectively improving the bonding quality and bonding efficiency of the semiconductor structure .
本公开一示例性的实施例还提供了一种半导体设备。该半导体设备包括承载台40、处理组件70、翻转组件(图中未示出)、对准组件(图中未示出)和探针组件50。An exemplary embodiment of the present disclosure also provides a semiconductor device. The semiconductor device includes a carrier 40 , a processing component 70 , a turning component (not shown in the figure), an alignment component (not shown in the figure) and a probe component 50 .
其中,承载台40上设有固定组件60,该固定组件60用于将第一半导体结构10固定于承载台40上。待键合的第二半导体结构20固定于承载台40的旁侧。其中,第一半导体结构10具有相对设置的第一面101和第 二面102。Wherein, a fixing component 60 is disposed on the carrier platform 40 , and the fixing component 60 is used for fixing the first semiconductor structure 10 on the carrier platform 40 . The second semiconductor structure 20 to be bonded is fixed on the side of the carrying platform 40 . Wherein, the first semiconductor structure 10 has a first surface 101 and a second surface 102 oppositely disposed.
处理组件70用于对第一半导体结构10的第一面101或第二面102进行处理,从而在第一面101或第二面102上形成至少一个第一单体110,其中,第一单体110的顶面形成第一键合面1101。The processing component 70 is used to process the first surface 101 or the second surface 102 of the first semiconductor structure 10, so as to form at least one first unit 110 on the first surface 101 or the second surface 102, wherein the first unit The top surface of the body 110 forms a first bonding surface 1101 .
翻转组件与承载台40连接,用于对承载台40进行整体翻转,从而对第一半导体结构10进行整体翻转。The overturning component is connected with the carrying platform 40 and is used for turning over the carrying platform 40 as a whole, so as to turn over the first semiconductor structure 10 as a whole.
对准组件用于对至少一个第一单体110的第一键合面1101与第二半导体结构20的至少一个第二单体210的第二键合面2101进行对准处理。其中,对准组件进行对准处理的过程可以参照上述步骤S600中的对准处理过程。The alignment component is used for aligning the first bonding surface 1101 of the at least one first monomer 110 and the second bonding surface 2101 of the at least one second monomer 210 of the second semiconductor structure 20 . Wherein, the alignment processing process performed by the alignment component may refer to the alignment processing process in step S600 above.
探针组件50用于实现第一键合面1101和第二键合面1201之间的键合连接。需要说明的是,该键合连接方式包括混合键合、金属-金属键合和电介质-电介质键合。The probe assembly 50 is used to realize the bonding connection between the first bonding surface 1101 and the second bonding surface 1201 . It should be noted that the bonding connection methods include hybrid bonding, metal-metal bonding and dielectric-dielectric bonding.
如图3和图4所示,在一些实施例中,固定组件60包括固定环601和固定薄膜602。固定环601可拆卸地连接在承载台40上。固定薄膜602贴附于固定环601上,用于将第一半导体结构10固定在固定环上。As shown in FIGS. 3 and 4 , in some embodiments, the fixing component 60 includes a fixing ring 601 and a fixing film 602 . The fixing ring 601 is detachably connected to the carrying platform 40 . The fixing film 602 is pasted on the fixing ring 601 for fixing the first semiconductor structure 10 on the fixing ring.
其中,固定环601可以采用半导体设备中的边缘环。固定薄膜602采用胶质材制成,例如采用芯片胶带等。第一半导体结构10的第一面101或者第二面102粘附于固定薄膜602。利用固定环601和固定薄膜602能快速且准确的将第一半导体结构10进行固定,提高后续对第一半导体结构10进行锯切处理时的稳定性,以有效保证第一半导体结构10的锯切精度。Wherein, the fixing ring 601 may adopt an edge ring in a semiconductor device. The fixing film 602 is made of glue material, such as chip tape. The first surface 101 or the second surface 102 of the first semiconductor structure 10 is adhered to the fixing film 602 . Using the fixing ring 601 and the fixing film 602 can quickly and accurately fix the first semiconductor structure 10, improve the stability of the subsequent sawing process of the first semiconductor structure 10, and effectively ensure the sawing of the first semiconductor structure 10 precision.
参照图2和图3所示,在一些实施例中,处理组件70包括切割机,那么第一半导体结构10上至少一个第一单体110的形成过程可以采用如下方法:Referring to FIG. 2 and FIG. 3, in some embodiments, the processing component 70 includes a cutting machine, then the formation process of at least one first monomer 110 on the first semiconductor structure 10 can adopt the following method:
在第一半导体结构10的第一面101或者第二面102上设有多个横纵交错的切割道103。On the first surface 101 or the second surface 102 of the first semiconductor structure 10 are provided a plurality of criss-crossing dicing lines 103 .
而后,利用切割机沿切割道103对第一半导体结构10进行锯切,从而在第一面101或第二面102上形成至少一个第一单体110。通过预先在第一面101或第二面102上设计切割道103,并采用切割机进行切割的方式形成第一单体110,操作简单,能有效保证每个第一单体110的切割尺寸。Then, the first semiconductor structure 10 is sawed along the cutting line 103 by a cutting machine, so as to form at least one first monomer 110 on the first surface 101 or the second surface 102 . By pre-designing the cutting line 103 on the first surface 101 or the second surface 102 and cutting with a cutting machine to form the first unit 110 , the operation is simple and the cutting size of each first unit 110 can be effectively guaranteed.
在一些实施例中,翻转组件包括第一机械手,该第一机械手与承载台40连接。通过第一机械手对承载台40进行整体翻转,从而实现对第一半导体结构10进行整体翻转。In some embodiments, the turning assembly includes a first manipulator connected to the carrying platform 40 . The first manipulator turns over the carrying platform 40 as a whole, so as to realize the whole turning over of the first semiconductor structure 10 .
通过第一机械手,能有效保证第一半导体结构10的翻转精度,提高后续对准制程中的准确性,进而提高半导体结构的键合质量。Through the first manipulator, the flipping accuracy of the first semiconductor structure 10 can be effectively guaranteed, and the accuracy in the subsequent alignment process can be improved, thereby improving the bonding quality of the semiconductor structure.
在一些实施例中,对准组件包括第二机械手和观察装置。第二机械手设置在承载台40的边缘处,用于对至少一个第一单体110的第一键合面1101与第二半导体结构20的至少一个第二单体210的第二键合面2101进行对准处理。观察装置设置在第二机械手的工作端,其中,观察装置可以包括高速摄像机,用于获取第一半导体结构10的第一中心点A、第一虚拟连线L1和第二虚拟连线L2,以及获取第二半导体结构20的第二中心点B和第三虚拟连线L3。利用第二机械手配合观察装置,使得第一中心点A与第二中心点B重合,第三虚拟连线L3与第一虚拟连线L1或第二虚拟连线L2重合。从而快速实现第一单体110与第二单体210之间的对准,提高半导体结构的对准精度,进而提高半导体结构的键合质量和键合效率。In some embodiments, the alignment assembly includes a second manipulator and a viewing device. The second manipulator is arranged at the edge of the carrying platform 40, and is used to align the first bonding surface 1101 of at least one first monomer 110 with the second bonding surface 2101 of at least one second monomer 210 of the second semiconductor structure 20. Alignment processing is performed. The observation device is arranged at the working end of the second manipulator, wherein the observation device may include a high-speed camera for acquiring the first center point A of the first semiconductor structure 10, the first virtual line L1 and the second virtual line L2, and The second central point B and the third virtual connection line L3 of the second semiconductor structure 20 are obtained. Using the second manipulator to cooperate with the observation device, the first center point A coincides with the second center point B, and the third virtual line L3 coincides with the first virtual line L1 or the second virtual line L2. Therefore, the alignment between the first monomer 110 and the second monomer 210 can be quickly realized, the alignment accuracy of the semiconductor structure can be improved, and the bonding quality and bonding efficiency of the semiconductor structure can be improved.
如图10和图11所示,在一些实施例中,探针组件50包括探针座501和探针502。探针座501设置在第二机械手的工作端,并靠近观察装置设置。探针502的个数为多个,并设置在探针座501的内部。其中,探针502可沿探针座501的轴向方向移动,以推动第一单体110运动预定距离,使第一单体110的第一键合面1101贴合于第二单体210的第二键合面2101上。As shown in FIGS. 10 and 11 , in some embodiments, the probe assembly 50 includes a probe base 501 and a probe 502 . The probe base 501 is set at the working end of the second manipulator and is set close to the observation device. There are multiple probes 502 , and they are arranged inside the probe holder 501 . Wherein, the probe 502 can move along the axial direction of the probe base 501 to push the first monomer 110 to move a predetermined distance, so that the first bonding surface 1101 of the first monomer 110 is attached to the surface of the second monomer 210. on the second bonding surface 2101 .
在一个实施例中,参照图10所示,探针座501包括静电卡盘,多个探针502位于静电卡盘内,其中,探针502的一端可伸出至静电卡盘的外侧。其中,静电卡盘具有吸附功能,可以将第一单体110背离第一键合面1101的一面吸附住,防止经过对准处理后的第一单体110发生位置偏移,而后,多个探针502从静电卡盘中缓慢顶出,沿第一单体110的顶出方向,使该第一单体110与其周围的第一单体构成位置差,从而将该第一单体110的第一键合面1101与与其相对的第二键合面2101贴合。然后再进行混合键合处理,使第一单体110与第二单体210键合连接。In one embodiment, as shown in FIG. 10 , the probe base 501 includes an electrostatic chuck, and a plurality of probes 502 are located in the electrostatic chuck, wherein one end of the probes 502 can protrude to the outside of the electrostatic chuck. Wherein, the electrostatic chuck has an adsorption function, and can absorb the side of the first monomer 110 facing away from the first bonding surface 1101, so as to prevent the position shift of the first monomer 110 after the alignment process, and then, multiple probes The needle 502 is slowly ejected from the electrostatic chuck, and along the ejection direction of the first monomer 110, the position difference between the first monomer 110 and the surrounding first monomers is formed, so that the first monomer 110 of the first monomer 110 A bonding surface 1101 is attached to a second bonding surface 2101 opposite to it. Then, a mixed bonding treatment is performed to bond the first monomer 110 and the second monomer 210 .
在一个实施例中,参照图11所示,探针座501包括探针座本体5011, 探针座本体5011具有工作面5012,工作面5012上设置有吸附区域5013,吸附区域5013与负压装置连通。通过在探针座本体5011上设置吸附区域5013,可以将第一单体110背离第一键合面1101的一面吸附住,防止经过对准处理后的第一单体110发生位置偏移。In one embodiment, as shown in FIG. 11 , the probe base 501 includes a probe base body 5011, the probe base body 5011 has a working surface 5012, an adsorption region 5013 is arranged on the working surface 5012, the adsorption region 5013 and the negative pressure device connected. By setting the adsorption region 5013 on the probe base body 5011 , the side of the first monomer 110 away from the first bonding surface 1101 can be adsorbed, preventing the position displacement of the first monomer 110 after the alignment process.
其中,多个探针502位于探针座本体5011内部,且探针502的一端可由吸附区域5013中穿出,沿第一单体110的顶出方向,使该第一单体110与其周围的第一单体构成位置差,从而将该第一单体110的第一键合面1101与与其相对的第二键合面2101贴合。然后再进行混合键合处理,使第一单体110与第二单体210键合连接。Wherein, a plurality of probes 502 are located inside the probe holder body 5011, and one end of the probes 502 can pass through the adsorption area 5013, along the ejection direction of the first monomer 110, make the first monomer 110 and its surroundings The first monomer forms a position difference, so that the first bonding surface 1101 of the first monomer 110 is bonded to the second bonding surface 2101 opposite thereto. Then, a mixed bonding treatment is performed to bond the first monomer 110 and the second monomer 210 .
在本实施例的半导体设备中,通过将形成至少一个第一单体的第一半导体结构进行整体翻转,而后对第一单体和第二单体进行对准处理,再利用探针组件使第一键合面与与其相对的第二键合面进行混合键合处理,省去了将第一单体从第一半导体结构中单独分离转运的过程,避免了因多次翻转而导致的半导体结构的键合面的表面污染问题,从而有效提高了半导体结构的键合质量和键合效率。In the semiconductor device of this embodiment, the first semiconductor structure forming at least one first unit is turned over as a whole, and then the first unit and the second unit are aligned, and then the probe assembly is used to make the first unit One bonding surface and the second bonding surface opposite to it are mixed and bonded, which saves the process of separately separating and transporting the first monomer from the first semiconductor structure, and avoids the semiconductor structure caused by multiple flipping. The surface contamination of the bonding surface can effectively improve the bonding quality and bonding efficiency of the semiconductor structure.
在本说明书的描述中,参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。In the description of this specification, descriptions with reference to the terms "embodiments", "exemplary embodiments", "some implementations", "exemplary implementations", "examples" and the like mean that the descriptions are described in conjunction with the implementations or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure.
在本说明书中,对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
在本公开的描述中,需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的顶或位置关系为基于附图所示的顶或位置关系,仅是为了便于描述本公开和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的顶、以特定的顶构造和操作,因此不能理解为对本公开的限制。In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated top or positional relationship is based on the top or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific top, use a specific top construction and operation are therefore not to be construed as limitations on the present disclosure.
可以理解的是,本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构,但这些结构不受这些术语的限制。这些术语仅用于将第一 个结构与另一个结构区分。It can be understood that the terms "first", "second" and the like used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
在一个或多个附图中,相同的元件采用类似的附图标记来表示。为了清楚起见,附图中的多个部分没有按比例绘制。此外,可能未示出某些公知的部分。为了简明起见,可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样,可以不按照这些特定的细节来实现本公开。In one or more drawings, like elements are indicated with like reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of devices, are described for a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
最后应说明的是:以上各实施例仅用以说明本公开的技术方案,而非对其限制;尽管参照前述各实施例对本公开进行了详细的说明,本领域技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some or all of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the various embodiments of the present invention.
工业实用性Industrial Applicability
本公开实施例所提供的半导体结构的键合方法和半导体设备中,通过将具有至少一个第一单体的第一半导体结构进行整体翻转,而后再进行键合过程,大大减少了半导体结构键合过程中的翻转次数,避免了因多次翻转而导致的半导体结构的表面污染问题,从而有效提高了半导体结构的键合质量和键合效率。In the semiconductor structure bonding method and semiconductor device provided by the embodiments of the present disclosure, the first semiconductor structure with at least one first monomer is turned over as a whole, and then the bonding process is performed, which greatly reduces the bonding of the semiconductor structure. The number of flips in the process avoids the surface contamination of the semiconductor structure caused by multiple flips, thereby effectively improving the bonding quality and bonding efficiency of the semiconductor structure.

Claims (16)

  1. 一种半导体结构的键合方法,包括:A bonding method for a semiconductor structure, comprising:
    提供第一半导体结构,所述第一半导体结构具有相对设置的第一面和第二面;providing a first semiconductor structure having oppositely disposed first and second sides;
    对所述第一面或所述第二面进行处理,使所述第一面或所述第二面上形成至少一个第一单体,其中,所述第一单体具有第一键合面;processing the first surface or the second surface so that at least one first monomer is formed on the first surface or the second surface, wherein the first monomer has a first bonding surface ;
    对所述第一半导体结构进行扩片处理;performing wafer expansion on the first semiconductor structure;
    提供具有至少一个第二单体的第二半导体结构,所述第二单体具有第二键合面,所述第二半导体结构固定;providing a second semiconductor structure having at least one second monomer having a second bonding surface, the second semiconductor structure being immobilized;
    整体翻转所述第一半导体结构,使所述至少一个第一单体的第一键合面与所述至少一个第二单体的第二键合面相对;Flipping the first semiconductor structure as a whole, so that the first bonding surface of the at least one first monomer is opposite to the second bonding surface of the at least one second monomer;
    对所述至少一个第一单体和所述至少一个第二单体进行对准处理,使所述第一键合面与所述第二键合面对准;performing an alignment process on the at least one first monomer and the at least one second monomer to align the first bonding surface with the second bonding surface;
    所述第一键合面和所述第二键合面键合连接。The first bonding surface is bonded to the second bonding surface.
  2. 根据权利要求1所述的半导体结构的键合方法,其中,在整体翻转所述第一半导体结构,使所述第一键合面与所述第二键合面相对中,包括:The bonding method of a semiconductor structure according to claim 1, wherein, in flipping the first semiconductor structure as a whole, so that the first bonding surface is opposite to the second bonding surface, comprising:
    以所述第一半导体结构的任意一条中轴线为旋转轴,所述第一半导体结构旋转第一预设角度,以使所述第一键合面与所述第二键合面相对;Taking any central axis of the first semiconductor structure as a rotation axis, the first semiconductor structure is rotated by a first preset angle so that the first bonding surface is opposite to the second bonding surface;
    或者,or,
    所述第一半导体结构具有曲线边缘,以所述第一半导体结构的任意一条边缘切线,或者,与所述边缘切线相互平行的平行线为翻转轴,所述第一半导体结构整体翻转第二预设角度,以使所述第一键合面与所述第二键合面相对。The first semiconductor structure has a curved edge, and any edge tangent of the first semiconductor structure, or a parallel line parallel to the edge tangent is used as a flip axis, and the first semiconductor structure is completely flipped over the second preset. An angle is set so that the first bonding surface is opposite to the second bonding surface.
  3. 根据权利要求1所述的半导体结构的键合方法,其中,在对所述第一半导体结构和所述第二半导体结构进行对准处理中,包括:The bonding method of a semiconductor structure according to claim 1, wherein, in performing alignment processing on the first semiconductor structure and the second semiconductor structure, comprising:
    获取所述第一单体的第一中心点和第一标志;Acquiring a first center point and a first mark of the first monomer;
    获取所述第二单体的第二中心点和第二标志;obtaining a second center point and a second mark of the second monomer;
    使所述第一中心点与所述第二中心点重合、所述第一标志与所述第二标志重合。The first center point coincides with the second center point, and the first mark coincides with the second mark.
  4. 根据权利要求3所述的半导体结构的键合方法,其中,在获取所述第一单体的第一中心点和第一标志中,包括:The bonding method of a semiconductor structure according to claim 3, wherein, in obtaining the first center point and the first mark of the first monomer, comprising:
    在所述第一键合面上进行第一标记处理,其中,所述第一标记处理包括在所述第一键合面上添加第一标记点和第二标记点,所述第一标记点的形状与所述第二标记点的形状不同,且所述第一标记点与所述第二标记点斜对角设置;Perform a first marking process on the first bonding surface, wherein the first marking process includes adding a first marking point and a second marking point on the first bonding surface, the first marking point The shape of the second marking point is different from that of the second marking point, and the first marking point and the second marking point are arranged diagonally;
    在获取所述第二单体的第二中心点和第二标志中,包括:Obtaining the second center point and the second mark of the second monomer includes:
    在所述第二键合面上进行第二标记处理,其中,所述第二标记处理包括在所述第二键合面上添加第三标记点和第四标记点,所述第三标记点的形状与所述第四标记点的形状不同,且所述第三标记点与所述第四标记点斜对角设置。Perform a second marking process on the second bonding surface, wherein the second marking process includes adding a third marking point and a fourth marking point on the second bonding surface, the third marking point The shape of is different from that of the fourth marking point, and the third marking point and the fourth marking point are arranged diagonally.
  5. 根据权利要求4所述的半导体结构的键合方法,其中,所述第一单体为方形,所述第一标记点的个数为一个,所述第二标记点的个数为大于等于1的奇数个;The method for bonding a semiconductor structure according to claim 4, wherein the first monomer is square, the number of the first marking point is one, and the number of the second marking point is greater than or equal to 1 an odd number of
    在所述第一键合面上进行第一标记处理中,包括:Performing the first marking process on the first bonding surface includes:
    将所述第一标记点布置于所述第一键合面的多个顶角中的一个顶角处,将奇数个所述第二标记点布置于所述第一键合面的多个顶角中的其余顶角处;arranging the first marking point at one of the apex corners of the first bonding surface, and arranging an odd number of the second marking points at a plurality of apexes of the first bonding surface at the remaining top corners of the corner;
    其中,所述第一标记点同与其呈对对角的顶角处的所述第二标记点之间形成第一虚拟连线,剩余的所述第二标记点之间形成第二虚拟连线,所述第一虚拟连线与所述第二虚拟连线的交点形成所述第一中心点;Wherein, a first virtual connection line is formed between the first marking point and the second marking point at the corner opposite to it, and a second virtual connection line is formed between the remaining second marking points , the intersection of the first virtual connection and the second virtual connection forms the first central point;
    所述第二单体为方形,所述第三标记点和所述第四标记点的个数均为一个;The second monomer is square, and the number of the third marking point and the number of the fourth marking point are both one;
    在所述第二键合面上进行第二标记处理中,包括:Performing the second marking process on the second bonding surface includes:
    将所述第三标记点布置于所述第二键合面的多个顶角中的一个顶角处,所述第四标记点布置于与所述第三标记点呈对对角的顶角处;arranging the third marking point at a vertex among the plurality of vertex corners of the second bonding surface, and the fourth marking point is arranged at a vertex opposite to the third marking point place;
    其中,所述第三标记点和所述第四标记点之间形成第三虚拟连线,所述 第三虚拟连线的中点为所述第二中心点。Wherein, a third virtual connection line is formed between the third marking point and the fourth marking point, and the midpoint of the third virtual connection line is the second central point.
  6. 根据权利要求1所述的半导体结构的键合方法,其中,对所述第一面或所述第二面进行处理中,包括:The bonding method of a semiconductor structure according to claim 1, wherein, processing the first surface or the second surface includes:
    对所述第一面或所述第二面进行锯切,以在所述第一面或所述第二面上形成所述至少一个第一单体,其中,所述第一单体的顶面形成所述第一键合面。performing sawing on the first surface or the second surface to form the at least one first monomer on the first surface or the second surface, wherein the top of the first monomer A surface forms the first bonding surface.
  7. 根据权利要求1所述的半导体结构的键合方法,其中,所述半导体结构的键合方法还包括:The bonding method of a semiconductor structure according to claim 1, wherein the bonding method of the semiconductor structure further comprises:
    对所述第一半导体结构中背离所述第一键合面的一侧照射UV射线。Irradiating UV rays to the side of the first semiconductor structure away from the first bonding plane.
  8. 根据权利要求1-7任一项所述的半导体结构的键合方法,其中,在所述第一键合面和所述第二键合面键合连接中,包括:The bonding method of a semiconductor structure according to any one of claims 1-7, wherein, in the bonding connection between the first bonding surface and the second bonding surface, comprising:
    将所述至少一个第一单体推出预定距离,并与与其相对准的所述第二单体抵接;pushing out the at least one first unit by a predetermined distance, and abutting against the second unit aligned therewith;
    对所述第一单体的所述第一键合面和所述第二单体的第二键合面进行混合键合连接。A mixed bonding connection is performed on the first bonding surface of the first monomer and the second bonding surface of the second monomer.
  9. 一种半导体设备,包括:A semiconductor device comprising:
    承载台,所述承载台上设有固定组件,所述固定组件用于将第一半导体结构固定于所述承载台上,第二半导体结构固定于所述承载台的旁侧,其中,所述第一半导体结构具有相对设置的第一面和第二面;The bearing platform, the fixing component is arranged on the bearing platform, and the fixing component is used to fix the first semiconductor structure on the bearing platform, and the second semiconductor structure is fixed on the side of the bearing platform, wherein the The first semiconductor structure has a first face and a second face disposed opposite to each other;
    处理组件,用于对所述第一半导体结构的所述第一面或所述第二面进行处理,使所述第一面或所述第二面上形成至少一个第一单体;a processing component, configured to process the first surface or the second surface of the first semiconductor structure, so that at least one first monomer is formed on the first surface or the second surface;
    翻转组件,与所述承载台连接,用于整体翻转所述承载台,以整体翻转所述第一半导体结构;An overturning component, connected to the carrying platform, is used to turn over the carrying platform as a whole, so as to turn over the first semiconductor structure as a whole;
    对准组件,用于对所述至少一个第一单体的第一键合面与所述第二半导体结构的至少一个第二单体的第二键合面进行对准处理;an alignment component for aligning the first bonding surface of the at least one first monomer with the second bonding surface of the at least one second monomer of the second semiconductor structure;
    探针组件,用于实现所述第一键合面和所述第二键合面键合连接。The probe assembly is used to realize the bonding connection between the first bonding surface and the second bonding surface.
  10. 根据权利要求9所述的半导体设备,其中,所述固定组件包括固定环和固定薄膜,所述固定环可拆卸地连接在所述承载台上,所述固定薄膜贴附于所述固定环上,用于将所述第一半导体结构固定在所述固定环上。The semiconductor device according to claim 9, wherein the fixing assembly comprises a fixing ring and a fixing film, the fixing ring is detachably connected to the carrier platform, and the fixing film is attached to the fixing ring , for fixing the first semiconductor structure on the fixing ring.
  11. 根据权利要求9所述的半导体设备,其中,所述第一半导体结构的所述第一面或所述第二面上设有多个横纵交错的切割道;The semiconductor device according to claim 9, wherein a plurality of criss-crossing dicing lines are provided on the first surface or the second surface of the first semiconductor structure;
    所述处理组件包括切割机,所述切割机沿所述切割道对所述第一半导体结构锯切,以使所述第一面或所述第二面上形成所述至少一个第一单体。The processing assembly includes a dicing machine that saws the first semiconductor structure along the dicing lane to form the at least one first monomer on the first face or the second face .
  12. 根据权利要求9所述的半导体设备,其中,所述翻转组件包括第一机械手,所述第一机械手与所述承载台连接。The semiconductor device according to claim 9, wherein the turning assembly includes a first manipulator connected to the carrier.
  13. 根据权利要求9所述的半导体设备,其中,所述对准组件包括第二机械手和观察装置,所述第二机械手设置在所述承载台的边缘处,所述观察装置设置在所述第二机械手的工作端。The semiconductor device according to claim 9, wherein the alignment assembly comprises a second manipulator and an observation device, the second manipulator is arranged at the edge of the carrier table, and the observation device is arranged on the second The working end of the manipulator.
  14. 根据权利要求13所述的半导体设备,其中,所述探针组件包括探针座和探针,所述探针座设置在所述第二机械手的工作端,所述探针座靠近所述观察装置设置,其中,所述探针为多个,且所述探针设在所述探针座内部,所述探针可沿所述探针座的轴向方向移动,以推动所述第一单体运动预定距离,使所述第一键合面贴合于所述第二键合面上。The semiconductor device according to claim 13, wherein the probe assembly comprises a probe base and a probe, the probe base is arranged at the working end of the second manipulator, the probe base is close to the observation The device is set, wherein there are multiple probes, and the probes are arranged inside the probe holder, and the probes can move along the axial direction of the probe holder to push the first The monomer moves a predetermined distance, so that the first bonding surface is attached to the second bonding surface.
  15. 根据权利要求14所述的半导体设备,其中,所述探针座包括静电卡盘,多个所述探针位于所述静电卡盘内,所述探针的一端可伸出至所述静电卡盘的外侧。The semiconductor device according to claim 14, wherein said probe base includes an electrostatic chuck, a plurality of said probes are located in said electrostatic chuck, and one end of said probes can extend to said electrostatic chuck outside of the disk.
  16. 根据权利要求14所述的半导体设备,其中,所述探针座包括探针座本体,所述探针座本体具有工作面,所述工作面上设置有吸附区域,所述吸附区域与负压装置连通;The semiconductor device according to claim 14, wherein the probe base includes a probe base body, the probe base body has a working surface, and the working surface is provided with an adsorption area, and the adsorption area and the negative pressure device connectivity;
    其中,多个所述探针位于所述探针座本体内部,且所述探针的一端可由所述吸附区域中穿出。Wherein, a plurality of the probes are located inside the probe holder body, and one end of the probes can pass through the adsorption area.
PCT/CN2021/129242 2021-10-18 2021-11-08 Semiconductor structure bonding method, and semiconductor device WO2023065410A1 (en)

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JP2005340423A (en) * 2004-05-26 2005-12-08 Renesas Technology Corp Method for manufacturing semiconductor device
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