CN215220714U - Three-dimensional stacked structure - Google Patents

Abstract

The utility model discloses a three-dimensional stacked structure, this three-dimensional stacked structure include the structure body and set up in the benchmark layer on the surface of structure body. The structure body comprises a first wafer and a second wafer, the first wafer and the second wafer are in face-to-face bonding, a plurality of storage units are arranged in the first wafer, a plurality of logic units are arranged in the second wafer, and each logic unit is matched with at least one storage unit to form a corresponding three-dimensional stacking unit. The reference layer comprises a plurality of reference units which correspond to the three-dimensional stacking units one by one, and each reference unit is arranged on the periphery of the corresponding three-dimensional stacking unit and used for marking the area range where the corresponding three-dimensional stacking unit is located so as to cut and align the three-dimensional stacking structure, thereby being beneficial to improving the cutting precision.

Description

Three-dimensional stacked structure

Technical Field

The utility model belongs to the technical field of the semiconductor, especially, relate to a three-dimensional stacked structure.

Background

A Three-Dimensional Integrated Circuits (3 DIC) technology is a technology for connecting a logic chip and a memory chip by a hybrid bonding (hybrid bonding) technology, and since communication channels of the logic chip and the memory chip are greatly increased, a bandwidth can be significantly increased. The logic chip and the memory chip are attached in a face-to-face mode, the wafer containing the logic chip can be turned over, and then the wafer containing the memory chip is bonded with the wafer containing the memory chip through a hybrid bonding technology. When the chip is packaged, the silicon substrate of the logic chip is seen from the front surface of the wafer, and the chip boundary cannot be seen, so that the cutting alignment is difficult to realize.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a through providing a three-dimensional stacked structure, can improve above-mentioned chip that piles up effectively and be difficult to realize the technical problem that the cutting was aimed at.

In a first aspect, an embodiment of the present invention provides a three-dimensional stacked structure, including:

the structure body comprises a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded in a face-to-face mode, a plurality of storage units are arranged in the first wafer, a plurality of logic units are arranged in the second wafer, and each logic unit is matched with at least one storage unit to form a corresponding three-dimensional stacking unit;

the datum layer is arranged on the surface of the structure body and comprises a plurality of datum units which are in one-to-one correspondence with the three-dimensional stacking units, and each datum unit is arranged on the periphery of the corresponding three-dimensional stacking unit and used for marking the area range where the corresponding three-dimensional stacking unit is located so as to cut and align the three-dimensional stacking structure.

Further, the reference layer is disposed on the substrate surface of the second wafer.

Further, the reference layer is disposed on the substrate surface of the first wafer.

Further, the reference unit is ring-shaped.

Further, the reference unit includes a plurality of reference points or a plurality of reference line segments distributed at the periphery of the corresponding three-dimensional stacked unit.

Further, each memory unit and the periphery of each logic unit are provided with a protection ring, and each reference unit is arranged corresponding to the protection ring with the largest size in the corresponding three-dimensional stacking unit.

Further, an outer edge line of each reference unit coincides with an orthographic projection of an outer edge line of a largest-sized guard ring in the corresponding three-dimensional stacked unit on a reference plane, wherein the reference plane is a plane parallel to the first wafer and the second wafer.

Further, each reference unit coincides with an orthographic projection of the largest-sized guard ring in the corresponding three-dimensional stacked unit on a reference plane, wherein the reference plane is a plane parallel to the first wafer and the second wafer.

Further, the reference layer is made of a metal material.

Further, the metal material is copper or aluminum.

The embodiment of the utility model provides a three-dimensional stacked structure has add the benchmark layer on the structure body surface that first wafer of face-to-face bonding and second wafer obtained, and the benchmark layer includes a plurality of and each three-dimensional reference unit that piles up the unit one-to-one in the structure body, and every reference unit sets up in the periphery that corresponding three-dimensional unit that piles up for mark the regional scope at corresponding three-dimensional unit place that piles up. Therefore, in the chip packaging process, the reference units arranged on the periphery of each three-dimensional stacking unit are used as cutting references, and the cutting channels of the three-dimensional stacking structure are defined so as to be aligned with the cutting channels for cutting, so that the cutting precision is improved, the scrappage caused by cutting deviation is reduced, and the production yield is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a three-dimensional stacking structure according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating a reference unit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second wafer according to an embodiment of the present invention.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

When the inventor researches the 3DIC process, the inventor finds that the traditional chip is designed with a protection ring (seal ring), and the protection ring is used as the chip boundary to cut during cutting. For the 3DIC process chip, the logic chip is attached to the memory chip after top to bottom overturning, and the silicon substrate of the logic chip is seen from the front surface of the chip after attachment. The guard ring of the chip cannot be seen due to the thicker substrate, resulting in misalignment of the cut.

In view of this, the embodiment of the utility model provides a three-dimensional stacked structure has set up the reference layer on the structure body surface that bonding first wafer and second wafer obtained, just can follow-up chip package in-process to set up at every three-dimensional stacked unit outlying reference cell for the cutting benchmark, define out three-dimensional stacked structure's cutting street, so that aim at the cutting street and cut, thereby be favorable to improving cutting accuracy, reduce because scrap that the cutting deviation brought, improve the production yield.

Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

Fig. 1 shows a schematic structural diagram of a three-dimensional stacking structure provided by an embodiment of the present invention. As shown in fig. 1, the three-dimensional stacked structure 10 includes: a structural body 100 and a reference layer 120.

The structure body 100 includes a first wafer 101 and a second wafer 102 stacked in layers. The first wafer 101 has a plurality of memory cells, and the second wafer 102 has a plurality of logic cells. Each logic unit is matched with at least one storage unit to form a corresponding three-dimensional stacked unit. That is, the structure body 100 encapsulates a plurality of three-dimensional stacked units, which can be further separated by cutting. In specific implementation, the number of memory cells matched with the logic cells in the three-dimensional stacked cell can be determined according to the storage capacity of a single memory cell and the storage capacity requirement of the logic cell. The specific circuit structure of the logic unit may be designed according to the functional requirements of the actual application, for example, the logic unit may be used for AI and an application requiring cache, and is not limited herein.

It is understood that, from a material level, the first wafer 101 and the second wafer 102 each include a silicon substrate including a silicon dioxide layer and a silicon dielectric layer and a metal layer (top metal). The structure body 100 is formed by bonding the metal layers of the first wafer 101 and the second wafer 102 face to face. For example, the bonding may be performed using hybrid bonding (hybrid bonding) techniques.

The reference layer 120 is disposed on the surface of the structural body 100. In the implementation, the silicon substrate surface of the first wafer 101 or the silicon substrate surface of the second wafer 102 may be disposed in the structure body 100, and may be determined by a manufacturing process of the structure body 100. For example, if the fabrication process is to turn the second wafer 102 upside down and bond the second wafer with the first wafer 101, and all PADs (PADs) are on the second wafer 102 side, the silicon substrate of the second wafer 102 may be thinned first, and then the reference layer 120 may be grown on the silicon substrate surface of the second wafer 102, as shown in fig. 1. In the manufacturing process, when the first wafer 101 is turned upside down and bonded to the second wafer 102, and the PAD is on the first wafer 101 side, the silicon substrate of the first wafer 101 may be thinned, and then the reference layer 120 may be grown on the silicon substrate surface of the first wafer 101.

Specifically, the reference layer 120 includes a plurality of reference cells in one-to-one correspondence with the three-dimensional stacked cells. As shown in fig. 2, each reference unit 220 is disposed at the periphery of the corresponding three-dimensional stacking unit 110, and is used for marking the area range of the corresponding three-dimensional stacking unit 110, so as to perform cutting alignment on the three-dimensional stacking structure 10. It should be noted that fig. 2 is a schematic diagram illustrating a single three-dimensional stacked cell 110 and a peripheral reference cell 220 thereof, and as an example, the three-dimensional stacked cell 110 in fig. 2 includes a memory cell 201 and a logic cell 202, and for convenience of distinction, the reference cell 220 is represented by a square ring area filled with oblique lines.

In this embodiment, when the reference layer 120 is designed to be patterned, the shape and the position of each reference unit 220 need to be determined according to the shape and the position of the region where the corresponding three-dimensional stacked unit is located.

For example, the reference unit 220 may be a ring shape, and if the three-dimensional stacked unit is a square shape, the reference unit 220 may be a square ring, as shown in fig. 2, surrounding the periphery of the three-dimensional stacked unit. Of course, in other embodiments of the present invention, the reference unit 220 may also include a plurality of reference points or a plurality of reference line segments distributed on the periphery of the three-dimensional stacking unit, and the area range where the corresponding three-dimensional stacking unit is located may be defined, which is not limited herein.

In an alternative embodiment, each memory cell and each logic cell periphery is provided with a guard ring as a boundary of each cell. As shown in fig. 3, taking the second wafer 102 as an example, the second wafer includes a silicon substrate 301 and a metal layer, the metal layer includes a plurality of repeating units 302, and a guard ring 303 is disposed around each repeating unit, so as to identify a scribe line 304 of the second wafer 102 itself. Although the protection rings cannot be recognized because the upper and lower surfaces of the structure body are silicon substrates after the first wafer 101 and the second wafer 102 are bonded face to form the structure body, the position of the reference unit 220 may be determined with reference to the position of the protection rings in the three-dimensional stacked unit. As an embodiment, each reference unit 220 may be disposed corresponding to the guard ring having the largest size in the corresponding three-dimensional stacked unit. For example, the three-dimensional stacked cell includes a logic cell and a memory cell, and if the area of the logic cell is larger than that of the memory cell, the size of the guard ring of the logic cell is larger than that of the guard ring of the memory cell, and at this time, the corresponding reference cell 220 should be disposed corresponding to the guard ring of the logic cell, and otherwise, the corresponding reference cell should be disposed corresponding to the guard ring of the memory cell.

Taking the ring-shaped reference unit 220 as an example, a plane parallel to the first wafer 101 and the second wafer 102 is taken as a reference plane, and the reference unit 220 and the guard rings in the corresponding three-dimensional stacking units are orthographically projected onto the reference plane. Assuming that an orthographic projection of the outer edge line of the fiducial cell 220 on the reference plane is denoted as L1, and an orthographic projection of the outer edge line of the guard ring of the largest size among the corresponding three-dimensional stacked cells on the reference plane is denoted as L2, as an embodiment, L1 may coincide with L2.

Further, to simplify the manufacturing process, the ring width of the ring-shaped fiducial unit 220 may also coincide with the ring width of the guard ring, in which case each fiducial unit 220 coincides with the orthographic projection of the largest-sized guard ring in the corresponding three-dimensional stacked unit on the reference plane.

In an alternative embodiment, the reference layer 120 may be made of a metal material. The metal material is not only convenient to grow on the silicon substrate, but also has high reflectivity, which is beneficial to identifying the reference unit 220 during cutting. Further, in consideration of production cost, the metal material may be copper or aluminum, which facilitates processing and is beneficial to reducing production cost. Of course, in other embodiments of the present invention, the reference layer 120 may also be made of other suitable materials, which are not limited herein.

When the three-dimensional stacked structure 10 is cut, the reference unit 220 can be used as a cutting reference, a cutting channel of the three-dimensional stacked structure is defined from the surface of the silicon substrate on the front surface of the structure body so as to be aligned with the cutting channel for cutting, meanwhile, the reference unit 220 is used for reference, and a wafer which is cut off from the reference can be conveniently and timely found, so that the cutting precision can be improved, the scrap caused by cutting deviation can be reduced, and the production yield can be improved.

In addition, in an application scenario, the three-dimensional stacked structure 10 provided by the above embodiment may be manufactured by the following steps:

firstly, providing a first wafer with a plurality of storage units and a second wafer with a plurality of logic units;

then, bonding the first wafer and the second wafer in a face-to-face mode to form a structure body, wherein a logic unit in the structure body is matched with at least one storage unit to obtain a corresponding three-dimensional stacking unit;

and then, forming a reference layer on the surface of the structure body, wherein the reference layer comprises a plurality of reference units which correspond to the three-dimensional stacking units one by one, and each reference unit is arranged at the periphery of the corresponding three-dimensional stacking unit and used for marking the area range of the corresponding three-dimensional stacking unit so as to cut and align the three-dimensional stacking structure.

In particular, the memory cells in the first wafer 101 and the logic cells in the second wafer 102 may be fabricated according to conventional fabrication processes, such as photolithography, etching, and ion implantation. It should be noted that the memory cell and the logic cell can be processed by different processes, and are not limited herein.

After the first wafer 101 and the second wafer 102 are obtained, the first wafer 101 and the second wafer 102 may be bonded to each other in a face-to-face manner, so as to obtain the structure body 100 of the three-dimensional stacked structure 10. For example, the second wafer 102 may be flipped upside down and bonded to the first wafer 101 through a hybrid bonding (hybrid bonding) process. During bonding, the metal layers of the first wafer 101 and the second wafer 102 may be respectively planarized, then a hybrid bonding unit is grown, and then the second wafer 102 is turned upside down, so that the metal layer of the second wafer 102 is bonded to the metal layer of the first wafer 101, and after bonding, the front surface of the structure body 100 is the silicon substrate of the second wafer 102, and the back surface is the silicon substrate of the first wafer 101. On the contrary, if the first wafer 101 is turned upside down and then bonded to the metal layer of the second wafer 102, the front surface of the structure body 100 is the silicon substrate of the first wafer 101, and the back surface is the silicon substrate of the second wafer 102.

After the structural body 100 is obtained, the reference layer 120 may be formed on the surface of the structural body 100 so as to perform cutting alignment on the three-dimensional stacked unit. In a specific manufacturing process, the reference layer 120 may be formed on the front surface of the structural body 100. That is, if the structure body 100 is formed by flipping the second wafer 102 and bonding with the first wafer 101, the reference layer 120 may be formed on the surface of the silicon substrate of the second wafer 102; if the structure body 100 is formed by flipping the first wafer 101 and bonding with the second wafer 102, a reference layer 120 may be formed on the surface of the silicon substrate of the first wafer 101.

Taking the reference layer 120 formed on the silicon substrate surface of the second wafer 102 as an example, a metal layer, such as copper or aluminum, may be formed on the substrate surface of the second wafer 102 in the structure body 100, and then the metal layer may be subjected to patterning etching to form the plurality of reference cells 220.

For example, a photoresist layer may be coated on the surface of the metal layer, and then the photoresist layer is subjected to patterned exposure and development, and then the region of the metal layer exposed after development is etched to remove the excess metal, and then the photoresist layer is removed, so as to obtain the plurality of reference units 220.

Of course, in other embodiments of the present invention, other suitable processes and materials may be used to form the reference layer 120. For example, a photoresist layer may be coated on the surface of the silicon substrate of the second wafer 102, and then the photoresist layer is subjected to a patterned exposure and development process, and after the development process, the regions of the silicon substrate surface that are not covered by the photoresist layer are plated with a metal material or other suitable materials, so as to form the plurality of reference cells 220. This embodiment is not limited to this.

It should be noted that, the specific shape and position of the reference unit 220 may refer to the corresponding descriptions in the above embodiment of the three-dimensional stacked structure 10, and details are not described herein.

It is understood that, after the three-dimensional stacked structure is obtained, the cutting lines of the three-dimensional stacked structure may be determined by using the reference units 220 included in the reference layer 120 as cutting references, so that the three-dimensional stacked units are cut off and subjected to a packaging process to obtain the desired three-dimensional stacked chip.

For example, a reference unit on the surface of the three-dimensional stacked structure may be identified; then, with the reference unit as a reference, a cutting lane of the three-dimensional stacked structure is determined so as to align the cutting lane for cutting.

For example, the position of each reference cell on the surface of the three-dimensional stacked structure can be determined by detecting the intensity difference of reflected light using the difference in reflectivity of the reference cell material and the silicon substrate material. Alternatively, an image of a reference layer on the surface of the three-dimensional stacked structure may be captured, and the position of each reference unit on the surface of the three-dimensional stacked structure may be determined by image recognition.

After the positions of the reference units are identified, the reference units are used as cutting references, and the areas between the adjacent reference units are determined as cutting paths to be cut. The implementation details of the specific cutting process can refer to the related art, and are not limited herein.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A three-dimensional stacked structure, comprising:

the structure body comprises a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded in a face-to-face mode, a plurality of storage units are arranged in the first wafer, a plurality of logic units are arranged in the second wafer, and each logic unit is matched with at least one storage unit to form a corresponding three-dimensional stacking unit;

the datum layer is arranged on the surface of the structure body and comprises a plurality of datum units which are in one-to-one correspondence with the three-dimensional stacking units, and each datum unit is arranged on the periphery of the corresponding three-dimensional stacking unit and used for marking the area range where the corresponding three-dimensional stacking unit is located so as to cut and align the three-dimensional stacking structure.

2. The three-dimensional stack structure of claim 1, wherein the reference layer is disposed on a substrate surface of the second wafer.

3. The three-dimensional stack structure of claim 1, wherein the reference layer is disposed on a substrate surface of the first wafer.

4. The three-dimensional stacked structure according to claim 1, wherein the reference unit is ring-shaped.

5. The three-dimensional stacked structure according to claim 1, wherein the reference cell comprises a plurality of reference points or a plurality of reference line segments distributed on the periphery of the corresponding three-dimensional stacked cell.

6. The three-dimensional stacked structure according to claim 1, wherein each memory cell and each logic cell periphery is provided with a guard ring, and each reference cell is provided corresponding to the guard ring with the largest size in the corresponding three-dimensional stacked cell.

7. The three-dimensional stacked structure of claim 6, wherein an outer edge line of each fiducial unit coincides with an orthographic projection of an outer edge line of a largest-sized guard ring in a corresponding three-dimensional stacked unit on a reference plane, wherein the reference plane is a plane parallel to the first wafer and the second wafer.

8. The three-dimensional stacked structure of claim 6, wherein each fiducial unit coincides with an orthographic projection of a largest-sized guard ring in the corresponding three-dimensional stacked unit on a reference plane, wherein the reference plane is a plane parallel to the first and second wafers.

9. The three-dimensional stacked structure according to claim 1, wherein the reference layer is made of a metal material.

10. The three-dimensional stacked structure according to claim 9, wherein the metal material is copper or aluminum.

Images