WO2023060865A1 - Procédé et dispositif de codage, et procédé et dispositif de décodage - Google Patents

Procédé et dispositif de codage, et procédé et dispositif de décodage Download PDF

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WO2023060865A1
WO2023060865A1 PCT/CN2022/087391 CN2022087391W WO2023060865A1 WO 2023060865 A1 WO2023060865 A1 WO 2023060865A1 CN 2022087391 W CN2022087391 W CN 2022087391W WO 2023060865 A1 WO2023060865 A1 WO 2023060865A1
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code
code block
overhead
matrix
gel
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PCT/CN2022/087391
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Chinese (zh)
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格里岑弗拉基米尔•维塔利耶维奇
李启庆
弗拉迪斯拉夫奥博连采夫·尼古拉耶维奇
马耶夫斯基阿列克谢•爱德华多维奇
于鸿晨
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华为技术有限公司
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Publication of WO2023060865A1 publication Critical patent/WO2023060865A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of optical communication, and more specifically, to a codec method and a codec device.
  • forward error correction code forward error correction
  • spatially coupled error correction codes spatially coupled error correction code, SC ECC
  • SC ECC spatially coupled error correction code
  • the embodiment of the present application provides a codec method and codec device, which can reduce the error floor and enhance the spatially coupled forward error correction code, so as to realize the spatially coupled code in the low-delay, high-throughput, high-speed communication transmission scenario in the application.
  • an encoding method including: encoding an original data stream to generate a forward error correction (FEC) code block, where the FEC code block includes a plurality of data code blocks, a first overhead code block, and a second overhead code block, wherein the FEC code block includes N rows, the first overhead code block is located in each of the N rows of the FEC code block, the second overhead code block is located in M rows of the FEC code block, and M is less than or equal to N, M and N is an integer greater than zero; send the FEC code block.
  • FEC forward error correction
  • a decoding method including: receiving a forward error correction FEC code block; decoding the FEC code block to restore the original data stream, the FEC code block includes a plurality of data code blocks, a first overhead code block and a second overhead code block, wherein the FEC code block includes N rows, the first overhead code block is located in each of the N rows of the FEC code block, and the second overhead code block is located in M rows of the FEC code block, and M is less than or equal to N, M and N are integers greater than zero.
  • the currently transmitted FEC code block is based on the structure of the existing spatially coupled code, coupled with a generalized error location code (generalized error location codes, GEL) code to generate additional redundancy, as Each row generates the original redundancy of the existing spatially coupled code.
  • GEL generalized error location codes
  • the currently transmitted FEC code block is based on the structure of the spatially coupled code, and coupled with the GEL code to generate original redundancy and additional redundancy.
  • the original redundancy can be generated by the inner code B 1 of the GEL code according to the complete GEL codec method; or, the original redundancy can be generated by the component code B of the original space-coupled code according to the partial GEL codec method, which exists in Each row of the FEC code block, and each row of the FEC code block is half of the codeword B.
  • Additional redundancy is generated by the outer code A2 of the GEL, present in some rows of the FEC code block.
  • the FEC code block includes s matrices of n rows and h columns arranged in h rows and h columns of matrices.
  • the FEC code block contains k 2 ⁇ h+K ⁇ m 2 payload bits (ie, bits of the original data stream), m 1 ⁇ h bits of original overhead and (hK) ⁇ m 2 bits of overhead.
  • s, h, n, m 1 , k 2 , K, and m 2 are all positive integers.
  • the second overhead code block may occupy some bits in any one data code block of the multiple data code blocks.
  • the second overhead code block is a matrix located in rows 14-15 and columns 7-14 of the seventh code block, which is not specifically limited in the present application.
  • the first overhead code block of the space-coupled code in this implementation is generated by the GEL inner code B 1 (that is, according to the complete GEL encoding and decoding method), or the first overhead code block is generated by the original space
  • the component code B of the coupled code is generated (that is, according to a partial GEL encoding and decoding mode); the second overhead code block is generated by re-encoding the encoding result of the inner code with the outer code of the GEL.
  • additional redundancy eg, a second overhead code block
  • additional redundancy provides increased error correction capability, which is beneficial for reducing the error floor and providing faster convergence.
  • overhead symbol can be replaced in non-specific cases
  • overhead code block can include “overhead symbol” and “redundant symbol” , “check symbol”, etc.
  • code block and “matrix” can be replaced by each other in non-specific cases, or in other words, a code block is composed of a matrix.
  • one symbol may correspond to multiple bits
  • one code block may include multiple symbols
  • a code block includes multiple bits or multiple symbols, which is not specifically limited in this application.
  • the original data stream may include multiple bits, symbols, etc., which are not specifically limited in this application.
  • a suitable new space-coupled code is designed to allow low-complexity decoding
  • any code word in the general error position GEL code, the general concatenated code GCC, the tensor product and the general integrated interleaving GII code is selected as the component of the spatially coupled code codes to generate a first overhead code block and a second overhead code block.
  • the check matrix H B of the C GEL is used to check the column code of the GEL code
  • the second overhead code block is generated by encoding the row codes of the first parity check matrix, and the first parity check matrix is determined according to the product of the sub-matrix of the H B and the sub-matrix of the GEL code.
  • GEL codes are a class of block codes with good properties.
  • the H B matrix used to generate column code check symbols in GEL codes is a check matrix of 2 ⁇ n ⁇ 2 ⁇ n, the check matrix H 1 of B 1 in rows k+1 to 2 ⁇ n, and the check matrix H 1 of k 2 + Lines 1 to k are H 2 , and H 1 and H 2 constitute the parity check matrix of B 2 .
  • the first to k 2 rows of H 3 include a k 2 ⁇ k 2 identity matrix and a 2 ⁇ nk 2 zero matrix.
  • the m 2 ⁇ (hK) matrix determined by the k 2 +1 to k th columns to k th columns is 0 before encoding, and is used to store the second overhead after encoding.
  • the matrix determined in rows k+1 to 2 ⁇ n is all 0s before encoding, and is used to store the first overhead after encoding.
  • h, n, m 1 , k 2 , K, k, and m 2 are all positive integers.
  • the component code GEL there are two encoding methods of the component code GEL.
  • the first one is to use the complete GEL code C GEL encoding method for encoding, using the code from the historical code block and k 2 ⁇ h+K ⁇ m 2 payload bits to generate all m 1 ⁇ h+(hK) ⁇ m 2 check bits (ie, original overhead + additional overhead).
  • the transposition of the selected corresponding sub-matrix from the transmitted s different FEC code blocks constitutes That is, the historical code block.
  • the second is to use GEL codes.
  • the encoding process of the GEL part generates overhead, using blocks from historical code blocks bits, k 2 ⁇ h+K ⁇ m 2 payload bits, and m 2 ⁇ (hK) overhead, the original space-coupled code component code encoding method is used to generate m 1 ⁇ h-bit original overhead.
  • the 1st to k 2 keep the original values, and the k 2 + 1 to kth rows get the first parity check matrix of the column code, and then the first parity check matrix of the column code is performed Encoding, putting the generated parity check matrix into the m 2 ⁇ (hK) matrix determined by the k 2 +1 to kth rows and k to h columns of the GEL code matrix, as the second overhead generation method.
  • the inner code B 1 (that is, the component code B of the original space-coupled code) is encoded for each column of the 1st to k rows, and the resulting check bits are put into the k+1 to 2 ⁇ n rows as the first overhead .
  • h represents the number of codeword symbols after encoding
  • K represents the number of payload symbols before encoding
  • D represents the minimum Hamming distance after encoding.
  • the component code A i of the spatially coupled code is a GEL code
  • the component code A i includes a historical code block C i , a plurality of data code blocks, a first overhead code block and the second overhead code block.
  • the historical code block C i may refer to a code block before the current FEC code block to be transmitted. Among them, the historical code block C i can be understood as transmitted in sequence.
  • one of the cores of the encoding method of the space-coupled code is to construct the code block to be encoded of the component code A i at the current moment, where i is an integer greater than or equal to 0.
  • the component code is a GEL code; wherein, C GEL is composed of 4 inner codes and The matrix of 2 ⁇ n rows and h columns of 3 outer codes, the code length of the inner code and the code length of the outer code are 2 ⁇ n and h respectively, and the inner code B 0 of C GEL is the identity code word [2 ⁇ n, 2 ⁇ n,1] 2 , B 1 is the codeword [2 ⁇ n,k,d] 2 , B 2 is the codeword [2 ⁇ n,k 2 ,d 2 ] 2 , B 3 is the all-zero codeword,
  • the outer code A 1 of C GEL is the Galois Field
  • 2 ⁇ n is the number of bits contained in the encoded codewords of B 0 , B 1 , and B 3
  • 2 ⁇ n, k, and k 2 are respectively contained in the codewords of B 0 , B 1 , and B 3
  • the number of bits, 1, d and d 2 are the minimum Hamming distances of the encoded codewords of B 0 , B 1 and B 3 respectively.
  • h is the number of symbols contained in the encoded codewords of A2 and A3
  • K and h are the number of symbols contained in the codewords before and after A2 and A3 encoding respectively.
  • m 1 , m 2 , m 3 represent the number of bits contained in the symbols in A 1 , A 2 and A 3 codewords respectively (or, they can also represent the extended field GF(2 m1 ) of GF(2), GF (2 m2 ), the dimensions of the elements in GF(2 m3 ) under the vector representation).
  • the historical code block includes n ⁇ h bits
  • the multiple data code blocks include k 2 h+K m 2 bits of the original data stream (that is, payload bits )
  • the first overhead code block includes m 1 ⁇ h bits of original overhead
  • the second overhead code block includes (hK) ⁇ m 2 bits of additional overhead.
  • V i is a binary matrix with h rows and n columns
  • V i is an all-zero matrix with h rows and n columns;
  • the component code in the space coupling code is a GEL code
  • the GEL code is The code word of each column in the GEL code is the component code B[2 n, k, d] 2 of the original space coupling code (for example, OFEC code block);
  • V T is the transpose of matrix V
  • N 0 is a non-negative integer determined according to the coupling mode of space-coupled codes
  • the continuously sent FEC code blocks constitute a semi-infinite sequence
  • one FEC code block includes N rows and K columns
  • the corresponding semi-infinite sequence includes N rows and infinitely many columns.
  • the semi-infinite sequence V is the bit sum of the first overhead code block generated based on the bits of the historical code block and the bits of the original data stream according to the encoding method of the GEL code Bits of the second overhead code block.
  • the semi-infinite sequence V is based on historical code blocks bits and k 2 ⁇ h+K ⁇ m 2 payload bits to generate all m 1 ⁇ h+(hK) ⁇ m 2 original overhead and additional overhead.
  • the semi-infinite sequence V is the bits of the second overhead code block generated based on the bits of the historical code block and the bits of the original data stream according to the encoding method of the GEL code, and the bits of the first overhead code block generated based on the bits of the second overhead code block.
  • the semi-infinite sequence V is based on historical code blocks bits, k 2 ⁇ h+K ⁇ m 2 payload bits and m 2 ⁇ (hK) overhead to generate m 1 ⁇ h bits of original overhead.
  • the FEC code block V i is a sub-matrix for the component code A i A' i transpose (A' i ) rearrangement of T , wherein, the component code A i is a matrix of 256 rows and 16 columns, and the sub-matrix A' i is the rear 128 row and 16 column matrix of A i , and the component code A i includes Historical code block C i , a plurality of data code blocks and the first overhead code block, V i includes 8 sub-matrices V i,t (r,c) of 16 rows and 16 columns arranged in a row-wise matrix of 16 rows and 128 columns , i is the row number of the FEC code block, t is the column number of the FEC code block, r and c are the row number and column number of the sub-matr
  • the code word C of the GEL code and the GEL inner code B 0 are Identity code word [256,256,1] 2
  • B 1 is extended BCH code word [256,239,6] 2
  • B 2 is extended BCH code word [256,231,8] 2
  • the code word C of GEL code A 1 of GEL outer code is the all-zero code word on GF(2 17 )
  • a 2 is the cyclic RS code on GF(2 8 )
  • a 3 is the identity codeword on GF(2 231 )
  • the sub-matrix A' i transpose (A' i ) T of the component code A i is a plurality of data code blocks, the first overhead code block and the second overhead code
  • the transposition of the block, (A′ i ) T includes 8 sub-matrices of 16 rows and 16 columns (A' i,t (r,c)) T is a matrix of 16 rows and 128 columns arranged in the row direction, where r and c is the row number and column number of sub-matrix (A' i,t (r,c)) T respectively, t is an integer greater than or equal to 0 and less than or equal to 7, i is an integer greater than or equal to 0, r and c is an integer greater than or equal to 0 and less than or equal to 15.
  • the second overhead code block is located at (A′ i,6 (r,c)) T , where r is an integer greater than or equal to 14 and less than or equal to 15 , c is an integer greater than or equal to 7 and less than or equal to 14, the first overhead code block is located at (A′ i,6 (r,c 1 )) T and (A′ i,7 (r,c 2 )) T , r is an integer greater than or equal to 0 and less than or equal to 15, c 1 is 15, and c 2 is an integer greater than or equal to 0 and less than or equal to 15.
  • the historical code block C i includes eight 16-row and 16-column sub-matrices C i, t arranged in a column-wise 128-row and 16-column matrix, when the FEC code block When i in V i is an even number, select the j-th 16-row 16-column matrix V i-19+2*j, j of the historical FEC code block with the serial number i-19+2*j, and then transpose and rearrange Transpose to obtain C i, j in the historical code block; when i in the FEC code block V i is an odd number, select the jth 16th row 16 of the historical FEC code block with the sequence number i-21+2*j The column matrix V i-21+2*j,j is transposed and rearranged and then transposed to obtain C i,j in the historical code block.
  • the historical code block C i includes eight 16-row and 16-column sub-matrices C i, t arranged in a column-wise 16-row and 128-column matrix, and the FEC code block V i select the j-th 16-row 16-column matrix V i-27+j, j of the historical FEC code block with the serial number i-27+j to transpose and rearrange and then transpose to obtain C i in the historical code block ,j .
  • the data code block is the same as the second overhead code block
  • the code block constitutes a code block with 16 rows and 111 columns (among them, columns 103-110 (serial numbers start from 0) of rows 14-15 (serial numbers start from 0) are the second overhead code blocks, and the rest are original data ),
  • the first overhead code block is an encoding information matrix with 16 rows and 17 columns.
  • the first overhead code block is at the same position as the OFEC overhead code block, and the second overhead code block is at a part of the OFEC original data code block.
  • the rearrangement rule definition of ⁇ as follows:
  • ⁇ i, j represent the elements of row i and column j in a matrix W with 16 rows and 16 columns, and i and j are integers greater than or equal to 0 and less than or equal to 15, respectively.
  • the FEC code block V is composed of Eight rearranged sub-matrixes B t are determined, i represents the serial number of the FEC code block, V i,t represents the t-th sub-matrix B t with 16 rows and 16 columns, and t is greater than or equal to 0 and less than or equal to 7 integer.
  • the GEL code is 256 A matrix block with 16 rows and 16 columns, wherein, the matrix block of the 0-127 row is determined from the historical FEC code block, the matrix block of the 128-230 row is a data code block, and the first 14 columns of the matrix block of the 231-238 row are For the data code block, the second overhead code block occupies the last two columns of the matrix block in rows 231-238 of the GEL code, and the first overhead code block is located in rows 239-255.
  • an encoding device including: a processing unit, configured to encode an original data stream to generate a forward error correction (FEC) code block, the FEC code block includes a plurality of data code blocks, a first overhead code block and a second overhead code block, wherein the FEC code block includes N rows, the first overhead code block is located in each of the N rows of the FEC code block, and the second overhead code block is located in M rows of the FEC code block, and M is less than or equal to N, M and N are integers greater than zero; the transceiver unit is used to send the FEC code block.
  • FEC forward error correction
  • a decoding device including: a transceiver unit, used for forward error correction FEC code blocks; a processing unit, used for decoding the FEC code blocks to restore the original data stream, and the FEC code blocks include multiple A data code block, a first overhead code block and a second overhead code block, wherein the FEC code block includes N rows, the first overhead code block is located in each of the N rows of the FEC code block, and the second overhead code block is located in the FEC code block M rows of blocks, where M is less than or equal to N, where M and N are integers greater than zero.
  • the currently transmitted FEC code block is based on the structure of the existing spatially coupled code, coupled with the general error position GEL code to generate additional redundancy, and generate the existing spatially coupled code for each row The original redundancy of the code.
  • the currently transmitted FEC code block is based on the structure of the spatially coupled code, and coupled with the GEL code to generate original redundancy and additional redundancy.
  • the original redundancy can be generated by the inner code B 1 of the GEL code according to the complete GEL codec method; or, the original redundancy can be generated by the component code B of the original space-coupled code according to the partial GEL codec method, which exists in Each row of the FEC code block, and each row of the FEC code block is half of the codeword B.
  • Additional redundancy is generated by the outer code A2 of the GEL, present in some rows of the FEC code block.
  • the FEC code block includes s matrices of n rows and h columns arranged in h rows and h columns of matrices.
  • the FEC code block contains k 2 ⁇ h+K ⁇ m 2 payload bits (ie, bits of the original data stream), m 1 ⁇ h bits of original overhead and (hK) ⁇ m 2 bits of overhead.
  • the second overhead code block may occupy some bits in any one data code block of the multiple data code blocks.
  • the second overhead code block is a matrix located in rows 14-15 and columns 7-14 of the seventh code block, etc., which is not specifically limited in the present application.
  • the first overhead code block of the space-coupled code in this implementation is generated by the GEL inner code B 1 (that is, according to the complete GEL encoding and decoding method), or the first overhead code block is generated by the original space
  • the component code B of the coupled code is generated (that is, according to a partial GEL encoding and decoding mode); the second overhead code block is generated by re-encoding the encoding result of the inner code with the outer code of the GEL.
  • the additional redundancy in this implementation (eg, a second overhead code block) provides improved error correction capability, which is beneficial for reducing the error floor and providing faster convergence.
  • overhead symbol can be replaced in non-specific cases
  • overhead code block can include “overhead symbol”, “redundant symbol”, “Check symbol”, etc.
  • code block and “matrix” can be replaced by each other in non-specific cases, or in other words, a code block is composed of a matrix.
  • one symbol may correspond to multiple bits
  • one code block may include multiple symbols
  • a code block includes multiple bits or multiple symbols, which is not specifically limited in this application.
  • the original data stream may include multiple bits, symbols, etc., which are not specifically limited in this application.
  • the processing unit is also used to: select any codeword in the general error location GEL code, the general concatenated code GCC, the tensor product and the general integrated interleaving GII code A component code serving as a spatially coupled code to generate a first overhead code block and a second overhead code block.
  • the processing unit is further configured to: when the second overhead code block is generated according to the code word C GEL of the GEL code, use the parity check matrix H B of C GEL to pair GEL The column code of the code is checked, and the second overhead code block is generated by encoding the row code of the first parity check matrix.
  • the first parity check matrix is determined according to the product of the sub-matrix of H B and the sub-matrix of the GEL code .
  • GEL codes are a class of block codes with good properties.
  • the H B matrix used to generate column code check symbols in GEL codes is a check matrix of 2 ⁇ n ⁇ 2 ⁇ n, the check matrix H 1 of B 1 in rows k+1 to 2 ⁇ n, and the check matrix H 1 of k 2 + Rows 1 to k are H 2 , and H 1 and H 2 constitute the parity check matrix of B 2 .
  • the first to k 2 rows of H 3 include a k 2 ⁇ k 2 identity matrix and a 2 ⁇ nk 2 zero matrix.
  • the m 2 ⁇ (hK) matrix determined by the k 2 +1 to k th columns to k th columns is 0 before encoding, and is used to store the second overhead after encoding.
  • the matrix determined in rows k+1 to 2 ⁇ n is all 0s before encoding, and is used to store the first overhead after encoding.
  • the first is to use the complete GEL code C GEL encoding method to encode, using the historical code block bits and k 2 h+K m 2 payload bits to generate all m 1 h+(hK) m 2 parity bits (that is, original overhead m 1 h+extra overhead m 2 ⁇ (hK) ).
  • the second is to use GEL codes.
  • the encoding process of the GEL part generates overhead, using blocks from historical code blocks bits, k 2 ⁇ h+K ⁇ m 2 payload bits, and m 2 ⁇ (hK) overhead, the original space-coupled code component code encoding method is used to generate m 1 ⁇ h-bit original overhead.
  • the 1st to k 2 keep the original values, and the k 2 + 1 to kth rows get the first parity check matrix of the column code, and then the first parity check matrix of the column code is performed Encoding, putting the generated parity check matrix into the m 2 ⁇ (hK) matrix determined by the k 2 +1 to kth rows and k to h columns of the GEL code matrix, as the second overhead generation method.
  • the inner code B 1 (that is, the component code B of the original space-coupled code) is encoded for each column of the 1st to k rows, and the resulting check bits are put into the k+1 to 2 ⁇ n rows as the first overhead .
  • the component code A i of the space-coupled code is a GEL code
  • the component code A i includes a historical code block C i , a plurality of data code blocks, a first overhead code block and the second overhead code block.
  • the historical code block C i may refer to a code block before the current FEC code block to be transmitted.
  • one of the cores of the encoding method of the space-coupled code is to construct the code block to be encoded of the component code A i at the current moment, where i is an integer greater than or equal to 0.
  • the component code is a GEL code; wherein, C GEL includes 4 inner codes and The matrix of 2 ⁇ n rows and h columns of 3 outer codes, the code length of the inner code and the code length of the outer code are 2 ⁇ n and h respectively, and the inner code B 0 of C GEL is the identity code word [2 ⁇ n, 2 ⁇ n,1] 2 , B 1 is the codeword [2 ⁇ n,k,d] 2 , B 2 is the codeword [2 ⁇ n,k 2 ,d 2 ] 2 , B 3 is the all-zero codeword,
  • the outer code A 1 of C GEL is the Galois Field
  • the historical code block includes n ⁇ h bits
  • the multiple data code blocks include k 2 h+K m 2 bits (that is, payload bits )
  • the first overhead code block includes m 1 ⁇ h bits of original overhead
  • the second overhead code block includes (hK) ⁇ m 2 bits of additional overhead.
  • V i is a binary matrix with h rows and n columns
  • V i is an all-zero matrix with h rows and n columns;
  • the component code in the space coupling code is a GEL code
  • the GEL code is The codeword of each column in the GEL code is the component code B[2 ⁇ n,k,d] 2 of the original space-coupled code (eg, OFEC code block).
  • V T is the transpose of matrix V
  • N 0 is a non-negative integer determined according to the coupling mode of space-coupled codes
  • the continuously sent FEC code blocks constitute a semi-infinite sequence
  • one FEC code block includes N rows and K columns
  • the corresponding semi-infinite sequence includes N rows and infinitely many columns.
  • the semi-infinite sequence V is the bit sum of the first overhead code block generated based on the bits of the historical code block and the bits of the original data stream according to the encoding method of the GEL code Bits of the second overhead code block.
  • the semi-infinite sequence V is based on historical code blocks bits and k 2 ⁇ h+K ⁇ m 2 payload bits to generate all m 1 ⁇ h+(hK) ⁇ m 2 original overhead and additional overhead.
  • the semi-infinite sequence V is the bits of the second overhead code block generated based on the bits of the historical code block and the bits of the original data stream according to the encoding method of the GEL code, and the bits of the first overhead code block generated based on the bits of the second overhead code block.
  • the semi-infinite sequence V is based on historical code blocks bits, k 2 ⁇ h+K ⁇ m 2 payload bits and m 2 ⁇ (hK) overhead to generate m 1 ⁇ h bits of original overhead.
  • the FEC code block V i is a sub-matrix for the component code A i A' i transpose (A' i ) rearrangement of T , wherein, the component code A i is a matrix of 256 rows and 16 columns, and the sub-matrix A' i is the rear 128 row and 16 column matrix of A i , and the component code A i includes Historical code block C i , a plurality of data code blocks and the first overhead code block, V i includes 8 sub-matrices V i,t (r,c) of 16 rows and 16 columns arranged in a row-wise matrix of 16 rows and 128 columns , i is the row number of the FEC code block, t is the column number of the FEC code block, r and c are the row number and column number of the sub-matr
  • the code word C of the GEL code GEL inner code B 0 is Identity code word [256,256,1] 2
  • B 1 is extended BCH code word [256,239,6] 2
  • B 2 is extended BCH code word [256,231,8] 2
  • the code word C of GEL code A 1 of GEL outer code is the all-zero code word on GF(2 17 )
  • a 2 is the cyclic RS code on GF(2 8 )
  • a 3 is the identity codeword on GF(2 231 )
  • the sub-matrix A' i transpose (A' i ) T of the component code A i is a plurality of data code blocks, the first overhead code block and the second overhead code
  • the transposition of the block, (A′ i ) T includes 8 sub-matrices of 16 rows and 16 columns (A' i,t (r,c)) T is a matrix of 16 rows and 128 columns arranged in the row direction, where r and c is the row number and column number of sub-matrix (A' i,t (r,c)) T respectively, t is an integer greater than or equal to 0 and less than or equal to 7, i is an integer greater than or equal to 0, r and c is an integer greater than or equal to 0 and less than or equal to 15.
  • the second overhead code block is located at (A′ i,6 (r,c)) T , where r is an integer greater than or equal to 14 and less than or equal to 15 , c is an integer greater than or equal to 7 and less than or equal to 14, the first overhead code block is located at (A′ i,6 (r,c 1 )) T and (A′ i,7 (r,c 2 )) T , r is an integer greater than or equal to 0 and less than or equal to 15, c 1 is 15, and c 2 is an integer greater than or equal to 0 and less than or equal to 15.
  • the historical code block C i includes eight 16-row and 16-column sub-matrices C i, t arranged in a column-wise 128-row and 16-column matrix, when the FEC code block When i in V i is an even number, select the j-th 16-row 16-column matrix V i-19+2*j, j of the historical FEC code block with the serial number i-19+2*j, and then transpose and rearrange Transpose to obtain C i, j in the historical code block; when i in the FEC code block V i is an odd number, select the jth 16th row 16 of the historical FEC code block with the sequence number i-21+2*j The column matrix V i-21+2*j,j is transposed and rearranged and then transposed to obtain C i,j in the historical code block.
  • the historical code block C i includes eight 16-row and 16-column sub-matrices C i, t arranged in a column-wise 16-row and 128-column matrix, and the FEC code block V i select the j-th 16-row 16-column matrix V i-27+j, j of the historical FEC code block with the serial number i-27+j to transpose and rearrange and then transpose to obtain C i in the historical code block ,j .
  • the data code block and the second overhead code determines a code block with 16 rows and 111 columns (wherein, the 103-110 columns (serial numbers start from 0) of the 14th-15th rows (serial numbers start from 0) are the second overhead code blocks, and the rest are original data),
  • the first overhead code block is an encoding information matrix with 16 rows and 17 columns. After rearranging the bits (or symbols) in the original data, the first overhead and the second overhead code block, the coded FEC code block can be obtained.
  • the first overhead code block is at the same position as the OFEC overhead code block, and the second overhead code block is at a part of the OFEC original data code block.
  • the rearrangement rule of ⁇ is defined as follows:
  • ⁇ i, j represent the elements of row i and column j in a matrix W with 16 rows and 16 columns, and i and j are integers greater than or equal to 0 and less than or equal to 15, respectively.
  • the FEC code block V i is composed of Eight rearranged sub-matrixes B t are determined, i represents the serial number of the FEC code block, V i,t represents the t-th sub-matrix B t with 16 rows and 16 columns, and t is greater than or equal to 0 and less than or equal to 7 integer.
  • the GEL code is 256 A matrix block with 16 rows and 16 columns, wherein, the matrix block of the 0-127 row is determined from the historical FEC codeword, the matrix block of the 128-230 row is a data code block, and the first 14 columns of the matrix block of the 231-238 row are For the data code block, the second overhead code block occupies the last two columns of the matrix block in rows 231-238 of the GEL code, and the first overhead code block is located in rows 239-255.
  • a coding device including a processor, and optionally, a memory, the processor is used to control the transceiver to send and receive signals, the memory is used to store a computer program, and the processor is used to call from the memory And run the computer program, so that the encoding device executes the method in the above first aspect or any possible implementation manner of the first aspect.
  • processors there are one or more processors, and one or more memories.
  • the memory can be integrated with the processor, or the memory can be set separately from the processor.
  • the encoding device further includes a transceiver, which may specifically be a transmitter (transmitter) and a receiver (receiver).
  • a transceiver which may specifically be a transmitter (transmitter) and a receiver (receiver).
  • a decoding device including a processor, and optionally, a memory
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store a computer program
  • the processor is used to call from the memory And run the computer program, so that the coding device executes the method in the above second aspect or any possible implementation manner of the second aspect.
  • processors there are one or more processors, and one or more memories.
  • the memory can be integrated with the processor, or the memory can be set separately from the processor.
  • the decoding device further includes a transceiver, which may specifically be a transmitter (transmitter) and a receiver (receiver).
  • a transceiver which may specifically be a transmitter (transmitter) and a receiver (receiver).
  • a codec device including: various modules or units for implementing the method in the first aspect or any possible implementation manner of the first aspect; or, for implementing the second aspect or the second Each module or unit of the method in any possible implementation of the aspect.
  • an optical communication system including: a codec device, configured to execute the method in the above first aspect or any possible implementation manner of the first aspect, or to execute the above second aspect or the method in the first aspect The method in any one of the possible implementations of the two aspects.
  • a computer-readable storage medium stores computer programs or codes, and when the computer programs or codes run on a computer, the computer executes the above-mentioned first aspect or the first aspect The method in any possible implementation manner, or causing the computer to execute the above second aspect or the method in any possible implementation manner of the second aspect.
  • a chip including at least one processor, the at least one processor is coupled to a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the installed
  • the encoding device of the chip system executes the method in the above-mentioned first aspect or any possible implementation of the first aspect, or makes the decoding device installed with the chip system execute the above-mentioned second aspect or any of the possible implementations of the second aspect method in .
  • the chip may include an input circuit or interface for sending information or data, and an output circuit or interface for receiving information or data.
  • a computer program product in an eleventh aspect, includes computer program code, and when the computer program code is run by a coding device, the coding device is made to perform any one of the above-mentioned first aspect or the first aspect.
  • a codec method is provided, by using one of the coding methods such as general error location GEL, general concatenated GCC, tensor product (tensor product) and general integrated interleaving code word GII as Component codes of space-coupled codes, resulting in overhead.
  • the first overhead equal to the overhead size of the current spatially coupled code
  • the second overhead and the characteristics of the GEL code
  • decoding is performed using the current spatially coupled code.
  • the delay is reduced, the slope of the performance curve is improved, and the bit error floor is significantly reduced; the output bit error rate (bit error rate) is reduced by negligible power and complexity costs, and a reasonable overhead (overhead).
  • BER bit error floor is reduced to 1e-15 level.
  • FIG. 1 is a schematic diagram of an example of spatial coupling where the component codes applicable to the present application are BCH codes.
  • FIG. 2 is a schematic diagram of an example of a spatially coupled code to which the block code of the present application is applied.
  • FIG. 3 is a schematic diagram of an example of a decoding process of sliding window decoding to which the spatially coupled code of the present application is applied.
  • FIG. 4 is a schematic diagram of an example of a general error location GEL code applicable to this application.
  • FIG. 5 is a schematic diagram of an example of the encoding process of the GEL code to which this application is applied.
  • FIG. 6 is a schematic diagram of an example of a decoding process of a GEL code to which the present application is applied.
  • FIG. 7 is a schematic diagram showing an example of using GEL codes as component codes in a space coupling structure to which the present application is applied.
  • FIG. 8 is a schematic diagram of an example of using GEL codes as component codes in a spatially coupled staircase applicable to the present application.
  • Fig. 9 is a schematic diagram of an example of the error floor of the staircase and staircase-GEL codes applicable to the present application.
  • FIG. 10 is a schematic diagram of an example of a spatial coupling FEC encoding method applicable to the present application.
  • FIG. 11 is a schematic diagram of an example of a decoding method for spatial coupling forward error correction applicable to the present application.
  • Fig. 12 is a schematic diagram of an example of a coupling frame structure of the space coupling code open FEC and the GEL code applicable to the present application.
  • FIG. 13 is a schematic diagram of an example of an FEC applicable to an optical transmission scenario of the present application.
  • Fig. 14 is a schematic diagram of another example of the FEC applicable to the optical transmission scenario of the present application.
  • Fig. 15 is a schematic diagram of an example of a spatial coupling forward error correction coding device applicable to the present application.
  • Fig. 16 is a schematic diagram of an example of a spatial coupling forward error correction decoding device applicable to the present application.
  • Fig. 17 is a schematic diagram of an example of a spatial coupling forward error correction coding device applicable to the present application.
  • Fig. 18 is a schematic diagram of an example of a spatial coupling forward error correction decoding device applicable to the present application.
  • FEC forward error correction
  • Spatial coupling codes include braided block codes (braided block codes, BBC), continuous interleaved BCH (continuously-interleaved bose-chaudhuri-hocquenghem, CI-BCH) codes, staircase codes (staircase), open forward error correction codes (open forward error correction, OFEC) and zipper codes, these error-correcting codes take advantage of low decoding complexity to achieve high performance.
  • spatially coupled error correction code spatially coupled error correction code, SC ECC
  • SC ECC spatially coupled error correction code
  • FIG. 1 is a schematic diagram of an example of a spatially coupled code in which the component code applicable to the present application is a BCH code.
  • the 128-bit Info_Pad represents the historical code block, and some bits in the previously transmitted codeword (through a certain mapping relationship ), 111 bits are the original data bits to be transmitted currently.
  • Different space coupling codes can be simply understood as different rules for selecting the Info_Pad of the component codes.
  • the component code of the original open FEC is a (256, 239) single parity bit extended BCH code.
  • the transmitted i-th FEC code block W i includes eight matrices of 16 rows and 16 columns, i represents the serial number of the FEC code block, and W i,t can be used to represent the t-th code block in W i (0 ⁇ t ⁇ 7 integer).
  • a 16-row 111-column data code block D i is obtained from the current information to be transmitted, and a 16-row 239-column code block to be encoded is obtained by splicing the historical code block C i code block and the data code block D i back and forth, and then for each Extended BCH (256, 239) encoding for one line, and finally a code block A i with 16 rows and 256 columns can be obtained, which is equivalent to 16 sub-matrices with 16 rows and 16 columns arranged in rows, and A i,p represents the pth in A i A code block with 16 rows and 16 columns (0 ⁇ p ⁇ 15).
  • the first 16 rows and 128 columns of A i come from the historical code block C i and will not be transmitted.
  • A' i is divided into eight 16-row and 16-column matrices A' i,t , where A' i,t represents the t-th 16-row and 16-column code block in A' i (0 ⁇ t ⁇ 7). After rearranging each sub-matrix A' i in A' i , W i can be obtained.
  • the rearrangement rules can be arbitrary, and W is ⁇ (W) after rearrangement.
  • ⁇ (W) i,j represents the element corresponding to the i-th (0 ⁇ i ⁇ 15) row and j-th column (0 ⁇ j ⁇ 15) column of the matrix.
  • the rearrangement rules in open FEC can be expressed by the following formula:
  • This implementation can utilize the interleaving relationship between codewords to improve error correction capabilities, that is, to improve bit error performance.
  • the number of trap sets is higher and the error floor is higher.
  • FIG. 2 is a schematic diagram of an example of a space-coupled code to which this application is applied. That is, a spatially coupled code is constructed from the historical code block and the newly input data code block. As shown in Figure 2, each code block consists of information symbols (data) and parity symbols (overhead).
  • any space-coupled code can be simply constructed by the following process: data is divided into blocks; where each block is composed of information symbols and check symbols; current information symbols are put into new code blocks; new code blocks The verification part of is obtained by selecting some symbols in the historical coding block, combining with the current information symbols, and performing component code coding (GEL in this application).
  • the core part of this implementation is the selected block code (the component codes are block codes) and the mapper.
  • the main difference between these different types of space-coupled codes lies in the internal structure of the mapper and the selected component codes.
  • Decoding of space-coupled codes is performed using a "sliding window" decoding technique. That is, the receiver collects s code block matrices V i from the channel and/or from previous processing, V i+1? ,...,V i+s-1 (window). Then, the decoding step of sliding window decoding (as shown in Fig. 3) is applied for decoding. Thereafter, the window "shifts" and the decoder utilizes only the following matrices V i+1 , V i+2 , . . . , V i+s .
  • FIG. 3 is a schematic diagram of an example of a decoding process of sliding window decoding to which the spatially coupled code of the present application is applied.
  • the specific decoding steps are as follows:
  • the codewords that can generate the second overhead include: generalized concatenated codewords (generalized concatenated code, GCC), generalized error location codes (generalized error location codes, GEL) codes, locally repairable codes (locally repairable codes, LRC), generalized integrated interleaved (generalized integrated interleaved, GII) code, etc.
  • GCC generalized concatenated code
  • GEL generalized error location codes
  • LRC locally repairable codes
  • GII generalized integrated interleaved
  • the second overhead of the GEL is a matrix obtained by matrix multiplication of the GEL code sub-matrix by the H B matrix, and then the overhead of the row code generated by performing row code encoding on the matrix.
  • FIG. 4 is a schematic diagram of an example of a general error location GEL code applicable to this application.
  • the GEL code structure includes row codes and column codes, and the check symbols of the GEL code are usually obtained by encoding the check symbols of the column codes by using the row codes.
  • Row codes can also be called outer codes, and column codes can also be called inner codes.
  • F q be a finite field with q elements
  • B i be [n,k i ,d i ] q linear code, where i ⁇ 0,1,...,L ⁇ , n represents the encoded code character
  • k represents the length of the payload symbol before encoding
  • d represents the minimum Hamming distance after encoding.
  • H i is a m i ⁇ n sub-matrix
  • m i can represent the number of bits contained in the codeword symbol of the outer code A i , and can also be expressed as the dimension under the vector representation of the elements in the F Qi field.
  • m i k i ? 1 ? k i ⁇ ⁇ 1,2,...,L ⁇ ; moreover, the matrix H i , H i? 1 ,...,H 1 form the parity check matrix of Bi .
  • N represents the codeword length after encoding
  • K represents the payload length before encoding
  • D represents the minimum Hamming distance after encoding.
  • C satisfies the following conditions:
  • the linear subspace C based on the n ⁇ N matrix of F q is called the general error location (GEL) code, which has L+1 inner code and L outer code B 0 , B 1 ,..., BL and A 1 , A 2 , ... A L .
  • GEL general error location
  • c represents an n ⁇ N matrix in C
  • c is an element in C space.
  • the outer code uses a systematic form of encoding and adopts a special form of matrix H B , namely:
  • I i is the identity matrix of m i ⁇ m i ;
  • O i,j is the zero matrix of m i ⁇ m j ;
  • P i,j is the m i ⁇ m j matrix based on the finite field F q .
  • the codeword c of the GEL code can be split into 2L sub-matrices whose size is m i ⁇ K i or m i ⁇ (NK i ), where i ⁇ 1,2 ,...,L ⁇ , as follows:
  • X i and Y i are respectively m i ⁇ K i and m i ⁇ (NK i ) sub-matrices, i ⁇ 1,2,...,N ⁇ .
  • Fig. 5 is a schematic diagram of an example of the encoding process of the GEL code applicable to the present application.
  • the specific decoding steps are as follows:
  • the matrix H B -1 is the standard matrix inverse of H B.
  • FIG. 6 is a schematic diagram of an example of a decoding process of a GEL code to which the present application is applied.
  • the specific decoding steps are as follows:
  • the decoding of the GEL code can be done step by step. In fact, a partial iterative loop and update can be performed on the codeword v. It can reduce the number of erroneous symbols in a codeword, but it cannot correct all errors. Encoding and decoding using GEL codes will help to enhance existing spatially coupled codes and design new spatially coupled codes
  • FIG. 7 is a schematic diagram showing an example of using GEL codes as component codes in a space coupling structure to which the present application is applied.
  • GEL codes as component codes in a space coupling structure to which the present application is applied.
  • FIG. 7 in order to design long GEL codes with high performance, it is necessary to use codewords with larger minimum Hamming distance in larger finite fields.
  • existing GEL codes do not support iterative decoding. Therefore, the embodiment of the present application adopts the GEL code as the component code in the spatial coupling structure.
  • FIG. 8 is a schematic diagram of an example of using GEL codes as component codes in a spatially coupled staircase applicable to the present application.
  • the component code can correct up to two errors using the original overhead, and has a relatively high error floor.
  • the designed GEL-based ladder code can correct up to 2 errors per column, and may correct up to 3 errors in some columns using original overhead and additional overhead.
  • FIG. 9 is a schematic diagram of an example of the error floor of the staircase and staircase-GEL codes applicable to the present application.
  • the combination of staircase and GEL structure has better performance and lower error. That is, the FEC obtained by the staircase-GEL code space coupling has a lower error floor and a better slope of the performance curve. It should be understood that both FECs have the same overhead and delay.
  • the error floor has nothing to do with the delay of the decoding algorithm, the two are independent.
  • staircase-GEL is suitable for high-rate and extremely low-latency structures, which cannot be achieved by Staircase-BCH and GEL respectively.
  • Classical staircase-BCH requires a large decoding window size to avoid poor performance.
  • the present application provides a codec method to obtain subcodes of the original code with better properties (i.e., larger minimum distance) by adding additional overhead, and to provide performance improvement, reduce errors in decoding new features.
  • Reduce latency by adding overhead improve the slope of the performance curve, and significantly reduce the error floor; reduce the error floor to 1e-15 by outputting BER at negligible power and complexity costs, and adding reasonable OH .
  • "at least one” means one or more than two.
  • "And/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • a and/or B which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • the character "/" generally indicates that the contextual objects are an "or” relationship.
  • FIG. 10 is a schematic diagram of an example of a method 1000 for spatially coupled FEC coding applicable to the present application.
  • the specific implementation steps include:
  • the FEC code block includes a plurality of data code blocks, a first overhead code block and a second overhead code block (for example, as shown in FIG. 13 ), wherein the FEC code block includes N rows, and the first overhead code block is located in the FEC code block In each row of the N rows, the second overhead code block is located in the M rows of the FEC code block, M is less than or equal to N, and M and N are integers greater than zero.
  • the original data stream may include bits, symbols, etc., which are not specifically limited in the present application.
  • the first overhead code block is generated by encoding the information matrix to be encoded determined by the data code block and the second overhead code block based on the encoding method of the space coupling code
  • the second overhead code block is based on the general error location GEL code , general concatenated code GCC, tensor product and general integrated interleaved GII code generated by any one codeword
  • the second check symbol occupies Q bits of the data code block
  • Q is an integer greater than zero.
  • a possible implementation is to select any one of the general error position GEL code, the general concatenated code GCC, the tensor product and the general integrated interleaving GII code as the component code of the spatially coupled code to generate the first overhead code block and the second overhead code block.
  • the check matrix H B of C GEL is used to check the column code of the GEL code
  • the second overhead code block is the first
  • the first check matrix is generated by encoding the row codes of the check matrix, and the first check matrix is determined according to the product of the sub-matrix of the H B and the sub-matrix of the GEL code.
  • GEL codes are a class of block codes with good properties.
  • the H B matrix used to generate column code check symbols in GEL codes is a check matrix of 2 ⁇ n ⁇ 2 ⁇ n, the check matrix H 1 of B 1 in rows k+1 to 2 ⁇ n, and the check matrix H 1 of k 2 + Rows 1 to k are H 2 , and H 1 and H 2 constitute the parity check matrix of B 2 .
  • the first to k 2 rows of H 3 include a k 2 ⁇ k 2 identity matrix and a 2 ⁇ nk 2 zero matrix.
  • the m 2 ⁇ (hK) matrix determined by the k 2 +1 to k th columns to k th columns is 0 before encoding, and is used to store the second overhead after encoding.
  • the matrix determined in rows k+1 to 2 ⁇ n is all 0s before encoding, and is used to store the first overhead after encoding.
  • the improved space-coupled code is a special subcode of the original space-coupled code.
  • the 1st to k 2 keep the original values, and the k 2 + 1 to kth rows get the first parity check matrix of the column code, and then the first parity check matrix of the column code is performed Encoding, putting the generated parity check matrix into the m 2 ⁇ (hK) matrix determined by the k 2 +1 to kth rows and k to h columns of the GEL code matrix, as the second overhead generation method.
  • the inner code B 1 (that is, the component code B of the original space-coupled code) is encoded for each column of the 1st to k rows, and the resulting check bits are put into the k+1 to 2 ⁇ n rows as the first overhead .
  • the component code A i of the spatially coupled code is a GEL code
  • the component code A i includes a historical code block C i , multiple data code blocks, a first overhead code block, and a second overhead code block.
  • the historical code block C i may refer to a code block before the current FEC code block to be transmitted.
  • one of the cores of the encoding method of the space-coupled code is to construct the code block to be encoded of the component code A i at the current moment, where i is an integer greater than or equal to 0.
  • V i is composed of s square matrices (V i,0 V i,1 ... V i,s-1 ) of h ⁇ h (h rows and h columns). So a semi-infinite sequence V can be defined as:
  • V i is an all-zero matrix of h ⁇ n (h rows and n columns);
  • Each row of is a codeword in the codeword space of the component code B of the space-coupled code
  • the original space coupling code corresponds to the semi-infinite sequence
  • W i is a binary matrix of h ⁇ n (h rows and n columns)
  • h is a divisor of n
  • s n/h.
  • W i is composed of s square matrices (W i,0 W i,1 ...W i,s-1 ) of h ⁇ n (h rows and h columns). So a semi-infinite sequence can be defined as:
  • the matrix W i is an all-zero matrix of h ⁇ n (h rows and n columns);
  • a suitable new space-coupled code is designed to allow FEC codewords with low-complexity decoding process and low error floor at low delay and high throughput Applications in high-volume, high-speed communication transmission scenarios.
  • the semi-infinite sequence V is the bits of the first overhead code block and the bits of the second overhead code block generated based on the bits of the historical code block and the bits of the original data stream according to the encoding method of the GEL code.
  • the semi-infinite sequence V is based on historical code blocks bits and k 2 ⁇ h+K ⁇ m 2 payload bits to generate all m 1 ⁇ h+(hK) ⁇ m 2 original overhead and additional overhead.
  • the semi-infinite sequence V is based on the encoding method of the GEL code, based on the bits of the historical code block and the bits of the original data stream, the bits of the generated second overhead code block, and the bits based on the second overhead code block
  • the bits of are the bits of the generated first overhead code block.
  • the semi-infinite sequence V is based on historical code blocks bits, k 2 ⁇ h+K ⁇ m 2 payload bits and m 2 ⁇ (hK) overhead to generate m 1 ⁇ h bits of original overhead.
  • the modified semi-infinite sequence V contains (hK) ⁇ m 2 additional overheads in each code block V i , while retaining the structure of the original space-coupled code.
  • the extra overhead is introduced by the GEL codeword C GEL , which is more overhead than the overhead of the original space-coupled code.
  • the inner code word B 0 and B 3 of C GEL are the identity code word [2 n, 2 n, 1] 2 and the all-zero code word respectively, B 1 and the component code B of the original space coupling code are the same code word, B 2 is the codeword [2 ⁇ n,k 2 ,d2] 2 , which is also the subcode of B 1 , so there is According to the above description of GEL, the obtained H B matrix is:
  • all the outer codes of the GEL code word C GEL are code words defined on different extension fields of the binary field. That is, the outer code A 1 of C GEL is the Galois Field The all-zero codeword on A 2 is the Galois Field codeword on A 3 is Galois field identity codeword on Wherein, in this implementation, A 2 is used as an error correction code for encoding and decoding.
  • the historical code block includes n ⁇ h bits
  • the multiple data code blocks include k 2 h+K m 2 bits (that is, payload bits) of the original data stream
  • the first overhead code block includes m 1 ⁇ h bits of original overhead
  • the second overhead code block includes (hK) ⁇ m 2 bits of overhead.
  • the FEC code block V i is a rearrangement of the transpose (A' i ) T of the sub-matrix A' i of the component code A i , where the component code A i is a matrix with 256 rows and 16 columns, The sub-matrix A' i is the last 128 rows and 16 columns matrix of A i , the component code A i includes the historical code block C i , multiple data code blocks and the first overhead code block, V i includes eight sub-matrixes with 16 rows and 16 columns Matrix V i,t (r, c) is a matrix of 16 rows and 128 columns arranged in the row direction, i is the row number of the FEC code block, t is the column number of the FEC code block, r and c are sub-matrixes V i, The row number and column number of t (r,c), t is an integer greater than or equal to 0 and less than or equal to 7, i is an
  • the sub-matrix A' i transpose (A' i ) T of the component code A i is the transpose of multiple data code blocks, the first overhead code block and the second overhead code block
  • (A' i ) T includes 8 sub-matrices (A' i,t (r,c)) of 16 rows and 16 columns (A' i,t (r,c)) T is a matrix of 16 rows and 128 columns arranged in the row direction, where r and c are sub-matrices (A' i,t (r,c))
  • the row number and column number of T , t is an integer greater than or equal to 0 and less than or equal to 7
  • i is an integer greater than or equal to
  • r and c are greater than or equal to 0 and less than or an integer equal to 15.
  • the second overhead code block is located at (A′ i,6 (r,c)) T , where r is an integer greater than or equal to 14 and less than or equal to 15, c is greater than or equal to 7 and An integer less than or equal to 14, the first overhead code block is located at (A′ i,6 (r,c 1 )) T and (A′ i,7 (r,c 2 )) T , r is greater than or equal to 0 and An integer less than or equal to 15, c 1 is 15, and c 2 is an integer greater than or equal to 0 and less than or equal to 15.
  • the historical code block C i includes 8 sub-matrices C i,t with 16 rows and 16 columns arranged in the column direction, and a matrix with 128 rows and 16 columns, when i in the FEC code block V i is an even number , select the j-th 16-row and 16-column matrix V i-19+2*j ,j of the historical FEC code block with the serial number i-19+2*j to transpose and rearrange and then transpose to obtain the historical code block C i,j in ; when i in the FEC code block V i is an odd number, select the j-th 16-row 16-column matrix V i-21+2 of the historical FEC code block whose serial number is i-21+ 2*j *j,j are transposed and rearranged and then transposed to obtain C i,j in the historical code block.
  • the historical code block C i includes eight 16-row and 16-column sub-matrices C i, t arranged in a column-wise 16-row and 128-column matrix, and the sequence number of the FEC code block V i is i-27+ The j-th 16-row and 16-column matrix V i-27+j,j of j 's historical FEC code block is transposed, rearranged and then transposed to obtain C i,j in the historical code block.
  • the code word C of the GEL code GEL inner code B 0 is the identity code word [256,256,1] 2
  • B 1 is the extended BCH code word [256,239,6] 2
  • B 2 is the extended BCH code word [256,231,8] 2
  • the outer code A 1 is the all-zero code word on GF(2 17 )
  • a 2 is the cyclic RS code on GF(2 8 )
  • a 3 is the identity codeword on GF(2 231 )
  • the data code block and the second overhead code block determine a 16-row 111-column code blocks (wherein, the 14th-15th row (the serial number starts from 0), the 103-110 column (the serial number starts from 0) is the second overhead code block, and the rest is the original data), the first overhead code block is 16 An encoded information matrix with 17 rows and 17 columns. After rearranging the bits (or symbols) in the data code block, the first overhead code block and the second overhead code block, an encoded FEC code block can be obtained.
  • the first overhead code block is at the same position as the OFEC overhead code block, and the second overhead code block is at a part of the OFEC original data code block.
  • the rearrangement rule of ⁇ is defined as follows:
  • ⁇ i, j represent the elements of row i and column j in a matrix W with 16 rows and 16 columns, and i and j are integers greater than or equal to 0 and less than or equal to 15, respectively.
  • the FEC code block V i consists of 8 rearranged sub-matrices B t is determined, i represents the serial number of the FEC code block, V i,t represents the t-th sub-matrix B t with 16 rows and 16 columns, and t is an integer greater than or equal to 0 and less than or equal to 7.
  • the GEL code is an information matrix block with 256 rows and 16 columns
  • the matrix blocks of rows 0-127 are determined from historical FEC code blocks
  • the matrix blocks of rows 128-230 are data code blocks
  • the first 14 columns of information matrix blocks of rows 231-238 are data code blocks
  • the second The overhead code blocks occupy the last two columns of the matrix block in rows 231-238 of the GEL code
  • the first overhead code block is located in rows 239-255.
  • FIG. 11 is a schematic diagram of an example of a method 1100 for spatially coupled FEC decoding applicable to the present application.
  • the specific implementation steps include:
  • the FEC code block includes a plurality of data code blocks, a first overhead code block and a second overhead code block (for example, as shown in FIG. 13 ), wherein the FEC code block includes N rows, and the first overhead code block is located in the FEC code block In each row of the N rows, the second overhead code block is located in the M rows of the FEC code block, M is less than or equal to N, and M and N are integers greater than zero.
  • the original data stream may include bits, symbols, etc., which are not specifically limited in the present application.
  • overhead symbol can be replaced in non-specific cases
  • overhead code block can include “overhead symbol”, “redundant symbol”, “Check symbol”, etc.
  • code block and “matrix” can be replaced by each other in non-specific cases, or in other words, a code block is composed of a matrix.
  • one symbol may correspond to multiple bits
  • one code block may include multiple symbols
  • a code block includes multiple bits or multiple symbols, which is not specifically limited in this application.
  • the first overhead code block is generated by encoding the information matrix to be encoded determined by the data code block and the second overhead code block based on the encoding method of the space coupling code
  • the second overhead code block is based on the general error location GEL code , general concatenated code GCC, tensor product and general integrated interleaved GII code generated by any one codeword
  • the second overhead code block occupies Q bits of the data code block, and Q is an integer greater than zero.
  • a possible implementation is to select any one of the general error position GEL code, the general concatenated code GCC, the tensor product and the general integrated interleaving GII code as the component code of the spatially coupled code to generate the first overhead code block and the second overhead code block.
  • the check matrix H B of C GEL is used to check the column code of the GEL code
  • the second overhead code block is It is generated by encoding the row codes of the first check matrix, and the first check matrix is determined according to the product of the sub-matrix of the H B and the sub-matrix of the GEL code.
  • GEL codes are a class of block codes with good properties.
  • the H B matrix used to generate column code check symbols in GEL codes is a check matrix of 2 ⁇ n ⁇ 2 ⁇ n, the check matrix H 1 of B 1 in rows k+1 to 2 ⁇ n, and the check matrix H 1 of k 2 + Rows 1 to k are H 2 , and H 1 and H 2 constitute the parity check matrix of B 2 .
  • the first to k 2 rows of H 3 include a k 2 ⁇ k 2 identity matrix and a 2 ⁇ nk 2 zero matrix.
  • the m 2 ⁇ (hK) matrix determined by the k 2 +1 to k th columns to k th columns is 0 before encoding, and is used to store the second overhead after encoding.
  • the matrix determined in rows k+1 to 2 ⁇ n is all 0s before encoding, and is used to store the first overhead after encoding.
  • the improved space-coupled code is a special subcode of the original space-coupled code.
  • the 1st to k 2 keep the original values, and the k 2 + 1 to kth rows get the first parity check matrix of the column code, and then the first parity check matrix of the column code is performed Encoding, putting the generated parity check matrix into the m 2 ⁇ (hK) matrix determined by the k 2 +1 to kth rows and k to h columns of the GEL code matrix, as the second overhead generation method.
  • the inner code B 1 (that is, the component code B of the original space-coupled code) is encoded for each column of the 1st to k rows, and the resulting check bits are put into the k+1 to 2 ⁇ n rows as the first overhead .
  • the component code A i when the component code A i is a GEL code, the component code A i includes a historical code block C i , multiple data code blocks, a first overhead code block, and a second overhead code block.
  • the historical code block C i may refer to a code block before the current FEC code block to be transmitted.
  • one of the cores of the encoding method of the space-coupled code is to construct the code block to be encoded of the component code A i at the current moment, where i is an integer greater than or equal to 0.
  • V i is composed of s square matrices (V i,0 V i,1 ... V i,s-1 ) of h ⁇ h (h rows and h columns). So a semi-infinite sequence V can be defined as:
  • V i is an all-zero matrix of h ⁇ n (h rows and n columns);
  • Each row of is a codeword in the codeword space of the component code B of the space-coupled code
  • the original space coupling code corresponds to the semi-infinite sequence
  • W i is a binary matrix of h ⁇ n (h rows and n columns)
  • h is a divisor of n
  • s n/h.
  • W i is composed of s square matrices (W i,0 W i,1 ...W i,s-1 ) of h ⁇ n (h rows and h columns). So a semi-infinite sequence can be defined as:
  • the matrix W i is an all-zero matrix of h ⁇ n (h rows and n columns);
  • a suitable new space-coupled code is designed to allow FEC codewords with low-complexity decoding process and low error floor at low delay and high throughput Applications in high-volume, high-speed communication transmission scenarios.
  • the semi-infinite sequence V is the bits of the first overhead code block and the bits of the second overhead code block generated based on the bits of the historical code block and the bits of the original data stream according to the encoding method of the GEL code.
  • the semi-infinite sequence V is based on historical code blocks bits and k 2 ⁇ h+K ⁇ m 2 payload bits to generate all m 1 ⁇ h+(hK) ⁇ m 2 original overhead and additional overhead.
  • the semi-infinite sequence V is based on the encoding method of the GEL code, based on the bits of the historical code block and the bits of the original data stream, the bits of the generated second overhead code block, and the bits based on the second overhead code block
  • the bits of are the bits of the generated first overhead code block.
  • the semi-infinite sequence V is based on historical code blocks bits, k 2 ⁇ h+K ⁇ m 2 payload bits and m 2 ⁇ (hK) overhead to generate m 1 ⁇ h bits of original overhead.
  • the modified semi-infinite sequence V contains (hK) ⁇ m 2 additional overheads in each code block V i , while retaining the structure of the original space-coupled code.
  • the extra overhead is introduced by the GEL codeword C GEL , which is more overhead than the overhead of the original space-coupled code.
  • the inner code word B 0 and B 3 of C GEL are the identity code word [2 n, 2 n, 1] 2 and the all-zero code word respectively, B 1 and the component code B of the original space coupling code are the same code word, B 2 is the codeword [2 ⁇ n,k 2 ,d2] 2 , which is also the subcode of B 1 , so there is According to the above description of GEL, the obtained H B matrix is:
  • all the outer codes of the GEL code word C GEL are code words defined on different extension fields of the binary field. That is, the outer code A 1 of C GEL is the Galois Field The all-zero codeword on A 2 is the Galois Field codeword on A 3 is Galois field identity codeword on Wherein, in this implementation, A 2 is used as an error correction code for encoding and decoding.
  • the historical code block includes n ⁇ h bits
  • the multiple data code blocks include k 2 h+K m 2 bits (that is, payload bits) of the original data stream
  • the first overhead code block includes m 1 ⁇ h bits of original overhead
  • the second overhead code block includes (hK) ⁇ m 2 bits of overhead.
  • the FEC code block V i is a rearrangement of the transpose (A' i ) T of the sub-matrix A' i of the component code A i , where the component code A i is a matrix with 256 rows and 16 columns, The sub-matrix A' i is the last 128 rows and 16 columns matrix of A i , the component code A i includes the historical code block C i , multiple data code blocks and the first overhead code block, V i includes eight sub-matrixes with 16 rows and 16 columns Matrix V i,t (r, c) is a matrix of 16 rows and 128 columns arranged in the row direction, i is the row number of the FEC code block, t is the column number of the FEC code block, r and c are sub-matrixes V i, The row number and column number of t (r,c), t is an integer greater than or equal to 0 and less than or equal to 7, i is an
  • the sub-matrix A' i transpose (A' i ) T of the component code A i is the transpose of multiple data code blocks, the first overhead code block and the second overhead code block
  • (A' i ) T includes 8 sub-matrices (A' i,t (r,c)) of 16 rows and 16 columns (A' i,t (r,c)) T is a matrix of 16 rows and 128 columns arranged in the row direction, where r and c are sub-matrices (A' i,t (r,c))
  • the row number and column number of T , t is an integer greater than or equal to 0 and less than or equal to 7
  • i is an integer greater than or equal to
  • r and c are greater than or equal to 0 and less than or an integer equal to 15.
  • the second overhead code block is located at (A′ i,6 (r,c)) T , where r is an integer greater than or equal to 14 and less than or equal to 15, c is greater than or equal to 7 and An integer less than or equal to 14, the first overhead code block is located at (A′ i,6 (r,c 1 )) T and (A′ i,7 (r,c 2 )) T , r is greater than or equal to 0 and An integer less than or equal to 15, c 1 is 15, and c 2 is an integer greater than or equal to 0 and less than or equal to 15.
  • the historical code block C i includes 8 sub-matrices C i,t with 16 rows and 16 columns arranged in the column direction, and a matrix with 128 rows and 16 columns, when i in the FEC code block V i is an even number , select the j-th 16-row and 16-column matrix V i-19+2*j,j of the historical FEC code block with the serial number i-19+2*j to transpose and rearrange and then transpose to obtain the historical code block C i,j in ; when i in the FEC code block V i is an odd number, select the j-th 16-row 16-column matrix V i-21+2 of the historical FEC code block whose serial number is i-21+ 2*j *j,j are transposed and rearranged and then transposed to obtain C i,j in the historical code block.
  • the historical code block C i includes eight 16-row and 16-column sub-matrices C i, t arranged in a column-wise 16-row and 128-column matrix, and the sequence number of the FEC code block V i is i-27+ The j-th 16-row and 16-column matrix V i-27+j,j of j 's historical FEC code block is transposed, rearranged and then transposed to obtain C i,j in the historical code block.
  • the code word C of the GEL code GEL inner code B 0 is the identity code word [256,256,1] 2
  • B 1 is the extended BCH code word [256,239,6] 2
  • B 2 is the extended BCH code word [256,231,8] 2
  • the outer code A 1 is the all-zero code word on GF(2 17 )
  • a 2 is the cyclic RS code on GF(2 8 )
  • a 3 is the identity codeword on GF(2 231 )
  • the data code block and the second overhead code block determine a 16-row 111-column
  • the code blocks of (among them, lines 14-15 (serial numbers start from 0), columns 103-110 (serial numbers start from 0) are the second overhead code blocks, and the rest are original data), and the first overhead code block is 16 lines A matrix of encoded information with 17 columns.
  • the first overhead code block is at the same position as the OFEC overhead code block, and the second overhead code block is at a part of the OFEC original data code block.
  • the rearrangement rule of ⁇ is defined as follows:
  • ⁇ i, j represent the elements of row i and column j in a matrix W with 16 rows and 16 columns, and i and j are integers greater than or equal to 0 and less than or equal to 15, respectively.
  • the FEC code block V i consists of 8 rearranged sub-matrices B t is determined, i represents the serial number of the FEC code block, V i,t represents the t-th sub-matrix B t with 16 rows and 16 columns, and t is an integer greater than or equal to 0 and less than or equal to 7.
  • the GEL code is an information matrix block with 256 rows and 16 columns
  • the matrix blocks of rows 0-127 are determined from historical FEC code blocks
  • the matrix blocks of rows 128-230 are data code blocks
  • the first 14 columns of information matrix blocks of rows 231-238 are data code blocks
  • the second The overhead code blocks occupy the last two columns of the matrix block in rows 231-238 of the GEL code
  • the first overhead code block is located in rows 239-255.
  • the component code B is the extended binary BCH[256,239,6] 2
  • the component code in the new spatially coupled code is the GEL code
  • the GEL code is a matrix of 256 rows and 16 columns including 4 inner codes and 3 outer codes.
  • GEL code word C GEL inner code word B 0 and B 3 are the identity code word [256,256,1] 2 and all-zero code word respectively
  • B 1 and the component code B of the original space coupling code are the same code word [256,239,6] 2
  • B 2 is the extended BCH codeword [256,231,8] 2
  • B 1 and B 2 are the extensions of the original binary BCH code in the narrow sense, and the extended bits are obtained through single parity check.
  • the generator polynomial of B 2 g 2 (x) x 24 +x 23 +x 21 +x 20 +x 19 +x 17 +x 16 +x 15 +x 13 +x 8 +x 7 +x 5 + x 4 + x 2 +1
  • B 3 is an all-0 codeword with a length of 256.
  • the outer codewords of GEL include three codewords of length 16 on different binary domain extension domains. That is, A 1 is an all-zero codeword on the GF(2 17 ) field. A 2 is on the field of GF(2 8 ) A cyclic (Reed-Solomon, RS) codeword of the form whose generator polynomial is ⁇ is the primitive element of GF(2 8 ). A 3 is the identity codeword on GF(2 231 ) field
  • the GEL code word C GEL is a linear block code in the binary field with a length of 4096 and a dimension of 3808.
  • a code word c in the code word C GEL can be regarded as a 256 ⁇ 16 binary matrix.
  • each column in the codeword c in GEL is a codeword constructed by the codeword B1 construction rule.
  • the matrix product of H2 and c is the codeword of RS code A2 .
  • codeword C 1 can be divided into 3 steps:
  • the failed column can mark the corresponding column of the A2 codeword, and in the second decoding process, the symbol of A2 corresponding to the marked column is erased.
  • the Error and/or erasure values obtained during the A2 decoding process are the adjoint values of the columns involved in the H2 parity check matrix. Since H 2 and H 1 determine the parity check matrix of the code word B 2 , the syndromes calculated in the first and second steps of the decoding process proposed above can be passed through the syndrome decoder of B 2 Decoding column.
  • the component codes in the new space coupling code are GEL codes.
  • VT is the matrix transpose of V.
  • g is a non-negative integer
  • ⁇ i, k (V) is some arrangement of matrix items
  • k can take values 0, 1, 2, ..., 15, which is not specifically limited in this application.
  • the number in each cell of each row represents the element in this cell of the matrix after rearrangement, which is the element corresponding to the column of this row before the matrix arrangement.
  • the encoding of this semi-infinite sequence is to use the encoding process of code word C1 to perform continuous encoding matrix by matrix. That is, one can use the matrix and 1760-bit payload (original information, that is, multiple data code blocks) as the information bits of the codeword, and then obtain 288 overheads consisting of 16 additional overheads (second overhead) and 272 original overheads (first overhead) A matrix V i of parity bits, payload, and parity bits.
  • FIG. 12 is a schematic diagram of an example of the combination of open FEC and GEL codes applicable to this application.
  • the GEL code C 1 outer code A2 combined with the inner code B 2 generates an additional 16-bit second overhead, the first overhead of which is generated by the inner codeword eBCH[256,239,6].
  • eBCH means that the BCH codeword is expanded by a single-bit parity bit (that is, a parity bit is added to the lowest bit of the BCH codeword to ensure that the modulo two sum of the entire codeword bits is 0). Codeword.
  • Table 3 is the general design of the OFEC space coupling structure and GEL as component codes applicable to the embodiments of the present application, and g is a constant. Among them, the extra overhead bit is generated by the principle of GEL encoding. Its internal code is eBCH[256,239,6] and eBCH[256,231,8], and its external code is RS[16,14,3].
  • each frame corresponds to a codeword of the GEL code, which can be represented as a 16 ⁇ 256-bit block, and each row is a codeword of the eBCH [256, 239, 6].
  • Each frame is half of the corresponding GEL code, and the second half can be obtained using the coupling structure of the open FEC. If the other 14 codewords of the frame are error-free, up to 2 lines can be decoded into eBCH[256,231,8] (correcting up to 3 errors in that line) using 16 bits of overhead.
  • the component code ⁇ is the extended binary BCH[256,239,6] 2 , in the new space coupling code
  • the component code of is GEL code
  • the GEL code word C GEL is a matrix including 4 inner codes and 3 outer codes.
  • GEL code word C GEL inner code word B 0 and B 3 are the identity code word eBCH[256,256,1] 2 and all-zero code word respectively, B 1 and the component code B of the original space coupling code are the same code
  • the word eBCH[256,239,6] 2 , B 2 is the extended BCH code word eBCH[256,231,8] 2 , B 1 and B 2 are the extensions of the original binary BCH code in the narrow sense, and the extended bits are obtained through single parity check.
  • B 0 is the identity code word eBCH[256,256,1] 2
  • B 1 is the same code word [256,239,6] 2 as the component code B of the original space-coupled code
  • B 3 is a codeword of all 0s with a length of 256.
  • the outer codewords of GEL include three codewords of length 16 on different binary domain extension domains. That is, A 1 is an all-zero codeword on the GF(2 17 ) field. A 2 is on the field of GF(2 8 ) A cyclic RS codeword of the form whose generator polynomial is ⁇ is the primitive element of GF(2 8 ). A 3 is the identity codeword on GF(2 231 ) field
  • the GEL codeword C 1 is a linear block code over a binary field with length 4096 and dimension 3808.
  • a code word c in code word C 1 can be regarded as a 256 ⁇ 16 binary matrix.
  • each column in the codeword c in GEL is a codeword constructed by the codeword B1 construction rule.
  • the matrix product of H2 and c is the codeword of RS code A2 .
  • codeword C 1 can be divided into 3 steps:
  • the failed column can mark the column corresponding to the A2 codeword
  • the A2 symbol corresponding to the marked column is erased.
  • the Error and/or erasure values obtained during the A2 decoding process are the adjoint values of the columns involved in the H2 parity check matrix. Since H 2 and H 1 determine the parity check matrix of the code word B 2 , the adjoint formula calculated in the first and second steps of the decoding process proposed above can be decoded by the adjoint formula of B 2 Decoder column.
  • the GEL code C GEL is used to generate additional overhead bits.
  • the component codes in the new space coupling code are GEL codes.
  • Semi-infinite sequence determined by 16 ⁇ 128 binary matrix
  • VT is the matrix transpose of V.
  • g is a non-negative integer
  • ⁇ i, k (V) is some arrangement of matrix items
  • k can take values 0, 1, 2, ..., 15, which is not specifically limited in this application.
  • the number in each cell of each row represents the element of the matrix in this cell after rearrangement, which is the element of the column corresponding to this row before the matrix arrangement.
  • the encoding of this semi-infinite sequence is to use the encoding process of code word C1 to perform continuous encoding matrix by matrix. That is, one can use the matrix and 1760-bit payload (original information, for example, multiple data code blocks involved in this application) as the information bits of the codeword, and then obtain 16 additional overheads (second overhead) and 272 original overheads (first overhead) Overhead) is a matrix V i of 288 parity bits, payload, and parity bits.
  • Table 4 shows the main design of a similar OFEC spatial coupling structure and GEL as component codes applicable to the embodiment of the present application.
  • the GEL code C 1 outer code A 2 combined with the inner code B 2 generates an additional 16-bit second overhead, the first overhead of which is generated by the inner codeword eBCH[256,239,6].
  • Table 5 is a general design of a space-coupled code structure similar to OFEC but more compact and GEL as a component code applicable to the embodiment of the present application, and g is a constant. Among them, the extra overhead bit is generated by the principle of GEL encoding. Its internal code is eBCH[256,239,6] and eBCH[256,231,8], and its external code is RS[16,14,3].
  • matrices with 16 rows and 16 columns are generated from the transmitted historical FEC code blocks according to the coupling rules of specific space coupling codes to form historical code blocks.
  • the historical code block and the current code block are spliced into a matrix Q with 16 rows and 256 columns. Transpose this matrix to get a matrix Q T with 256 rows and 16 columns.
  • there is only original data in Q and the first overhead and the second overhead are filled with all 0s.
  • the matrix Y (256 rows and 16 columns) is transposed to obtain Y T (16 rows and 256 columns), and the 128-255 columns of Y T are selected and rearranged to obtain the FEC code block to be transmitted.
  • the generated first overhead is equivalent to the overhead obtained by performing eBCH[256,239] encoding on the first 239 bits of each row of Y T when the second overhead position is filled with all 0s).
  • FIG. 13 is a schematic diagram of an example of an FEC applicable to an optical transmission scenario of the present application.
  • the abscissa is the input BER
  • the ordinate is the bit error rate BER. It can be seen from the figure that the error floor of the FEC with additional overhead is significantly lower than that of the original FEC.
  • the power consumption estimation can include: SD1 P3 HD2 ⁇ 280mW, SD1 P6 HD2 ⁇ 450mW.
  • SDx Py HD z x represents the number of iterations of soft-decision decoding, y represents the number of selected least reliable positions, and z represents the number of iterations of hard-decision decoding.
  • the original FEC has 15.3% OH.
  • FEC adds +1% redundancy (over head, OH) as additional overhead. It can be seen that at negligible added power and complexity cost, the slope of the FEC performance curve with overhead is significantly improved, achieving 0.5/0.7dB at an output BER of 1e-15 gain.
  • FIG. 14 is a schematic diagram of an example of an FEC applicable to an optical transmission scenario of the present application.
  • the abscissa is the input bit error rate (BER), and the ordinate is the output BER. It can be seen from the figure that the error floor of the FEC with additional overhead is significantly lower than that of the original FEC.
  • the power consumption estimation can include: SD1 P6 HD5 ⁇ 600mW. .
  • SDx Py HD z x represents the number of iterations of soft-decision decoding, y represents the number of selected least reliable positions, and z represents the number of iterations of hard-decision decoding.
  • the original FEC has 15.3% OH.
  • FEC adds +1% OH as an additional overhead. It can be seen that the slope of the FEC performance curve with overhead is significantly improved with negligible power and complexity cost
  • this application provides a method for spatially coupled forward error correction codec, by adding additional overhead to obtain a subcode of the original code with better properties (ie, a larger minimum Hamming distance), As well as new features in decoding that provide performance improvements and reduce errors. Support new requirements for latency and performance, improve the slope of the performance curve and significantly reduce the error floor, provide backward compatibility and improvements in FEC characteristics, design a single FEC that supports various performance, latency and complexity requirements. Reduces bit error floor to 1e-15 level at negligible power and complexity cost and adds reasonable OH by outputting BER or less;
  • the technical solution of this application can improve the minimum distance of FEC; reduce the bit error level, and improve the convergence of iterative decoding by using all overhead (original and extra); reduce the number of trap sets; low delay, high rate, low bit error rate , Low-complexity decoding process to achieve high performance.
  • Fig. 15 is a schematic diagram of an example of encoding equipment for spatially coupled forward error correction codes provided by an embodiment of the present application.
  • the device 1500 may include a processing unit 1520 and a transceiver unit 1510 .
  • the device 1500 may correspond to the encoding device in the above method embodiments, for example, may be an encoding device, or a component configured in the encoding device (such as a circuit, a chip, or a chip system, etc.).
  • the processing unit 1520 is configured to encode the original data stream to generate a forward error correction FEC code block, where the FEC code block includes a plurality of data code blocks, a first overhead code block, and a second overhead code block, where , the FEC code block includes N rows, the first overhead code block is located in each of the N rows of the FEC code block, the second overhead code block is located in the M rows of the FEC code block, M is less than or equal to N, and M and N are greater than zero an integer of
  • the transceiver unit 1510 is configured to send the FEC code block.
  • the device 1500 may correspond to the encoding device in the method 1000 according to the embodiment of the present application, and the device 1500 may include a unit for performing the method performed by the encoding device in the method 1000 in FIG. 10 . Moreover, each unit in the device 1500 and other operations and/or functions mentioned above are respectively intended to implement a corresponding flow of the method 1000 in FIG. 10 .
  • the transceiver unit 1510 in the coding device 1500 can be implemented by a transceiver, for example, it can correspond to the transceiver 1820 in the coding device shown in FIG.
  • the processor implements, for example, may correspond to the processor 1810 in the encoding device 1800 shown in FIG. 18 .
  • the transceiver unit 1510 in the coding device 1500 can be realized through an input/output interface, a circuit, etc.
  • the processing unit 1520 in the coding device 1500 can be It is realized by the processor, microprocessor or integrated circuit integrated on the chip or chip system.
  • Fig. 16 is a schematic diagram of an example of a spatial coupling forward error correction decoding device provided by an embodiment of the present application.
  • the device 1600 may include a processing unit 1620 and a transceiver unit 1610 .
  • the device 1600 may correspond to the decoding device in the above method embodiment, for example, may be a decoding device, or a component (such as a circuit, a chip, or a chip system, etc.) configured in the decoding device.
  • the transceiver unit 1610 is configured to receive a forward error correction FEC code block
  • the processing unit 1620 is configured to decode the FEC code block to restore the original data stream, the FEC code block includes a plurality of data code blocks, the first overhead code block and the second overhead code block, wherein the FEC code block includes N rows, The first overhead code block is located in each of the N lines of the FEC code block, the second overhead code block is located in the M lines of the FEC code block, M is less than or equal to N, and M and N are integers greater than zero.
  • the device 1600 may correspond to the decoding device in the method 1100 according to the embodiment of the present application, and the device 1600 may include a unit for performing the method performed by the decoding device in the method 1100 in FIG. 11 . Moreover, each unit in the device 1600 and the above-mentioned other operations and/or functions are respectively intended to implement a corresponding flow of the method 1100 in FIG. 11 .
  • the transceiver unit 1610 in the decoding device 1600 can be implemented by a transceiver, for example, it can correspond to the transceiver 1820 in the encoding device shown in FIG.
  • the processor implements, for example, may correspond to the processor 1810 in the encoding device 1800 shown in FIG. 18 .
  • the transceiver unit 1610 in the coding device 1600 can be realized through an input/output interface, a circuit, etc.
  • the processing unit 1620 in the coding device 1600 can be It is realized by the processor, microprocessor or integrated circuit integrated on the chip or chip system.
  • Fig. 17 is a schematic diagram of an example of a spatial coupling forward error correction coding device provided by an embodiment of the present application.
  • the apparatus 1700 may include a processor 1710 and a transceiver 1720 .
  • a memory 1730 is also included.
  • the processor 1710, the transceiver 1720 and the memory 1730 communicate with each other through an internal connection path, the memory 1730 is used to store instructions, and the processor 1710 is used to execute the instructions stored in the memory 1730 to control the transceiver 1720 to send signals and /or to receive a signal.
  • the encoding apparatus 1700 may correspond to the encoding device in the above method embodiments, and may be used to execute various steps and/or processes performed by the encoding device in the above method embodiments.
  • the memory 1730 may include read-only memory and random-access memory, and provides instructions and data to the processor. A portion of the memory may also include non-volatile random access memory.
  • the memory 1730 can be an independent device, or can be integrated in the processor 1710 .
  • the processor 1710 may be used to execute the instructions stored in the memory 1730, and when the processor 1710 executes the instructions stored in the memory, the processor 1710 is used to execute the steps of the above-mentioned method embodiments corresponding to the encoding device and/or or process.
  • the encoding device 1700 is the encoding device in the foregoing embodiments.
  • the processor 1710 is configured to encode the original data stream to generate a forward error correction FEC code block, where the FEC code block includes a plurality of data code blocks, a first overhead code block, and a second overhead code block, where , the FEC code block includes N rows, the first overhead code block is located in each of the N rows of the FEC code block, the second overhead code block is located in the M rows of the FEC code block, M is less than or equal to N, and M and N are greater than zero an integer of
  • the transceiver 1720 is configured to send the FEC code block.
  • the transceiver 1720 may include a transmitter and a receiver.
  • the processor 1710, memory 1730 and transceiver 1720 may be devices integrated on different chips.
  • the processor 1710 and the memory 1730 may be integrated in a baseband chip, and the transceiver 1720 may be integrated in a radio frequency chip.
  • the processor 1710, the memory 1730 and the transceiver 1720 may also be devices integrated on the same chip. This application is not limited to this.
  • the encoding device 1700 is a component configured in an encoding device, such as a circuit, a chip, a chip system, and the like.
  • the transceiver 1720 may also be a communication interface, such as an input/output interface, a circuit, and the like.
  • the transceiver 1720, the processor 1710 and the memory 1720 may be integrated in the same chip, such as a baseband chip.
  • Fig. 18 is a schematic diagram of an example of a spatial coupling forward error correction decoding device provided by an embodiment of the present application.
  • the apparatus 1800 may include a processor 1810 and a transceiver 1820 .
  • a memory 1830 is also included.
  • the processor 1810, the transceiver 1820 and the memory 1830 communicate with each other through an internal connection path, the memory 1830 is used to store instructions, and the processor 1810 is used to execute the instructions stored in the memory 1830 to control the transceiver 1820 to send signals and /or to receive a signal.
  • the decoding apparatus 1800 may correspond to the decoding device in the foregoing method embodiments, and may be configured to execute various steps and/or processes performed by the decoding device in the foregoing method embodiments.
  • the memory 1830 may include read-only memory and random-access memory, and provides instructions and data to the processor. A portion of the memory may also include non-volatile random access memory.
  • the memory 1830 can be an independent device, or can be integrated in the processor 1810 .
  • the processor 1810 may be used to execute the instructions stored in the memory 1830, and when the processor 1810 executes the instructions stored in the memory, the processor 1810 is used to execute the steps of the above-mentioned method embodiments corresponding to the decoding device and/or or process.
  • the decoding apparatus 1800 is the decoding device in the foregoing embodiments.
  • the transceiver 1820 is configured to receive a forward error correction FEC code block
  • the processor 1810 is configured to decode the FEC code block to restore the original data stream, the FEC code block includes a plurality of data code blocks, the first overhead code block and the second overhead code block, wherein the FEC code block includes N rows, The first overhead code block is located in each of the N lines of the FEC code block, the second overhead code block is located in the M lines of the FEC code block, M is less than or equal to N, and M and N are integers greater than zero.
  • the transceiver 1820 may include a transmitter and a receiver.
  • the processor 1810, memory 1830 and transceiver 1820 may be devices integrated on different chips.
  • the processor 1810 and the memory 1830 may be integrated in a baseband chip, and the transceiver 1820 may be integrated in a radio frequency chip.
  • the processor 1810, the memory 1830 and the transceiver 1820 may also be devices integrated on the same chip. This application is not limited to this.
  • the decoding apparatus 1800 is a component configured in a decoding device, such as a circuit, a chip, a chip system, and the like.
  • the transceiver 1820 may also be a communication interface, such as an input/output interface, a circuit, and the like.
  • the transceiver 1820, the processor 1810 and the memory 1820 may be integrated in the same chip, for example, integrated in a baseband chip.
  • the actions or methods executed by the controller may be implemented in whole or in part by software, hardware, firmware or any other combination.
  • the actions or methods performed by the controller may be fully or partially implemented in the form of computer program products.
  • the computer program product comprises one or more computer instructions or computer programs.
  • the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more sets of available media.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium, and the semiconductor medium may be a solid-state hard disk.
  • the memory and the processor in the foregoing apparatus embodiments may be physically independent units, or the memory and the processor may also be integrated together, which is not limited in the present application.
  • the processor in this embodiment of the present application may be an integrated circuit chip capable of processing signals.
  • each step of the above-mentioned method embodiments may be completed by an integrated logic circuit of hardware in a processor or instructions in the form of software.
  • the processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable Logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application-specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the steps of the methods disclosed in the embodiments of the present application may be directly implemented by a hardware coded processor, or executed by a combination of hardware and software modules in the coded processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.
  • the memory in the embodiments of the present application may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories.
  • the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM direct memory bus random access memory
  • direct rambus RAM direct rambus RAM
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

Abstract

Les modes de réalisation de la présente demande concernent un procédé de codage et un procédé de décodage. Le procédé de codage comprend : le codage d'un flux de données d'origine pour générer un bloc de code de correction d'erreur sans voie de retour (FEC) , qui comprend une pluralité de blocs de code de données, des premiers blocs de code de surdébit et des deuxièmes blocs de code de surdébit, le bloc de code FEC comprenant N rangées, les premiers blocs de code de surdébit sont situés dans chacune des N rangées du bloc de code FEC, les deuxièmes blocs de code de surdébit sont situés dans M rangées du bloc de code FEC, M est inférieur ou égal à N, et M et N sont des nombres entiers supérieurs à 0 ; et l'envoi du bloc de code FEC. Au moyen du procédé, un code de correction d'erreur sans voie de retour couplé spatialement peut être amélioré, et un plancher d'erreur est abaissé, réalisant ainsi l'application d'un code couplé spatialement dans un scénario de transmission de communication ayant un faible retard, un haut débit et un taux élevé.
PCT/CN2022/087391 2021-10-15 2022-04-18 Procédé et dispositif de codage, et procédé et dispositif de décodage WO2023060865A1 (fr)

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CN108292925A (zh) * 2015-11-02 2018-07-17 华为技术有限公司 通过使用m阶GEL码对数据进行编码/解码的方法与设备
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US20090040081A1 (en) * 2007-08-08 2009-02-12 Xueshi Yang Encoding and decoding methods using generalized concatenated codes (gcc)
CN101779379A (zh) * 2007-08-08 2010-07-14 马维尔国际贸易有限公司 使用通用级联码(gcc)进行编码和解码
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