WO2023056640A1

WO2023056640A1 - Latch, flip-flop, and chip

Info

Publication number: WO2023056640A1
Application number: PCT/CN2021/122896
Authority: WO
Inventors: 景蔚亮; 吴颖; 侯朝昭; 范人士; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2023-04-13
Also published as: CN117546239A

Abstract

The present application relates to the field of digital circuits, and provides a latch, a flip-flop, and a chip, which can decrease the number of transistors in the flip-flop. The latch comprises a signal input end, a signal output end, a control signal end, a first voltage end, a second voltage end, a pull-up circuit, and a pull-down circuit, wherein the transistors in the flip-flop are all N-type field effect transistors; the pull-up circuit is connected to the first voltage end and the signal output end; the pull-up circuit is configured to pull up the voltage of the signal output end according to the voltage of the first voltage end; the pull-down circuit is connected to the signal input end, the control signal end, the signal output end, and the second voltage end; and the pull-down circuit is configured to pull down the voltage of the signal output end according to the voltage of the second voltage end under signal control of the control signal end and the signal input end.

Description

Latches, flip flops and chips

technical field

The present application relates to the field of digital circuits, in particular to a latch, a flip-flop and a chip.

Background technique

In a digital logic chip, a flip-flop (flip-flop, FF) occupies 50% of the area of the entire digital logic circuit. Reducing the area overhead of flip-flops is very important for the scaling and performance improvement of digital logic chips.

In the traditional flip-flop using CMOS (complementary metal oxide semiconductor, complementary metal oxide semiconductor) process in the related art, the number of transistors is about 18, so if the number of transistors required by CMOS can be reduced, it can effectively reduce the number of transistors. The area required for small flip-flops.

Contents of the invention

Embodiments of the present application provide a latch, a flip-flop, and a chip. The flip-flop is formed by using an NFET-based latch, which can reduce the number of transistors in the flip-flop.

The present application provides a latch, including a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit and a pull-down circuit. Wherein, the transistors in the latch are all N-type field effect transistors (n-channel field effect transistors, NFETs; also called electronic channel field effect transistors). The pull-up circuit is connected with the first voltage terminal and the signal output terminal; the pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal. The pull-down circuit is connected to the signal input terminal, the control signal terminal, the signal output terminal and the second voltage terminal. The pull-down circuit is configured to: under the control of the signals of the control signal terminal and the signal input terminal, pull down the voltage of the signal output terminal according to the voltage of the second voltage terminal.

In this case, both the pull-up circuit and the pull-down circuit in the latch use NFETs, and the high-level voltage of the first voltage terminal is output to the signal output terminal through the pull-up circuit, and the voltage of the signal output terminal is pulled up. The signal terminal and the signal input terminal control the pull-down circuit, output the low-level voltage of the second voltage terminal to the signal output terminal, pull down the voltage of the signal output terminal and realize the latching of the signal.

In some possible implementation manners, the pull-up circuit includes a first resistor. One end of the first resistor is connected to the first voltage end, and the other end of the first resistor is connected to the signal output end.

In some possible implementations, the pull-up circuit includes a first NFET; the first NFET is a depletion-type NFET; the first pole of the first NFET is connected to the first voltage terminal, and the gate of the first NFET is connected to the second pole. Connect to signal output. In the case where the first NFET is a depletion-type NFET, the threshold voltage (V _th ) of the first NFET is less than zero, so as to ensure that the first NFET remains on.

In some possible implementation manners, the pull-up circuit includes a first NFET; the first NFET is an enhanced NFET; both the first pole and the gate of the first NFET are connected to the first voltage terminal, and the second pole and the gate of the first NFET are connected to the first voltage terminal. Signal output connection. In the case that the first NFET is an enhanced NFET, the threshold voltage (V _th ) of the first NFET is greater than zero, so as to ensure that the first NFET remains on.

In some possible implementation manners, the pull-up circuit includes a first NFET; the first NFET includes a first gate and a second gate; the first gate and the first pole of the first NFET are connected to the first voltage terminal, and the first NFET Both the second gate and the second pole of an NFET are connected to the signal output end. In this case, the first NFET is turned on under the control of the high-level voltage of the first voltage terminal, and outputs the high-level voltage of the first voltage terminal to the signal output terminal; the high-level voltage of the signal output terminal will be sent to The second gate of the first NFET forms positive feedback to further turn on the first NFET, thereby rapidly increasing the potential of the signal output terminal.

In some possible implementation manners, the pull-down circuit includes a second NFET, a third NFET and a first capacitor. The first gate of the second NFET is connected to the control signal terminal, the first pole of the second NFET is connected to the signal input terminal, and the second pole of the second NFET is connected to the first node. The first gate of the third NFET is connected to the first node, the first pole of the third NFET is connected to the signal output terminal, and the second pole of the third NFET is connected to the second voltage terminal. The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the second voltage terminal. In this case, by controlling the signal at the signal terminal to turn on and off the second NFET, the signal at the signal input terminal can be transmitted to the gate of the third NFET; and the first capacitor connected to the gate of the third NFET can transfer the signal The input signal is stored. When the voltage input by the signal input terminal is a high-level voltage (that is, logic "1"), the third NFET is turned on, and outputs the low-level voltage of the second voltage terminal (such as the ground terminal) to the signal output terminal; At the same time, due to the existence of the first capacitor, even when the second NFET is turned off, the high-level potential stored in the first capacitor can still keep the third NFET turned on, that is, the latching of the signal is realized.

In some possible implementation manners, the second NFET further includes a second gate; the second gate of the second NFET is connected to the control signal terminal.

In some possible implementation manners, the third NFET further includes a second gate; the second gate of the third NFET is connected to the first node.

An embodiment of the present application provides a latch, including a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit and a pull-down circuit. The transistors in the latch are all NFETs. The pull-up circuit is connected with the signal input terminal, the signal control terminal, the first voltage terminal and the signal output terminal. The pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal under the control of the signals of the control signal terminal and the signal input terminal. The pull-down circuit is connected with the signal output terminal and the second voltage terminal. The pull-down circuit is configured to: pull down the voltage of the signal output terminal according to the voltage of the second voltage terminal.

In this case, both the pull-up circuit and the pull-down circuit in the latch use NFETs, and the low-level voltage of the second voltage terminal is output to the signal output terminal through the pull-down circuit to pull down the voltage of the signal output terminal; through the control signal The terminal and the signal input terminal control the pull-up circuit, and output the high-level voltage of the first voltage terminal to the signal output terminal, so as to pull up the voltage of the signal output terminal and realize the latching of the signal.

In some possible implementation manners, the pull-down circuit includes a first resistor; one end of the first resistor is connected to the second voltage end, and the other end of the first resistor is connected to the signal output end.

In some possible implementations, the pull-down circuit includes a first NFET; the first NFET is a depletion NFET; the gate and the first pole of the first NFET are connected to the second voltage terminal, and the second pole of the first NFET Connect to the signal output. In the case where the first NFET is a depletion NFET, the threshold voltage (V _th ) of the first NFETa1 is less than zero, so as to ensure that the first NFET remains on.

In some possible implementations, the pull-down circuit includes a first NFET; the first NFET is a depletion NFET; the first NFET includes a first gate and a second gate; the first gate of the first NFET, the second gate Both the pole and the first pole are connected to the second voltage terminal, and the second pole of the first NFET is connected to the signal output terminal. When the first NFET is a depletion-type NFET, the threshold voltage (V _th ) of the first NFET is less than zero, which can ensure that the first NFET is always on.

In some possible implementation manners, the pull-up circuit includes a second NFET, a third NFET and a first capacitor. The first gate of the second NFET is connected to the control signal terminal, the first pole of the second NFET is connected to the signal input terminal, and the second pole of the second NFET is connected to the first node. The first gate of the third NFET is connected to the first node, the first pole of the third NFET is connected to the first voltage terminal, and the second pole of the third NFET is connected to the signal output terminal. The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the second voltage terminal. In this case, by controlling the signal at the signal terminal to turn on and off the second NFET, the signal at the signal input terminal can be transmitted to the gate of the third NFET; and the first capacitor connected to the gate of the third NFET can transfer the signal The input signal is stored. When the voltage input by the signal input terminal is a high-level voltage (that is, logic "1"), the third NFET is turned on, and the high-level voltage of the first voltage terminal is output to the signal output terminal; due to the existence of the first capacitor, Even when the second NFET is turned off, the high-level potential stored in the first capacitor can still keep the third NFET turned on, that is, the latching of the signal is realized.

The embodiment of the present application also provides a flip-flop, including a first latch and a second latch; both the first latch and the second latch adopt the lock provided in any of the aforementioned possible implementation methods. a latch; the signal output end of the first latch is connected to the signal input end of the second latch.

Compared with about 18 transistors in a traditional flip-flop using a CMOS process, in the flip-flop provided by some embodiments of the present application, the number of NFETs is only 6 (i.e. 6T structure); In the case of an inverter with four transistors (FETs), the number of transistors in the flip-flop is only 8 (that is, the 8T structure), that is, the flip-flop provided by the embodiment of the present application can greatly reduce the number of transistors.

An embodiment of the present application further provides a chip, including a digital logic circuit; the digital logic circuit includes the latch provided in any one of the foregoing possible implementation manners.

In some possible implementation methods, in the chip, the latch can be integrated in the subsequent process to meet the requirements of the chip for the three-dimensional monomer stacking technology, reduce the area of the chip, reduce the power consumption of the chip, and improve the power consumption of the chip. performance.

In some possible implementation manners, the chip further includes a substrate and a first device layer and a second device layer disposed on the substrate. The second device layer is located on the side of the first device layer away from the substrate, and the first device layer and the second device layer are electrically connected. CMOS transistors are arranged in the first device layer. The NFETs in the latch are oxide semiconductor field effect transistors, and the NFETs in the latch are distributed in the second device layer.

By setting the digital logic circuit of the chip, using the flip-flop and/or latch provided by the embodiment of the present application, and setting the NFET in the flip-flop and/or latch to use an N-type oxide semiconductor field effect transistor, the chip can be satisfied. In the production temperature conditions of the back-end process, in this way, the first device layer can be fabricated in the front-end process (front end of line, FEOL) through CMOS technology, and then the second device layer can be made in the back-end process (backend of line, BEOL). The production of the device layer; that is, to integrate the digital logic circuit and the subsequent process of the chip to meet the requirements of the chip for three-dimensional monomer stacking technology, reduce the area of the chip, reduce the power consumption of the chip, and improve the performance of the chip.

An embodiment of the present application further provides an electronic device, the electronic device includes a printed circuit board and a chip provided in any of the foregoing possible implementation manners; the chip is electrically connected to the printed circuit board.

Description of drawings

FIG. 1 is a schematic structural diagram of a latch provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of four different pull-up circuits provided by the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a pull-down circuit provided in an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a pull-down circuit provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a latch provided by an embodiment of the present application;

Fig. 6 is the simulation result of the latch of Fig. 5;

FIG. 7 is a schematic structural diagram of a latch provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of three different pull-down circuits provided by the embodiment of the present application;

FIG. 9 is a schematic structural diagram of a pull-up circuit provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of a pull-up circuit provided in an embodiment of the present application;

FIG. 11 is a schematic structural diagram of a latch provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of a trigger provided by an embodiment of the present application;

Fig. 13 is the simulation result of the trigger of Fig. 12;

FIG. 14 is a schematic structural diagram of a chip provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, and Not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. Words such as "connected" and "connected" are used to express intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device. "Up", "Down", "Left", "Right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts, and they are used for description and clarification relative to , which may change accordingly according to changes in the orientation in which components are placed in the drawings.

It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

An embodiment of the present application provides a flip-flop (FF), which can be formed by using a set of latches (that is, two latches) in series, and the transistors in the latch (latch) are all NFET (n-channel field effect transistor, electronic channel field effect transistor) is used. Compared with about 18 transistors that need to be provided in a flip-flop using a CMOS process, the flip-flop provided by the embodiment of the present application can greatly reduce the number of transistors.

It should be noted here that, for the NFETs used in the embodiments of the present application, some NFETs may have a single-gate structure (that is, have one gate), and some NFETs may have a double-gate structure (that is, have two gates, the second A gate and a second gate), for details, please refer to the relevant description below. Of course, it can be understood that, in addition to the gate, the NFET also includes a first pole and a second pole, one of the first pole and the second pole is a source, and the other is a drain, and the first pole and the second pole can be equivalent exchange. In the following embodiments of the present application, the first pole is the source and the second pole is the drain as an example for schematic illustration.

Two different types of latches (latch 1 and latch 2) are provided below, and setting of the flip-flop provided by the embodiment of the present application will be described in combination with the first latch and the second latch.

latch one

As shown in FIG. 1 , the latch one 10 includes: a pull-up circuit PUN (pull up network; also called a pull-up network circuit), a pull-down circuit PDN (pull down network; also called a pull-down network circuit), a signal An input terminal Input, a signal output terminal Output, a control signal terminal CLK, a first voltage terminal, and a second voltage terminal. Wherein, the first voltage terminal may be a high-level voltage terminal, such as a power supply terminal V _DD ; the second voltage terminal may be a low-level voltage terminal, such as a ground terminal GND, but not limited thereto. The following embodiments are all described by taking the first voltage terminal as the high-level voltage terminal as the power supply terminal V _DD and the second voltage terminal as the ground terminal GND as an example.

Referring to FIG. 1 , in the latch one 10, the pull-up circuit PUN is connected to the first voltage terminal (V _DD ) and the signal output terminal Output. The pull-up circuit PUN is configured to pull up the voltage of the signal output terminal Output according to the voltage of the first voltage terminal (V _DD ).

Schematically, referring to FIG. 1 and FIG. 2 (a), in some possible implementation manners, the pull-up circuit PUN may include a first resistor R1. One terminal of the first resistor R1 is connected to the first voltage terminal (V _DD ), and the other terminal of the first resistor R1 is connected to the signal output terminal Output.

Schematically, referring to FIG. 1 and FIG. 2 (b), in some possible implementation manners, the pull-up circuit PUN may include a first NFET a1. The first NFETa1 is a depletion NFET. Wherein, the source of the first NFETa1 is connected to the first voltage terminal (V _DD ), and both the gate and the drain of the first NFETa1 are connected to the signal output terminal Output.

It can be understood here that, in the case where the first NFETa1 is a depletion-type NFET, the threshold voltage (V _th ) of the first NFETa1 is less than zero, so that in the circuit connection mode of (b) in FIG. 2 , it is possible to Ensure that the first NFETa1 remains on.

Schematically, as shown in FIG. 1 and (c) in FIG. 2 , in some possible implementation manners, the pull-up circuit PUN may include a first NFET. The first NFET is an enhanced NFET; wherein, the source and gate of the first NFET are connected to the first voltage terminal (V _DD ), and the drain of the first NFET is connected to the signal output terminal Output (not shown in FIG. 2 ). )connect.

It can be understood here that, in the case where the first NFETa1 is an enhanced NFET, the threshold voltage (V _th ) of the first NFETa1 is greater than zero, so that in the circuit connection mode of (c) in FIG. 2 , it can be ensured that The first NFET a1 is kept on, so as to output the voltage of the first voltage terminal (V _DD ) to the signal output terminal Output, and pull up the voltage of the signal output terminal Output.

Schematically, as shown in FIG. 1 and (d) in FIG. 2 , in some possible implementation manners, the pull-up circuit PUN may include a first NFET a1. The first NFETa1 includes a first gate g1 and a second gate g2, that is, the first NFET has a double gate structure. Wherein, the first gate g1 and the source of the first NFETa1 are connected to the first voltage terminal (V _DD ), and the second gate g2 and the drain of the first NFETa1 are connected to the signal output terminal Output (not shown in FIG. 2 ). out). Wherein, (d) in FIG. 2 is only schematically illustrated by taking the first gate g1 as the top gate and the second gate g2 as the back gate as an example. In some other possible implementation modes, the first gate g1 may be a back gate, and the second gate g2 may be a top gate. In the following embodiments, the first gate g1 is used as the top gate, and the second gate g2 is used as the back gate as an example for schematic illustration.

As shown in (d) in FIG. 2, in the case where the first NFET a1 adopts a double gate structure, the first NFET a1 is turned on under the control of the high level voltage of the first voltage terminal (V _DD ), And output the high-level voltage of the first voltage terminal (V _DD ) to the signal output terminal Output, and pull up the voltage of the signal output terminal Output; at the same time, the high-level voltage of the signal output terminal Output will be sent to the first NFET a1 The second gate g2 forms a positive feedback to further turn on the first NFET a1, thereby rapidly increasing the potential of the signal output terminal Output.

In addition, referring to FIG. 1 , in the latch one 10, the pull-down circuit PDN is connected to the signal input terminal Input, the control signal terminal CLK, the signal output terminal Output, and the second voltage terminal (GND). The pull-down circuit PDN is configured to pull down the voltage of the signal output terminal Output according to the voltage of the second voltage terminal (GND) under the control of the signals of the control signal terminal CLK and the signal input terminal Input.

Schematically, in some possible implementation manners, as shown in FIG. 1 and FIG. 3 , the pull-down circuit PDN may include a second NFET a2, a third NFET a3, and a first capacitor C1. The gate of the second NFET a2 is connected to the control signal terminal CLK, the source of the second NFET a2 is connected to the signal input terminal Input, and the drain of the second NFET a2 is connected to the first node N1. The gate of the third NFET a3 is connected to the first node N1, the source of the third NFET a3 is connected to the signal output terminal Output, and the drain of the third NFET a3 is connected to the second voltage terminal (GND). A first pole of the first capacitor C1 is connected to the first node N1, and a second pole of the first capacitor C1 is connected to the second voltage terminal (GND). It should be pointed out that the first capacitor C1 may be composed of the gate capacitor of the third NFET a3, or a separately designed load capacitor, or a combination thereof.

In this case, by controlling the signal of the signal terminal CLK to control the opening and closing of the second NFET a2, the signal of the signal input terminal Input can be transmitted to the gate of the third NFET a3; and connected to the gate of the third NFET a3 The first capacitor C1 can store the signal of the signal input terminal Input. When the voltage input by the signal input terminal Input is a high-level voltage (that is, logic "1"), the third NFET a3 is turned on, and outputs the low-level voltage of the second voltage terminal (GND) to the signal output terminal Output , to pull down the voltage of the signal output terminal Output; at the same time, due to the existence of the first capacitor C1, even when the second NFET a2 is turned off, the high-level potential stored in the first capacitor C1 can still maintain the third NFET a3 on, That is, the latching of the signal is realized.

Of course, as another alternative implementation, as shown in Figure 4, the above-mentioned second NFET a2 can be a double-gate structure, that is, the second NFET a2 includes two gates (the first gate and the second gate ), and both gates of the second NFET a2 are connected to the control signal terminal CLK.

Similarly, in some possible implementation manners, the third NFET a3 can also be a double-gate structure, that is, the third NFET a3 includes two gates (a first gate and a second gate), and the third NFET a3 Both gates of are connected to the first node N1.

Figure 4 is only schematically illustrated by taking the second NFET a2 and the third NFET a3 as an example of a double-gate structure. In other possible implementation methods, one of the second NFET a2 and the third NFET a3 can be set One is a double gate structure and the other is a single gate structure. For example, the second NFET a2 has a double-gate structure (refer to FIG. 4 ), and the third NFET a3 has a single-gate structure (refer to FIG. 3 ). For another example, the second NFET a2 has a single-gate structure (refer to FIG. 3 ), and the third NFET a3 has a double-gate structure (refer to FIG. 4 ).

Figure 5 shows a latch-10 with a 3T (i.e. 3 NFET) structure; in this latch-10, the pull-up circuit PUN adopts the circuit structure of (d) in Figure 2, and the pull-down circuit PDN adopts the circuit structure of Figure 2 3 in the circuit structure. FIG. 6 is a simulation result of the latch one 10 of FIG. 5 . The working principle of the latch one 10 provided by the present application will be briefly and schematically described below with reference to FIG. 5 and FIG. 6 .

Referring to FIG. 5 and FIG. 6, when the clock signal input by the control signal terminal CLK is a high-level voltage, the second NFET a2 is turned on, and the high-level voltage (that is, logic “1”) input by the signal input terminal Input is transmitted to the third NFET a2. The gate of NFET a3, and the first capacitor C1 is charged, the third NFET a3 is turned on, and the low-level voltage of the second voltage terminal (GND) is output to the signal output terminal Output, so as to control the voltage of the signal output terminal Output pull-down, at this time the resistance of the pull-down circuit PDN is much smaller than the resistance of the pull-up circuit PUN. When the clock signal input by the control signal terminal CLK turns to a low-level voltage, the second NFET a2 is turned off, and the high-level voltage previously stored in the first capacitor C1 keeps the third NFET a3 turned on, and the second voltage terminal (GND ) is continuously output to the signal output terminal Output, which realizes the latching of the signal. When the clock signal input by the control signal terminal CLK is a high-level voltage, and the signal input terminal Input inputs a low-level voltage (that is, logic "0"), the second NFET a2 is turned on, and the third NFET a3 is turned off. At this time, the pull-down circuit PDN The resistance of the pull-up circuit PUN is much larger than that of the pull-up circuit PUN, and the high-level voltage of the first voltage terminal (V _DD ) is output to the signal output terminal Output through the first NFET a1, so as to pull up the voltage of the signal output terminal Output.

latch two

As shown in FIG. 7, the latch 2 20 includes: a pull-up circuit PUN, a pull-down circuit PDN, a signal input terminal Input, a signal output terminal Output, a control signal terminal CLK, a first voltage terminal (V _DD ), a second voltage terminal terminal (GND).

Referring to FIG. 7, in the second latch 20, the pull-down circuit PDN is connected to the signal output terminal Output and the second voltage terminal (GND). The pull-down circuit PDN is configured to: pull down the voltage of the signal output terminal Output according to the voltage of the second voltage terminal (GND).

Schematically, in some possible implementation manners, as shown in FIG. 7 and (a) of FIG. 8 , the above-mentioned pull-down circuit PDN may include a first resistor R1. One terminal of the first resistor R1 is connected to the second voltage terminal (GND), and the other terminal of the first resistor R1 is connected to the signal output terminal Output.

Schematically, in some possible implementation manners, as shown in (b) of FIG. 7 and FIG. 8 , the above-mentioned pull-down circuit PDN may include a first NFET a1. The first NFET a1 is a depletion NFET. Both the gate and the source of the first NFET a1 are connected to the second voltage terminal (GND), and the drain of the first NFET a1 is connected to the signal output terminal Output.

It can be understood here that, in the case where the first NFETa1 is a depletion-type NFET, the threshold voltage (V _th ) of the first NFETa1 is less than zero, so that in the circuit connection mode of (b) in FIG. 8 , it is possible to Ensure that the first NFET a1 remains on, so as to output the voltage of the second voltage terminal (GND) to the signal output terminal Output, and pull down the voltage of the signal output terminal Output.

Schematically, in some possible implementation manners, as shown in FIG. 7 and (c) in FIG. 8 , the above-mentioned pull-down circuit PDN may include a first NFET a1. The first NFETa1 is a depletion-type NFET, and the first NFETa1 includes a first gate g1 and a second gate g2, that is, the first NFET has a double-gate structure. The first gate g1, the second gate g2 and the source of the first NFETa1 are all connected to the second voltage terminal (GND), and the drain of the first NFETa1 is connected to the signal output terminal Output. In the case where the first NFET a1 is a depletion-type NFET, the threshold voltage (V _th ) of the first NFET a1 is less than zero, which can ensure that the first NFET a1 is always on, so that the voltage of the second voltage terminal (GND) The signal output terminal Output is output, and the voltage of the signal output terminal Output is pulled down. Among them, (c) in FIG. 8 is only schematically illustrated by taking the first gate g1 as the top gate and the second gate g2 as the back gate as an example. In other possible implementation methods, the first gate g1 may be a back gate, and the second gate g2 may be a top gate.

In addition, referring to FIG. 7 , in the second latch 20 , the pull-up circuit PUN is connected to the signal input terminal Input, the control signal terminal CLK, the first voltage terminal (V _DD ), and the signal output terminal Output. The pull-up circuit PUN is configured to pull up the voltage of the signal output terminal Output according to the voltage of the first voltage terminal (V _DD ) under the control of the signal control signal terminal CLK and the signal input terminal Input.

Schematically, in some possible implementation manners, as shown in FIG. 7 and FIG. 9 , the pull-up circuit PUN may include a second NFET a2, a third NFET a3, and a first capacitor C1. Wherein, the gate of the second NFET a2 is connected to the control signal terminal CLK, the source of the second NFET a2 is connected to the signal input terminal Input, and the drain of the second NFET a2 is connected to the first node N1. The gate of the third NFET a3 is connected to the first node N1, the source of the third NFET a3 is connected to the first voltage terminal (V _DD ), and the drain of the third NFET a3 is connected to the signal output terminal Output. A first pole of the first capacitor C1 is connected to the first node N1, and a second pole of the first capacitor C1 is connected to the second voltage terminal (GND). It should be pointed out that the first capacitor C1 may be composed of the gate capacitor of the third NFET a3, or a separately designed load capacitor, or a combination thereof.

In this case, by controlling the signal of the signal terminal CLK to control the opening and closing of the second NFET a2, the signal of the signal input terminal Input can be transmitted to the gate of the third NFET a3; and connected to the gate of the third NFET a3 The first capacitor C1 can store the signal of the signal input terminal Input. When the voltage input by the signal input terminal Input is a high-level voltage (that is, logic “1”), the third NFET a3 is turned on, and outputs the high-level voltage of the first voltage terminal (V _DD ) to the signal output terminal Output , to pull up the voltage of the signal output terminal Output; due to the existence of the first capacitor C1, even when the second NFET a2 is turned off, the high-level potential stored in the first capacitor C1 can still maintain the third NFET a3 to be turned on, That is, the latching of the signal is realized.

Of course, as another alternative implementation, as shown in Figure 10, the above-mentioned second NFET a2 can be a double-gate structure, that is, the second NFET a2 includes two gates (the first gate and the second gate ), the two gates of the second NFET a2 are connected to the control signal terminal CLK.

Similarly, in some possible implementations, as shown in FIG. 10, the third NFET a3 can also be a double-gate structure, that is, the third NFET a3 includes two gates (a first gate and a second gate) , both gates of the third NFET a3 are connected to the first node N1.

Figure 10 is only schematically illustrated by taking the second NFET a2 and the third NFET a3 as an example of a double-gate structure. In other possible implementation methods, one of the second NFET a2 and the third NFET a3 can be set One is a double gate structure and the other is a single gate structure. For example, the second NFET a2 has a double-gate structure (refer to FIG. 10 ), and the third NFET a3 has a single-gate structure (refer to FIG. 9 ). For another example, the second NFET a2 has a single-gate structure (refer to FIG. 9 ), and the third NFET a3 has a double-gate structure (refer to FIG. 10 ).

Figure 11 shows a latch two 20 with a 3T (i.e. 3 NFET) structure; in this latch two 20, the pull-up circuit PUN adopts the circuit structure of Figure 9, and the pull-down circuit PDN adopts the circuit structure of Figure 8 ( b) Circuit structure. The working principle of the latch 2 20 provided in the present application will be briefly described below with reference to FIG. 11 .

As shown in FIG. 11, when the clock signal input by the control signal terminal CLK is a high-level voltage (that is, logic "1"), the second NFET a2 is turned on, and the high-level voltage input by the signal input terminal Input is transmitted to the third NFET The gate of a3 charges the first capacitor C1, the third NFET a3 is turned on, and outputs the high-level voltage of the first voltage terminal (V _DD ) to the signal output terminal Output, so as to increase the voltage of the signal output terminal Output Pull; at this time, the resistance of the pull-up circuit PUN is much smaller than the resistance of the pull-down circuit PDN. When the clock signal input by the control signal terminal CLK turns to a low-level voltage, the second NFET a2 is turned off, and the high-level voltage previously stored in the first capacitor C1 keeps the third NFET a3 turned on, and the first voltage terminal (V _DD ) high-level voltage is continuously output to the signal output terminal Output. When the clock signal input by the control signal terminal CLK is a high-level voltage, and the signal input terminal Input inputs a low-level voltage (that is, logic "0"), the second NFET a2 is turned on, and the third NFET a3 is turned off; at this time, the pull-down circuit PDN The resistance of the pull-up circuit PUN is much smaller than the resistance of the pull-up circuit PUN, and the low-level voltage of the second voltage terminal (GND) is output to the signal output terminal Output through the first NFET a1, so as to pull down the voltage of the signal output terminal Output.

In the following, the flip-flop proposed in the embodiment of the present application will be described in combination with the foregoing latches (eg, 10 and 20 ).

As shown in FIG. 12 , the flip-flop F provided by the embodiment of the present application may include two latches (a first latch A1 and a second latch A2 ). Wherein, the first latch A1 may also be called a master latch, and the second latch A2 may also be called a slave latch. The two latches (A1, A2) can respectively use any one of the aforementioned latches (eg, 10, 20). Wherein, the signal output terminal Output of the first latch A1 is connected to the signal input terminal Input of the second latch A2 (corresponding to the S terminal in FIG. 12 ). The signal input terminal Input of the first latch A1 serves as the input terminal D of the flip-flop F, and the signal output terminal Output of the second latch A2 serves as the output terminal Q of the flip-flop F.

It should be noted that, in FIG. 12 , the first latch A1 and the second latch A2 both adopt the aforementioned latch one 10 as an example for schematic illustration, but the present application is not limited thereto. For example, in some possible implementation manners, both the first latch A1 and the second latch A2 may use the aforementioned latch two 20 . For another example, in some possible implementation manners, one of the first latch A1 and the second latch A2 may use the aforementioned latch one 10 , and the other may use the aforementioned latch two 20 .

In addition, it should be noted that the circuit structures of the first latch A1 and the second latch A2 may be completely the same or different; this application does not limit this. For example, as shown in Figure 12, in some possible implementations, the two latches-10 used by the flip-flop F may have the same circuit structure; for another example, in other possible implementations, the flip-flop F The two latches-10 employed can have different circuit configurations.

Fig. 13 is the simulation result of flip-flop F in Fig. 12; wherein, the signal input by the control signal terminal CLK1 of the first latch A1 in Fig. 12 is the CLK signal in Fig. 13, and the control signal of the second latch A2 The control signal input by terminal CLK2 is

signal; CLK signal and

The signal is a set of inverted clock signals.

As shown in Figure 12 and Figure 13, when the signal input to the control signal terminal CLK1 of the first latch A1 is a high level voltage, the control signal input to the control signal terminal CLK2 of the second latch A2 is a low level voltage Voltage (i.e. CLK=1,

); the input signal of the input terminal D of the flip-flop F is transmitted to the S terminal through the first latch A1. but due to

At this time, the output state of the second latch A2 has nothing to do with the output of the S terminal. When the signal input by the control signal terminal CLK1 of the first latch A1 becomes a low level voltage (that is, CLK=0,

), the output of the first latch A1 (that is, the S terminal) has nothing to do with the input of the input terminal D, and the output of the S terminal remains unchanged and is output to the output terminal Q through the second latch A2. Therefore, only when the CLK signal changes from a high-level voltage to a low-level voltage (that is, the negative CLK edge, that is, the falling edge of the clock signal), the signal at the input terminal D of the flip-flop F can be output to the output terminal Q, and also That is, the trigger implements falling edge triggering (that is, negative-edge-triggered FF).

Of course, in some other possible implementation ways, the input signals of the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2 can be exchanged, that is, the control signal of the second latch A2 The signal terminal CLK2 inputs the CLK signal in Figure 13, and the input of the control signal terminal CLK1 of the first latch A1

Signal. In this case, the flip-flop can realize rising edge triggering (that is, positive-edge-triggered FF), that is, only when the clock signal changes from a low potential to a high potential, the input signal of the input terminal D of the flip-flop F can be output to Output Q.

For a set of inverted clock signals input by the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2, in some possible implementations, an inverter can be used to convert CLK After inverting the signal, we get

signal to meet the signal requirements of the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2 in the above flip-flop.

In the present application, there is no limitation on the specific arrangement form of the above-mentioned inverters. For example, in some possible implementation manners, an inverter formed by NFETs may be used, so that the inverter and the flip-flop may be manufactured using the same manufacturing process. As another example, in some possible implementation manners, a CMOS inverter may be used; in practice, the setting may be selected as required.

It can be understood that, compared with about 18 transistors in a traditional flip-flop using a CMOS process, the flip-flop provided in the embodiment of the present application has only 6 NFETs (ie, a 6T structure); in some embodiments In the case where the flip-flop uses an inverter with 2 transistors (FET), the number of transistors is only 8 (that is, the 8T structure), that is, the flip-flop provided by the embodiment of the present application can greatly reduce the number of transistors.

It should be noted that the application of the latch provided in the embodiment of the present application is not limited to the above-mentioned flip-flops. According to actual needs, the latch provided in the embodiment of the present application can also be applied in other logic function devices.

The embodiment of the present application also provides a chip, and the logic function devices in the digital logic circuit in the chip can use the aforementioned flip-flops and/or latches.

In some chips, the flip-flop will occupy 50% of the area of the entire digital logic circuit. In this case, when the flip-flop provided by the embodiment of the present application is used, the area cost of the chip can be greatly reduced, which is more beneficial to the chip. Miniaturization and performance improvements.

In addition, for the fabrication of the flip-flop and/or the latch provided in the embodiment of the present application, in some possible implementation manners, the NFET in the flip-flop and/or the latch provided in the embodiment of the present application can use N Type oxide semiconductor (oxide semiconductor, OS) field effect transistor, that is, the channel layer of NFET adopts oxide semiconductor material. In other possible implementations, the flip-flop and/or the NFET in the latch provided by the embodiment of the present application can be made by low temperature polycrystalline silicon (LTPS), that is, the channel layer of the NFET is made of polysilicon material .

Taking the production of chips as an example, since the backend of line (BEOL) of the chip cannot meet the high-temperature production of CMOS technology, the digital logic circuit cannot be compatible with the backend process, which in turn makes the chip require three-dimensional monomer stacking technology. However, LTPS technology has problems such as complex process, high cost, large fluctuations in device electrical characteristics, and poor uniformity, which makes it difficult to meet the requirements of circuit design and large-scale integration. In contrast, NFETs in flip-flops and/or latches provided by the embodiments of the present application may use N-type oxide semiconductor field effect transistors, so as to meet the manufacturing temperature conditions of chips in subsequent processes. Based on this, in some possible implementation methods, the logic function devices of the above-mentioned flip-flops and/or latches can be integrated into the subsequent process of the chip, so as to meet the requirements of the chip for three-dimensional cell stacking technology and reduce the The area of the chip reduces the power consumption of the chip and improves the performance of the chip.

Schematically, as shown in FIG. 14 , an embodiment of the present application provides a chip, which includes a substrate 100 , and a first device layer 101 and a second device layer 102 disposed on the substrate 100 . Wherein, the second device layer 102 is located on a side of the first device layer 101 away from the substrate 100 , and the first device layer 101 and the second device layer 102 are electrically connected. Schematically, the first device layer 201 and the second device layer 202 may be electrically connected through metal micro-vias.

CMOS transistors (Complementary Metal Oxide Semiconductor Field Effect Transistors) are disposed in the first device layer 101 . The digital logic circuit in the chip includes the flip-flop and/or the latch provided by the foregoing embodiment, and the NFETs in the flip-flop and/or the latch all adopt N-type oxide semiconductor field-effect transistors, and are distributed in the second device layer 202 .

In this case, the first device layer 101 can be fabricated by CMOS technology in the front end of line (FEOL), and then the second device layer 102 can be fabricated in the back process (BEOL); to realize the digital logic circuit Compatible with the subsequent process, so as to meet the requirements of the chip for the three-dimensional single stacking technology.

In addition, the embodiment of the present application also provides an electronic device, the electronic device includes a printed circuit board (printed circuit board, PCB) and the aforementioned chip; the chip is electrically connected to the PCB.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A latch, characterized in that it includes a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit and a pull-down circuit;

The transistors in the latch all adopt N-type field effect transistor NFET;

The pull-up circuit is connected to the first voltage terminal and the signal output terminal; the pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal;

The pull-down circuit is connected to the signal input end, the control signal end, the signal output end, and the second voltage end; the pull-down circuit is configured to: Under the control of the signal at the input terminal, the voltage at the signal output terminal is pulled down according to the voltage at the second voltage terminal.
The latch of claim 1, wherein

The pull-up circuit includes a first resistor; one end of the first resistor is connected to the first voltage end, and the other end of the first resistor is connected to the signal output end;

Alternatively, the pull-up circuit includes a first NFET; the first NFET is a depletion NFET; the first pole of the first NFET is connected to the first voltage terminal, and the gate of the first NFET is connected to the first voltage terminal. The second poles are all connected to the signal output terminals;

Or, the pull-up circuit includes a first NFET; the first NFET is an enhanced NFET; the first electrode and the gate of the first NFET are connected to the first voltage terminal, and the second NFET of the first NFET The pole is connected to the signal output terminal;

Alternatively, the pull-up circuit includes a first NFET; the first NFET includes a first gate and a second gate; the first gate and the first pole of the first NFET are connected to the first voltage terminal , both the second gate and the second pole of the first NFET are connected to the signal output terminal.
A latch according to claim 1 or 2, characterized in that

The pull-down circuit includes a second NFET, a third NFET and a first capacitor;

The first gate of the second NFET is connected to the control signal terminal, the first pole of the second NFET is connected to the signal input terminal, and the second pole of the second NFET is connected to the first node;

The first gate of the third NFET is connected to the first node, the first pole of the third NFET is connected to the signal output terminal, and the second pole of the third NFET is connected to the second voltage terminal connection;

A first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to the second voltage terminal.
The latch of claim 3, wherein

The second NFET also includes a second gate; the second gate of the second NFET is connected to the control signal terminal.
A latch according to claim 3 or 4, characterized in that

The third NFET further includes a second gate; the second gate of the third NFET is connected to the first node.
A latch, characterized in that it includes a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit and a pull-down circuit;

The transistors in the latch all adopt NFET;

The pull-up circuit is connected to the signal input terminal, the signal control terminal, the first voltage terminal, and the signal output terminal; the pull-up circuit is configured to connect the control signal terminal and the signal Under the control of the signal at the input terminal, pull up the voltage at the signal output terminal according to the voltage at the first voltage terminal;

The pull-down circuit is connected to the signal output terminal and the second voltage terminal; the pull-down circuit is configured to: pull down the voltage of the signal output terminal according to the voltage of the second voltage terminal.
The latch of claim 6, wherein

The pull-down circuit includes a first resistor; one end of the first resistor is connected to the second voltage end, and the other end of the first resistor is connected to the signal output end;

Alternatively, the pull-down circuit includes a first NFET; the first NFET is a depletion NFET; the gate and the first pole of the first NFET are connected to the second voltage terminal, and the first NFET of the first NFET The two poles are connected to the signal output terminal;

Or, the pull-down circuit includes a first NFET; the first NFET is a depletion NFET; the first NFET includes a first gate and a second gate; the first gate of the first NFET, the second gate Both poles and the first pole are connected to the second voltage terminal, and the second pole of the first NFET is connected to the signal output terminal.
A latch according to claim 6 or 7, characterized in that

The pull-up circuit includes a second NFET, a third NFET and a first capacitor;

The first gate of the second NFET is connected to the control signal terminal, the first pole of the second NFET is connected to the signal input terminal, and the second pole of the second NFET is connected to the first node;

The first gate of the third NFET is connected to the first node, the first pole of the third NFET is connected to the first voltage terminal, and the second pole of the third NFET is connected to the signal output terminal connection;

A first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to the second voltage terminal.
The latch of claim 8, wherein

The second NFET also includes a second gate; the second gate of the second NFET is connected to the control signal terminal.
A latch according to claim 8 or 9, characterized in that

The third NFET further includes a second gate; the second gate of the third NFET is connected to the first node.
A flip-flop, characterized in that it includes a first latch and a second latch; the first latch and the second latch are all adopted as described in any one of claims 1-10 Latches;

The signal output end of the first latch is connected to the signal input end of the second latch.
A chip, characterized in that it includes a digital logic circuit;

The digital logic circuit includes the latch according to any one of claims 1-10.
The chip according to claim 12, wherein the latch is integrated in a subsequent process.
An electronic device, characterized by comprising a printed circuit board and the chip according to claim 12 or 13; the chip is electrically connected to the printed circuit board.