CN214122808U

CN214122808U - Negative voltage generating circuit and chip

Info

Publication number: CN214122808U
Application number: CN202022809542.7U
Authority: CN
Inventors: 蒋新喜; 程珍娟; 孙天奇; 张靖恺
Original assignee: Inferpoint Systems Shenzhen Ltd
Current assignee: Inferpoint Systems Shenzhen Ltd
Priority date: 2020-11-27
Filing date: 2020-11-27
Publication date: 2021-09-03
Anticipated expiration: 2030-11-27
Also published as: TWM618930U

Abstract

The utility model discloses a negative pressure produces circuit and chip, the negative pressure produces the circuit and includes: a first capacitor, one polar plate of which is connected with a first node, wherein the first node is used for outputting a first voltage signal; the other polar plate is connected with a second node, and the second node is used for outputting a second voltage signal; a first switch connecting a port to which an external power supply voltage is input and the first node; a second switch through which the first node is grounded; a third switch through which the second node is grounded; wherein the first switch, the second switch, and the third switch periodically switch the second voltage signal between a preset negative voltage signal equal to a negative value of the external power voltage based on a switch control signal. The negative voltage generating circuit is simple in circuit structure and high in response speed. And the first voltage signal can also be used as a power supply voltage of the circuit module.

Description

Negative voltage generating circuit and chip

Technical Field

The utility model relates to an integrated circuit technical field, more specifically the utility model relates to a negative pressure produces circuit and chip.

Background

With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The core of the electronic device for realizing various functions is various circuit systems, and some circuit systems need to be connected with a floating ground voltage signal based on the functions required to be realized, and the floating ground voltage signal is switched between 0V and a preset negative voltage.

In the prior art, a negative voltage charge pump is generally adopted to generate a floating ground voltage signal switched between 0V and a preset negative voltage, and the negative voltage charge pump has a complex structure and a slow response speed.

SUMMERY OF THE UTILITY MODEL

In view of this, the present application provides a negative voltage generating circuit and a chip, and the scheme is as follows:

a negative voltage generating circuit, comprising:

a first capacitor, one polar plate of which is connected with a first node, wherein the first node is used for outputting a first voltage signal; the other polar plate is connected with a second node, and the second node is used for outputting a second voltage signal;

a first switch connecting a port to which an external power supply voltage is input and the first node;

a second switch through which the first node is grounded;

a third switch through which the second node is grounded;

wherein the first switch, the second switch, and the third switch periodically switch the second voltage signal between 0V and a preset negative voltage signal based on a switch control signal, the preset negative voltage signal being equal to a negative value of the external power voltage.

Preferably, in the negative voltage generating circuit, the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor;

the grid electrode of the first transistor is connected with a first switch control signal, the source electrode of the first transistor is connected with the external power supply voltage, and the drain electrode of the first transistor is connected with the first node;

the grid electrode of the second transistor is connected with a second switch control signal, the drain electrode of the second transistor is connected with the first node, and the source electrode of the second transistor is grounded;

and the grid electrode of the third transistor is connected with a third switch control signal, the source electrode of the third transistor is connected with the second node, and the drain electrode of the third transistor is grounded.

Preferably, in the negative voltage generating circuit, the first transistor is a PMOS, and the second transistor and the third transistor are both NMOS.

Preferably, in the negative voltage generating circuit, the first transistor, the second transistor, and the third transistor are each connected to a logic controller for generating the switching control signal;

the logic controller is used for inputting a first switch control signal to the grid electrode of the first transistor, inputting a second switch control signal to the grid electrode of the second transistor and inputting a third switch control signal to the grid electrode of the third transistor;

wherein the first transistor and the second transistor are not turned on at the same time, and the second transistor and the third transistor are not turned on at the same time.

Preferably, in the negative voltage generating circuit, the logic controller includes:

a first output module for outputting a second signal and the third switch control signal based on an input first signal;

a second output module for outputting the first switch control signal and the second switch control signal based on the second signal;

the logic controller has an input terminal for inputting the first signal, a first output terminal for outputting the first switch control signal, a second output terminal for outputting the second switch control signal, and a third output terminal for outputting the third switch control signal.

Preferably, in the negative voltage generating circuit, the first output module includes: the circuit comprises a first buffer, a first AND gate, a level shifter, a first inverter, a second inverter and a first OR gate; the first AND gate is an AND gate with three input ends;

the input end of the first buffer is connected with the input end of the logic controller;

one input end of the first AND gate is connected with the output end of the first buffer, the other two input ends of the first AND gate are respectively connected with the third node and the output end of the first phase inverter, and the output end of the first AND gate is connected with the input end of the level shifter;

the input end of the first inverter is connected with the third output end of the logic controller;

one input end of the first OR gate is connected with the third node, the other input end of the first OR gate is connected with the output end of the first buffer, and the output end of the first OR gate is connected with the input end of the second inverter;

the output end of the second inverter is connected with the third output end of the logic controller;

and the output end of the level shifter is connected with a fourth node and is used for outputting the second signal.

Preferably, in the negative voltage generating circuit, the second output module includes: a second OR gate, a second AND gate, a second buffer and a third buffer; the second AND gate is an AND gate with two input ends;

one input end of the second OR gate is connected with the fourth node, the other input end of the second OR gate is connected with the second output end of the logic controller, and the output end of the second OR gate is connected with the input end of the second buffer;

the output end of the second buffer is connected with the first output end of the logic controller;

one input end of the second AND gate is connected with the fourth node, the other input end of the second AND gate is connected with the first output end of the logic controller, and the output end of the second AND gate is connected with the input end of the third buffer;

and the output end of the third buffer is connected with the second output end of the logic controller.

Preferably, in the negative voltage generating circuit, a voltage detecting module is connected between the first output module and the second output module, and the voltage detecting module is configured to output a fourth signal based on an input third signal and the input second signal;

the second output module outputs the first switch control signal and the second switch control signal based on the input fourth signal.

Preferably, in the negative voltage generating circuit, the voltage detecting module includes: the first inverter, the second inverter, the NOR gate, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor and the third AND gate;

the input end of the third inverter is used for inputting the third signal, and the output end of the third inverter is connected with one input end of the NOR gate;

the other input end of the NOR gate is connected with the fifth node, and the output end of the NOR gate is connected with the sixth node;

one input end of the third and gate inputs the second signal, the other input end of the third and gate is connected with the sixth node, and the output end of the third and gate is used for outputting the fourth signal;

the input end of the fourth inverter is used for inputting the second signal, and the output end of the fourth inverter is connected with the grid electrode of the fourth transistor;

the source electrode of the fourth transistor is connected with the fifth node, the drain electrode of the fourth transistor is connected with the drain electrode of the fifth transistor, and the substrate of the fourth transistor is connected with the source electrode;

the grid electrode of the fifth transistor is input with the first voltage signal, the source electrode of the fifth transistor is input with the second voltage signal, and the substrate of the fifth transistor is connected with the source electrode;

a gate of the sixth transistor is connected to the sixth node, a source thereof is supplied with the external power supply voltage, a drain thereof is connected to the fifth node, and a substrate thereof is connected to the source;

the seventh transistor has a gate connected to the sixth node, a drain connected to the fifth node, a source connected to ground, and a substrate connected to the source.

Preferably, in the negative voltage generating circuit, the fourth transistor and the sixth transistor are both PMOS, and the fifth transistor and the seventh transistor are both NMOS.

Preferably, in the negative voltage generating circuit, the negative voltage generating circuit is used for supplying power to the circuit module;

the first voltage signal is used as a power supply voltage of the circuit module, and the second voltage signal is used as a floating ground voltage signal of the circuit module.

Preferably, in the negative voltage generating circuit, the negative voltage generating circuit and the circuit module are integrated on the same chip, or are integrated on different chips.

The utility model also provides a chip, including above-mentioned arbitrary negative pressure produce the circuit.

According to the above description, the present invention provides a negative voltage generating circuit and a chip, wherein the negative voltage generating circuit comprises: a first capacitor, one polar plate of which is connected with a first node, wherein the first node is used for outputting a first voltage signal; the other polar plate is connected with a second node, and the second node is used for outputting a second voltage signal; a first switch connecting a port to which an external power supply voltage is input and the first node; a second switch through which the first node is grounded; a third switch through which the second node is grounded; wherein the first switch, the second switch, and the third switch periodically switch the second voltage signal between a preset negative voltage signal equal to a negative value of the external power voltage based on a switch control signal. The utility model discloses technical scheme provides three switch and an electric capacity can realize the voltage with predetermine the second voltage signal of periodic switching between the negative pressure signal, circuit structure is simple, and response speed is fast. And the first voltage signal can also be used as a power supply voltage of the circuit module.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structure, ratio, size and the like shown in the drawings of the present specification are only used for matching with the content disclosed in the specification, so as to be known and read by people familiar with the technology, and are not used for limiting the limit conditions which can be implemented by the present invention, so that the present invention does not have the substantial significance in the technology, and any structure modification, ratio relationship change or size adjustment should still fall within the scope which can be covered by the technical content disclosed by the present invention without affecting the efficacy which can be produced by the present invention and the achievable purpose.

FIG. 1 is a schematic diagram of a conventional negative voltage generating circuit;

FIG. 2 is a circuit diagram of a conventional negative voltage charge pump;

fig. 3 is a circuit diagram of a negative voltage generating circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating the on state of a switch and the current flow path in the circuit of FIG. 3;

FIG. 5 is a schematic diagram of the conducting state of another switch and the current flow path in the circuit of FIG. 3;

fig. 6 is a schematic diagram of a specific implementation of the negative voltage generating circuit according to an embodiment of the present invention;

fig. 7 is a circuit block diagram of a system having a negative pressure generating circuit according to an embodiment of the present invention;

fig. 8 is a timing diagram of a switch control signal according to an embodiment of the present invention;

fig. 9 is a circuit diagram of a logic controller according to an embodiment of the present invention;

FIG. 10 is a timing diagram of the voltages at the nodes of the circuit of FIG. 9;

fig. 11 is a circuit diagram of another logic controller according to an embodiment of the present invention;

fig. 12 is a circuit diagram of a voltage detection module according to an embodiment of the present invention.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1, fig. 1 is a schematic diagram of a conventional negative voltage generating circuit, and the circuit shown in fig. 1 includes: switch K11, switch K12, switch K13, capacitor C11 and negative charge pump. Two plates of the capacitor C11 are respectively connected to a node N11 and a node N12, a switch K11 is connected to a port of the external power SUPPLY voltage VDD _ SUPPLY and a node N11, a switch K13 is connected to a ground terminal GND (0 potential) and a node N12, and a switch K12 is connected to the negative charge pump and the node N12. Wherein the node N11 can provide the power supply voltage VDD for the circuit block, and the node N12 can provide the floating ground voltage VSS for the circuit block. The floating ground voltage signal VSS can be switched between the negative voltage OUT and 0V supplied from the negative charge pump based on the conductive states of the three switches.

When the switch K11 and the switch K13 are closed and the switch K12 is open, the voltage of the node N11 is the external power SUPPLY voltage VDD _ SUPPLY, and at this time VDD _ SUPPLY, the circuit module is powered by the external power SUPPLY voltage VDD _ SUPPLY. At the same time, the external power SUPPLY voltage VDD _ SUPPLY charges the capacitor C11. When the switch K11 and the switch K13 are turned off and the switch K12 is turned on, the node N12 and the negative charge pump are turned on, VSS is OUT, and the circuit module is discharged from the capacitor C11 to supply current.

In order to realize the negative voltage OUT required by the floating ground voltage signal VSS, a negative voltage charge pump is generally required in the conventional technology, but the negative voltage charge pump needs four MOS switches with larger sizes, and two capacitors are also required to be respectively used as a pump capacitor and an output voltage stabilizing capacitor, so that the number of off-chip devices is large, the area of an on-chip capacitor is large, the control logic is complex, the power consumption is large, the circuit of the negative voltage charge pump needs starting time, and the response speed of a system is slow. The structure of the negative pressure charge pump is shown in fig. 2.

As shown in fig. 2, fig. 2 is a circuit diagram of a conventional negative voltage charge pump, which includes: the switch K14-switch K17, the capacitor C12 and the capacitor C13, two pole plates of the capacitor C13 are respectively connected with a node N13 and a node N14, the switch K14 is connected with a ground terminal GND and a node N13, the switch K15 is connected with a port of inputting an external power SUPPLY voltage VDD _ SUPPLY and the node N13, the switch K16 is connected with an output terminal VOUT and the node N14, the switch K17 is connected with the node N14 and the ground terminal GND, two pole plates of the capacitor C12 are respectively connected with the output terminal VOUT and the ground terminal GND, and the output terminal VOUT outputs negative voltage OUT.

The negative charge pump shown in fig. 2 requires four switches and two capacitors, and thus requires a larger area and a larger logic control current for the load. Meanwhile, when the negative voltage pump is started, the capacitor C12 and the capacitor C13 need to be charged, and the starting time is related to the size of the two capacitors and the starting current, so that the charging of the two capacitors influences the response speed.

As can be seen from the above description, the conventional negative voltage generation circuit needs to use a negative voltage charge pump, and has many circuit devices, a large area, a complicated circuit structure and control method, and strict design for the types of the devices and the substrate potential selection of the switch.

In order to solve the problem, the embodiment of the utility model provides a negative pressure produces circuit, circuit structure is simple, and control is simple, the low power dissipation, and response speed is fast, and off-chip device is few, and the circuit layout area is little, the good reliability.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

As shown in fig. 3, fig. 3 is a circuit diagram of a negative voltage generating circuit according to an embodiment of the present invention, the negative voltage generating circuit includes:

a first capacitor C1, one plate of the first capacitor C1 being connected to a first node N1, the first node N1 being for outputting a first voltage signal VDD; the other polar plate is connected with a second node N2, and the second node N2 is used for outputting a second voltage signal VSS;

a first switch K1, the first switch K1 connecting a port of an input external power SUPPLY voltage VDD _ SUPPLY with the first node N1;

a second switch K2, the first node N1 being connected to ground through the second switch K2;

a third switch K3, wherein the second node N2 is grounded through the third switch K3, that is, the second node N2 is connected to a ground terminal GND through the third switch K3;

wherein the first switch K1, the second switch K2, and the third switch K3 cause the second voltage signal VSS to be periodically switched between 0V and a preset negative voltage signal equal to a negative value of the external power SUPPLY voltage VDD _ SUPPLY based on a switch control signal. Specifically, the voltage of the second node N2 can be switched between GND (0V) and-VDD _ SUPPLY by controlling the on states of three switches by the switch control signal, and the second node N2 can be connected to the ground GND through the third switch K3. The embodiment of the utility model provides an in earthing terminal GND be the ground connection of system.

When the first switch K1 and the third switch K3 are turned on and the second switch K2 is turned off, the first node N1 is connected to the port to which the external power voltage VDD _ SUPPLY is input, and the second node N2 is connected to the ground GND, that is, VSS is 0V. The respective switch states are shown in fig. 4.

As shown in fig. 4, fig. 4 is a schematic diagram illustrating a switch conducting state and a current flowing path in the circuit shown in fig. 3, at this time, the external power voltage VDD _ SUPPLY supplies current to the circuit module through the conducting first switch K1, and can charge the first capacitor C1. The dashed arrows indicate the path and direction of current flow.

When the second switch K2 is closed and the first switch K1 and the third switch K3 are open, the first node N1 is connected to the ground GND through the second switch K2 which is turned on, and the second node N2 is disconnected from the ground GND, and the respective switch states are as shown in fig. 5.

As shown in fig. 5, fig. 5 is a schematic diagram of another switch conducting state and a current flowing path in the circuit shown in fig. 3, and dotted arrows indicate the current flowing path and direction. Based on the principle that the voltage across the first capacitor C1 cannot suddenly change, there is the following relationship:

V_C1＝VDD_SUPPLY-0＝0-VSS

VSS＝-VDD_SUPPLY

therefore, the second voltage signal VSS becomes a negative value of the external power voltage VDD _ SUPPLY, and the negative voltage function can be realized by a simple circuit and a switch control method.

The voltage across the first capacitor C1 changes:

wherein, I is the discharging current of the first capacitor C1, and t is the negative working time of VSS. Based on I and t and the magnitude of the first capacitor C1, the voltage change Δ V across the first capacitor C1 can be calculated_C1。

The second voltage signal VSS can be periodically changed between-VDD _ SUPPLY and 0V by periodically controlling the conduction state of the switch, the current I and the period time t are well controlled, the preset first capacitor C1 is selected, the current can be supplied by the first capacitor C1, and the voltage change delta V of the two poles of the capacitor can be satisfied_C1The work of the circuit module in the chip is not influenced.

The embodiment of the utility model provides a circuit module that negative pressure production circuit used can be the circuit module in the fingerprint identification chip. The first voltage signal VDD can be used as a power supply for the internal circuit module of the chip, the second voltage signal VSS can be used as an internal floating ground signal of the chip, the ground GND is a system ground of 0V, and the first capacitor C1 is an off-chip capacitor. Obviously, the embodiment of the utility model provides a negative pressure produces circuit is not restricted to the circuit module who is arranged in the fingerprint identification chip, also can be for the circuit module of other any needs superficial ground voltage signal, the embodiment of the utility model provides a do not specifically limit to its use scene.

The embodiment of the utility model provides a negative pressure produces the circuit, through electric capacity of three switch, can realize at 0V and predetermine the second voltage signal VSS that the periodicity switched between the negative pressure signal, circuit structure is simple, and control is simple. And the negative pressure generating circuit does not need a negative pressure charge pump, avoids the starting time required by adopting the negative pressure charge pump, has high system response speed and low power consumption, does not need additional capacitor, does not occupy the area of a layout, does not increase off-chip devices and has low cost.

As shown in fig. 6, fig. 6 is a specific implementation diagram of the negative voltage generating circuit according to the embodiment of the present invention, and based on the manner shown in fig. 3, the first switch K1 is a first transistor MP, the second switch K2 is a second transistor MN1, and the third switch K3 is a third transistor MN 2. As is readily known, a transistor has a gate, a source, and a drain, the transistor serves as a switching element, the gate serves as a control terminal, and the gate and the source can be equivalently replaced. In the present application, the substrate potential of the transistor is selected to ensure that the PN junction cannot be forward biased.

The gate of the first transistor MP is connected to the first switch control signal TX1_ P, the source is connected to the external power voltage VDD _ SUPPLY, the drain is connected to the first node, and the substrate is connected to the source. The gate of the second transistor MN1 is connected to a second switch control signal TX1_ N, the drain is connected to the first node N1, the source is grounded, i.e., the source is connected to the ground GND, and the substrate is connected to the source. The gate of the third transistor MN2 is connected to a third switch control signal TX2, the source is connected to the second node N2, the drain is grounded, i.e., the drain is connected to the ground GND, and the substrate is connected to the source.

In the mode shown in fig. 6, all three switches in the negative voltage generating circuit are easily realized by MOS. The first voltage signal VDD is switched between VDD _ SUPPLY and 0V through the first transistor MP and the second transistor MN1, and the second voltage signal VSS is connected to or disconnected from the ground GND through the third transistor MN 2. According to the voltage ranges of the first voltage signal VDD and the second voltage signal VSS, the first transistor MP is selected to be PMOS, and the second transistor MN1 and the third transistor MN2 are both NMOS. The substrates of the PMOS and the NMOS are connected with the respective sources. The three switches can be designed to be NMOS or PMOS based on the requirement, and are not limited to the method shown in fig. 6.

Through the current trend, the first transistor MP and the third transistor MN2 will draw the current of the circuit module, and in order to reduce the voltage drop (IR drop), the sizes of the first transistor MP and the third transistor MN2 need to be designed to be appropriately large according to the system requirements, so as to meet the voltage drop requirements of the system. The second transistor MN1 does not need to flow the circuit module working current, so it does not need to be designed to be too large, and it avoids occupying a large layout area. The size of the second transistor MN1 is smaller than the size of the first transistor MP and the third transistor MN 2.

As shown in fig. 7, fig. 7 is a system circuit block diagram of the negative voltage generating circuit according to the embodiment of the present invention, and referring to fig. 3, fig. 6 and fig. 7, the first transistor MP, the second transistor MN1 and the third transistor MN2 are respectively connected to a logic controller, and the logic controller is configured to generate the switch control signal. The logic controller is configured to input a first switch control signal TX1_ P to the gate of the first transistor MP, to input a second switch control signal TX1_ N to the gate of the second transistor MN1, and to input a third switch control signal TX2 to the gate of the third transistor MN 2.

In order to avoid a path from the external power voltage VDD _ SUPPLY to the ground GND and a path from the two plates of the first capacitor C1 to be directly short-circuited in the switching process, the first transistor MP and the second transistor MN1 are not turned on simultaneously, and the second transistor MN1 and the third transistor MN2 are not turned on simultaneously.

As shown in fig. 8, fig. 8 is a timing diagram of a switch control signal according to an embodiment of the present invention, in which a first switch control signal TX1_ P is used as a gate control voltage of the first transistor MP, a second switch control signal TX1_ N is used as a gate control voltage of the second transistor MN1, and a third switch control signal TX2 is used as a gate control voltage of the third transistor MN 2.

As shown in fig. 9, fig. 9 is a circuit diagram of a logic controller according to an embodiment of the present invention, where the logic controller includes: a first output module 21, the first output module 21 being configured to output a second signal TX1_ IN _ LS and the third switch control signal TX2 based on an input first signal TX; a second output module 22 for outputting the first switch control signal TX1_ P and the second switch control signal TX1_ N based on the second signal TX1_ IN _ LS.

Wherein the logic controller has an input terminal for inputting the first signal TX, a first output terminal for outputting the first switch control signal TX1_ P, a second output terminal for outputting the second switch control signal TX1_ N, and a third output terminal for outputting the third switch control signal TX 2.

As shown in fig. 9, the first output module 21 includes: a first buffer BUF1, a first AND gate AND1, a level shifter LS, a first inverter ISLN1, a second inverter ISLN2, a first OR gate OR 1; the first AND gate AND1 is an AND gate with three input terminals.

Wherein, the input terminal of the first buffer BUF1 is connected to the input terminal of the logic controller to input the first signal TX, and the output terminal thereof outputs a signal TX _ D. One input end of the first AND gate AND1 is connected to the output end of the first buffer BUF1, the other two input ends thereof are respectively connected to the third node N3 AND the output end of the first inverter ISLN1, AND the output end thereof is connected to the input end of the level shifter LS. An input end of the first inverter ISLN1 is connected to a third output end of the logic controller. One input terminal of the first OR gate OR1 is connected to the third node N3, the other input terminal is connected to the output terminal of the first buffer BUF1, and the output terminal is connected to the input terminal of the second inverter ISLN 2. An output terminal of the second inverter ISLN2 is connected to a third output terminal of the logic controller. An output terminal of the level shifter LS is connected to a fourth node N4 for outputting the second signal TX1_ IN _ LS.

As shown in fig. 9, the second output module 22 includes: a second OR gate OR2, a second AND gate AND2, a second buffer BUF2, AND a third buffer BUF 3; the second AND gate AND2 is an AND gate with two input ends.

Wherein, one input end of the second OR gate OR2 is connected to the fourth node N4, the other input end is connected to the second output end of the logic controller, and the output end is connected to the input end of the second buffer BUF 2. An output terminal of the second buffer BUF2 is connected to a first output terminal of the logic controller. One input end of the second AND gate AND2 is connected to the fourth node N4, the other input end is connected to the first output end of the logic controller, AND the output end is connected to the input end of the third buffer BUF 3. An output terminal of the third buffer BUF3 is connected to a second output terminal of the logic controller.

Based on the logic controller shown in FIG. 9, it is possible to generate a floating ground voltage signal that controls the circuit shown in FIG. 6 to periodically switch VSS between 0V and-VDD _ SUPPLY, as shown in the timing diagram of FIG. 8. The logic controller is controlled by a first signal TX, which may be provided by a digital logic circuit, and is a square wave signal with a period T and a duty cycle of 50%. It should be noted that the duty ratio of the square wave signal in the present application may be limited based on the requirement, and is not limited to 50%.

As shown in fig. 10, fig. 10 is a voltage timing diagram of each node in the circuit shown in fig. 9, which can generate logic control signals required by the system, thereby preventing the first transistor MP and the second transistor MN1 from being turned on simultaneously, and preventing the second transistor MN1 and the third transistor MN2 from being turned on simultaneously. The second voltage signal VSS is periodically switched between 0V and-VDD _ SUPPLY.

The negative voltage required by the second voltage signal VSS is realized through the logic controller and the voltage timing, through a simple circuit structure and control logic, compared to the conventional negative voltage charge pump circuit,

the circuit has simple structure, saves the layout area, reduces the circuit power consumption, reduces the system response time, and has extremely simple circuit.

As shown IN fig. 11, fig. 11 is a circuit diagram of another logic controller according to an embodiment of the present invention, based on the mode shown IN fig. 9, IN the mode shown IN fig. 11, a voltage detection module is connected between the first output module 21 and the second output module 22, and the voltage detection module is configured to output a fourth signal TX1 based on an input third signal POR _ IN and the input second signal TX1_ IN _ LS. The second output module 22 outputs the first switch control signal TX1_ P and the second switch control signal TX1_ N based on the fourth signal TX1 being input.

As shown in fig. 12, fig. 12 is a circuit diagram of a voltage detection module according to an embodiment of the present invention, the voltage detection module includes: a third inverter ISLN3, a fourth inverter ISLN4, a NOR gate NOR, a fourth transistor MP41, a fifth transistor MN51, a sixth transistor MP62, a seventh transistor MN72, AND a third AND gate AND 3. Wherein the fourth transistor MP41 and the sixth transistor MP62 are both PMOS, and the fifth transistor MN51 and the seventh transistor MN72 are both NMOS.

The input terminal of the third inverter ISLN3 is used for inputting the third signal POR _ IN, and the output terminal thereof is connected to one input terminal of the NOR gate NOR. The NOR gate NOR has another input terminal connected to the fifth node N5 and an output terminal connected to the sixth node N6. An input terminal of the third AND gate AND3 inputs the second signal TX1_ IN _ LS, AND another input terminal thereof is connected to the sixth node N6, AND an output terminal thereof is configured to output the fourth signal TX 1. An input end of the fourth inverter ISLN4 is used for inputting the second signal TX1_ IN _ LS, and an output end thereof is connected to a gate of the fourth transistor MP 41.

The source of the fourth transistor MP41 is connected to the fifth node N5, the drain thereof is connected to the drain of the fifth transistor MN51, and the substrate thereof is connected to the source. The gate of the fifth transistor MN51 receives the first voltage signal VDD, the source thereof receives the second voltage signal VSS, and the substrate thereof is connected to the source. The sixth transistor MP62 has a gate connected to the sixth node N6, a source to which the external power SUPPLY voltage VDD _ SUPPLY is input, a drain connected to the fifth node N5, and a substrate connected to a source. The gate of the seventh transistor MN72 is connected to the sixth node N6, the drain thereof is connected to the fifth node N5, the source thereof is grounded GND, and the substrate thereof is connected to the source.

Through the voltage detection module shown in fig. 12, when the external power SUPPLY voltage VDD _ SUPPLY is powered on, the inside of the circuit module can be normally powered on through the first voltage signal VDD, and the circuit structure of the voltage detection module is simple.

As shown IN fig. 6, 11 and 12, the third signal POR _ IN is a reset release signal for detecting the external power voltage VDD _ SUPPLY, when the third signal POR _ IN is powered on, the third signal POR _ IN is at a low level, the sixth transistor MP62 is turned on, the drain voltage of the fourth transistor MP41 is VDD _ SUPPLY, TX1_ IN and TX are at a low level, TX1 is at a low level, TX2 is at a high level, the first transistor MP and the third transistor MN2 are turned on, the first node N1 is connected to the external power voltage VDD _ SUPPLY, the second node N2 is connected to the ground GND, the first voltage signal VDD starts to rise, when the first voltage VDD signal VDD rises to a sufficiently high level, the fifth transistor MN51 is turned on, the fourth transistor MP41 is controlled by TX1_ IN _ LS and is also turned on, the drain (the fifth node N5) of the fourth transistor MP41 gradually decreases to the third voltage VSS, after the third signal POR _ IN is released, at high level, the output terminal (the sixth node N6) of the NOR gate NOR is at high level, and the fourth signal TX1 is fully controlled by the second signal TX1_ IN _ LS.

By adjusting the sizes of the second transistor MN1, the third transistor MN2, the fourth transistor MP41 and the sixth transistor MP62, the detection voltage of the first voltage signal VDD can be adjusted, and the power SUPPLY of the whole system is ensured to be normal when the external power SUPPLY voltage VDD _ SUPPLY is powered on.

As described above, the embodiment of the utility model provides a negative pressure generating circuit is used for supplying power for circuit module. The first voltage signal VDD is used as a power supply voltage of the circuit module, and the second voltage signal VSS is used as a floating ground voltage signal of the circuit module. The negative voltage generating circuit and the circuit module are integrated on the same chip or respectively integrated on different chips.

Based on the above embodiment, the utility model discloses another embodiment still provides a chip, the chip includes the negative pressure production circuit as above-mentioned embodiment, the chip adopts above-mentioned negative pressure production circuit, and circuit structure is simple, the low power dissipation, and is with low costs, and response speed is fast.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. For the chip disclosed by the embodiment, since the chip corresponds to the negative voltage generating circuit disclosed by the embodiment, the description is relatively simple, and relevant points can be referred to the description of the corresponding part of the negative voltage generating circuit.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A negative voltage generating circuit, comprising:

a second switch through which the first node is grounded;

a third switch through which the second node is grounded;

2. The negative voltage generating circuit according to claim 1, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor;

3. The negative voltage generating circuit according to claim 2, wherein the first transistor is a PMOS, and the second transistor and the third transistor are both an NMOS.

4. The negative voltage generating circuit according to claim 2, wherein the first transistor, the second transistor, and the third transistor are respectively connected to a logic controller for generating the switch control signal;

5. The negative voltage generating circuit of claim 4, wherein the logic controller comprises:

6. The negative voltage generating circuit according to claim 5, wherein the first output module comprises: the circuit comprises a first buffer, a first AND gate, a level shifter, a first inverter, a second inverter and a first OR gate; the first AND gate is an AND gate with three input ends;

7. The negative voltage generating circuit according to claim 6, wherein the second output module comprises: a second OR gate, a second AND gate, a second buffer and a third buffer; the second AND gate is an AND gate with two input ends;

8. The negative voltage generating circuit of claim 5, wherein a voltage detecting module is connected between the first output module and the second output module, and the voltage detecting module is configured to output a fourth signal based on the input third signal and the input second signal;

9. The negative voltage generating circuit according to claim 8, wherein the voltage detecting module comprises: the first inverter, the second inverter, the NOR gate, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor and the third AND gate;

10. The negative voltage generating circuit according to claim 9, wherein the fourth transistor and the sixth transistor are both PMOS, and the fifth transistor and the seventh transistor are both NMOS.

11. The negative voltage generating circuit according to any one of claims 1-10, wherein the negative voltage generating circuit is configured to power a circuit module;

12. The negative voltage generating circuit of claim 11, wherein the negative voltage generating circuit is integrated on a same chip as the circuit module or integrated on different chips.

13. A chip comprising the negative voltage generating circuit according to any one of claims 1 to 12.