CN117546239A - Latch, trigger and chip - Google Patents

Latch, trigger and chip Download PDF

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Publication number
CN117546239A
CN117546239A CN202180099650.4A CN202180099650A CN117546239A CN 117546239 A CN117546239 A CN 117546239A CN 202180099650 A CN202180099650 A CN 202180099650A CN 117546239 A CN117546239 A CN 117546239A
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China
Prior art keywords
nfet
voltage
latch
pull
gate
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CN202180099650.4A
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Chinese (zh)
Inventor
景蔚亮
吴颖
侯朝昭
范人士
许俊豪
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN117546239A publication Critical patent/CN117546239A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)

Abstract

The application provides a latch, a trigger and a chip, relates to the field of digital circuits, and can reduce the number of transistors in the trigger. The latch includes a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit, and a pull-down circuit. Wherein, the transistors in the latch are all N-type field effect transistors. The pull-up circuit is connected with the first voltage end and the signal output end. The pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal. The pull-down circuit is connected with the signal input end, the control signal end, the signal output end and the second voltage end. The pull-down circuit is configured to: under the control of the control signal end and the signal input end, the voltage of the signal output end is pulled down according to the voltage of the second voltage end.

Description

Latch, trigger and chip Technical Field
The present disclosure relates to the field of digital circuits, and more particularly, to a latch, a flip-flop, and a chip.
Background
In a digital logic chip, flip-flop (FF) occupies 50% of the entire digital logic circuit. The area overhead of the flip-flop is reduced, which is very important for the miniaturization and performance improvement of the digital logic chip.
In the conventional flip-flop using the CMOS (complementary metal oxide semiconductor ) process in the related art, the number of transistors is about 18, so that if the required number of transistors of the CMOS can be reduced, the area required for the flip-flop can be effectively reduced.
Disclosure of Invention
The embodiment of the application provides a latch, a trigger and a chip, wherein the latch based on an NFET is adopted to form the trigger, so that the number of transistors in the trigger can be reduced.
The application provides a latch, including signal input part, signal output part, control signal end, first voltage end, second voltage end, pull-up circuit and pull-down circuit. The transistors in the latch are all N-type field effect transistors (N-channel field effect transistor, NFET; also referred to as electronic channel field effect transistors). The pull-up circuit is connected with the first voltage end and the signal output end; the pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal. The pull-down circuit is connected with the signal input end, the control signal end, the signal output end and the second voltage end. The pull-down circuit is configured to: under the control of the control signal end and the signal input end, the voltage of the signal output end is pulled down according to the voltage of the second voltage end.
In this case, the pull-up circuit and the pull-down circuit in the latch both adopt NFETs, the pull-up circuit outputs the high-level voltage of the first voltage terminal to the signal output terminal, the voltage of the signal output terminal is pulled up, the pull-down circuit is controlled by the control signal terminal and the signal input terminal, the low-level voltage of the second voltage terminal is output to the signal output terminal, the voltage of the signal output terminal is pulled down, and the latch of the signal is realized.
In some possible implementations, the pull-up circuit includes a first resistor. One end of the first resistor is connected with the first voltage end, and the other end of the first resistor is connected with the signal output end.
In some possible implementations, the pull-up circuit includes a first NFET; the first NFET is a depletion mode NFET; the first pole of the first NFET is connected to the first voltage terminal, and both the gate and the second pole of the first NFET are connected to the signal output terminal. In the case of a first NFET employing a depletion mode NFET, the threshold voltage (V th ) Less than zero, thereby ensuring that the first NFET remains on.
In some possible implementations, the pull-up circuit includes a first NFET; the first NFET is an enhancement NFET; the first pole and gate of the first NFET are both connected to a first voltage terminal and the second pole of the first NFET is connected to the signal output terminal. In the case of the first NFET employing an enhancement mode NFET, the threshold voltage (V th ) Greater than zero, thereby ensuring that the first NFET remains on.
In some possible implementations, the pull-up circuit includes a first NFET; the first NFET includes a first gate and a second gate; the first gate and the first pole of the first NFET are both connected to a first voltage terminal, and the second gate and the second pole of the first NFET are both connected to a signal output terminal. In this case, the first NFET is turned on under the control of the high level voltage of the first voltage terminal, and outputs the high level voltage of the first voltage terminal to the signal output terminal; the high level voltage at the signal output terminal forms positive feedback to the second gate of the first NFET and further opens the first NFET, thereby enabling the potential at the signal output terminal to be rapidly increased.
In some possible implementations, the pull-down circuit includes a second NFET, a third NFET, and a first capacitance. A first gate of the second NFET is coupled to the control signal terminal, a first pole of the second NFET is coupled to the signal input terminal, and a second pole of the second NFET is coupled to the first node. A first gate of the third NFET is coupled to the first node, a first pole of the third NFET is coupled to the signal output terminal, and a second pole of the third NFET is coupled to the second voltage terminal. The first electrode of the first capacitor is connected with the first node, and the second electrode of the first capacitor is connected with the second voltage end. In this case, the signal of the signal input terminal can be transmitted to the gate of the third NFET by controlling the on and off of the second NFET by the signal of the control signal terminal; and a first capacitor connected to the gate of the third NFET is capable of storing the signal at the signal input. In the case that the voltage input from the signal input terminal is a high level voltage (i.e., logic "1"), the third NFET is turned on, and outputs a low level voltage of the second voltage terminal (e.g., ground) to the signal output terminal; meanwhile, due to the existence of the first capacitor, the high-level potential stored by the first capacitor can still maintain the opening of the third NFET even when the second NFET is closed, namely, the latching of signals is realized.
In some possible implementations, the second NFET further includes a second gate; the second gate of the second NFET is connected to the control signal terminal.
In some possible implementations, the third NFET further includes a second gate; the second gate of the third NFET is connected to the first node.
The embodiment of the application provides a latch, which comprises a signal input end, a signal output end, a control signal end, a first voltage end, a second voltage end, a pull-up circuit and a pull-down circuit. The transistors in the latch are all NFETs. The pull-up circuit is connected with the signal input end, the signal control end, the first voltage end and the signal output end. The pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal under the signal control of the control signal terminal and the signal input terminal. The pull-down circuit is connected with the signal output end and the second voltage end. The pull-down circuit is configured to: and pulling down the voltage of the signal output end according to the voltage of the second voltage end.
In this case, both the pull-up circuit and the pull-down circuit in the latch adopt NFETs, and the pull-down circuit outputs the low-level voltage of the second voltage terminal to the signal output terminal so as to pull down the voltage of the signal output terminal; the pull-up circuit is controlled through the control signal end and the signal input end, and the high-level voltage of the first voltage end is output to the signal output end so as to pull up the voltage of the signal output end and realize latching of signals.
In some possible implementations, the pull-down circuit includes a first resistor; one end of the first resistor is connected with the second voltage end, and the other end of the first resistor is connected with the signal output end.
In some possible implementations, the pull-down circuit includes a first NFET; the first NFET is a depletion mode NFET; the gate and the first pole of the first NFET are both connected to the second voltage terminal and the second pole of the first NFET is connected to the signal output terminal. In the case where the first NFET employs a depletion mode NFET, the threshold voltage (V th ) Less than zero, thereby ensuring that the first NFET remains on.
In some possible implementations, the pull-down circuit includes a first NFET; the first NFET is a depletion mode NFET; the first NFET includes a first gate and a second gate; the first gate, the second gate, and the first pole of the first NFET are all connected to the second voltage terminal, and the second pole of the first NFET is connected to the signal output terminal. In the case of a first NFET employing a depletion mode NFET, the threshold voltage (V th ) Less than zero can ensure that the first NFET is always on.
In some possible implementations, the pull-up circuit includes a second NFET, a third NFET, and a first capacitance. A first gate of the second NFET is coupled to the control signal terminal, a first pole of the second NFET is coupled to the signal input terminal, and a second pole of the second NFET is coupled to the first node. A first gate of the third NFET is coupled to the first node, a first pole of the third NFET is coupled to the first voltage terminal, and a second pole of the third NFET is coupled to the signal output terminal. The first electrode of the first capacitor is connected with the first node, and the second electrode of the first capacitor is connected with the second voltage end. In this case, the signal of the signal input terminal can be transmitted to the gate of the third NFET by controlling the on and off of the second NFET by the signal of the control signal terminal; and a first capacitor connected to the gate of the third NFET is capable of storing the signal at the signal input. When the voltage input by the signal input end is a high-level voltage (namely logic '1'), the third NFET is started to output the high-level voltage of the first voltage end to the signal output end; due to the existence of the first capacitor, the high-level potential stored by the first capacitor can still maintain the opening of the third NFET even when the second NFET is closed, namely, the latching of signals is realized.
In some possible implementations, the second NFET further includes a second gate; the second gate of the second NFET is connected to the control signal terminal.
In some possible implementations, the third NFET further includes a second gate; the second gate of the third NFET is connected to the first node.
The embodiment of the application also provides a trigger, which comprises a first latch and a second latch; both the first latch and the second latch employ a latch as provided in any one of the possible implementations described above; the signal output end of the first latch is connected with the signal input end of the second latch.
In the flip-flop provided in some embodiments of the present application, the number of NFETs is only 6 (i.e., a 6T structure) compared to about 18 transistors in a conventional flip-flop using CMOS technology; even in the case of a flip-flop using an inverter with 2 transistors (FETs), the number of transistors in the flip-flop is only 8 (i.e., an 8T structure), i.e., the flip-flop provided in the embodiment of the present application can greatly reduce the number of transistors.
The embodiment of the application also provides a chip, which comprises a digital logic circuit; the digital logic circuit includes a latch as provided in any one of the possible implementations described above.
In some possible implementation manners, the latch can be integrated in a subsequent process in the chip, so that the requirement of the chip on the three-dimensional monomer stacking technology is met, the area of the chip is reduced, the power consumption of the chip is reduced, and the performance of the chip is improved.
In some possible implementations, the chip further includes a substrate, and a first device layer and a second device layer disposed on the substrate. The second device layer is positioned on one side of the first device layer, which is away from the substrate, and the first device layer is electrically connected with the second device layer. A CMOS transistor is disposed in the first device layer. NFETs in the latch employ oxide semiconductor field effect transistors and NFETs in the latch are distributed in the second device layer.
By setting the digital logic circuit of the chip, adopting the flip-flop and/or the latch provided by the embodiment of the application, and setting the NFET in the flip-flop and/or the latch to adopt the N-type oxide semiconductor field effect transistor, the manufacturing temperature condition of the chip in the subsequent process can be met, so that the first device layer can be manufactured firstly in the previous process (front end of line, FEOL) through the CMOS technology, and then the second device layer can be manufactured in the subsequent process (BEOL); namely, the digital logic circuit is integrated with the subsequent working procedure of the chip, so that the requirement of the chip on the three-dimensional monomer stacking technology is met, the area of the chip is reduced, the power consumption of the chip is reduced, and the performance of the chip is improved.
The embodiment of the application also provides electronic equipment, which comprises a printed circuit board and a chip provided in any one of the possible modes; the chip is electrically connected to the printed wiring board.
Drawings
FIG. 1 is a schematic diagram of a latch according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of four different pull-up circuits according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a pull-down circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a pull-down circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a latch according to an embodiment of the present disclosure;
FIG. 6 is a simulation result of the latch of FIG. 5;
FIG. 7 is a schematic diagram of a latch according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of three different pull-down circuits according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a pull-up circuit according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of a pull-up circuit according to an embodiment of the present disclosure;
FIG. 11 is a schematic diagram of a latch according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a trigger according to an embodiment of the present application;
FIG. 13 is a simulation result of the flip-flop of FIG. 12;
fig. 14 is a schematic structural diagram of a chip according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. "connected," "coupled," and the like, are used to indicate interworking or interaction between different components, and may include direct coupling or indirect coupling via other components. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. "upper", "lower", "left", "right", etc. are used merely with respect to the orientation of the components in the drawings, these directional terms are relative terms, which are used for description and clarity with respect thereto, and which may vary accordingly depending on the orientation in which the components are placed in the drawings.
It should be understood that in this application, "at least one" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The present embodiments provide a flip-flop (FF) that may be formed using a set of latches (i.e., two latches) in series, and the transistors in the latches (latch) are all NFET (n-channel field effect transistor, electron channel field effect transistor). Compared with a trigger adopting a CMOS process, the trigger provided by the embodiment of the application can greatly reduce the number of transistors compared with the trigger adopting the CMOS process, wherein about 18 transistors are required to be arranged.
It should be noted here that, for the NFET used in the embodiments of the present application, a part of the NFET may be a single-gate structure (i.e., having one gate), and a part of the NFET may be a double-gate structure (i.e., having two gates, a first gate and a second gate), and reference is made to the following related descriptions. Of course, it is understood that NFETs include a first pole and a second pole in addition to a gate, one of the first pole and the second pole being a source and the other being a drain, the first pole and the second pole being equivalently interchangeable. The following examples are illustrative of the application using the first electrode as the source electrode and the second electrode as the drain electrode.
Two different types of latches (latch one and latch two) are provided below, and the setting of the flip-flop provided in the embodiments of the present application is described in connection with latch one and latch two.
Latch I
As shown in fig. 1, the latch one 10 includes: a pull-up circuit put (also referred to as a pull-up network circuit), a pull-down circuit PDN (pull down network, also referred to as a pull-down network circuit), a signal Input terminal Input, a signal Output terminal Output, a control signal terminal CLK, a first voltage terminal, and a second voltage terminal. Wherein the first voltage terminal may be a high-level voltage terminal, such as a power terminal V DD The method comprises the steps of carrying out a first treatment on the surface of the The second voltage terminal may be a low level voltage terminal, such as the ground terminal GND, but is not limited thereto. The following embodiments all use the first voltage terminal as the high level voltage terminal as the power terminal V DD The method comprises the steps of carrying out a first treatment on the surface of the The second voltage terminal is exemplified as the ground terminal GND.
Referring to FIG. 1, in the latch one 10, a pull-up circuit PUN is connected to a first voltage terminal (V DD ) And the signal Output end is connected. The pull-up circuit PUN is configured to control the voltage according to a first voltage terminal (V DD ) The voltage of the signal Output terminal Output is pulled up.
Schematically, referring to fig. 1 and 2 (a), in some possible implementations, the pull-up circuit PUN may include a first resistor R1. One end of the first resistor R1 is connected with a first voltage end (V DD ) The other end of the first resistor R1 is connected with the signal Output end Output.
Schematically, referring to fig. 1 and 2 (b), in some possible implementations, the pull-up circuit PUN may include a first NFET a1. The first NFETa1 is a depletion mode NFET. Wherein the source of the first NFETa1 is connected to a first voltage terminal (V DD ) The gate and drain of the first NFETa1 are connected to the signal Output terminal Output.
It is understood herein that where the first NFETa1 employs a depletion mode NFET, the threshold voltage (V th ) Less than zero, thereby enabling, in a circuit-connection mode employing (b) in fig. 2It can be ensured that the first NFETa1 remains in an on state.
Schematically, referring to fig. 1 and 2 (c), in some possible implementations, the pull-up circuit PUN may include a first NFET. The first NFET is an enhancement mode NFET; wherein the source and gate of the first NFET are both connected to a first voltage terminal (V DD ) The drain of the first NFET is connected to a signal Output terminal Output (not shown in fig. 2).
It is understood herein that where the first NFETa1 employs an enhanced NFET, the threshold voltage (V th ) Greater than zero, thereby ensuring that the first NFET a1 remains on to place the first voltage terminal (V DD ) The voltage of the signal Output terminal Output is pulled up.
Schematically, referring to fig. 1 and (d) of fig. 2, in some possible implementations, the pull-up circuit PUN may include a first NFET a1. The first NFETa1 includes a first gate g1 and a second gate g2, i.e., the first NFET is a dual-gate structure. Wherein the first gate g1 and the source of the first NFETa1 are both connected to a first voltage terminal (V DD ) The second gate g2 and the drain of the first NFETa1 are both connected to a signal Output (not shown in fig. 2). In fig. 2 (d), the first gate g1 is taken as a top gate, and the second gate g2 is taken as a back gate as an example, and in other possible implementations, the first gate g1 may be a back gate, and the second gate g2 is a top gate. In the following embodiments, the first gate g1 is taken as a top gate, and the second gate g2 is taken as a back gate for illustration.
Referring to fig. 2 (d), in the case where the first NFET a1 adopts a double-gate structure, the first NFET a1 is formed at the first voltage terminal (V DD ) Under control of a high level voltage of (a) the first NFET a1 is turned on and the first voltage terminal (V DD ) The high level voltage of the voltage source is Output to the signal Output end Output, and the voltage of the signal Output end Output is pulled up; at the same time, the high voltage of the signal Output end Output forms positive feedback to the second gate g2 of the first NFET a1 to further open the first NFET a1, thereby enabling the potential of the signal Output terminal Output to be rapidly increased.
In addition, referring to fig. 1, in the latch one 10, the pull-down circuit PDN is connected to the signal Input terminal Input, the control signal terminal CLK, the signal Output terminal Output, and the second voltage terminal (GND). The pull-down circuit PDN is configured to: under the control of the signals of the control signal terminal CLK and the signal Input terminal Input, the voltage of the signal Output terminal Output is pulled down according to the voltage of the second voltage terminal (GND).
Illustratively, in some possible implementations, as shown with reference to fig. 1 and 3, the pull-down circuit PDN may include a second NFET a2, a third NFET a3, and a first capacitance C1. The gate of the second NFET a2 is connected to the control signal terminal CLK, the source of the second NFET a2 is connected to the signal Input terminal Input, and the drain of the second NFET a2 is connected to the first node N1. The gate of the third NFET a3 is connected to the first node N1, the source of the third NFET a3 is connected to the signal Output terminal Output, and the drain of the third NFET a3 is connected to the second voltage terminal (GND). A first pole of the first capacitor C1 is connected to the first node N1, and a second pole of the first capacitor C1 is connected to the second voltage terminal (GND). It should be noted that the first capacitor C1 may be composed of the gate capacitance of the third NFET a3, or may be a load capacitance designed alone or in combination thereof.
In this case, the signal of the signal Input terminal Input can be transmitted to the gate of the third NFET a3 by controlling the on and off of the second NFET a2 by the signal of the control signal terminal CLK; and the first capacitor C1 connected to the gate of the third NFET a3 is capable of storing the signal of the signal Input. In the case that the voltage Input from the signal Input terminal Input is a high level voltage (i.e., logic "1"), the third NFET a3 is turned on, and outputs a low level voltage of the second voltage terminal (GND) to the signal Output terminal Output so as to pull down the voltage of the signal Output terminal Output; meanwhile, due to the existence of the first capacitor C1, even when the second NFET a2 is closed, the high level potential stored by the first capacitor C1 can still maintain the opening of the third NFET a3, namely, the latching of signals is realized.
Of course, as another alternative implementation, as shown in fig. 4, the second NFET a2 may have a dual-gate structure, that is, the second NFET a2 includes two gates (a first gate and a second gate), and both gates of the second NFET a2 are connected to the control signal terminal CLK.
Similarly, in some possible implementations, the third NFET a3 may also be a dual-gate structure, i.e., the third NFET a3 includes two gates (a first gate and a second gate), and both gates of the third NFET a3 are connected to the first node N1.
The illustration in fig. 4 is given by way of example only in which the second NFET a2 and the third NFET a3 are each of a double-gate structure, and in other possible implementations, one of the second NFET a2 and the third NFET a3 may be provided as a double-gate structure, and the other as a single-gate structure. For example, the second NFET a2 is a double-gate structure (refer to fig. 4), and the third NFET a3 is a single-gate structure (refer to fig. 3). For another example, the second NFET a2 is a single-gate structure (refer to fig. 3), and the third NFET a3 is a double-gate structure (refer to fig. 4).
A latch one 10 of a 3T (i.e., 3 NFET) structure is shown in fig. 5; in the latch one 10, the pull-up circuit PUN adopts the circuit configuration of fig. 2 (d), and the pull-down circuit PDN adopts the circuit configuration of fig. 3. Fig. 6 is a simulation result of latch one 10 of fig. 5. The following is a brief schematic description of the operation of the latch one 10 provided in this application, with reference to fig. 5 and 6.
Referring to fig. 5 and 6, when the clock signal Input from the control signal terminal CLK is a high level voltage, the second NFET a2 is turned on, the high level voltage (i.e., logic "1") Input from the signal Input terminal Input is transmitted to the gate of the third NFET a3, and the first capacitor C1 is charged, the third NFET a3 is turned on, and the low level voltage of the second voltage terminal (GND) is Output to the signal Output terminal Output, so as to pull down the voltage of the signal Output terminal Output, and at this time, the resistance of the pull-down circuit PDN is far smaller than the resistance of the pull-up circuit fin. When the clock signal input by the control signal terminal CLK is turned into a low level voltage, the second NFET a2 is turned off, and the high level voltage stored in the first capacitor C1 keeps the third NFET a3 turned on, and the low level voltage of the second voltage terminal (GND) is continuously Output to the signal Output terminal Output, so that the latching of the signal is realized. When the clock signal is input from the control signal terminal CLKFor high level voltage, when the signal Input terminal Input inputs low level voltage (i.e. logic "0"), the second NFET a2 is turned on and the third NFET a3 is turned off, and the resistance of the pull-down circuit PDN is much larger than that of the pull-up circuit PUN, the first voltage terminal (V DD ) Is Output to the signal Output terminal Output through the first NFET a1 to pull up the voltage of the signal Output terminal Output.
Latch II
As shown in fig. 7, the latch two 20 includes: pull-up circuit PUN, pull-down circuit PDN, signal Input terminal Output terminal, control signal terminal CLK, first voltage terminal (V DD ) A second voltage terminal (GND).
Referring to fig. 7, in the latch two 20, the pull-down circuit PDN is connected to the signal Output terminal Output and the second voltage terminal (GND). The pull-down circuit PDN is configured to: the voltage of the signal Output terminal Output is pulled down according to the voltage of the second voltage terminal (GND).
Illustratively, in some possible implementations, referring to fig. 7 and 8 (a), the pull-down circuit PDN may include a first resistor R1. One end of the first resistor R1 is connected to the second voltage terminal (GND), and the other end of the first resistor R1 is connected to the signal Output terminal Output.
Illustratively, in some possible implementations, the pull-down circuit PDN described above may include a first NFET a1, as shown with reference to (b) in fig. 7 and 8. The first NFET a1 is a depletion mode NFET. The gate and source of the first NFET a1 are both connected to the second voltage terminal (GND) and the drain of the first NFET a1 is connected to the signal Output terminal Output.
It is understood herein that where the first NFETa1 employs a depletion mode NFET, the threshold voltage (V th ) Less than zero, so that the first NFET a1 can be guaranteed to be kept in an on state in the circuit connection manner shown in (b) of fig. 8, so that the voltage of the second voltage terminal (GND) is outputted to the signal Output terminal Output, and the voltage of the signal Output terminal Output is pulled down.
Illustratively, in some possible implementations, the pull-down circuit PD described above is shown with reference to (c) in FIGS. 7 and 8N may include a first NFET a1. The first NFETa1 is a depletion mode NFET and the first NFETa1 includes a first gate g1 and a second gate g2, i.e., the first NFET is a double gate structure. The first gate g1, the second gate g2 and the source of the first NFETa1 are all connected to the second voltage terminal (GND), and the drain of the first NFETa1 is connected to the signal Output terminal Output. In the case where the first NFET a1 employs a depletion mode NFET, the threshold voltage (V th ) Being smaller than zero, the first NFET a1 can be guaranteed to be always in an on state, so that the voltage of the second voltage terminal (GND) is Output to the signal Output terminal Output, and the voltage of the signal Output terminal Output is pulled down. In fig. 8 (c), the first gate g1 is taken as a top gate, and the second gate g2 is taken as a back gate as an example, and in other possible implementations, the first gate g1 may be a back gate, and the second gate g2 may be a top gate.
In addition, referring to fig. 7, in the latch two 20, the pull-up circuit PUN and the signal Input terminal Input, the control signal terminal CLK, the first voltage terminal (V DD ) And the signal Output end is connected. The pull-up circuit PUN is configured to control the signal of the signal terminal CLK and the signal Input terminal Input according to a first voltage terminal (V DD ) The voltage of the signal Output terminal Output is pulled up.
Illustratively, in some possible implementations, referring to fig. 7 and 9, the pull-up circuit PUN may include a second NFET a2, a third NFET a3, and a first capacitor C1. The gate of the second NFETa2 is connected to the control signal terminal CLK, the source of the second NFETa2 is connected to the signal Input terminal Input, and the drain of the second NFET a2 is connected to the first node N1. The gate of the third NFET a3 is connected to the first node N1, and the source of the third NFET a3 is connected to a first voltage terminal (V DD ) The drain electrode of the third NFET a3 is connected with the signal Output end Output. A first pole of the first capacitor C1 is connected to the first node N1, and a second pole of the first capacitor C1 is connected to the second voltage terminal (GND). It should be noted that the first capacitor C1 may be composed of the gate capacitance of the third NFET a3, or may be a load capacitance designed alone or in combination thereof.
In this case the number of the elements to be formed is,the signal of the signal Input terminal Input can be transmitted to the gate of the third NFET a3 by controlling the on and off of the second NFET a2 through the signal of the control signal terminal CLK; and the first capacitor C1 connected to the gate of the third NFET a3 is capable of storing the signal of the signal Input. When the voltage Input from the signal Input terminal Input is a high level voltage (i.e., logic "1"), the third NFET a3 is turned on to supply the first voltage terminal (V DD ) The high level voltage of the voltage source is Output to the signal Output end Output so as to pull up the voltage of the signal Output end Output; due to the presence of the first capacitor C1, the high-level potential stored in the first capacitor C1 can still maintain the turn-on of the third NFET a3 even when the second NFET a2 is turned off, i.e., the latching of the signal is realized.
Of course, as another alternative implementation, as shown in fig. 10, the second NFET a2 may have a dual-gate structure, that is, the second NFET a2 includes two gates (a first gate and a second gate), and both gates of the second NFET a2 are connected to the control signal terminal CLK.
Similarly, in some possible implementations, as shown in fig. 10, the third NFET a3 may also be a dual-gate structure, that is, the third NFET a3 includes two gates (a first gate and a second gate), and both gates of the third NFET a3 are connected to the first node N1.
The illustration in fig. 10 is merely schematic and illustrates that the second NFET a2 and the third NFET a3 are each of a double-gate structure, and in other possible implementations, one of the second NFET a2 and the third NFET a3 may be provided as a double-gate structure, and the other as a single-gate structure. For example, the second NFET a2 is a double-gate structure (refer to fig. 10), and the third NFET a3 is a single-gate structure (refer to fig. 9). For another example, the second NFET a2 is a single-gate structure (refer to fig. 9), and the third NFET a3 is a double-gate structure (refer to fig. 10).
A latch two 20 of a 3T (i.e., 3 NFET) structure is shown in fig. 11; in the latch two 20, the pull-up circuit PUN adopts the circuit configuration of fig. 9, and the pull-down circuit PDN adopts the circuit configuration of fig. 8 (b). The working principle of the latch two 20 provided in the present application will be briefly described with reference to fig. 11.
As described with reference to fig. 11When the clock signal Input from the control signal terminal CLK is a high level voltage (i.e., logic "1"), the second NFET a2 is turned on, the high level voltage Input from the signal Input terminal Input is transmitted to the gate of the third NFET a3 and charges the first capacitor C1, the third NFET a3 is turned on, and the first voltage terminal (V DD ) The high level voltage of the voltage source is Output to the signal Output end Output so as to pull up the voltage of the signal Output end Output; the resistance of the pull-up circuit PUN is now much smaller than the resistance of the pull-down circuit PDN. When the clock signal input from the control signal terminal CLK is turned to a low level voltage, the second NFET a2 is turned off, the high level voltage previously stored in the first capacitor C1 keeps the third NFET a3 turned on, and the first voltage terminal (V DD ) Is continuously Output to the signal Output terminal Output. When the clock signal Input by the control signal terminal CLK is a high level voltage and the signal Input terminal Input inputs a low level voltage (i.e., logic "0"), the second NFET a2 is turned on and the third NFET a3 is turned off; the resistance of the pull-down circuit PDN is far smaller than that of the pull-up circuit put, and the low-level voltage of the second voltage terminal (GND) is Output to the signal Output terminal Output through the first NFET a1, so as to pull down the voltage of the signal Output terminal Output.
The flip-flops according to the embodiments of the present application will be described below with reference to the latches (e.g., 10 and 20).
As shown in fig. 12, the flip-flop F provided in the embodiment of the present application may include two latches (a first latch A1 and a second latch A2). The first latch A1 may be referred to as a master latch, and the second latch A2 may be referred to as a slave latch. The two latches (A1, A2) may each employ any of the latches (e.g., 10, 20) described above. The signal Output terminal Output of the first latch A1 is connected to the signal Input terminal Input of the second latch A2 (corresponding to the S terminal in fig. 12). The signal Input of the first latch A1 is used as the Input D of the flip-flop F and the signal Output of the second latch A2 is used as the Output Q of the flip-flop F.
It should be noted that fig. 12 is only a schematic illustration of the first latch A1 and the second latch A2 by taking the latch a 10 as an example, but the present application is not limited thereto. For example, in some possible implementations, the first latch A1 and the second latch A2 may each employ the latch two 20 described above. For another example, in some possible implementations, one of the first latch A1 and the second latch A2 may employ the first latch 10 and the other may employ the second latch 20.
In addition, it should be noted that the circuit structures of the first latch A1 and the second latch A2 may be identical or different; the present application is not limited in this regard. For example, as shown in fig. 12, in some possible implementations, two latches 10 employed by the flip-flop F may have the same circuit structure; for another example, in other possible implementations, the two latches 10 employed by the flip-flop F may have different circuit configurations.
FIG. 13 is a simulation result of the flip-flop F in FIG. 12; the signal input from the control signal terminal CLK1 of the first latch A1 in fig. 12 is the CLK signal in fig. 13, and the control signal input from the control signal terminal CLK2 of the second latch A2 is A signal; CLK signalThe signal is a set of inverted clock signals.
As shown in fig. 12 and 13, when the signal input to the control signal terminal CLK1 of the first latch A1 is a high level voltage, the control signal input to the control signal terminal CLK2 of the second latch A2 is a low level voltage (i.e., clk=1,) The method comprises the steps of carrying out a first treatment on the surface of the The input signal at input D of flip-flop F is transferred to the S terminal through the first latch A1. But due toThe output state of the second latch A2 is now independent of the output at the S terminal. When the signal input from the control signal terminal CLK1 of the first latch A1 becomes a low level voltage (i.e. clk=0,) The output of the first latch A1 (i.e. the S-terminal) is then independent of the input D, the output of the S-terminal being kept unchanged and being output to the output Q via the second latch A2. Therefore, the signal at the input D of the flip-flop F can be output to the output Q only when the CLK signal transitions from the high level voltage to the low level voltage (i.e., negative CLK edge, i.e., the falling edge of the clock signal), i.e., the flip-flop implements the falling edge trigger (i.e., the negative-edge-triggered FF).
Of course, in other possible implementations, the input signals of the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2 may be exchanged, i.e. the control signal terminal CLK2 of the second latch A2 inputs the CLK signal of FIG. 13, while the input of the control signal terminal CLK1 of the first latch A1 A signal. In this case, the flip-flop may implement rising edge triggering (i.e., positive-edge-triggered FF), that is, the input signal of the input terminal D of the flip-flop F may be output to the output terminal Q only when the clock signal transitions from the low potential to the high potential.
For a set of inverted clock signals input from the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2, in some possible implementations, an inverter may be used to invert the CLK signalA signal to satisfy the above triggerThe signal requirements of the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2.
The specific arrangement form of the inverter is not limited in this application. For example, in some possible implementations, an inverter formed of NFETs may be employed, such that the inverter may be fabricated using the same fabrication process as the flip-flop. As another example, in some possible implementations, CMOS inverters may be employed; in practice, the settings may be selected as desired.
It can be appreciated that the number of NFETs is only 6 (i.e., a 6T structure) for the flip-flop provided by the embodiments of the present application, compared to about 18 transistors in a conventional flip-flop using CMOS technology; in some embodiments, the flip-flop uses 2 transistors (FETs) in an inverter, the number of transistors is only 8 (i.e., an 8T structure), i.e., the flip-flop provided in the embodiments of the present application can greatly reduce the number of transistors.
It should be noted that, the latch provided in the embodiment of the present application is not limited to the application in the flip-flop, and according to actual needs, the latch provided in the embodiment of the present application may also be applied in other logic function devices.
The embodiment of the application also provides a chip, and the logic function device in the digital logic circuit in the chip can adopt the trigger and/or the latch.
In some chips, the flip-flop occupies 50% of the area of the whole digital logic circuit, in this case, when the flip-flop provided in the embodiment of the present application is adopted, the area overhead of the chip can be greatly reduced, so that the chip is more beneficial to the miniaturization and the performance improvement of the chip.
In addition, for the fabrication of the flip-flop and/or latch provided by the embodiments of the present application, in some possible implementations, the NFETs in the flip-flop and/or latch provided by the embodiments of the present application may employ N-type oxide semiconductor (oxide semiconductor, OS) field effect transistors, that is, the channel layers of the NFETs employ oxide semiconductor materials. In other possible implementations, NFETs in flip-flops and/or latches provided by embodiments of the present application may be fabricated using low temperature polysilicon technology (lowtemperature polycrystalline silicon, LTPS), i.e., the channel layer of the NFETs is made of polysilicon material.
Taking the fabrication of a chip as an example, the subsequent process (BEOL) of the chip cannot meet the high-temperature fabrication of the CMOS technology, so that the digital logic circuit cannot be compatible with the subsequent process, and the requirement of the chip on the three-dimensional single stacking technology is limited; the LTPS technology has the problems of complex process, high cost, large fluctuation of the electrical characteristics of devices, poor uniformity and the like, and is difficult to meet the requirements of circuit design and large-scale integration. In contrast, NFETs in flip-flops and/or latches provided by embodiments of the present application may employ N-type oxide semiconductor field effect transistors, so as to be able to meet the temperature conditions for the fabrication of the chip in a subsequent process. Based on this, in some possible implementation manners, the above-mentioned logic function devices of the flip-flop and/or latch may be adopted to integrate in the subsequent process of the chip, so as to further meet the requirement of the chip on the three-dimensional monomer stacking technology, reduce the area of the chip, reduce the power consumption of the chip, and improve the performance of the chip.
Schematically, as shown in fig. 14, an embodiment of the present application provides a chip, which includes a substrate 100, and a first device layer 101 and a second device layer 102 disposed on the substrate 100. Wherein the second device layer 102 is located at a side of the first device layer 101 remote from the substrate 100, and the first device layer 101 and the second device layer 102 are electrically connected. Illustratively, the first device layer 201 and the second device layer 202 may be electrically connected by metal micro-vias.
A CMOS transistor (complementary metal oxide semiconductor field effect transistor) is provided in the first device layer 101. The digital logic circuit in the chip includes the flip-flop and/or latch provided in the foregoing embodiments, and NFETs in the flip-flop and/or latch are N-type oxide semiconductor field effect transistors and distributed in the second device layer 202.
In this case, the first device layer 101 may be fabricated in a front-end-of-line (front end of line, FEOL) via CMOS technology, and then the second device layer 102 may be fabricated in a back-end-of-line (BEOL); the digital logic circuit is compatible with the subsequent process, so that the requirement of the chip on the three-dimensional monomer stacking technology can be met.
In addition, the embodiment of the application also provides an electronic device, which comprises a printed circuit board (printed circuit board, PCB) and the chip; the chip is electrically connected with the PCB.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (14)

  1. The latch is characterized by comprising a signal input end, a signal output end, a control signal end, a first voltage end, a second voltage end, a pull-up circuit and a pull-down circuit;
    transistors in the latch are N-type field effect transistors (NFETs);
    the pull-up circuit is connected with the first voltage end and the signal output end; the pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal;
    the pull-down circuit is connected with the signal input end, the control signal end, the signal output end and the second voltage end; the pull-down circuit is configured to: and under the control of the signals of the control signal end and the signal input end, the voltage of the signal output end is pulled down according to the voltage of the second voltage end.
  2. The latch of claim 1 wherein the latch is configured to hold the latch,
    the pull-up circuit comprises a first resistor; one end of the first resistor is connected with the first voltage end, and the other end of the first resistor is connected with the signal output end;
    alternatively, the pull-up circuit includes a first NFET; the first NFET is a depletion mode NFET; a first pole of the first NFET is connected with the first voltage end, and a gate and a second pole of the first NFET are connected to the signal output end;
    Alternatively, the pull-up circuit includes a first NFET; the first NFET is an enhancement NFET; the first pole and the gate of the first NFET are both connected to the first voltage end, and the second pole of the first NFET is connected to the signal output end;
    alternatively, the pull-up circuit includes a first NFET; the first NFET includes a first gate and a second gate; the first gate and the first pole of the first NFET are both connected with the first voltage end, and the second gate and the second pole of the first NFET are both connected with the signal output end.
  3. A latch according to claim 1 or 2, wherein,
    the pull-down circuit includes a second NFET, a third NFET, and a first capacitor;
    a first gate of the second NFET is connected with the control signal end, a first pole of the second NFET is connected with the signal input end, and a second pole of the second NFET is connected with a first node;
    a first gate of the third NFET is connected to the first node, a first pole of the third NFET is connected to the signal output terminal, and a second pole of the third NFET is connected to the second voltage terminal;
    the first pole of the first capacitor is connected with the first node, and the second pole of the first capacitor is connected with the second voltage end.
  4. The latch of claim 3 wherein the latch comprises a latch,
    the second NFET also includes a second gate; and a second grid electrode of the second NFET is connected with the control signal terminal.
  5. The latch according to claim 3 or 4, wherein,
    the third NFET also includes a second gate; a second gate of the third NFET is connected to the first node.
  6. The latch is characterized by comprising a signal input end, a signal output end, a control signal end, a first voltage end, a second voltage end, a pull-up circuit and a pull-down circuit;
    transistors in the latch are all NFETs;
    the pull-up circuit is connected with the signal input end, the signal control end, the first voltage end and the signal output end; the pull-up circuit is configured to pull up the voltage of the signal output end according to the voltage of the first voltage end under the control of signals of the control signal end and the signal input end;
    the pull-down circuit is connected with the signal output end and the second voltage end; the pull-down circuit is configured to: and pulling down the voltage of the signal output terminal according to the voltage of the second voltage terminal.
  7. The latch of claim 6 wherein the latch comprises a latch,
    The pull-down circuit comprises a first resistor; one end of the first resistor is connected with the second voltage end, and the other end of the first resistor is connected with the signal output end;
    alternatively, the pull-down circuit includes a first NFET; the first NFET is a depletion mode NFET; the grid electrode and the first electrode of the first NFET are connected to the second voltage end, and the second electrode of the first NFET is connected to the signal output end;
    alternatively, the pull-down circuit includes a first NFET; the first NFET is a depletion mode NFET; the first NFET includes a first gate and a second gate; the first gate, the second gate and the first pole of the first NFET are all connected to the second voltage terminal, and the second pole of the first NFET is connected to the signal output terminal.
  8. The latch according to claim 6 or 7, wherein,
    the pull-up circuit includes a second NFET, a third NFET and a first capacitor;
    a first gate of the second NFET is connected with the control signal end, a first pole of the second NFET is connected with the signal input end, and a second pole of the second NFET is connected with a first node;
    a first gate of the third NFET is connected with the first node, a first pole of the third NFET is connected with the first voltage end, and a second pole of the third NFET is connected with the signal output end;
    The first pole of the first capacitor is connected with the first node, and the second pole of the first capacitor is connected with the second voltage end.
  9. The latch of claim 8 wherein the latch is configured to hold the latch,
    the second NFET also includes a second gate; and a second grid electrode of the second NFET is connected with the control signal terminal.
  10. A latch according to claim 8 or 9, wherein,
    the third NFET also includes a second gate; a second gate of the third NFET is connected to the first node.
  11. A flip-flop comprising a first latch and a second latch; the first latch and the second latch each employing a latch as claimed in any one of claims 1 to 10;
    the signal output end of the first latch is connected with the signal input end of the second latch.
  12. A chip comprising a digital logic circuit;
    the digital logic circuit comprising a latch as claimed in any one of claims 1 to 10.
  13. The chip of claim 12, wherein the latch is integrated in a subsequent process.
  14. An electronic device comprising a printed wiring board and a chip as claimed in claim 12 or 13; the chip is electrically connected with the printed circuit board.
CN202180099650.4A 2021-10-09 2021-10-09 Latch, trigger and chip Pending CN117546239A (en)

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JP2010034710A (en) * 2008-07-25 2010-02-12 Nec Electronics Corp Semiconductor integrated circuit, and method for preventing malfunction thereof
US8030982B2 (en) * 2008-10-30 2011-10-04 Qualcomm Incorporated Systems and methods using improved clock gating cells
US8625334B2 (en) * 2011-12-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell
US9438211B1 (en) * 2015-07-16 2016-09-06 Huawei Technologies Co., Ltd. High speed latch and method
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