WO2023054230A1

WO2023054230A1 - Imaging device

Info

Publication number: WO2023054230A1
Application number: PCT/JP2022/035597
Authority: WO
Inventors: 琢己山口
Original assignee: 株式会社 Rosnes
Priority date: 2021-09-29
Filing date: 2022-09-26
Publication date: 2023-04-06

Abstract

[Problem] Conventional CMOS image sensors have a problem in that when signal charge of a light reception unit is added to an addition accumulation unit a plurality of times, output that is directly linearly proportional to the number of times of addition cannot be obtained. [Solution] An imaging device in which arranged are pixels each having: a light reception unit; a unit accumulation unit for accumulating a part or whole of signal charge of the light reception unit; a reading transistor disposed between the light reception unit and the unit accumulation unit; an adding accumulation unit for adding a part or whole of signal charge of the unit accumulation unit; an adding transistor disposed between the unit accumulation unit and the addition accumulation unit; and a source follower amplifier (AMP) in which a floating diffusion (FD) is disposed, wherein the unit accumulation unit is disposed between the light reception unit and the FD.

Description

[Title of invention determined by ISA based on Rule 37.2] Imaging device

The present invention relates to an image pickup apparatus, and in particular, when signal charges in a light receiving section are added to an addition accumulation section via a unit accumulation section and read out a plurality of times, the number of times of addition and accumulation in the addition accumulation section are performed. The present invention relates to a method of driving an image pickup device and an image pickup device in which the amount of signal charge is linearly proportional, or an electronic device having the image pickup device and requiring a wide dynamic range.　

In recent years, CMOS image sensors have become the mainstream of imaging devices used in cameras. Conventional CMOS sensors generally convert the charge in the light-receiving part of a pixel to a floating diffusion (FD) to convert it into a voltage and read it out from a source follower amplifier (AMP).

In recent years, the capacitance of FDs has been made as small as possible in order to achieve high gain of pixel amplifiers. Therefore, when a large amount of charge is transferred from the light receiving section at one time, or when a high dynamic range is achieved by transferring the charge of the light receiving section to the FD multiple times, the FD capacity becomes full and the correct signal is output from the AMP. There is a problem that the voltage cannot be read.

As means for solving this problem, a structure has been proposed in which a high capacitance is connected in parallel with the capacitance of the FD section via a transistor.

FIG. 14 is an example of a circuit diagram of a conventional pixel.
In the light-receiving portion 1 of the conventional pixel, incident light is photoelectrically converted to store signal charges. be.
In the source follower amplifier (AMP) 3, by applying a voltage to the reset transistor wiring (6-1) to turn on the FD reset transistor 6 (TR6), the floating diffusion (FD) 5 is The voltage of the amplifier power supply 10 is reset.

After that, when the readout transistor 2 (TR2) operates (turns on), the charge Q1 of the photodiode (PD) of the light receiving section 1 is transferred to the FD5 of the AMP3 and converted into a voltage. The converted voltage is read out from signal line 4 as the output of source follower transistor 7 (TR7) when row select transistor 8 (TR8) turns on.

On the other hand, when the charge transferred from the light receiving section 1 at one time is large, or when the charge of the light receiving section 1 is transferred to the FD multiple times, the floating diffusion (FD) capacity (5-1 ) cannot receive all the charges, by applying a voltage to the addition transistor wiring (9-1), the addition transistor 9 (TR9) is turned on, and the capacitance of the addition storage section (9-2) and It is configured such that electric charges are stored in both of the FD capacitors (5-1).

FIG. 15 is a cross-sectional view of the light receiving section and the FD section.
The FD capacitor (5-1) and the addition storage section (9-2) are made of a dense N+ diffusion layer.

FIG. 16 shows the basic operation of adding the signal charges of the sections of the light receiving section and the FD section.
The operation of (A-1) is a state in which signal charges are held in the light receiving section 1 .
The FD capacity (5-1) and the capacity of the addition storage section (9-2) are set by setting the FD reset transistor 6 adjacent to the FD capacity (5-1) shown in FIG. This is a state in which the amplifier power supply 10 is reset to 3V by changing the potential.

In the operation (B-1), a voltage is applied to the electrode of the readout transistor 2, and all or part of the signal charge in the light receiving section 1 is read out to the FD capacitor (5-1) only once. state. At this time, the FD capacitor (5-1) stores one signal charge of the light receiving section 1, and the FD capacitor (5-1) is called a unit storage section. In the case of this figure, 3 out of 12 signal charges of the light receiving portion 1 are read out to the unit storage portion of the FD capacitor (5-1).

In the operation of (C-1), TR9 turns on the signal charge of the FD capacitor (5-1), thereby transferring three signal charges in the unit storage section of the FD capacitor (5-1) to the FD capacitor (5 -1) and the addition storage unit (9-2).

what if,
FD capacity (5-1):addition storage unit (9-2)=1:2
In Case of,
3*(1/(1+2))=3*(1/3)=1 for FD capacity (5-1)
Three signal charges are divided like 3*(2/(1+2))=3*(2/3)=2.

In the operation (D-1), the addition transistor 9 is turned off and the first charge accumulation is completed.

FIG. 17 is a diagram of excerpts of the first basic motion and the second motion.
(A-1), (B-1), and (C-1) are part of the basic operation in FIG.

In the operation of (A-2), after (C-1), the adding transistor 9 is turned off, the FD capacitor (5-1) is reset to 3 V at TR6 in FIG. This is the state in which the electric charge is accumulated.

In the operation of (B-2), like the operation of (B-1), all or part of the signal charge of the light receiving section 1 is read out to the FD capacitor (5-1) only once. state. In the case of FIG. 17, 3 out of 12 signal charges of the light receiving section 1 are read out to the FD capacitor (5-1).
At this time point, the addition/storage section (9-2) is in a state of containing two charges at the time of the operation (C-1).

The operation of (C-2) is 3 signal charges of the FD capacitor (5-1) of the operation of (B-2) and 2 signal charges of the addition storage section (9-2), a total of 5 signals. the charge is
FD capacity (5-1):addition storage unit (9-2)=1:2
are redistributed at a rate of

At this time,
5*(1/(1+2))=5*(1/3)=5/3 for FD capacity (5-1)
5*(2/(1+2))=5*(2/3)=10/3.

here,
In the addition/storage unit (9-2), the signal charges are 2 at the time of the first operation (C-1), and the signal charges are 10/3 at the time of the second operation (C-2). ing.

Originally, the signal charges should be accumulated linearly in direct proportion each time. If two signal charges are accumulated in the first cycle, four signal charges in direct proportion are accumulated in the second cycle. need to However, the number is 10/3 in the second time compared to 2 in the first time, and the value in the second time is smaller than the proportional value of 4, resulting in a non-proportional state between the first time and the second time.

As a result, the signal charge of the light receiving section 1 cannot be added to the addition accumulation section (9-2) in proportion to the number of times. 16 and 17 show the addition results up to the second time, but as the number of additions increases to 3 times, 4 times, and 5 times, the distance from the linear line of proportionality increases.

As a result, when the added charge of the addition storage unit (9-2) is finally output as a voltage to the signal line 4 via the FD 5, the number of times of addition and the voltage output are not linearly proportional to each other. do.

JP 2006-245522 Patent No. 6024103

In the conventional CMOS image sensor, when the signal charge of the light-receiving section is added to the addition accumulation section a plurality of times, there is a problem that an output that is linearly proportional to the number of additions cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a driving method for an imaging device in which, when a signal from a light-receiving unit is read out by adding it to an addition/accumulation unit a plurality of times, the number of times of addition and the amount of signal charge accumulated in the addition/accumulation unit are linearly proportional to each other. and an imaging device or an electronic device equipped with the imaging device that requires a wide dynamic range.

a light receiving unit;
a unit storage section that stores part or all of the signal charge of the light receiving section;
a readout transistor arranged between the light receiving section and the unit storage section;
an addition storage unit that adds part or all of the signal charges of the unit storage units;
an addition transistor arranged between the unit storage section and the addition storage section;
a source follower amplifier (AMP) in which a floating diffusion (FD) is arranged;
In an imaging device in which pixels having
The unit storage section is arranged between the light receiving section and the FD.

The maximum potential of the potential of the addition transistor is set to a potential smaller than the maximum potential of the potential of the addition storage section.

a reset transistor is arranged adjacent to the unit storage section;
A configuration in which a Low potential of the potential of the unit storage section is determined by a Low potential of the potential of the reset transistor (a reference low potential of the potential),
When transferring the signal charge in the unit storage section to the addition storage section,
The charge transferred is
a low potential of the potential of the unit storage section determined by a low potential of the potential of the reset transistor (a reference low potential of the potential);
a high potential of the addition transistor when transferring the signal charge in the unit storage portion to the addition storage portion;
is a charge in the potential range between .

When transferring the signal charge in the unit storage section to the addition storage section,
The unit storage section is characterized by having a fully depleted structure or a structure in which afterimage of the unit storage section is less than 5%.

One or both of the unit storage section and the addition storage section has an electrode above a charge storage region.

When the unit storage portion and the summation storage portion are N-type semiconductors that store electrons, one or both of the unit storage portion and the summation storage portion have a semiconductor surface area above the N-type semiconductor. A P-type semiconductor is formed in the .

The electrode of the read transistor and the transfer gate electrode are formed of the same electrode or have the same voltage.

The electrode of the summing transistor and the summing gate electrode are formed of the same electrode or have the same voltage.

a light receiving unit;
a unit storage section that stores part or all of the signal charge of the light receiving section;
a readout transistor arranged between the light receiving section and the unit storage section;
an addition storage unit that adds part or all of the signal charges of the unit storage units;
an addition transistor arranged between the unit storage section and the addition storage section;
a source follower amplifier (AMP) in which a floating diffusion (FD) is arranged;
In an imaging device in which pixels having
A plurality of combinations of the readout transistors and the unit storage sections are provided.

A mixed transistor is provided between the plurality of unit storage portions.

By operating (turning on) the mixed transistor, the charges of the plurality of unit storage portions are summed, and then by stopping the operation (turning off) of the mixed transistor, the summed charges are transferred to the plurality of unit storage portions again. Distributing is characterized.

According to the present invention, it is possible to obtain an imaging apparatus in which the number of times of addition and the amount of signal charge accumulated in the addition/accumulation unit are linearly proportional when the signal of the light receiving portion is added to the addition/accumulation unit and read out a plurality of times. can be done.

FIGS. 1A and 1B are diagrams of the first and second driving methods of the imaging device of the present invention. 2A and 2B are diagrams for the third and fourth times of the driving method of the imaging device of the present invention. FIG. 3 is a diagram in which the potential under the addition transistor is increased to increase the amount of signal charge per transfer from the unit accumulation section to the addition accumulation section. FIG. 4 is a diagram of arranging a unit accumulation portion at a position different from that of the floating diffusion. FIG. 5 is a diagram using an avalanche photodiode in the light receiving section. FIG. 6 is a diagram in which the light receiving section is an avalanche photodiode and the unit storage section is arranged at a position different from the floating diffusion. FIG. 7 is a cross-sectional view of a semiconductor having a configuration in which a unit storage portion is arranged between a light receiving portion and a floating diffusion. FIG. 8 is a cross-sectional view of a semiconductor in which a unit storage portion is composed of an N − semiconductor and a MOS electrode. FIG. 9 is a cross-sectional view of a semiconductor having a configuration in which an electrode is formed on both the unit storage section and the addition storage section. FIG. 10 is a cross-sectional view of a semiconductor configured such that the electrode of the readout transistor and the electrode on the unit storage section are used as common electrodes, and the electrode of the addition transistor and the electrode on the addition storage section are used as common electrodes. FIG. 11 is a cross-sectional view of a semiconductor having a structure in which a P-type semiconductor is formed in a semiconductor surface region above an N-type semiconductor in which a unit accumulation portion and an addition accumulation portion accumulate electrons. FIG. 12 is a circuit diagram of a pixel having a plurality of sets (two sets) of combinations of readout transistors and unit storage portions. 13A and 13B are diagrams showing the average charge of a plurality of unit storage portions and the added capacitance of the addition storage portion. FIG. 14 is an example of a circuit diagram of a conventional pixel. FIG. 15 is a cross-sectional view of the light receiving section and the FD section. 16A and 16B are diagrams for explaining the basic operation of adding the signal charges of the sections of the light receiving portion and the FD portion. FIG. 17 is a diagram of excerpts of the first basic motion and the second motion.

A method for driving an imaging device and an imaging device in which the number of times of addition and the amount of signal charge accumulated in the addition/accumulation unit are linearly proportional when the signal of the light-receiving unit is added to the addition/accumulation unit and read out a plurality of times, or An electronic device having an imaging device is provided. An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIGS. 1A and 1B are diagrams of the first and second driving methods of the imaging device of the present invention.
In FIG. 1, the operations of (A-1) and (B-1) are similar to the conventional FIG. 16, and are applied to the circuit of FIG.
In the operation (B-1), three of the twelve signal charges in the light receiving section 1 are read out to the unit storage section of the FD capacitor (5-1).

In the operation of (C-3), the difference between the maximum potential (3V) of the addition storage section (9-2) and the potential of the addition transistor 9 when the voltage is applied to the addition transistor 9 is ΔV2. is set to
At this time, among the three signal charges in the unit storage section of the FD capacitor (5-1), the signal charge having a potential lower than ΔV1 rolls down to the addition storage section (9-2), and the addition storage section ( 9-2). At this time, the signal charge that rolls down is between the low potential (0.5 V) of the potential of the unit storage section determined by the low potential of the reset transistor and the high potential ΔV1 of the potential of the addition transistor 9. It becomes a charge in the potential range.
Here, the maximum potential ΔV1 of the potential of the addition transistor 9 is set to a potential smaller than the maximum potential ΔV1+ΔV2 of the potential of the addition storage section (9-2).

In the operation of (A-4), only the unit storage portion of the FD capacitor (5-1) is reset to 3V by the reset transistor 6. FIG.

In the operation of (B-4), similarly to the operation of (B-1), three of the 12 signal charges in the light receiving section 1 are stored in the unit storage section of the FD capacitor (5-1). I am doing a second reading.

In the operation of (C-4), similarly to the operation of (C-3), one of the three signal charges in the unit accumulation portion of the FD capacitor (5-1) has a potential lower than ΔV1. rolls down to the addition storage section (9-2) and is added to the one charge that was stored at (C-3), so that the addition storage section (9-2) has a total of two charges. becomes. At this time as well, the signal charge that rolls down is between the low potential (0.5 V) of the potential of the unit storage section determined by the low potential of the reset transistor and the high potential ΔV1 of the potential of the addition transistor 9. becomes a charge in the potential range of . In (C-3) of FIG. 1, the read transistor 2 is at a Low potential (OFF), and the light receiving section 1 and the unit storage section of the FD capacitor (5-1) are in a separated state.
At this time, even if the reference low potential, which is the Low potential of the potential of the reset transistor, is changed to a voltage lower than 0.5 V, for example, to 0 V, the number of charges in the unit accumulation portion of the FD capacitor (5-1) is does not change.
Therefore, the Low potential of the potential of the reset transistor shown in FIG. means For example, when the low potential changes from 0V to 0.5V before the addition transistor 9 turns on after the readout transistor 2 turns off, the number of charges stored in the unit accumulation part of the FD capacitor (5-1) is determined. The low potential in the case of 1 is 0.5 V, which is the upper limit.
Also in this case, the maximum potential ΔV1 of the potential of the addition transistor 9 is set to a potential smaller than the maximum potential ΔV1+ΔV2 of the potential of the addition storage section (9-2).

2A and 2B are diagrams for the third and fourth times of the driving method of the imaging device of the present invention.
The third (A-5) and the fourth (A-5) are the same operations as the second (A-3), and the third (B-5) and the fourth (B -5) is the same as the second (B-3).

As a result, in the operation (C-5), the third addition operation results in a total of three charges accumulated in the addition accumulation section (9-2).
Furthermore, in the operation (C-6), the fourth addition operation results in a total of four charges accumulated in the addition accumulation section (9-2).

As can be seen from FIGS. 1 and 2, in the case of the first time (C-3), the maximum potential of the addition storage section (9-2) is set to ΔV1+ΔV2=3V, and the addition when voltage is applied to the addition transistor 9 By setting the difference from the potential of the transistor 9 to ΔV2, the maximum potential of the addition transistor 9 is set to ΔV1, and the maximum potential of the addition transistor 9 becomes the potential of the addition storage unit (9-2). is smaller than the maximum potential of the light-receiving unit 1, when the signal charge of the light-receiving unit 1 is read out by being added to the addition accumulation unit (9-2) via the unit accumulation unit a plurality of times, the number of times of addition , and the amount of signal charge accumulated in the addition accumulation section (9-2) is linearly proportional.

At this time, by setting ΔV1 to a small potential difference, the amount of signal charge accumulated in the addition accumulation unit (9-2) per time can be reduced. You can increase the number of times. The limit value of the number of times of accumulation that can increase the amount of signal charge in the addition/accumulation section (9-2) in linear proportion is when the potential due to the charge accumulated in the addition/accumulation section (9-2) exceeds ΔV2. There is no problem as long as it is within the range of no.

When the potential due to the charge accumulated in the addition accumulation section (9-2) exceeds ΔV2, part of the charge accumulated in the addition accumulation section (9-2) exceeds the potential of the addition transistor 9. The signal charge amount of the addition storage section (9-2) cannot be linearly proportional because it exceeds and flows backward to the unit storage section of the FD capacitor (5-1).

FIG. 3 shows the potential of the addition transistor 9 when the voltage is applied to the addition transistor 9, and the potential of the addition transistor 9 is increased to transfer from the unit storage section (5-1) to the addition storage section (9-2). It is the figure which increased the signal electric charge amount.
In the operation of (C-3) in FIG. 1, the difference ΔV1 between the potential of the addition transistor 9 and the potential of the addition transistor 9 when a voltage is applied to the addition transistor 9 is small. 9-2), but in the operation of (C-7) in FIG. Two electric charges can be transferred to the addition storage section (9-2) at one time, and the voltage of the addition storage section (9-2) can be greatly changed, so that the gain and sensitivity read out from the signal line 4 are increased. be able to. In FIG. 3, the difference between the maximum potential (3V) of the addition storage section (9-2) and the potential of the addition transistor 9 when a voltage is applied to the addition transistor 9 is smaller than ΔV4 and ΔV2. Therefore, the limit value of the number of times of accumulation that can increase the amount of signal charge in the addition/accumulation section (9-2) in direct proportion is determined by the potential due to the charge accumulated in the addition/accumulation section (9-2). Since the range does not exceed ΔV4, the limit number of times is smaller than in FIG.

1 and FIG. 3, the difference between the maximum potential (3 V) of the addition storage section (9-2) and the potential of the addition transistor 9 when a voltage is applied to the addition transistor 9 is By adopting a driving method that provides ΔV2 or ΔV4, it is possible to realize an imaging device that can increase the amount of signal charge in the addition accumulation section (9-2) linearly and in direct proportion.

FIG. 4 is a diagram of arranging the unit accumulation portion at a position different from that of the floating diffusion (FD). The unit storage section 14 is arranged adjacent to the light receiving section 1, and is characterized in that it is arranged between the light receiving section 1 and the floating diffusion 5 (FD). Further, the addition accumulation section (9-2) is arranged between the unit accumulation section 14 and the FD5. As a result, the light receiving section 1, the readout transistor 2, the unit storage section 14, the addition transistor 9, the addition storage section (9-2), the readout transistor 15 of the addition storage section, and the FD5 are arranged in this order. The unit storage section 14 in FIG. 4 replaces the FD capacitor (5-1) in FIGS.

At this time, in the case of driving (A-1), it is necessary to reset the unit storage section 14 and the addition storage section (9-2) to 3V. 6-3) to turn on both the reset transistor (6-2) of the addition accumulation section, thereby performing an initial reset operation. Other operations are completely the same as those in FIGS. 1 to 3, and the driving method can be realized.

As a result, when the signal charge of the light receiving section 1 is added to the addition accumulation section (9-2) via the unit accumulation section 14 and read out a plurality of times, the number of times of addition and the addition accumulation section (9- In 2), it is possible to realize a driving method in which the amount of accumulated signal charge is linearly proportional.
After that, when the readout transistor 15 of the addition/accumulation section is turned on, the signal charge accumulated in the addition/accumulation section (9-2) changes to a voltage due to the total capacitance of the addition/accumulation section (9-2) and the capacitance of the FD5. It is converted and read out to the outside through AMP 3 and signal line 4 .

The greatest advantage of FIG. 4 is that the size of the unit storage section 14 can be freely changed. Since the main purpose of the FD capacitor (5-1) is to play an important role in determining the conversion gain of the source follower amplifier 3, the biggest problem is that the FD capacitor (5-1) cannot be easily changed. On the other hand, since the unit storage section 14 in FIG. 4 does not affect the conversion gain, the capacity of the unit storage section 14 can be freely reduced.

In order to ensure the dynamic range of the addition storage section (9-2), a large area is required for the capacitance. By increasing the capacity ratio between the capacity and the large-capacity addition/accumulation section (9-2), while adding and accumulating in the addition/accumulation section (9-2), the signal charge amount can be linearly proportional to the limit number of times of addition. should be increased. Thereby, a wide dynamic range can be realized.

FIG. 5 is a diagram using an avalanche photodiode in the light receiving section.
FIG. 5 shows a case where an avalanche photodiode (APD) is adopted for the light receiving section 1 of FIG. Since it is necessary to apply a high voltage to the PN junction of the avalanche region 102 , a voltage of approximately 30 V is applied to the semiconductor substrate 13 .

A P-type well (P-well) 101 is sandwiched between an N-type well (N-well) 100 so that a high voltage of the semiconductor substrate 13 is not applied to the semiconductor P-type region of the circuit other than the light receiving unit 1. are separating.
0 V is applied to the P-type well (P-Well) 101 .
When light enters the avalanche region 102 in this state, an avalanche multiplication phenomenon occurs, signal charge is accumulated in the N region of the avalanche region 102 , and the charge connects the light receiving portion 1 and the source of the readout transistor 2 . A signal charge is transmitted to the source 103 of the read transistor 2 via the wiring 104 .
Signal charges connected to the source 103 of the readout transistor 2 can be driven by the same driving method as in FIGS. 1 to 3 by turning on the readout transistor 2 .

As a result, when the signal charges of the APD are read out by being added to the addition accumulation section (9-2) via the unit accumulation section 14 a plurality of times, the number of times of addition and the addition accumulation section (9-2) It is possible to realize a driving method in which the amount of signal charge accumulated in is linearly proportional.

In particular, the amount of signal charge generated in the avalanche region 100 of the APD is much larger than that in the normal light receiving section 1, but the generation probability is small. Therefore, the driving method shown in FIGS. 1 to 3 is the optimum driving method for wide dynamic range driving and multiple readout driving.

Therefore, even in wide dynamic range driving or multiple readout driving, the number of additions and the amount of signal charge accumulated in the addition accumulation section (9-2) are linearly proportional to each other, making it the most effective use. can.

FIG. 6 is a diagram in which the light receiving section is an avalanche photodiode and the unit storage section is arranged at a position different from the floating diffusion.

FIG. 6 shows an invention in which an avalanche photodiode structure and a driving method are used in the light receiving section 1 in contrast to the wide dynamic range structure of FIG.
Therefore, by combining the light receiving section 1 of the wide dynamic range APD as shown in FIG. A driving method in which the number of times signal charges are read out from and the amount of signal charges in the addition storage section (9-2) are directly proportional to each other can be used most effectively. Therefore, an imaging device with the widest dynamic range can be achieved.

FIG. 7 is a cross-sectional view of a semiconductor having a structure in which the unit storage section 14 is arranged between the light receiving section 1 and the floating diffusion 5. As shown in FIG. FIG. 7 is a cross-sectional view of the semiconductors of the light receiving section 1, the unit storage section 14, the addition storage section (9-2), and the floating diffusion 5 in the case of the circuit configuration of FIG.

As shown in FIG. 15, the FD capacitance (5-1) of the unit storage section and the capacitance of the addition storage section (9-2) are normally N+ semiconductor capacitors or MIM capacitors having N+ source/drain. be done.

In FIG. 7, similarly, the unit storage section 14 and the addition storage section (9-2) are N+ semiconductors. In this case, in the high-concentration N-type semiconductor, noise is generated due to leakage charges caused by lattice defects, resulting in a decrease in dynamic range.

FIG. 8 is a sectional view of a semiconductor in which the unit storage section 14 is composed of an N− semiconductor and a MOS electrode. In FIG. 8, in order to reduce noise due to leakage charges caused by lattice defects when a high-concentration N-type semiconductor is used for the unit storage section 14, the unit storage section 14 is provided with a low-concentration N− semiconductor and a MOS electrode. We are hiring. When the readout transistor 2 is turned on, a high voltage is applied to the wiring (14-1) of the unit storage section to increase the potential of the low-concentration N− semiconductor of the unit storage section 14, and the charge from the light receiving section 1 is increased. can be easily transferred to the unit storage section 14 . With this configuration, noise due to leakage charges caused by lattice defects is reduced, and a wide dynamic range with little noise is realized.

FIG. 9 is a cross-sectional view of a semiconductor in which capacitors are formed by N− semiconductors and MOS electrodes in both the unit storage section 14 and the addition storage section (9-2).

In FIG. 9, as in FIG. 8, both the unit storage section 14 and the addition storage section (9-2) can reduce noise due to leakage charges caused by lattice defects. It is possible to realize the ultimate wide dynamic range with less. Basically, since it is desired to increase the capacity of the addition storage section (9-2), a positive voltage is applied to the wiring (9-3) of the MOS electrode of the addition storage section (9-2). Since the potential difference of ΔV2 of 1 can be increased and the size of the dynamic range can be adjusted, the effect of realizing a wide dynamic range is great.

FIG. 10 is a cross-sectional view of a semiconductor having a structure in which the electrodes of the readout transistor and the electrodes on the unit storage section are used as common electrodes, and the electrodes of the addition transistor and the electrodes on the addition storage section are used as common electrodes.

As shown in FIG. 10, by sharing the electrodes, the number of electrodes can be reduced and the total capacitance area of both the unit storage section 14 and the addition storage section (9-2) can be increased. As a result, the capacity ratio between the unit storage section 14 and the addition storage section (9-2) can be increased, and a wide dynamic range can be achieved.

FIG. 11 is a cross-sectional view of a semiconductor having a structure in which a P-type semiconductor is formed in a semiconductor surface region above an N-type semiconductor in which the unit accumulation portion 14 and the addition accumulation portion (9-2) accumulate electrons.

In the structure of FIG. 11, a P-type semiconductor is formed in the surface layer as means for reducing leakage charges due to lattice defects on the surface of the unit storage section 14 and the addition storage section (9-2). In this case, since the process of forming the unit storage section 14 and the addition storage section (9-2) can be used simultaneously with the formation of the light receiving section 1, the manufacturing process can be reduced. As a result, it is possible to reduce the probability of lattice defects occurring during many manufacturing processes, so that a wider dynamic range can be achieved.

FIG. 12 is a circuit diagram of a pixel having a plurality of sets (two sets) of combinations of readout transistors and unit storage portions.

This structure works in the following order.
1) For the first time, a voltage is applied to the wiring (2-1) of the readout transistor 2 (TR2) to read the charge from the light receiving section 1 to the first capacitor (C14) of the unit storage section .
2) For the second time, a voltage is applied to the wiring (2-3) of the readout transistor 2-2 (TR2-2) to transfer the voltage from the light receiving section 1 to the second capacitor (C14-2) of the unit storage section 14-2. Read the charge.
3) By applying a voltage to the wiring (2-5) of the mixed transistor 2-4 (TR2-4), the charge of the first capacitor 14 (C14) of the unit storage section and the first capacitor (C14- The charges of 2) are mixed and averaged.
Therefore, the signal charge amount for two times can be halved for one time.
For example, in FIG. 4, when the ratio between the unit storage section 14 and the addition storage section (9-2) is 1:10, the charges in the unit storage section 14 could be added only 10 times. In this case, two times can be averaged to correspond to one time, so the capacity ratio of the addition storage unit (9-2) is 2 times*10 times=20 times. As a result, the number of times of addition is doubled, and a wider dynamic range can be realized.

13A and 13B are diagrams showing the average charge of a plurality of unit storage portions and the added capacitance of the addition storage portion. FIG. 13 is a specific example described in the structure of FIG.
(For Case 1)
When the first capacitor (C14) is signal 1 and the second capacitor (C14-2) is signal 1,
On average, 1.
(For Case 2)
When the first capacitor (C14) is signal 1 and the second capacitor (C14-2) is signal 0,
On average, 0.5.
(For Case 3)
When the first capacitor (C14) is signal 0 and the second capacitor (C14-2) is signal 1,
On average, 0.5.
(For Case 4)
When the first capacitor (C14) is signal 0 and the second capacitor (C14-2) is signal 0,
0 when averaged.
As described above, when the maximum value of two times is 1 and the addition storage unit is 10,
The effect of being able to accumulate charges for 20 times and realizing a wide dynamic range is clear.

In the configurations of FIGS. 9 to 12, when an avalanche photodiode is used in the light-receiving part, the wide dynamic range can be realized more effectively.

Electronic equipment equipped with an imaging device that employs the driving method according to the present invention is used in many fields that require a wide dynamic range, such as mobile phones, cameras for industrial equipment, and cameras for vehicles.

1 light receiving unit 2 readout transistor (TR2)
2-1 Readout transistor wiring 2-2 Readout transistor (TR2-2)
2-3 Readout transistor wiring 2-4 Mixed transistor (TR2-4)
2-5 Mixed transistor wiring 3 Source follower amplifier (AMP)
4 signal line 5 floating diffusion (FD)
5-1 Floating diffusion capacitance (FD capacitance, C5)
6 FD reset transistor (TR6)
6-1 FD reset transistor wiring 6-2 Addition storage unit reset transistor (TR6-2)
6-3 Addition accumulation unit reset transistor wiring 7 Source follower transistor (TR7)
8 row selection transistor (TR8)
8-1 Row selection transistor (TR8) wiring 9 Addition transistor (TR9)
9-1 addition transistor wiring 9-2 addition accumulation unit (C9)
9-3 addition/accumulation unit (C9) wiring 10 amplifier power supply 11 light receiving unit reset transistor (TR11)
11-1 Light-receiving part reset transistor (TR11) wiring 12 Light-receiving part reset power supply 13 Semiconductor substrate
14 unit storage unit (C14)
14-1 unit storage unit (C14) wiring 14-2 unit storage unit (C14-2)
15 readout transistor (TR15) of addition storage unit
15-1 Wiring of readout transistor (TR15) of adder/accumulator

100 N-well (N-Well)
101 P-type well (P-Well)
102 Avalanche region 103 Source of readout transistor 104 Wiring connecting light receiving portion and source of readout transistor

Claims

a light receiving unit;
a unit storage section that stores part or all of the signal charge of the light receiving section;
a readout transistor arranged between the light receiving section and the unit storage section;
an addition storage unit that adds part or all of the signal charges of the unit storage units;
an addition transistor arranged between the unit storage section and the addition storage section;
a source follower amplifier (AMP) in which a floating diffusion (FD) is arranged;
In an imaging device in which pixels having
An imaging apparatus, wherein the unit storage section is arranged between the light receiving section and the FD.
2. The imaging apparatus according to claim 1, wherein the maximum potential of the potential of said addition transistor is set to a potential smaller than the maximum potential of potential of said addition storage section.
a reset transistor is arranged adjacent to the unit storage section;
A configuration in which a Low potential of the potential of the unit storage section is determined by a Low potential of the potential of the reset transistor (a reference low potential of the potential),
When transferring the signal charge in the unit storage section to the addition storage section,
The charge transferred is
a low potential of the potential of the unit storage section determined by a low potential of the potential of the reset transistor (a reference low potential of the potential);
a high potential of the addition transistor when transferring the signal charge in the unit storage portion to the addition storage portion;
3. The imaging device according to claim 1, wherein the charge is in a potential range between .
When transferring the signal charge in the unit storage section to the addition storage section,
4. The imaging device according to claim 1, wherein said unit storage section has a structure that is completely depleted, or has a structure in which an afterimage of said unit storage section is less than 5%.
4. An image pickup apparatus according to claim 1, wherein one or both of said unit storage section and said addition storage section have an electrode above a charge storage region.
When the unit storage portion and the summation storage portion are N-type semiconductors that store electrons, one or both of the unit storage portion and the summation storage portion have a semiconductor surface area above the N-type semiconductor. 5. An image pickup apparatus according to claim 1, wherein a P-type semiconductor is formed in said region.
6. The imaging device according to claim 5, wherein the electrode of the readout transistor and the electrode of the transfer gate are formed of the same electrode or have the same voltage.
6. The image pickup apparatus according to claim 5, wherein the electrode of the addition transistor and the electrode of the addition gate are formed of the same electrode or have the same voltage.
a light receiving unit;
a unit storage section that stores part or all of the signal charge of the light receiving section;
a readout transistor arranged between the light receiving section and the unit storage section;
an addition storage unit that adds part or all of the signal charges of the unit storage units;
an addition transistor arranged between the unit storage section and the addition storage section;
a source follower amplifier (AMP) in which a floating diffusion (FD) is arranged;
In an imaging device in which pixels having
An image pickup device, wherein the combination of the readout transistor and the unit storage section is configured in a plurality of sets.
5. The imaging apparatus according to claim 1, wherein a plurality of combinations of said readout transistors and said unit storage sections are formed.
11. The imaging device according to claim 9, further comprising a mixed transistor between the plurality of unit storage sections.
By operating (turning on) the mixed transistor, the charges of the plurality of unit storage portions are summed, and then by stopping the operation (turning off) of the mixed transistor, the summed charges are transferred to the plurality of unit storage portions again. 11. The imaging apparatus according to claim 9, wherein the images are sorted.
13. The imaging apparatus according to claim 1, wherein said light receiving unit is an avalanche photodiode.